Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
a70491cc JP |
29 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
30 | ||
63eeaf38 | 31 | #include <linux/sysrq.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
b2c88f5b | 33 | #include <linux/circ_buf.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/i915_drm.h> | |
1da177e4 | 36 | #include "i915_drv.h" |
1c5d22f7 | 37 | #include "i915_trace.h" |
79e53945 | 38 | #include "intel_drv.h" |
1da177e4 | 39 | |
fca52a55 DV |
40 | /** |
41 | * DOC: interrupt handling | |
42 | * | |
43 | * These functions provide the basic support for enabling and disabling the | |
44 | * interrupt handling support. There's a lot more functionality in i915_irq.c | |
45 | * and related files, but that will be described in separate chapters. | |
46 | */ | |
47 | ||
e4ce95aa VS |
48 | static const u32 hpd_ilk[HPD_NUM_PINS] = { |
49 | [HPD_PORT_A] = DE_DP_A_HOTPLUG, | |
50 | }; | |
51 | ||
23bb4cb5 VS |
52 | static const u32 hpd_ivb[HPD_NUM_PINS] = { |
53 | [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB, | |
54 | }; | |
55 | ||
3a3b3c7d VS |
56 | static const u32 hpd_bdw[HPD_NUM_PINS] = { |
57 | [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG, | |
58 | }; | |
59 | ||
7c7e10db | 60 | static const u32 hpd_ibx[HPD_NUM_PINS] = { |
e5868a31 EE |
61 | [HPD_CRT] = SDE_CRT_HOTPLUG, |
62 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG, | |
63 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG, | |
64 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG, | |
65 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG | |
66 | }; | |
67 | ||
7c7e10db | 68 | static const u32 hpd_cpt[HPD_NUM_PINS] = { |
e5868a31 | 69 | [HPD_CRT] = SDE_CRT_HOTPLUG_CPT, |
73c352a2 | 70 | [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT, |
e5868a31 EE |
71 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
72 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
73 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT | |
74 | }; | |
75 | ||
26951caf | 76 | static const u32 hpd_spt[HPD_NUM_PINS] = { |
74c0b395 | 77 | [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT, |
26951caf XZ |
78 | [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT, |
79 | [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT, | |
80 | [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT, | |
81 | [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT | |
82 | }; | |
83 | ||
7c7e10db | 84 | static const u32 hpd_mask_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
85 | [HPD_CRT] = CRT_HOTPLUG_INT_EN, |
86 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN, | |
87 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN, | |
88 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN, | |
89 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN, | |
90 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN | |
91 | }; | |
92 | ||
7c7e10db | 93 | static const u32 hpd_status_g4x[HPD_NUM_PINS] = { |
e5868a31 EE |
94 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
95 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X, | |
96 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X, | |
97 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
98 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
99 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
100 | }; | |
101 | ||
4bca26d0 | 102 | static const u32 hpd_status_i915[HPD_NUM_PINS] = { |
e5868a31 EE |
103 | [HPD_CRT] = CRT_HOTPLUG_INT_STATUS, |
104 | [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915, | |
105 | [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915, | |
106 | [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS, | |
107 | [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS, | |
108 | [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS | |
109 | }; | |
110 | ||
e0a20ad7 SS |
111 | /* BXT hpd list */ |
112 | static const u32 hpd_bxt[HPD_NUM_PINS] = { | |
7f3561be | 113 | [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA, |
e0a20ad7 SS |
114 | [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB, |
115 | [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC | |
116 | }; | |
117 | ||
5c502442 | 118 | /* IIR can theoretically queue up two events. Be paranoid. */ |
f86f3fb0 | 119 | #define GEN8_IRQ_RESET_NDX(type, which) do { \ |
5c502442 PZ |
120 | I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \ |
121 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
122 | I915_WRITE(GEN8_##type##_IER(which), 0); \ | |
123 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
124 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
125 | I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \ | |
126 | POSTING_READ(GEN8_##type##_IIR(which)); \ | |
127 | } while (0) | |
128 | ||
f86f3fb0 | 129 | #define GEN5_IRQ_RESET(type) do { \ |
a9d356a6 | 130 | I915_WRITE(type##IMR, 0xffffffff); \ |
5c502442 | 131 | POSTING_READ(type##IMR); \ |
a9d356a6 | 132 | I915_WRITE(type##IER, 0); \ |
5c502442 PZ |
133 | I915_WRITE(type##IIR, 0xffffffff); \ |
134 | POSTING_READ(type##IIR); \ | |
135 | I915_WRITE(type##IIR, 0xffffffff); \ | |
136 | POSTING_READ(type##IIR); \ | |
a9d356a6 PZ |
137 | } while (0) |
138 | ||
337ba017 PZ |
139 | /* |
140 | * We should clear IMR at preinstall/uninstall, and just check at postinstall. | |
141 | */ | |
142 | #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \ | |
143 | u32 val = I915_READ(reg); \ | |
144 | if (val) { \ | |
145 | WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \ | |
146 | (reg), val); \ | |
147 | I915_WRITE((reg), 0xffffffff); \ | |
148 | POSTING_READ(reg); \ | |
149 | I915_WRITE((reg), 0xffffffff); \ | |
150 | POSTING_READ(reg); \ | |
151 | } \ | |
152 | } while (0) | |
153 | ||
35079899 | 154 | #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \ |
337ba017 | 155 | GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \ |
35079899 | 156 | I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \ |
7d1bd539 VS |
157 | I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \ |
158 | POSTING_READ(GEN8_##type##_IMR(which)); \ | |
35079899 PZ |
159 | } while (0) |
160 | ||
161 | #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \ | |
337ba017 | 162 | GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \ |
35079899 | 163 | I915_WRITE(type##IER, (ier_val)); \ |
7d1bd539 VS |
164 | I915_WRITE(type##IMR, (imr_val)); \ |
165 | POSTING_READ(type##IMR); \ | |
35079899 PZ |
166 | } while (0) |
167 | ||
c9a9a268 ID |
168 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir); |
169 | ||
0706f17c EE |
170 | /* For display hotplug interrupt */ |
171 | static inline void | |
172 | i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, | |
173 | uint32_t mask, | |
174 | uint32_t bits) | |
175 | { | |
176 | uint32_t val; | |
177 | ||
178 | assert_spin_locked(&dev_priv->irq_lock); | |
179 | WARN_ON(bits & ~mask); | |
180 | ||
181 | val = I915_READ(PORT_HOTPLUG_EN); | |
182 | val &= ~mask; | |
183 | val |= bits; | |
184 | I915_WRITE(PORT_HOTPLUG_EN, val); | |
185 | } | |
186 | ||
187 | /** | |
188 | * i915_hotplug_interrupt_update - update hotplug interrupt enable | |
189 | * @dev_priv: driver private | |
190 | * @mask: bits to update | |
191 | * @bits: bits to enable | |
192 | * NOTE: the HPD enable bits are modified both inside and outside | |
193 | * of an interrupt context. To avoid that read-modify-write cycles | |
194 | * interfer, these bits are protected by a spinlock. Since this | |
195 | * function is usually not called from a context where the lock is | |
196 | * held already, this function acquires the lock itself. A non-locking | |
197 | * version is also available. | |
198 | */ | |
199 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, | |
200 | uint32_t mask, | |
201 | uint32_t bits) | |
202 | { | |
203 | spin_lock_irq(&dev_priv->irq_lock); | |
204 | i915_hotplug_interrupt_update_locked(dev_priv, mask, bits); | |
205 | spin_unlock_irq(&dev_priv->irq_lock); | |
206 | } | |
207 | ||
d9dc34f1 VS |
208 | /** |
209 | * ilk_update_display_irq - update DEIMR | |
210 | * @dev_priv: driver private | |
211 | * @interrupt_mask: mask of interrupt bits to update | |
212 | * @enabled_irq_mask: mask of interrupt bits to enable | |
213 | */ | |
214 | static void ilk_update_display_irq(struct drm_i915_private *dev_priv, | |
215 | uint32_t interrupt_mask, | |
216 | uint32_t enabled_irq_mask) | |
036a4a7d | 217 | { |
d9dc34f1 VS |
218 | uint32_t new_val; |
219 | ||
4bc9d430 DV |
220 | assert_spin_locked(&dev_priv->irq_lock); |
221 | ||
d9dc34f1 VS |
222 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
223 | ||
9df7575f | 224 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 225 | return; |
c67a470b | 226 | |
d9dc34f1 VS |
227 | new_val = dev_priv->irq_mask; |
228 | new_val &= ~interrupt_mask; | |
229 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
230 | ||
231 | if (new_val != dev_priv->irq_mask) { | |
232 | dev_priv->irq_mask = new_val; | |
1ec14ad3 | 233 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
3143a2bf | 234 | POSTING_READ(DEIMR); |
036a4a7d ZW |
235 | } |
236 | } | |
237 | ||
47339cd9 | 238 | void |
d9dc34f1 | 239 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask) |
036a4a7d | 240 | { |
d9dc34f1 VS |
241 | ilk_update_display_irq(dev_priv, mask, mask); |
242 | } | |
c67a470b | 243 | |
d9dc34f1 VS |
244 | void |
245 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask) | |
246 | { | |
247 | ilk_update_display_irq(dev_priv, mask, 0); | |
036a4a7d ZW |
248 | } |
249 | ||
43eaea13 PZ |
250 | /** |
251 | * ilk_update_gt_irq - update GTIMR | |
252 | * @dev_priv: driver private | |
253 | * @interrupt_mask: mask of interrupt bits to update | |
254 | * @enabled_irq_mask: mask of interrupt bits to enable | |
255 | */ | |
256 | static void ilk_update_gt_irq(struct drm_i915_private *dev_priv, | |
257 | uint32_t interrupt_mask, | |
258 | uint32_t enabled_irq_mask) | |
259 | { | |
260 | assert_spin_locked(&dev_priv->irq_lock); | |
261 | ||
15a17aae DV |
262 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
263 | ||
9df7575f | 264 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 265 | return; |
c67a470b | 266 | |
43eaea13 PZ |
267 | dev_priv->gt_irq_mask &= ~interrupt_mask; |
268 | dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask); | |
269 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
270 | POSTING_READ(GTIMR); | |
271 | } | |
272 | ||
480c8033 | 273 | void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
274 | { |
275 | ilk_update_gt_irq(dev_priv, mask, mask); | |
276 | } | |
277 | ||
480c8033 | 278 | void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
43eaea13 PZ |
279 | { |
280 | ilk_update_gt_irq(dev_priv, mask, 0); | |
281 | } | |
282 | ||
b900b949 ID |
283 | static u32 gen6_pm_iir(struct drm_i915_private *dev_priv) |
284 | { | |
285 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR; | |
286 | } | |
287 | ||
a72fbc3a ID |
288 | static u32 gen6_pm_imr(struct drm_i915_private *dev_priv) |
289 | { | |
290 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR; | |
291 | } | |
292 | ||
b900b949 ID |
293 | static u32 gen6_pm_ier(struct drm_i915_private *dev_priv) |
294 | { | |
295 | return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER; | |
296 | } | |
297 | ||
edbfdb45 PZ |
298 | /** |
299 | * snb_update_pm_irq - update GEN6_PMIMR | |
300 | * @dev_priv: driver private | |
301 | * @interrupt_mask: mask of interrupt bits to update | |
302 | * @enabled_irq_mask: mask of interrupt bits to enable | |
303 | */ | |
304 | static void snb_update_pm_irq(struct drm_i915_private *dev_priv, | |
305 | uint32_t interrupt_mask, | |
306 | uint32_t enabled_irq_mask) | |
307 | { | |
605cd25b | 308 | uint32_t new_val; |
edbfdb45 | 309 | |
15a17aae DV |
310 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
311 | ||
edbfdb45 PZ |
312 | assert_spin_locked(&dev_priv->irq_lock); |
313 | ||
605cd25b | 314 | new_val = dev_priv->pm_irq_mask; |
f52ecbcf PZ |
315 | new_val &= ~interrupt_mask; |
316 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
317 | ||
605cd25b PZ |
318 | if (new_val != dev_priv->pm_irq_mask) { |
319 | dev_priv->pm_irq_mask = new_val; | |
a72fbc3a ID |
320 | I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask); |
321 | POSTING_READ(gen6_pm_imr(dev_priv)); | |
f52ecbcf | 322 | } |
edbfdb45 PZ |
323 | } |
324 | ||
480c8033 | 325 | void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
edbfdb45 | 326 | { |
9939fba2 ID |
327 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
328 | return; | |
329 | ||
edbfdb45 PZ |
330 | snb_update_pm_irq(dev_priv, mask, mask); |
331 | } | |
332 | ||
9939fba2 ID |
333 | static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv, |
334 | uint32_t mask) | |
edbfdb45 PZ |
335 | { |
336 | snb_update_pm_irq(dev_priv, mask, 0); | |
337 | } | |
338 | ||
9939fba2 ID |
339 | void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask) |
340 | { | |
341 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
342 | return; | |
343 | ||
344 | __gen6_disable_pm_irq(dev_priv, mask); | |
345 | } | |
346 | ||
3cc134e3 ID |
347 | void gen6_reset_rps_interrupts(struct drm_device *dev) |
348 | { | |
349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
350 | uint32_t reg = gen6_pm_iir(dev_priv); | |
351 | ||
352 | spin_lock_irq(&dev_priv->irq_lock); | |
353 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
354 | I915_WRITE(reg, dev_priv->pm_rps_events); | |
355 | POSTING_READ(reg); | |
096fad9e | 356 | dev_priv->rps.pm_iir = 0; |
3cc134e3 ID |
357 | spin_unlock_irq(&dev_priv->irq_lock); |
358 | } | |
359 | ||
b900b949 ID |
360 | void gen6_enable_rps_interrupts(struct drm_device *dev) |
361 | { | |
362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
363 | ||
364 | spin_lock_irq(&dev_priv->irq_lock); | |
78e68d36 | 365 | |
b900b949 | 366 | WARN_ON(dev_priv->rps.pm_iir); |
3cc134e3 | 367 | WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); |
d4d70aa5 | 368 | dev_priv->rps.interrupts_enabled = true; |
78e68d36 ID |
369 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | |
370 | dev_priv->pm_rps_events); | |
b900b949 | 371 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
78e68d36 | 372 | |
b900b949 ID |
373 | spin_unlock_irq(&dev_priv->irq_lock); |
374 | } | |
375 | ||
59d02a1f ID |
376 | u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask) |
377 | { | |
378 | /* | |
f24eeb19 | 379 | * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer |
59d02a1f | 380 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
f24eeb19 ID |
381 | * |
382 | * TODO: verify if this can be reproduced on VLV,CHV. | |
59d02a1f ID |
383 | */ |
384 | if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv)) | |
385 | mask &= ~GEN6_PM_RP_UP_EI_EXPIRED; | |
386 | ||
387 | if (INTEL_INFO(dev_priv)->gen >= 8) | |
388 | mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
389 | ||
390 | return mask; | |
391 | } | |
392 | ||
b900b949 ID |
393 | void gen6_disable_rps_interrupts(struct drm_device *dev) |
394 | { | |
395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
396 | ||
d4d70aa5 ID |
397 | spin_lock_irq(&dev_priv->irq_lock); |
398 | dev_priv->rps.interrupts_enabled = false; | |
399 | spin_unlock_irq(&dev_priv->irq_lock); | |
400 | ||
401 | cancel_work_sync(&dev_priv->rps.work); | |
402 | ||
9939fba2 ID |
403 | spin_lock_irq(&dev_priv->irq_lock); |
404 | ||
59d02a1f | 405 | I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0)); |
9939fba2 ID |
406 | |
407 | __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
b900b949 ID |
408 | I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & |
409 | ~dev_priv->pm_rps_events); | |
58072ccb ID |
410 | |
411 | spin_unlock_irq(&dev_priv->irq_lock); | |
412 | ||
413 | synchronize_irq(dev->irq); | |
b900b949 ID |
414 | } |
415 | ||
3a3b3c7d VS |
416 | /** |
417 | * bdw_update_port_irq - update DE port interrupt | |
418 | * @dev_priv: driver private | |
419 | * @interrupt_mask: mask of interrupt bits to update | |
420 | * @enabled_irq_mask: mask of interrupt bits to enable | |
421 | */ | |
422 | static void bdw_update_port_irq(struct drm_i915_private *dev_priv, | |
423 | uint32_t interrupt_mask, | |
424 | uint32_t enabled_irq_mask) | |
425 | { | |
426 | uint32_t new_val; | |
427 | uint32_t old_val; | |
428 | ||
429 | assert_spin_locked(&dev_priv->irq_lock); | |
430 | ||
431 | WARN_ON(enabled_irq_mask & ~interrupt_mask); | |
432 | ||
433 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) | |
434 | return; | |
435 | ||
436 | old_val = I915_READ(GEN8_DE_PORT_IMR); | |
437 | ||
438 | new_val = old_val; | |
439 | new_val &= ~interrupt_mask; | |
440 | new_val |= (~enabled_irq_mask & interrupt_mask); | |
441 | ||
442 | if (new_val != old_val) { | |
443 | I915_WRITE(GEN8_DE_PORT_IMR, new_val); | |
444 | POSTING_READ(GEN8_DE_PORT_IMR); | |
445 | } | |
446 | } | |
447 | ||
fee884ed DV |
448 | /** |
449 | * ibx_display_interrupt_update - update SDEIMR | |
450 | * @dev_priv: driver private | |
451 | * @interrupt_mask: mask of interrupt bits to update | |
452 | * @enabled_irq_mask: mask of interrupt bits to enable | |
453 | */ | |
47339cd9 DV |
454 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
455 | uint32_t interrupt_mask, | |
456 | uint32_t enabled_irq_mask) | |
fee884ed DV |
457 | { |
458 | uint32_t sdeimr = I915_READ(SDEIMR); | |
459 | sdeimr &= ~interrupt_mask; | |
460 | sdeimr |= (~enabled_irq_mask & interrupt_mask); | |
461 | ||
15a17aae DV |
462 | WARN_ON(enabled_irq_mask & ~interrupt_mask); |
463 | ||
fee884ed DV |
464 | assert_spin_locked(&dev_priv->irq_lock); |
465 | ||
9df7575f | 466 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
c67a470b | 467 | return; |
c67a470b | 468 | |
fee884ed DV |
469 | I915_WRITE(SDEIMR, sdeimr); |
470 | POSTING_READ(SDEIMR); | |
471 | } | |
8664281b | 472 | |
b5ea642a | 473 | static void |
755e9019 ID |
474 | __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
475 | u32 enable_mask, u32 status_mask) | |
7c463586 | 476 | { |
46c06a30 | 477 | u32 reg = PIPESTAT(pipe); |
755e9019 | 478 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 479 | |
b79480ba | 480 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 481 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 482 | |
04feced9 VS |
483 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
484 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
485 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
486 | pipe_name(pipe), enable_mask, status_mask)) | |
755e9019 ID |
487 | return; |
488 | ||
489 | if ((pipestat & enable_mask) == enable_mask) | |
46c06a30 VS |
490 | return; |
491 | ||
91d181dd ID |
492 | dev_priv->pipestat_irq_mask[pipe] |= status_mask; |
493 | ||
46c06a30 | 494 | /* Enable the interrupt, clear any pending status */ |
755e9019 | 495 | pipestat |= enable_mask | status_mask; |
46c06a30 VS |
496 | I915_WRITE(reg, pipestat); |
497 | POSTING_READ(reg); | |
7c463586 KP |
498 | } |
499 | ||
b5ea642a | 500 | static void |
755e9019 ID |
501 | __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
502 | u32 enable_mask, u32 status_mask) | |
7c463586 | 503 | { |
46c06a30 | 504 | u32 reg = PIPESTAT(pipe); |
755e9019 | 505 | u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; |
7c463586 | 506 | |
b79480ba | 507 | assert_spin_locked(&dev_priv->irq_lock); |
d518ce50 | 508 | WARN_ON(!intel_irqs_enabled(dev_priv)); |
b79480ba | 509 | |
04feced9 VS |
510 | if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK || |
511 | status_mask & ~PIPESTAT_INT_STATUS_MASK, | |
512 | "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", | |
513 | pipe_name(pipe), enable_mask, status_mask)) | |
46c06a30 VS |
514 | return; |
515 | ||
755e9019 ID |
516 | if ((pipestat & enable_mask) == 0) |
517 | return; | |
518 | ||
91d181dd ID |
519 | dev_priv->pipestat_irq_mask[pipe] &= ~status_mask; |
520 | ||
755e9019 | 521 | pipestat &= ~enable_mask; |
46c06a30 VS |
522 | I915_WRITE(reg, pipestat); |
523 | POSTING_READ(reg); | |
7c463586 KP |
524 | } |
525 | ||
10c59c51 ID |
526 | static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask) |
527 | { | |
528 | u32 enable_mask = status_mask << 16; | |
529 | ||
530 | /* | |
724a6905 VS |
531 | * On pipe A we don't support the PSR interrupt yet, |
532 | * on pipe B and C the same bit MBZ. | |
10c59c51 ID |
533 | */ |
534 | if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)) | |
535 | return 0; | |
724a6905 VS |
536 | /* |
537 | * On pipe B and C we don't support the PSR interrupt yet, on pipe | |
538 | * A the same bit is for perf counters which we don't use either. | |
539 | */ | |
540 | if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)) | |
541 | return 0; | |
10c59c51 ID |
542 | |
543 | enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS | | |
544 | SPRITE0_FLIP_DONE_INT_EN_VLV | | |
545 | SPRITE1_FLIP_DONE_INT_EN_VLV); | |
546 | if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV) | |
547 | enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV; | |
548 | if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV) | |
549 | enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV; | |
550 | ||
551 | return enable_mask; | |
552 | } | |
553 | ||
755e9019 ID |
554 | void |
555 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
556 | u32 status_mask) | |
557 | { | |
558 | u32 enable_mask; | |
559 | ||
10c59c51 ID |
560 | if (IS_VALLEYVIEW(dev_priv->dev)) |
561 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
562 | status_mask); | |
563 | else | |
564 | enable_mask = status_mask << 16; | |
755e9019 ID |
565 | __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
566 | } | |
567 | ||
568 | void | |
569 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, | |
570 | u32 status_mask) | |
571 | { | |
572 | u32 enable_mask; | |
573 | ||
10c59c51 ID |
574 | if (IS_VALLEYVIEW(dev_priv->dev)) |
575 | enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev, | |
576 | status_mask); | |
577 | else | |
578 | enable_mask = status_mask << 16; | |
755e9019 ID |
579 | __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask); |
580 | } | |
581 | ||
01c66889 | 582 | /** |
f49e38dd | 583 | * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion |
01c66889 | 584 | */ |
f49e38dd | 585 | static void i915_enable_asle_pipestat(struct drm_device *dev) |
01c66889 | 586 | { |
2d1013dd | 587 | struct drm_i915_private *dev_priv = dev->dev_private; |
1ec14ad3 | 588 | |
f49e38dd JN |
589 | if (!dev_priv->opregion.asle || !IS_MOBILE(dev)) |
590 | return; | |
591 | ||
13321786 | 592 | spin_lock_irq(&dev_priv->irq_lock); |
01c66889 | 593 | |
755e9019 | 594 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); |
f898780b | 595 | if (INTEL_INFO(dev)->gen >= 4) |
3b6c42e8 | 596 | i915_enable_pipestat(dev_priv, PIPE_A, |
755e9019 | 597 | PIPE_LEGACY_BLC_EVENT_STATUS); |
1ec14ad3 | 598 | |
13321786 | 599 | spin_unlock_irq(&dev_priv->irq_lock); |
01c66889 ZY |
600 | } |
601 | ||
f75f3746 VS |
602 | /* |
603 | * This timing diagram depicts the video signal in and | |
604 | * around the vertical blanking period. | |
605 | * | |
606 | * Assumptions about the fictitious mode used in this example: | |
607 | * vblank_start >= 3 | |
608 | * vsync_start = vblank_start + 1 | |
609 | * vsync_end = vblank_start + 2 | |
610 | * vtotal = vblank_start + 3 | |
611 | * | |
612 | * start of vblank: | |
613 | * latch double buffered registers | |
614 | * increment frame counter (ctg+) | |
615 | * generate start of vblank interrupt (gen4+) | |
616 | * | | |
617 | * | frame start: | |
618 | * | generate frame start interrupt (aka. vblank interrupt) (gmch) | |
619 | * | may be shifted forward 1-3 extra lines via PIPECONF | |
620 | * | | | |
621 | * | | start of vsync: | |
622 | * | | generate vsync interrupt | |
623 | * | | | | |
624 | * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx | |
625 | * . \hs/ . \hs/ \hs/ \hs/ . \hs/ | |
626 | * ----va---> <-----------------vb--------------------> <--------va------------- | |
627 | * | | <----vs-----> | | |
628 | * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2) | |
629 | * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+) | |
630 | * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi) | |
631 | * | | | | |
632 | * last visible pixel first visible pixel | |
633 | * | increment frame counter (gen3/4) | |
634 | * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4) | |
635 | * | |
636 | * x = horizontal active | |
637 | * _ = horizontal blanking | |
638 | * hs = horizontal sync | |
639 | * va = vertical active | |
640 | * vb = vertical blanking | |
641 | * vs = vertical sync | |
642 | * vbs = vblank_start (number) | |
643 | * | |
644 | * Summary: | |
645 | * - most events happen at the start of horizontal sync | |
646 | * - frame start happens at the start of horizontal blank, 1-4 lines | |
647 | * (depending on PIPECONF settings) after the start of vblank | |
648 | * - gen3/4 pixel and frame counter are synchronized with the start | |
649 | * of horizontal active on the first line of vertical active | |
650 | */ | |
651 | ||
4cdb83ec VS |
652 | static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe) |
653 | { | |
654 | /* Gen2 doesn't have a hardware frame counter */ | |
655 | return 0; | |
656 | } | |
657 | ||
42f52ef8 KP |
658 | /* Called from drm generic code, passed a 'crtc', which |
659 | * we use as a pipe index | |
660 | */ | |
f71d4af4 | 661 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 | 662 | { |
2d1013dd | 663 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a3e67a4 JB |
664 | unsigned long high_frame; |
665 | unsigned long low_frame; | |
0b2a8e09 | 666 | u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal; |
f3a5c3f6 DV |
667 | struct intel_crtc *intel_crtc = |
668 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); | |
fc467a22 | 669 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
0a3e67a4 | 670 | |
f3a5c3f6 DV |
671 | htotal = mode->crtc_htotal; |
672 | hsync_start = mode->crtc_hsync_start; | |
673 | vbl_start = mode->crtc_vblank_start; | |
674 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
675 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
391f75e2 | 676 | |
0b2a8e09 VS |
677 | /* Convert to pixel count */ |
678 | vbl_start *= htotal; | |
679 | ||
680 | /* Start of vblank event occurs at start of hsync */ | |
681 | vbl_start -= htotal - hsync_start; | |
682 | ||
9db4a9c7 JB |
683 | high_frame = PIPEFRAME(pipe); |
684 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 685 | |
0a3e67a4 JB |
686 | /* |
687 | * High & low register fields aren't synchronized, so make sure | |
688 | * we get a low value that's stable across two reads of the high | |
689 | * register. | |
690 | */ | |
691 | do { | |
5eddb70b | 692 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
391f75e2 | 693 | low = I915_READ(low_frame); |
5eddb70b | 694 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
0a3e67a4 JB |
695 | } while (high1 != high2); |
696 | ||
5eddb70b | 697 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
391f75e2 | 698 | pixel = low & PIPE_PIXEL_MASK; |
5eddb70b | 699 | low >>= PIPE_FRAME_LOW_SHIFT; |
391f75e2 VS |
700 | |
701 | /* | |
702 | * The frame counter increments at beginning of active. | |
703 | * Cook up a vblank counter by also checking the pixel | |
704 | * counter against vblank start. | |
705 | */ | |
edc08d0a | 706 | return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff; |
0a3e67a4 JB |
707 | } |
708 | ||
f71d4af4 | 709 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 | 710 | { |
2d1013dd | 711 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 712 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 | 713 | |
9880b7a5 JB |
714 | return I915_READ(reg); |
715 | } | |
716 | ||
ad3543ed MK |
717 | /* raw reads, only for fast reads of display block, no need for forcewake etc. */ |
718 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) | |
ad3543ed | 719 | |
a225f079 VS |
720 | static int __intel_get_crtc_scanline(struct intel_crtc *crtc) |
721 | { | |
722 | struct drm_device *dev = crtc->base.dev; | |
723 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fc467a22 | 724 | const struct drm_display_mode *mode = &crtc->base.hwmode; |
a225f079 | 725 | enum pipe pipe = crtc->pipe; |
80715b2f | 726 | int position, vtotal; |
a225f079 | 727 | |
80715b2f | 728 | vtotal = mode->crtc_vtotal; |
a225f079 VS |
729 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
730 | vtotal /= 2; | |
731 | ||
732 | if (IS_GEN2(dev)) | |
733 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2; | |
734 | else | |
735 | position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3; | |
736 | ||
737 | /* | |
80715b2f VS |
738 | * See update_scanline_offset() for the details on the |
739 | * scanline_offset adjustment. | |
a225f079 | 740 | */ |
80715b2f | 741 | return (position + crtc->scanline_offset) % vtotal; |
a225f079 VS |
742 | } |
743 | ||
f71d4af4 | 744 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
abca9e45 VS |
745 | unsigned int flags, int *vpos, int *hpos, |
746 | ktime_t *stime, ktime_t *etime) | |
0af7e4df | 747 | { |
c2baf4b7 VS |
748 | struct drm_i915_private *dev_priv = dev->dev_private; |
749 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
750 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fc467a22 | 751 | const struct drm_display_mode *mode = &intel_crtc->base.hwmode; |
3aa18df8 | 752 | int position; |
78e8fc6b | 753 | int vbl_start, vbl_end, hsync_start, htotal, vtotal; |
0af7e4df MK |
754 | bool in_vbl = true; |
755 | int ret = 0; | |
ad3543ed | 756 | unsigned long irqflags; |
0af7e4df | 757 | |
fc467a22 | 758 | if (WARN_ON(!mode->crtc_clock)) { |
0af7e4df | 759 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " |
9db4a9c7 | 760 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
761 | return 0; |
762 | } | |
763 | ||
c2baf4b7 | 764 | htotal = mode->crtc_htotal; |
78e8fc6b | 765 | hsync_start = mode->crtc_hsync_start; |
c2baf4b7 VS |
766 | vtotal = mode->crtc_vtotal; |
767 | vbl_start = mode->crtc_vblank_start; | |
768 | vbl_end = mode->crtc_vblank_end; | |
0af7e4df | 769 | |
d31faf65 VS |
770 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
771 | vbl_start = DIV_ROUND_UP(vbl_start, 2); | |
772 | vbl_end /= 2; | |
773 | vtotal /= 2; | |
774 | } | |
775 | ||
c2baf4b7 VS |
776 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; |
777 | ||
ad3543ed MK |
778 | /* |
779 | * Lock uncore.lock, as we will do multiple timing critical raw | |
780 | * register reads, potentially with preemption disabled, so the | |
781 | * following code must not block on uncore.lock. | |
782 | */ | |
783 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
78e8fc6b | 784 | |
ad3543ed MK |
785 | /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ |
786 | ||
787 | /* Get optional system timestamp before query. */ | |
788 | if (stime) | |
789 | *stime = ktime_get(); | |
790 | ||
7c06b08a | 791 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
0af7e4df MK |
792 | /* No obvious pixelcount register. Only query vertical |
793 | * scanout position from Display scan line register. | |
794 | */ | |
a225f079 | 795 | position = __intel_get_crtc_scanline(intel_crtc); |
0af7e4df MK |
796 | } else { |
797 | /* Have access to pixelcount since start of frame. | |
798 | * We can split this into vertical and horizontal | |
799 | * scanout position. | |
800 | */ | |
ad3543ed | 801 | position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; |
0af7e4df | 802 | |
3aa18df8 VS |
803 | /* convert to pixel counts */ |
804 | vbl_start *= htotal; | |
805 | vbl_end *= htotal; | |
806 | vtotal *= htotal; | |
78e8fc6b | 807 | |
7e78f1cb VS |
808 | /* |
809 | * In interlaced modes, the pixel counter counts all pixels, | |
810 | * so one field will have htotal more pixels. In order to avoid | |
811 | * the reported position from jumping backwards when the pixel | |
812 | * counter is beyond the length of the shorter field, just | |
813 | * clamp the position the length of the shorter field. This | |
814 | * matches how the scanline counter based position works since | |
815 | * the scanline counter doesn't count the two half lines. | |
816 | */ | |
817 | if (position >= vtotal) | |
818 | position = vtotal - 1; | |
819 | ||
78e8fc6b VS |
820 | /* |
821 | * Start of vblank interrupt is triggered at start of hsync, | |
822 | * just prior to the first active line of vblank. However we | |
823 | * consider lines to start at the leading edge of horizontal | |
824 | * active. So, should we get here before we've crossed into | |
825 | * the horizontal active of the first line in vblank, we would | |
826 | * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that, | |
827 | * always add htotal-hsync_start to the current pixel position. | |
828 | */ | |
829 | position = (position + htotal - hsync_start) % vtotal; | |
0af7e4df MK |
830 | } |
831 | ||
ad3543ed MK |
832 | /* Get optional system timestamp after query. */ |
833 | if (etime) | |
834 | *etime = ktime_get(); | |
835 | ||
836 | /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ | |
837 | ||
838 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
839 | ||
3aa18df8 VS |
840 | in_vbl = position >= vbl_start && position < vbl_end; |
841 | ||
842 | /* | |
843 | * While in vblank, position will be negative | |
844 | * counting up towards 0 at vbl_end. And outside | |
845 | * vblank, position will be positive counting | |
846 | * up since vbl_end. | |
847 | */ | |
848 | if (position >= vbl_start) | |
849 | position -= vbl_end; | |
850 | else | |
851 | position += vtotal - vbl_end; | |
0af7e4df | 852 | |
7c06b08a | 853 | if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
3aa18df8 VS |
854 | *vpos = position; |
855 | *hpos = 0; | |
856 | } else { | |
857 | *vpos = position / htotal; | |
858 | *hpos = position - (*vpos * htotal); | |
859 | } | |
0af7e4df | 860 | |
0af7e4df MK |
861 | /* In vblank? */ |
862 | if (in_vbl) | |
3d3cbd84 | 863 | ret |= DRM_SCANOUTPOS_IN_VBLANK; |
0af7e4df MK |
864 | |
865 | return ret; | |
866 | } | |
867 | ||
a225f079 VS |
868 | int intel_get_crtc_scanline(struct intel_crtc *crtc) |
869 | { | |
870 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
871 | unsigned long irqflags; | |
872 | int position; | |
873 | ||
874 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
875 | position = __intel_get_crtc_scanline(crtc); | |
876 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
877 | ||
878 | return position; | |
879 | } | |
880 | ||
f71d4af4 | 881 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
882 | int *max_error, |
883 | struct timeval *vblank_time, | |
884 | unsigned flags) | |
885 | { | |
4041b853 | 886 | struct drm_crtc *crtc; |
0af7e4df | 887 | |
7eb552ae | 888 | if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) { |
4041b853 | 889 | DRM_ERROR("Invalid crtc %d\n", pipe); |
0af7e4df MK |
890 | return -EINVAL; |
891 | } | |
892 | ||
893 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
894 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
895 | if (crtc == NULL) { | |
896 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
897 | return -EINVAL; | |
898 | } | |
899 | ||
fc467a22 | 900 | if (!crtc->hwmode.crtc_clock) { |
4041b853 CW |
901 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); |
902 | return -EBUSY; | |
903 | } | |
0af7e4df MK |
904 | |
905 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
906 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
907 | vblank_time, flags, | |
7da903ef | 908 | crtc, |
fc467a22 | 909 | &crtc->hwmode); |
0af7e4df MK |
910 | } |
911 | ||
d0ecd7e2 | 912 | static void ironlake_rps_change_irq_handler(struct drm_device *dev) |
f97108d1 | 913 | { |
2d1013dd | 914 | struct drm_i915_private *dev_priv = dev->dev_private; |
b5b72e89 | 915 | u32 busy_up, busy_down, max_avg, min_avg; |
9270388e | 916 | u8 new_delay; |
9270388e | 917 | |
d0ecd7e2 | 918 | spin_lock(&mchdev_lock); |
f97108d1 | 919 | |
73edd18f DV |
920 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
921 | ||
20e4d407 | 922 | new_delay = dev_priv->ips.cur_delay; |
9270388e | 923 | |
7648fa99 | 924 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
925 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
926 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
927 | max_avg = I915_READ(RCBMAXAVG); |
928 | min_avg = I915_READ(RCBMINAVG); | |
929 | ||
930 | /* Handle RCS change request from hw */ | |
b5b72e89 | 931 | if (busy_up > max_avg) { |
20e4d407 DV |
932 | if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay) |
933 | new_delay = dev_priv->ips.cur_delay - 1; | |
934 | if (new_delay < dev_priv->ips.max_delay) | |
935 | new_delay = dev_priv->ips.max_delay; | |
b5b72e89 | 936 | } else if (busy_down < min_avg) { |
20e4d407 DV |
937 | if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay) |
938 | new_delay = dev_priv->ips.cur_delay + 1; | |
939 | if (new_delay > dev_priv->ips.min_delay) | |
940 | new_delay = dev_priv->ips.min_delay; | |
f97108d1 JB |
941 | } |
942 | ||
7648fa99 | 943 | if (ironlake_set_drps(dev, new_delay)) |
20e4d407 | 944 | dev_priv->ips.cur_delay = new_delay; |
f97108d1 | 945 | |
d0ecd7e2 | 946 | spin_unlock(&mchdev_lock); |
9270388e | 947 | |
f97108d1 JB |
948 | return; |
949 | } | |
950 | ||
74cdb337 | 951 | static void notify_ring(struct intel_engine_cs *ring) |
549f7365 | 952 | { |
93b0a4e0 | 953 | if (!intel_ring_initialized(ring)) |
475553de CW |
954 | return; |
955 | ||
bcfcc8ba | 956 | trace_i915_gem_request_notify(ring); |
9862e600 | 957 | |
549f7365 | 958 | wake_up_all(&ring->irq_queue); |
549f7365 CW |
959 | } |
960 | ||
43cf3bf0 CW |
961 | static void vlv_c0_read(struct drm_i915_private *dev_priv, |
962 | struct intel_rps_ei *ei) | |
31685c25 | 963 | { |
43cf3bf0 CW |
964 | ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); |
965 | ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT); | |
966 | ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT); | |
967 | } | |
31685c25 | 968 | |
43cf3bf0 CW |
969 | static bool vlv_c0_above(struct drm_i915_private *dev_priv, |
970 | const struct intel_rps_ei *old, | |
971 | const struct intel_rps_ei *now, | |
972 | int threshold) | |
973 | { | |
974 | u64 time, c0; | |
31685c25 | 975 | |
43cf3bf0 CW |
976 | if (old->cz_clock == 0) |
977 | return false; | |
31685c25 | 978 | |
43cf3bf0 CW |
979 | time = now->cz_clock - old->cz_clock; |
980 | time *= threshold * dev_priv->mem_freq; | |
31685c25 | 981 | |
43cf3bf0 CW |
982 | /* Workload can be split between render + media, e.g. SwapBuffers |
983 | * being blitted in X after being rendered in mesa. To account for | |
984 | * this we need to combine both engines into our activity counter. | |
31685c25 | 985 | */ |
43cf3bf0 CW |
986 | c0 = now->render_c0 - old->render_c0; |
987 | c0 += now->media_c0 - old->media_c0; | |
988 | c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000; | |
31685c25 | 989 | |
43cf3bf0 | 990 | return c0 >= time; |
31685c25 D |
991 | } |
992 | ||
43cf3bf0 | 993 | void gen6_rps_reset_ei(struct drm_i915_private *dev_priv) |
31685c25 | 994 | { |
43cf3bf0 CW |
995 | vlv_c0_read(dev_priv, &dev_priv->rps.down_ei); |
996 | dev_priv->rps.up_ei = dev_priv->rps.down_ei; | |
43cf3bf0 | 997 | } |
31685c25 | 998 | |
43cf3bf0 CW |
999 | static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) |
1000 | { | |
1001 | struct intel_rps_ei now; | |
1002 | u32 events = 0; | |
31685c25 | 1003 | |
6f4b12f8 | 1004 | if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0) |
43cf3bf0 | 1005 | return 0; |
31685c25 | 1006 | |
43cf3bf0 CW |
1007 | vlv_c0_read(dev_priv, &now); |
1008 | if (now.cz_clock == 0) | |
1009 | return 0; | |
31685c25 | 1010 | |
43cf3bf0 CW |
1011 | if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { |
1012 | if (!vlv_c0_above(dev_priv, | |
1013 | &dev_priv->rps.down_ei, &now, | |
8fb55197 | 1014 | dev_priv->rps.down_threshold)) |
43cf3bf0 CW |
1015 | events |= GEN6_PM_RP_DOWN_THRESHOLD; |
1016 | dev_priv->rps.down_ei = now; | |
1017 | } | |
31685c25 | 1018 | |
43cf3bf0 CW |
1019 | if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { |
1020 | if (vlv_c0_above(dev_priv, | |
1021 | &dev_priv->rps.up_ei, &now, | |
8fb55197 | 1022 | dev_priv->rps.up_threshold)) |
43cf3bf0 CW |
1023 | events |= GEN6_PM_RP_UP_THRESHOLD; |
1024 | dev_priv->rps.up_ei = now; | |
31685c25 D |
1025 | } |
1026 | ||
43cf3bf0 | 1027 | return events; |
31685c25 D |
1028 | } |
1029 | ||
f5a4c67d CW |
1030 | static bool any_waiters(struct drm_i915_private *dev_priv) |
1031 | { | |
1032 | struct intel_engine_cs *ring; | |
1033 | int i; | |
1034 | ||
1035 | for_each_ring(ring, dev_priv, i) | |
1036 | if (ring->irq_refcount) | |
1037 | return true; | |
1038 | ||
1039 | return false; | |
1040 | } | |
1041 | ||
4912d041 | 1042 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 1043 | { |
2d1013dd JN |
1044 | struct drm_i915_private *dev_priv = |
1045 | container_of(work, struct drm_i915_private, rps.work); | |
8d3afd7d CW |
1046 | bool client_boost; |
1047 | int new_delay, adj, min, max; | |
edbfdb45 | 1048 | u32 pm_iir; |
4912d041 | 1049 | |
59cdb63d | 1050 | spin_lock_irq(&dev_priv->irq_lock); |
d4d70aa5 ID |
1051 | /* Speed up work cancelation during disabling rps interrupts. */ |
1052 | if (!dev_priv->rps.interrupts_enabled) { | |
1053 | spin_unlock_irq(&dev_priv->irq_lock); | |
1054 | return; | |
1055 | } | |
c6a828d3 DV |
1056 | pm_iir = dev_priv->rps.pm_iir; |
1057 | dev_priv->rps.pm_iir = 0; | |
a72fbc3a ID |
1058 | /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */ |
1059 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); | |
8d3afd7d CW |
1060 | client_boost = dev_priv->rps.client_boost; |
1061 | dev_priv->rps.client_boost = false; | |
59cdb63d | 1062 | spin_unlock_irq(&dev_priv->irq_lock); |
3b8d8d91 | 1063 | |
60611c13 | 1064 | /* Make sure we didn't queue anything we're not going to process. */ |
a6706b45 | 1065 | WARN_ON(pm_iir & ~dev_priv->pm_rps_events); |
60611c13 | 1066 | |
8d3afd7d | 1067 | if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost) |
3b8d8d91 JB |
1068 | return; |
1069 | ||
4fc688ce | 1070 | mutex_lock(&dev_priv->rps.hw_lock); |
7b9e0ae6 | 1071 | |
43cf3bf0 CW |
1072 | pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir); |
1073 | ||
dd75fdc8 | 1074 | adj = dev_priv->rps.last_adj; |
edcf284b | 1075 | new_delay = dev_priv->rps.cur_freq; |
8d3afd7d CW |
1076 | min = dev_priv->rps.min_freq_softlimit; |
1077 | max = dev_priv->rps.max_freq_softlimit; | |
1078 | ||
1079 | if (client_boost) { | |
1080 | new_delay = dev_priv->rps.max_freq_softlimit; | |
1081 | adj = 0; | |
1082 | } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
dd75fdc8 CW |
1083 | if (adj > 0) |
1084 | adj *= 2; | |
edcf284b CW |
1085 | else /* CHV needs even encode values */ |
1086 | adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1; | |
7425034a VS |
1087 | /* |
1088 | * For better performance, jump directly | |
1089 | * to RPe if we're below it. | |
1090 | */ | |
edcf284b | 1091 | if (new_delay < dev_priv->rps.efficient_freq - adj) { |
b39fb297 | 1092 | new_delay = dev_priv->rps.efficient_freq; |
edcf284b CW |
1093 | adj = 0; |
1094 | } | |
f5a4c67d CW |
1095 | } else if (any_waiters(dev_priv)) { |
1096 | adj = 0; | |
dd75fdc8 | 1097 | } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { |
b39fb297 BW |
1098 | if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq) |
1099 | new_delay = dev_priv->rps.efficient_freq; | |
dd75fdc8 | 1100 | else |
b39fb297 | 1101 | new_delay = dev_priv->rps.min_freq_softlimit; |
dd75fdc8 CW |
1102 | adj = 0; |
1103 | } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { | |
1104 | if (adj < 0) | |
1105 | adj *= 2; | |
edcf284b CW |
1106 | else /* CHV needs even encode values */ |
1107 | adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1; | |
dd75fdc8 | 1108 | } else { /* unknown event */ |
edcf284b | 1109 | adj = 0; |
dd75fdc8 | 1110 | } |
3b8d8d91 | 1111 | |
edcf284b CW |
1112 | dev_priv->rps.last_adj = adj; |
1113 | ||
79249636 BW |
1114 | /* sysfs frequency interfaces may have snuck in while servicing the |
1115 | * interrupt | |
1116 | */ | |
edcf284b | 1117 | new_delay += adj; |
8d3afd7d | 1118 | new_delay = clamp_t(int, new_delay, min, max); |
27544369 | 1119 | |
ffe02b40 | 1120 | intel_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 | 1121 | |
4fc688ce | 1122 | mutex_unlock(&dev_priv->rps.hw_lock); |
3b8d8d91 JB |
1123 | } |
1124 | ||
e3689190 BW |
1125 | |
1126 | /** | |
1127 | * ivybridge_parity_work - Workqueue called when a parity error interrupt | |
1128 | * occurred. | |
1129 | * @work: workqueue struct | |
1130 | * | |
1131 | * Doesn't actually do anything except notify userspace. As a consequence of | |
1132 | * this event, userspace should try to remap the bad rows since statistically | |
1133 | * it is likely the same row is more likely to go bad again. | |
1134 | */ | |
1135 | static void ivybridge_parity_work(struct work_struct *work) | |
1136 | { | |
2d1013dd JN |
1137 | struct drm_i915_private *dev_priv = |
1138 | container_of(work, struct drm_i915_private, l3_parity.error_work); | |
e3689190 | 1139 | u32 error_status, row, bank, subbank; |
35a85ac6 | 1140 | char *parity_event[6]; |
e3689190 | 1141 | uint32_t misccpctl; |
35a85ac6 | 1142 | uint8_t slice = 0; |
e3689190 BW |
1143 | |
1144 | /* We must turn off DOP level clock gating to access the L3 registers. | |
1145 | * In order to prevent a get/put style interface, acquire struct mutex | |
1146 | * any time we access those registers. | |
1147 | */ | |
1148 | mutex_lock(&dev_priv->dev->struct_mutex); | |
1149 | ||
35a85ac6 BW |
1150 | /* If we've screwed up tracking, just let the interrupt fire again */ |
1151 | if (WARN_ON(!dev_priv->l3_parity.which_slice)) | |
1152 | goto out; | |
1153 | ||
e3689190 BW |
1154 | misccpctl = I915_READ(GEN7_MISCCPCTL); |
1155 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
1156 | POSTING_READ(GEN7_MISCCPCTL); | |
1157 | ||
35a85ac6 BW |
1158 | while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) { |
1159 | u32 reg; | |
e3689190 | 1160 | |
35a85ac6 BW |
1161 | slice--; |
1162 | if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))) | |
1163 | break; | |
e3689190 | 1164 | |
35a85ac6 | 1165 | dev_priv->l3_parity.which_slice &= ~(1<<slice); |
e3689190 | 1166 | |
35a85ac6 | 1167 | reg = GEN7_L3CDERRST1 + (slice * 0x200); |
e3689190 | 1168 | |
35a85ac6 BW |
1169 | error_status = I915_READ(reg); |
1170 | row = GEN7_PARITY_ERROR_ROW(error_status); | |
1171 | bank = GEN7_PARITY_ERROR_BANK(error_status); | |
1172 | subbank = GEN7_PARITY_ERROR_SUBBANK(error_status); | |
1173 | ||
1174 | I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE); | |
1175 | POSTING_READ(reg); | |
1176 | ||
1177 | parity_event[0] = I915_L3_PARITY_UEVENT "=1"; | |
1178 | parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row); | |
1179 | parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank); | |
1180 | parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank); | |
1181 | parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice); | |
1182 | parity_event[5] = NULL; | |
1183 | ||
5bdebb18 | 1184 | kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj, |
35a85ac6 | 1185 | KOBJ_CHANGE, parity_event); |
e3689190 | 1186 | |
35a85ac6 BW |
1187 | DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n", |
1188 | slice, row, bank, subbank); | |
e3689190 | 1189 | |
35a85ac6 BW |
1190 | kfree(parity_event[4]); |
1191 | kfree(parity_event[3]); | |
1192 | kfree(parity_event[2]); | |
1193 | kfree(parity_event[1]); | |
1194 | } | |
e3689190 | 1195 | |
35a85ac6 | 1196 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); |
e3689190 | 1197 | |
35a85ac6 BW |
1198 | out: |
1199 | WARN_ON(dev_priv->l3_parity.which_slice); | |
4cb21832 | 1200 | spin_lock_irq(&dev_priv->irq_lock); |
480c8033 | 1201 | gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev)); |
4cb21832 | 1202 | spin_unlock_irq(&dev_priv->irq_lock); |
35a85ac6 BW |
1203 | |
1204 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
e3689190 BW |
1205 | } |
1206 | ||
35a85ac6 | 1207 | static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir) |
e3689190 | 1208 | { |
2d1013dd | 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
e3689190 | 1210 | |
040d2baa | 1211 | if (!HAS_L3_DPF(dev)) |
e3689190 BW |
1212 | return; |
1213 | ||
d0ecd7e2 | 1214 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1215 | gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev)); |
d0ecd7e2 | 1216 | spin_unlock(&dev_priv->irq_lock); |
e3689190 | 1217 | |
35a85ac6 BW |
1218 | iir &= GT_PARITY_ERROR(dev); |
1219 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1) | |
1220 | dev_priv->l3_parity.which_slice |= 1 << 1; | |
1221 | ||
1222 | if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT) | |
1223 | dev_priv->l3_parity.which_slice |= 1 << 0; | |
1224 | ||
a4da4fa4 | 1225 | queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work); |
e3689190 BW |
1226 | } |
1227 | ||
f1af8fc1 PZ |
1228 | static void ilk_gt_irq_handler(struct drm_device *dev, |
1229 | struct drm_i915_private *dev_priv, | |
1230 | u32 gt_iir) | |
1231 | { | |
1232 | if (gt_iir & | |
1233 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1234 | notify_ring(&dev_priv->ring[RCS]); |
f1af8fc1 | 1235 | if (gt_iir & ILK_BSD_USER_INTERRUPT) |
74cdb337 | 1236 | notify_ring(&dev_priv->ring[VCS]); |
f1af8fc1 PZ |
1237 | } |
1238 | ||
e7b4c6b1 DV |
1239 | static void snb_gt_irq_handler(struct drm_device *dev, |
1240 | struct drm_i915_private *dev_priv, | |
1241 | u32 gt_iir) | |
1242 | { | |
1243 | ||
cc609d5d BW |
1244 | if (gt_iir & |
1245 | (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)) | |
74cdb337 | 1246 | notify_ring(&dev_priv->ring[RCS]); |
cc609d5d | 1247 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
74cdb337 | 1248 | notify_ring(&dev_priv->ring[VCS]); |
cc609d5d | 1249 | if (gt_iir & GT_BLT_USER_INTERRUPT) |
74cdb337 | 1250 | notify_ring(&dev_priv->ring[BCS]); |
e7b4c6b1 | 1251 | |
cc609d5d BW |
1252 | if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT | |
1253 | GT_BSD_CS_ERROR_INTERRUPT | | |
aaecdf61 DV |
1254 | GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) |
1255 | DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir); | |
e3689190 | 1256 | |
35a85ac6 BW |
1257 | if (gt_iir & GT_PARITY_ERROR(dev)) |
1258 | ivybridge_parity_error_irq_handler(dev, gt_iir); | |
e7b4c6b1 DV |
1259 | } |
1260 | ||
74cdb337 | 1261 | static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv, |
abd58f01 BW |
1262 | u32 master_ctl) |
1263 | { | |
abd58f01 BW |
1264 | irqreturn_t ret = IRQ_NONE; |
1265 | ||
1266 | if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) { | |
74cdb337 | 1267 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(0)); |
abd58f01 | 1268 | if (tmp) { |
cb0d205e | 1269 | I915_WRITE_FW(GEN8_GT_IIR(0), tmp); |
abd58f01 | 1270 | ret = IRQ_HANDLED; |
e981e7b1 | 1271 | |
74cdb337 CW |
1272 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) |
1273 | intel_lrc_irq_handler(&dev_priv->ring[RCS]); | |
1274 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT)) | |
1275 | notify_ring(&dev_priv->ring[RCS]); | |
1276 | ||
1277 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1278 | intel_lrc_irq_handler(&dev_priv->ring[BCS]); | |
1279 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT)) | |
1280 | notify_ring(&dev_priv->ring[BCS]); | |
abd58f01 BW |
1281 | } else |
1282 | DRM_ERROR("The master control interrupt lied (GT0)!\n"); | |
1283 | } | |
1284 | ||
85f9b5f9 | 1285 | if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) { |
74cdb337 | 1286 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(1)); |
abd58f01 | 1287 | if (tmp) { |
cb0d205e | 1288 | I915_WRITE_FW(GEN8_GT_IIR(1), tmp); |
abd58f01 | 1289 | ret = IRQ_HANDLED; |
e981e7b1 | 1290 | |
74cdb337 CW |
1291 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) |
1292 | intel_lrc_irq_handler(&dev_priv->ring[VCS]); | |
1293 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT)) | |
1294 | notify_ring(&dev_priv->ring[VCS]); | |
abd58f01 | 1295 | |
74cdb337 CW |
1296 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) |
1297 | intel_lrc_irq_handler(&dev_priv->ring[VCS2]); | |
1298 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT)) | |
1299 | notify_ring(&dev_priv->ring[VCS2]); | |
0961021a | 1300 | } else |
abd58f01 | 1301 | DRM_ERROR("The master control interrupt lied (GT1)!\n"); |
0961021a BW |
1302 | } |
1303 | ||
abd58f01 | 1304 | if (master_ctl & GEN8_GT_VECS_IRQ) { |
74cdb337 | 1305 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(3)); |
abd58f01 | 1306 | if (tmp) { |
74cdb337 | 1307 | I915_WRITE_FW(GEN8_GT_IIR(3), tmp); |
abd58f01 | 1308 | ret = IRQ_HANDLED; |
e981e7b1 | 1309 | |
74cdb337 CW |
1310 | if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) |
1311 | intel_lrc_irq_handler(&dev_priv->ring[VECS]); | |
1312 | if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT)) | |
1313 | notify_ring(&dev_priv->ring[VECS]); | |
abd58f01 BW |
1314 | } else |
1315 | DRM_ERROR("The master control interrupt lied (GT3)!\n"); | |
1316 | } | |
1317 | ||
0961021a | 1318 | if (master_ctl & GEN8_GT_PM_IRQ) { |
74cdb337 | 1319 | u32 tmp = I915_READ_FW(GEN8_GT_IIR(2)); |
0961021a | 1320 | if (tmp & dev_priv->pm_rps_events) { |
cb0d205e CW |
1321 | I915_WRITE_FW(GEN8_GT_IIR(2), |
1322 | tmp & dev_priv->pm_rps_events); | |
38cc46d7 | 1323 | ret = IRQ_HANDLED; |
c9a9a268 | 1324 | gen6_rps_irq_handler(dev_priv, tmp); |
0961021a BW |
1325 | } else |
1326 | DRM_ERROR("The master control interrupt lied (PM)!\n"); | |
1327 | } | |
1328 | ||
abd58f01 BW |
1329 | return ret; |
1330 | } | |
1331 | ||
63c88d22 ID |
1332 | static bool bxt_port_hotplug_long_detect(enum port port, u32 val) |
1333 | { | |
1334 | switch (port) { | |
1335 | case PORT_A: | |
195baa06 | 1336 | return val & PORTA_HOTPLUG_LONG_DETECT; |
63c88d22 ID |
1337 | case PORT_B: |
1338 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1339 | case PORT_C: | |
1340 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
63c88d22 ID |
1341 | default: |
1342 | return false; | |
1343 | } | |
1344 | } | |
1345 | ||
6dbf30ce VS |
1346 | static bool spt_port_hotplug2_long_detect(enum port port, u32 val) |
1347 | { | |
1348 | switch (port) { | |
1349 | case PORT_E: | |
1350 | return val & PORTE_HOTPLUG_LONG_DETECT; | |
1351 | default: | |
1352 | return false; | |
1353 | } | |
1354 | } | |
1355 | ||
74c0b395 VS |
1356 | static bool spt_port_hotplug_long_detect(enum port port, u32 val) |
1357 | { | |
1358 | switch (port) { | |
1359 | case PORT_A: | |
1360 | return val & PORTA_HOTPLUG_LONG_DETECT; | |
1361 | case PORT_B: | |
1362 | return val & PORTB_HOTPLUG_LONG_DETECT; | |
1363 | case PORT_C: | |
1364 | return val & PORTC_HOTPLUG_LONG_DETECT; | |
1365 | case PORT_D: | |
1366 | return val & PORTD_HOTPLUG_LONG_DETECT; | |
1367 | default: | |
1368 | return false; | |
1369 | } | |
1370 | } | |
1371 | ||
e4ce95aa VS |
1372 | static bool ilk_port_hotplug_long_detect(enum port port, u32 val) |
1373 | { | |
1374 | switch (port) { | |
1375 | case PORT_A: | |
1376 | return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT; | |
1377 | default: | |
1378 | return false; | |
1379 | } | |
1380 | } | |
1381 | ||
676574df | 1382 | static bool pch_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1383 | { |
1384 | switch (port) { | |
13cf5504 | 1385 | case PORT_B: |
676574df | 1386 | return val & PORTB_HOTPLUG_LONG_DETECT; |
13cf5504 | 1387 | case PORT_C: |
676574df | 1388 | return val & PORTC_HOTPLUG_LONG_DETECT; |
13cf5504 | 1389 | case PORT_D: |
676574df JN |
1390 | return val & PORTD_HOTPLUG_LONG_DETECT; |
1391 | default: | |
1392 | return false; | |
13cf5504 DA |
1393 | } |
1394 | } | |
1395 | ||
676574df | 1396 | static bool i9xx_port_hotplug_long_detect(enum port port, u32 val) |
13cf5504 DA |
1397 | { |
1398 | switch (port) { | |
13cf5504 | 1399 | case PORT_B: |
676574df | 1400 | return val & PORTB_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1401 | case PORT_C: |
676574df | 1402 | return val & PORTC_HOTPLUG_INT_LONG_PULSE; |
13cf5504 | 1403 | case PORT_D: |
676574df JN |
1404 | return val & PORTD_HOTPLUG_INT_LONG_PULSE; |
1405 | default: | |
1406 | return false; | |
13cf5504 DA |
1407 | } |
1408 | } | |
1409 | ||
42db67d6 VS |
1410 | /* |
1411 | * Get a bit mask of pins that have triggered, and which ones may be long. | |
1412 | * This can be called multiple times with the same masks to accumulate | |
1413 | * hotplug detection results from several registers. | |
1414 | * | |
1415 | * Note that the caller is expected to zero out the masks initially. | |
1416 | */ | |
fd63e2a9 | 1417 | static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask, |
8c841e57 | 1418 | u32 hotplug_trigger, u32 dig_hotplug_reg, |
fd63e2a9 ID |
1419 | const u32 hpd[HPD_NUM_PINS], |
1420 | bool long_pulse_detect(enum port port, u32 val)) | |
676574df | 1421 | { |
8c841e57 | 1422 | enum port port; |
676574df JN |
1423 | int i; |
1424 | ||
676574df | 1425 | for_each_hpd_pin(i) { |
8c841e57 JN |
1426 | if ((hpd[i] & hotplug_trigger) == 0) |
1427 | continue; | |
676574df | 1428 | |
8c841e57 JN |
1429 | *pin_mask |= BIT(i); |
1430 | ||
cc24fcdc ID |
1431 | if (!intel_hpd_pin_to_port(i, &port)) |
1432 | continue; | |
1433 | ||
fd63e2a9 | 1434 | if (long_pulse_detect(port, dig_hotplug_reg)) |
8c841e57 | 1435 | *long_mask |= BIT(i); |
676574df JN |
1436 | } |
1437 | ||
1438 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n", | |
1439 | hotplug_trigger, dig_hotplug_reg, *pin_mask); | |
1440 | ||
1441 | } | |
1442 | ||
515ac2bb DV |
1443 | static void gmbus_irq_handler(struct drm_device *dev) |
1444 | { | |
2d1013dd | 1445 | struct drm_i915_private *dev_priv = dev->dev_private; |
28c70f16 | 1446 | |
28c70f16 | 1447 | wake_up_all(&dev_priv->gmbus_wait_queue); |
515ac2bb DV |
1448 | } |
1449 | ||
ce99c256 DV |
1450 | static void dp_aux_irq_handler(struct drm_device *dev) |
1451 | { | |
2d1013dd | 1452 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ee32fea | 1453 | |
9ee32fea | 1454 | wake_up_all(&dev_priv->gmbus_wait_queue); |
ce99c256 DV |
1455 | } |
1456 | ||
8bf1e9f1 | 1457 | #if defined(CONFIG_DEBUG_FS) |
277de95e DV |
1458 | static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, |
1459 | uint32_t crc0, uint32_t crc1, | |
1460 | uint32_t crc2, uint32_t crc3, | |
1461 | uint32_t crc4) | |
8bf1e9f1 SH |
1462 | { |
1463 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1464 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
1465 | struct intel_pipe_crc_entry *entry; | |
ac2300d4 | 1466 | int head, tail; |
b2c88f5b | 1467 | |
d538bbdf DL |
1468 | spin_lock(&pipe_crc->lock); |
1469 | ||
0c912c79 | 1470 | if (!pipe_crc->entries) { |
d538bbdf | 1471 | spin_unlock(&pipe_crc->lock); |
34273620 | 1472 | DRM_DEBUG_KMS("spurious interrupt\n"); |
0c912c79 DL |
1473 | return; |
1474 | } | |
1475 | ||
d538bbdf DL |
1476 | head = pipe_crc->head; |
1477 | tail = pipe_crc->tail; | |
b2c88f5b DL |
1478 | |
1479 | if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) { | |
d538bbdf | 1480 | spin_unlock(&pipe_crc->lock); |
b2c88f5b DL |
1481 | DRM_ERROR("CRC buffer overflowing\n"); |
1482 | return; | |
1483 | } | |
1484 | ||
1485 | entry = &pipe_crc->entries[head]; | |
8bf1e9f1 | 1486 | |
8bc5e955 | 1487 | entry->frame = dev->driver->get_vblank_counter(dev, pipe); |
eba94eb9 DV |
1488 | entry->crc[0] = crc0; |
1489 | entry->crc[1] = crc1; | |
1490 | entry->crc[2] = crc2; | |
1491 | entry->crc[3] = crc3; | |
1492 | entry->crc[4] = crc4; | |
b2c88f5b DL |
1493 | |
1494 | head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
d538bbdf DL |
1495 | pipe_crc->head = head; |
1496 | ||
1497 | spin_unlock(&pipe_crc->lock); | |
07144428 DL |
1498 | |
1499 | wake_up_interruptible(&pipe_crc->wq); | |
8bf1e9f1 | 1500 | } |
277de95e DV |
1501 | #else |
1502 | static inline void | |
1503 | display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe, | |
1504 | uint32_t crc0, uint32_t crc1, | |
1505 | uint32_t crc2, uint32_t crc3, | |
1506 | uint32_t crc4) {} | |
1507 | #endif | |
1508 | ||
eba94eb9 | 1509 | |
277de95e | 1510 | static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5a69b89f DV |
1511 | { |
1512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1513 | ||
277de95e DV |
1514 | display_pipe_crc_irq_handler(dev, pipe, |
1515 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1516 | 0, 0, 0, 0); | |
5a69b89f DV |
1517 | } |
1518 | ||
277de95e | 1519 | static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
eba94eb9 DV |
1520 | { |
1521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1522 | ||
277de95e DV |
1523 | display_pipe_crc_irq_handler(dev, pipe, |
1524 | I915_READ(PIPE_CRC_RES_1_IVB(pipe)), | |
1525 | I915_READ(PIPE_CRC_RES_2_IVB(pipe)), | |
1526 | I915_READ(PIPE_CRC_RES_3_IVB(pipe)), | |
1527 | I915_READ(PIPE_CRC_RES_4_IVB(pipe)), | |
1528 | I915_READ(PIPE_CRC_RES_5_IVB(pipe))); | |
eba94eb9 | 1529 | } |
5b3a856b | 1530 | |
277de95e | 1531 | static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe) |
5b3a856b DV |
1532 | { |
1533 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0b5c5ed0 DV |
1534 | uint32_t res1, res2; |
1535 | ||
1536 | if (INTEL_INFO(dev)->gen >= 3) | |
1537 | res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe)); | |
1538 | else | |
1539 | res1 = 0; | |
1540 | ||
1541 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
1542 | res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe)); | |
1543 | else | |
1544 | res2 = 0; | |
5b3a856b | 1545 | |
277de95e DV |
1546 | display_pipe_crc_irq_handler(dev, pipe, |
1547 | I915_READ(PIPE_CRC_RES_RED(pipe)), | |
1548 | I915_READ(PIPE_CRC_RES_GREEN(pipe)), | |
1549 | I915_READ(PIPE_CRC_RES_BLUE(pipe)), | |
1550 | res1, res2); | |
5b3a856b | 1551 | } |
8bf1e9f1 | 1552 | |
1403c0d4 PZ |
1553 | /* The RPS events need forcewake, so we add them to a work queue and mask their |
1554 | * IMR bits until the work is done. Other interrupts can be processed without | |
1555 | * the work queue. */ | |
1556 | static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) | |
baf02a1f | 1557 | { |
a6706b45 | 1558 | if (pm_iir & dev_priv->pm_rps_events) { |
59cdb63d | 1559 | spin_lock(&dev_priv->irq_lock); |
480c8033 | 1560 | gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events); |
d4d70aa5 ID |
1561 | if (dev_priv->rps.interrupts_enabled) { |
1562 | dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events; | |
1563 | queue_work(dev_priv->wq, &dev_priv->rps.work); | |
1564 | } | |
59cdb63d | 1565 | spin_unlock(&dev_priv->irq_lock); |
baf02a1f | 1566 | } |
baf02a1f | 1567 | |
c9a9a268 ID |
1568 | if (INTEL_INFO(dev_priv)->gen >= 8) |
1569 | return; | |
1570 | ||
1403c0d4 PZ |
1571 | if (HAS_VEBOX(dev_priv->dev)) { |
1572 | if (pm_iir & PM_VEBOX_USER_INTERRUPT) | |
74cdb337 | 1573 | notify_ring(&dev_priv->ring[VECS]); |
12638c57 | 1574 | |
aaecdf61 DV |
1575 | if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) |
1576 | DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir); | |
12638c57 | 1577 | } |
baf02a1f BW |
1578 | } |
1579 | ||
8d7849db VS |
1580 | static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe) |
1581 | { | |
8d7849db VS |
1582 | if (!drm_handle_vblank(dev, pipe)) |
1583 | return false; | |
1584 | ||
8d7849db VS |
1585 | return true; |
1586 | } | |
1587 | ||
c1874ed7 ID |
1588 | static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir) |
1589 | { | |
1590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
91d181dd | 1591 | u32 pipe_stats[I915_MAX_PIPES] = { }; |
c1874ed7 ID |
1592 | int pipe; |
1593 | ||
58ead0d7 | 1594 | spin_lock(&dev_priv->irq_lock); |
055e393f | 1595 | for_each_pipe(dev_priv, pipe) { |
91d181dd | 1596 | int reg; |
bbb5eebf | 1597 | u32 mask, iir_bit = 0; |
91d181dd | 1598 | |
bbb5eebf DV |
1599 | /* |
1600 | * PIPESTAT bits get signalled even when the interrupt is | |
1601 | * disabled with the mask bits, and some of the status bits do | |
1602 | * not generate interrupts at all (like the underrun bit). Hence | |
1603 | * we need to be careful that we only handle what we want to | |
1604 | * handle. | |
1605 | */ | |
0f239f4c DV |
1606 | |
1607 | /* fifo underruns are filterered in the underrun handler. */ | |
1608 | mask = PIPE_FIFO_UNDERRUN_STATUS; | |
bbb5eebf DV |
1609 | |
1610 | switch (pipe) { | |
1611 | case PIPE_A: | |
1612 | iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT; | |
1613 | break; | |
1614 | case PIPE_B: | |
1615 | iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
1616 | break; | |
3278f67f VS |
1617 | case PIPE_C: |
1618 | iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
1619 | break; | |
bbb5eebf DV |
1620 | } |
1621 | if (iir & iir_bit) | |
1622 | mask |= dev_priv->pipestat_irq_mask[pipe]; | |
1623 | ||
1624 | if (!mask) | |
91d181dd ID |
1625 | continue; |
1626 | ||
1627 | reg = PIPESTAT(pipe); | |
bbb5eebf DV |
1628 | mask |= PIPESTAT_INT_ENABLE_MASK; |
1629 | pipe_stats[pipe] = I915_READ(reg) & mask; | |
c1874ed7 ID |
1630 | |
1631 | /* | |
1632 | * Clear the PIPE*STAT regs before the IIR | |
1633 | */ | |
91d181dd ID |
1634 | if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | |
1635 | PIPESTAT_INT_STATUS_MASK)) | |
c1874ed7 ID |
1636 | I915_WRITE(reg, pipe_stats[pipe]); |
1637 | } | |
58ead0d7 | 1638 | spin_unlock(&dev_priv->irq_lock); |
c1874ed7 | 1639 | |
055e393f | 1640 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
1641 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
1642 | intel_pipe_handle_vblank(dev, pipe)) | |
1643 | intel_check_page_flip(dev, pipe); | |
c1874ed7 | 1644 | |
579a9b0e | 1645 | if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) { |
c1874ed7 ID |
1646 | intel_prepare_page_flip(dev, pipe); |
1647 | intel_finish_page_flip(dev, pipe); | |
1648 | } | |
1649 | ||
1650 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
1651 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
1652 | ||
1f7247c0 DV |
1653 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
1654 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
c1874ed7 ID |
1655 | } |
1656 | ||
1657 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) | |
1658 | gmbus_irq_handler(dev); | |
1659 | } | |
1660 | ||
16c6c56b VS |
1661 | static void i9xx_hpd_irq_handler(struct drm_device *dev) |
1662 | { | |
1663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1664 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
42db67d6 | 1665 | u32 pin_mask = 0, long_mask = 0; |
16c6c56b | 1666 | |
0d2e4297 JN |
1667 | if (!hotplug_status) |
1668 | return; | |
16c6c56b | 1669 | |
0d2e4297 JN |
1670 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); |
1671 | /* | |
1672 | * Make sure hotplug status is cleared before we clear IIR, or else we | |
1673 | * may miss hotplug events. | |
1674 | */ | |
1675 | POSTING_READ(PORT_HOTPLUG_STAT); | |
16c6c56b | 1676 | |
0d2e4297 JN |
1677 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
1678 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X; | |
16c6c56b | 1679 | |
58f2cf24 VS |
1680 | if (hotplug_trigger) { |
1681 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1682 | hotplug_trigger, hpd_status_g4x, | |
1683 | i9xx_port_hotplug_long_detect); | |
1684 | ||
1685 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1686 | } | |
369712e8 JN |
1687 | |
1688 | if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X) | |
1689 | dp_aux_irq_handler(dev); | |
0d2e4297 JN |
1690 | } else { |
1691 | u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915; | |
16c6c56b | 1692 | |
58f2cf24 VS |
1693 | if (hotplug_trigger) { |
1694 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1695 | hotplug_trigger, hpd_status_g4x, | |
1696 | i9xx_port_hotplug_long_detect); | |
1697 | ||
1698 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1699 | } | |
3ff60f89 | 1700 | } |
16c6c56b VS |
1701 | } |
1702 | ||
ff1f525e | 1703 | static irqreturn_t valleyview_irq_handler(int irq, void *arg) |
7e231dbe | 1704 | { |
45a83f84 | 1705 | struct drm_device *dev = arg; |
2d1013dd | 1706 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
1707 | u32 iir, gt_iir, pm_iir; |
1708 | irqreturn_t ret = IRQ_NONE; | |
7e231dbe | 1709 | |
2dd2a883 ID |
1710 | if (!intel_irqs_enabled(dev_priv)) |
1711 | return IRQ_NONE; | |
1712 | ||
7e231dbe | 1713 | while (true) { |
3ff60f89 OM |
1714 | /* Find, clear, then process each source of interrupt */ |
1715 | ||
7e231dbe | 1716 | gt_iir = I915_READ(GTIIR); |
3ff60f89 OM |
1717 | if (gt_iir) |
1718 | I915_WRITE(GTIIR, gt_iir); | |
1719 | ||
7e231dbe | 1720 | pm_iir = I915_READ(GEN6_PMIIR); |
3ff60f89 OM |
1721 | if (pm_iir) |
1722 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
1723 | ||
1724 | iir = I915_READ(VLV_IIR); | |
1725 | if (iir) { | |
1726 | /* Consume port before clearing IIR or we'll miss events */ | |
1727 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1728 | i9xx_hpd_irq_handler(dev); | |
1729 | I915_WRITE(VLV_IIR, iir); | |
1730 | } | |
7e231dbe JB |
1731 | |
1732 | if (gt_iir == 0 && pm_iir == 0 && iir == 0) | |
1733 | goto out; | |
1734 | ||
1735 | ret = IRQ_HANDLED; | |
1736 | ||
3ff60f89 OM |
1737 | if (gt_iir) |
1738 | snb_gt_irq_handler(dev, dev_priv, gt_iir); | |
60611c13 | 1739 | if (pm_iir) |
d0ecd7e2 | 1740 | gen6_rps_irq_handler(dev_priv, pm_iir); |
3ff60f89 OM |
1741 | /* Call regardless, as some status bits might not be |
1742 | * signalled in iir */ | |
1743 | valleyview_pipestat_irq_handler(dev, iir); | |
7e231dbe JB |
1744 | } |
1745 | ||
1746 | out: | |
1747 | return ret; | |
1748 | } | |
1749 | ||
43f328d7 VS |
1750 | static irqreturn_t cherryview_irq_handler(int irq, void *arg) |
1751 | { | |
45a83f84 | 1752 | struct drm_device *dev = arg; |
43f328d7 VS |
1753 | struct drm_i915_private *dev_priv = dev->dev_private; |
1754 | u32 master_ctl, iir; | |
1755 | irqreturn_t ret = IRQ_NONE; | |
43f328d7 | 1756 | |
2dd2a883 ID |
1757 | if (!intel_irqs_enabled(dev_priv)) |
1758 | return IRQ_NONE; | |
1759 | ||
8e5fd599 VS |
1760 | for (;;) { |
1761 | master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; | |
1762 | iir = I915_READ(VLV_IIR); | |
43f328d7 | 1763 | |
8e5fd599 VS |
1764 | if (master_ctl == 0 && iir == 0) |
1765 | break; | |
43f328d7 | 1766 | |
27b6c122 OM |
1767 | ret = IRQ_HANDLED; |
1768 | ||
8e5fd599 | 1769 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
43f328d7 | 1770 | |
27b6c122 | 1771 | /* Find, clear, then process each source of interrupt */ |
43f328d7 | 1772 | |
27b6c122 OM |
1773 | if (iir) { |
1774 | /* Consume port before clearing IIR or we'll miss events */ | |
1775 | if (iir & I915_DISPLAY_PORT_INTERRUPT) | |
1776 | i9xx_hpd_irq_handler(dev); | |
1777 | I915_WRITE(VLV_IIR, iir); | |
1778 | } | |
43f328d7 | 1779 | |
74cdb337 | 1780 | gen8_gt_irq_handler(dev_priv, master_ctl); |
43f328d7 | 1781 | |
27b6c122 OM |
1782 | /* Call regardless, as some status bits might not be |
1783 | * signalled in iir */ | |
1784 | valleyview_pipestat_irq_handler(dev, iir); | |
43f328d7 | 1785 | |
8e5fd599 VS |
1786 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); |
1787 | POSTING_READ(GEN8_MASTER_IRQ); | |
8e5fd599 | 1788 | } |
3278f67f | 1789 | |
43f328d7 VS |
1790 | return ret; |
1791 | } | |
1792 | ||
40e56410 VS |
1793 | static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
1794 | const u32 hpd[HPD_NUM_PINS]) | |
1795 | { | |
1796 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1797 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
1798 | ||
1799 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1800 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
1801 | ||
1802 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1803 | dig_hotplug_reg, hpd, | |
1804 | pch_port_hotplug_long_detect); | |
1805 | ||
1806 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1807 | } | |
1808 | ||
23e81d69 | 1809 | static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir) |
776ad806 | 1810 | { |
2d1013dd | 1811 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 1812 | int pipe; |
b543fb04 | 1813 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK; |
13cf5504 | 1814 | |
40e56410 VS |
1815 | if (hotplug_trigger) |
1816 | ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx); | |
91d131d2 | 1817 | |
cfc33bf7 VS |
1818 | if (pch_iir & SDE_AUDIO_POWER_MASK) { |
1819 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >> | |
1820 | SDE_AUDIO_POWER_SHIFT); | |
776ad806 | 1821 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", |
cfc33bf7 VS |
1822 | port_name(port)); |
1823 | } | |
776ad806 | 1824 | |
ce99c256 DV |
1825 | if (pch_iir & SDE_AUX_MASK) |
1826 | dp_aux_irq_handler(dev); | |
1827 | ||
776ad806 | 1828 | if (pch_iir & SDE_GMBUS) |
515ac2bb | 1829 | gmbus_irq_handler(dev); |
776ad806 JB |
1830 | |
1831 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
1832 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
1833 | ||
1834 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
1835 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
1836 | ||
1837 | if (pch_iir & SDE_POISON) | |
1838 | DRM_ERROR("PCH poison interrupt\n"); | |
1839 | ||
9db4a9c7 | 1840 | if (pch_iir & SDE_FDI_MASK) |
055e393f | 1841 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 JB |
1842 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1843 | pipe_name(pipe), | |
1844 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
1845 | |
1846 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
1847 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
1848 | ||
1849 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
1850 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
1851 | ||
776ad806 | 1852 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) |
1f7247c0 | 1853 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1854 | |
1855 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
1f7247c0 | 1856 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1857 | } |
1858 | ||
1859 | static void ivb_err_int_handler(struct drm_device *dev) | |
1860 | { | |
1861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1862 | u32 err_int = I915_READ(GEN7_ERR_INT); | |
5a69b89f | 1863 | enum pipe pipe; |
8664281b | 1864 | |
de032bf4 PZ |
1865 | if (err_int & ERR_INT_POISON) |
1866 | DRM_ERROR("Poison interrupt\n"); | |
1867 | ||
055e393f | 1868 | for_each_pipe(dev_priv, pipe) { |
1f7247c0 DV |
1869 | if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) |
1870 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
8bf1e9f1 | 1871 | |
5a69b89f DV |
1872 | if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { |
1873 | if (IS_IVYBRIDGE(dev)) | |
277de95e | 1874 | ivb_pipe_crc_irq_handler(dev, pipe); |
5a69b89f | 1875 | else |
277de95e | 1876 | hsw_pipe_crc_irq_handler(dev, pipe); |
5a69b89f DV |
1877 | } |
1878 | } | |
8bf1e9f1 | 1879 | |
8664281b PZ |
1880 | I915_WRITE(GEN7_ERR_INT, err_int); |
1881 | } | |
1882 | ||
1883 | static void cpt_serr_int_handler(struct drm_device *dev) | |
1884 | { | |
1885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1886 | u32 serr_int = I915_READ(SERR_INT); | |
1887 | ||
de032bf4 PZ |
1888 | if (serr_int & SERR_INT_POISON) |
1889 | DRM_ERROR("PCH poison interrupt\n"); | |
1890 | ||
8664281b | 1891 | if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN) |
1f7247c0 | 1892 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A); |
8664281b PZ |
1893 | |
1894 | if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN) | |
1f7247c0 | 1895 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B); |
8664281b PZ |
1896 | |
1897 | if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN) | |
1f7247c0 | 1898 | intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C); |
8664281b PZ |
1899 | |
1900 | I915_WRITE(SERR_INT, serr_int); | |
776ad806 JB |
1901 | } |
1902 | ||
23e81d69 AJ |
1903 | static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1904 | { | |
2d1013dd | 1905 | struct drm_i915_private *dev_priv = dev->dev_private; |
23e81d69 | 1906 | int pipe; |
6dbf30ce | 1907 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT; |
13cf5504 | 1908 | |
40e56410 VS |
1909 | if (hotplug_trigger) |
1910 | ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt); | |
91d131d2 | 1911 | |
cfc33bf7 VS |
1912 | if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) { |
1913 | int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >> | |
1914 | SDE_AUDIO_POWER_SHIFT_CPT); | |
1915 | DRM_DEBUG_DRIVER("PCH audio power change on port %c\n", | |
1916 | port_name(port)); | |
1917 | } | |
23e81d69 AJ |
1918 | |
1919 | if (pch_iir & SDE_AUX_MASK_CPT) | |
ce99c256 | 1920 | dp_aux_irq_handler(dev); |
23e81d69 AJ |
1921 | |
1922 | if (pch_iir & SDE_GMBUS_CPT) | |
515ac2bb | 1923 | gmbus_irq_handler(dev); |
23e81d69 AJ |
1924 | |
1925 | if (pch_iir & SDE_AUDIO_CP_REQ_CPT) | |
1926 | DRM_DEBUG_DRIVER("Audio CP request interrupt\n"); | |
1927 | ||
1928 | if (pch_iir & SDE_AUDIO_CP_CHG_CPT) | |
1929 | DRM_DEBUG_DRIVER("Audio CP change interrupt\n"); | |
1930 | ||
1931 | if (pch_iir & SDE_FDI_MASK_CPT) | |
055e393f | 1932 | for_each_pipe(dev_priv, pipe) |
23e81d69 AJ |
1933 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", |
1934 | pipe_name(pipe), | |
1935 | I915_READ(FDI_RX_IIR(pipe))); | |
8664281b PZ |
1936 | |
1937 | if (pch_iir & SDE_ERROR_CPT) | |
1938 | cpt_serr_int_handler(dev); | |
23e81d69 AJ |
1939 | } |
1940 | ||
6dbf30ce VS |
1941 | static void spt_irq_handler(struct drm_device *dev, u32 pch_iir) |
1942 | { | |
1943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1944 | u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT & | |
1945 | ~SDE_PORTE_HOTPLUG_SPT; | |
1946 | u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT; | |
1947 | u32 pin_mask = 0, long_mask = 0; | |
1948 | ||
1949 | if (hotplug_trigger) { | |
1950 | u32 dig_hotplug_reg; | |
1951 | ||
1952 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); | |
1953 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
1954 | ||
1955 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1956 | dig_hotplug_reg, hpd_spt, | |
74c0b395 | 1957 | spt_port_hotplug_long_detect); |
6dbf30ce VS |
1958 | } |
1959 | ||
1960 | if (hotplug2_trigger) { | |
1961 | u32 dig_hotplug_reg; | |
1962 | ||
1963 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2); | |
1964 | I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg); | |
1965 | ||
1966 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger, | |
1967 | dig_hotplug_reg, hpd_spt, | |
1968 | spt_port_hotplug2_long_detect); | |
1969 | } | |
1970 | ||
1971 | if (pin_mask) | |
1972 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1973 | ||
1974 | if (pch_iir & SDE_GMBUS_CPT) | |
1975 | gmbus_irq_handler(dev); | |
1976 | } | |
1977 | ||
40e56410 VS |
1978 | static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
1979 | const u32 hpd[HPD_NUM_PINS]) | |
1980 | { | |
1981 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1982 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
1983 | ||
1984 | dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
1985 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg); | |
1986 | ||
1987 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, | |
1988 | dig_hotplug_reg, hpd, | |
1989 | ilk_port_hotplug_long_detect); | |
1990 | ||
1991 | intel_hpd_irq_handler(dev, pin_mask, long_mask); | |
1992 | } | |
1993 | ||
c008bc6e PZ |
1994 | static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir) |
1995 | { | |
1996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40da17c2 | 1997 | enum pipe pipe; |
e4ce95aa VS |
1998 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG; |
1999 | ||
40e56410 VS |
2000 | if (hotplug_trigger) |
2001 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk); | |
c008bc6e PZ |
2002 | |
2003 | if (de_iir & DE_AUX_CHANNEL_A) | |
2004 | dp_aux_irq_handler(dev); | |
2005 | ||
2006 | if (de_iir & DE_GSE) | |
2007 | intel_opregion_asle_intr(dev); | |
2008 | ||
c008bc6e PZ |
2009 | if (de_iir & DE_POISON) |
2010 | DRM_ERROR("Poison interrupt\n"); | |
2011 | ||
055e393f | 2012 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2013 | if (de_iir & DE_PIPE_VBLANK(pipe) && |
2014 | intel_pipe_handle_vblank(dev, pipe)) | |
2015 | intel_check_page_flip(dev, pipe); | |
5b3a856b | 2016 | |
40da17c2 | 2017 | if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) |
1f7247c0 | 2018 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); |
5b3a856b | 2019 | |
40da17c2 DV |
2020 | if (de_iir & DE_PIPE_CRC_DONE(pipe)) |
2021 | i9xx_pipe_crc_irq_handler(dev, pipe); | |
c008bc6e | 2022 | |
40da17c2 DV |
2023 | /* plane/pipes map 1:1 on ilk+ */ |
2024 | if (de_iir & DE_PLANE_FLIP_DONE(pipe)) { | |
2025 | intel_prepare_page_flip(dev, pipe); | |
2026 | intel_finish_page_flip_plane(dev, pipe); | |
2027 | } | |
c008bc6e PZ |
2028 | } |
2029 | ||
2030 | /* check event from PCH */ | |
2031 | if (de_iir & DE_PCH_EVENT) { | |
2032 | u32 pch_iir = I915_READ(SDEIIR); | |
2033 | ||
2034 | if (HAS_PCH_CPT(dev)) | |
2035 | cpt_irq_handler(dev, pch_iir); | |
2036 | else | |
2037 | ibx_irq_handler(dev, pch_iir); | |
2038 | ||
2039 | /* should clear PCH hotplug event before clear CPU irq */ | |
2040 | I915_WRITE(SDEIIR, pch_iir); | |
2041 | } | |
2042 | ||
2043 | if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT) | |
2044 | ironlake_rps_change_irq_handler(dev); | |
2045 | } | |
2046 | ||
9719fb98 PZ |
2047 | static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir) |
2048 | { | |
2049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 2050 | enum pipe pipe; |
23bb4cb5 VS |
2051 | u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB; |
2052 | ||
40e56410 VS |
2053 | if (hotplug_trigger) |
2054 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb); | |
9719fb98 PZ |
2055 | |
2056 | if (de_iir & DE_ERR_INT_IVB) | |
2057 | ivb_err_int_handler(dev); | |
2058 | ||
2059 | if (de_iir & DE_AUX_CHANNEL_A_IVB) | |
2060 | dp_aux_irq_handler(dev); | |
2061 | ||
2062 | if (de_iir & DE_GSE_IVB) | |
2063 | intel_opregion_asle_intr(dev); | |
2064 | ||
055e393f | 2065 | for_each_pipe(dev_priv, pipe) { |
d6bbafa1 CW |
2066 | if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) && |
2067 | intel_pipe_handle_vblank(dev, pipe)) | |
2068 | intel_check_page_flip(dev, pipe); | |
40da17c2 DV |
2069 | |
2070 | /* plane/pipes map 1:1 on ilk+ */ | |
07d27e20 DL |
2071 | if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) { |
2072 | intel_prepare_page_flip(dev, pipe); | |
2073 | intel_finish_page_flip_plane(dev, pipe); | |
9719fb98 PZ |
2074 | } |
2075 | } | |
2076 | ||
2077 | /* check event from PCH */ | |
2078 | if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) { | |
2079 | u32 pch_iir = I915_READ(SDEIIR); | |
2080 | ||
2081 | cpt_irq_handler(dev, pch_iir); | |
2082 | ||
2083 | /* clear PCH hotplug event before clear CPU irq */ | |
2084 | I915_WRITE(SDEIIR, pch_iir); | |
2085 | } | |
2086 | } | |
2087 | ||
72c90f62 OM |
2088 | /* |
2089 | * To handle irqs with the minimum potential races with fresh interrupts, we: | |
2090 | * 1 - Disable Master Interrupt Control. | |
2091 | * 2 - Find the source(s) of the interrupt. | |
2092 | * 3 - Clear the Interrupt Identity bits (IIR). | |
2093 | * 4 - Process the interrupt(s) that had bits set in the IIRs. | |
2094 | * 5 - Re-enable Master Interrupt Control. | |
2095 | */ | |
f1af8fc1 | 2096 | static irqreturn_t ironlake_irq_handler(int irq, void *arg) |
b1f14ad0 | 2097 | { |
45a83f84 | 2098 | struct drm_device *dev = arg; |
2d1013dd | 2099 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1af8fc1 | 2100 | u32 de_iir, gt_iir, de_ier, sde_ier = 0; |
0e43406b | 2101 | irqreturn_t ret = IRQ_NONE; |
b1f14ad0 | 2102 | |
2dd2a883 ID |
2103 | if (!intel_irqs_enabled(dev_priv)) |
2104 | return IRQ_NONE; | |
2105 | ||
8664281b PZ |
2106 | /* We get interrupts on unclaimed registers, so check for this before we |
2107 | * do any I915_{READ,WRITE}. */ | |
907b28c5 | 2108 | intel_uncore_check_errors(dev); |
8664281b | 2109 | |
b1f14ad0 JB |
2110 | /* disable master interrupt before clearing iir */ |
2111 | de_ier = I915_READ(DEIER); | |
2112 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
23a78516 | 2113 | POSTING_READ(DEIER); |
b1f14ad0 | 2114 | |
44498aea PZ |
2115 | /* Disable south interrupts. We'll only write to SDEIIR once, so further |
2116 | * interrupts will will be stored on its back queue, and then we'll be | |
2117 | * able to process them after we restore SDEIER (as soon as we restore | |
2118 | * it, we'll get an interrupt if SDEIIR still has something to process | |
2119 | * due to its back queue). */ | |
ab5c608b BW |
2120 | if (!HAS_PCH_NOP(dev)) { |
2121 | sde_ier = I915_READ(SDEIER); | |
2122 | I915_WRITE(SDEIER, 0); | |
2123 | POSTING_READ(SDEIER); | |
2124 | } | |
44498aea | 2125 | |
72c90f62 OM |
2126 | /* Find, clear, then process each source of interrupt */ |
2127 | ||
b1f14ad0 | 2128 | gt_iir = I915_READ(GTIIR); |
0e43406b | 2129 | if (gt_iir) { |
72c90f62 OM |
2130 | I915_WRITE(GTIIR, gt_iir); |
2131 | ret = IRQ_HANDLED; | |
d8fc8a47 | 2132 | if (INTEL_INFO(dev)->gen >= 6) |
f1af8fc1 | 2133 | snb_gt_irq_handler(dev, dev_priv, gt_iir); |
d8fc8a47 PZ |
2134 | else |
2135 | ilk_gt_irq_handler(dev, dev_priv, gt_iir); | |
b1f14ad0 JB |
2136 | } |
2137 | ||
0e43406b CW |
2138 | de_iir = I915_READ(DEIIR); |
2139 | if (de_iir) { | |
72c90f62 OM |
2140 | I915_WRITE(DEIIR, de_iir); |
2141 | ret = IRQ_HANDLED; | |
f1af8fc1 PZ |
2142 | if (INTEL_INFO(dev)->gen >= 7) |
2143 | ivb_display_irq_handler(dev, de_iir); | |
2144 | else | |
2145 | ilk_display_irq_handler(dev, de_iir); | |
b1f14ad0 JB |
2146 | } |
2147 | ||
f1af8fc1 PZ |
2148 | if (INTEL_INFO(dev)->gen >= 6) { |
2149 | u32 pm_iir = I915_READ(GEN6_PMIIR); | |
2150 | if (pm_iir) { | |
f1af8fc1 PZ |
2151 | I915_WRITE(GEN6_PMIIR, pm_iir); |
2152 | ret = IRQ_HANDLED; | |
72c90f62 | 2153 | gen6_rps_irq_handler(dev_priv, pm_iir); |
f1af8fc1 | 2154 | } |
0e43406b | 2155 | } |
b1f14ad0 | 2156 | |
b1f14ad0 JB |
2157 | I915_WRITE(DEIER, de_ier); |
2158 | POSTING_READ(DEIER); | |
ab5c608b BW |
2159 | if (!HAS_PCH_NOP(dev)) { |
2160 | I915_WRITE(SDEIER, sde_ier); | |
2161 | POSTING_READ(SDEIER); | |
2162 | } | |
b1f14ad0 JB |
2163 | |
2164 | return ret; | |
2165 | } | |
2166 | ||
40e56410 VS |
2167 | static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger, |
2168 | const u32 hpd[HPD_NUM_PINS]) | |
d04a492d | 2169 | { |
cebd87a0 VS |
2170 | struct drm_i915_private *dev_priv = to_i915(dev); |
2171 | u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0; | |
d04a492d | 2172 | |
a52bb15b VS |
2173 | dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG); |
2174 | I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg); | |
d04a492d | 2175 | |
cebd87a0 | 2176 | intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger, |
40e56410 | 2177 | dig_hotplug_reg, hpd, |
cebd87a0 | 2178 | bxt_port_hotplug_long_detect); |
40e56410 | 2179 | |
676574df | 2180 | intel_hpd_irq_handler(dev, pin_mask, long_mask); |
d04a492d SS |
2181 | } |
2182 | ||
abd58f01 BW |
2183 | static irqreturn_t gen8_irq_handler(int irq, void *arg) |
2184 | { | |
2185 | struct drm_device *dev = arg; | |
2186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2187 | u32 master_ctl; | |
2188 | irqreturn_t ret = IRQ_NONE; | |
2189 | uint32_t tmp = 0; | |
c42664cc | 2190 | enum pipe pipe; |
88e04703 JB |
2191 | u32 aux_mask = GEN8_AUX_CHANNEL_A; |
2192 | ||
2dd2a883 ID |
2193 | if (!intel_irqs_enabled(dev_priv)) |
2194 | return IRQ_NONE; | |
2195 | ||
b4834a50 | 2196 | if (INTEL_INFO(dev_priv)->gen >= 9) |
88e04703 JB |
2197 | aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
2198 | GEN9_AUX_CHANNEL_D; | |
abd58f01 | 2199 | |
cb0d205e | 2200 | master_ctl = I915_READ_FW(GEN8_MASTER_IRQ); |
abd58f01 BW |
2201 | master_ctl &= ~GEN8_MASTER_IRQ_CONTROL; |
2202 | if (!master_ctl) | |
2203 | return IRQ_NONE; | |
2204 | ||
cb0d205e | 2205 | I915_WRITE_FW(GEN8_MASTER_IRQ, 0); |
abd58f01 | 2206 | |
38cc46d7 OM |
2207 | /* Find, clear, then process each source of interrupt */ |
2208 | ||
74cdb337 | 2209 | ret = gen8_gt_irq_handler(dev_priv, master_ctl); |
abd58f01 BW |
2210 | |
2211 | if (master_ctl & GEN8_DE_MISC_IRQ) { | |
2212 | tmp = I915_READ(GEN8_DE_MISC_IIR); | |
abd58f01 BW |
2213 | if (tmp) { |
2214 | I915_WRITE(GEN8_DE_MISC_IIR, tmp); | |
2215 | ret = IRQ_HANDLED; | |
38cc46d7 OM |
2216 | if (tmp & GEN8_DE_MISC_GSE) |
2217 | intel_opregion_asle_intr(dev); | |
2218 | else | |
2219 | DRM_ERROR("Unexpected DE Misc interrupt\n"); | |
abd58f01 | 2220 | } |
38cc46d7 OM |
2221 | else |
2222 | DRM_ERROR("The master control interrupt lied (DE MISC)!\n"); | |
abd58f01 BW |
2223 | } |
2224 | ||
6d766f02 DV |
2225 | if (master_ctl & GEN8_DE_PORT_IRQ) { |
2226 | tmp = I915_READ(GEN8_DE_PORT_IIR); | |
6d766f02 | 2227 | if (tmp) { |
d04a492d | 2228 | bool found = false; |
cebd87a0 VS |
2229 | u32 hotplug_trigger = 0; |
2230 | ||
2231 | if (IS_BROXTON(dev_priv)) | |
2232 | hotplug_trigger = tmp & BXT_DE_PORT_HOTPLUG_MASK; | |
2233 | else if (IS_BROADWELL(dev_priv)) | |
2234 | hotplug_trigger = tmp & GEN8_PORT_DP_A_HOTPLUG; | |
d04a492d | 2235 | |
6d766f02 DV |
2236 | I915_WRITE(GEN8_DE_PORT_IIR, tmp); |
2237 | ret = IRQ_HANDLED; | |
88e04703 | 2238 | |
d04a492d | 2239 | if (tmp & aux_mask) { |
38cc46d7 | 2240 | dp_aux_irq_handler(dev); |
d04a492d SS |
2241 | found = true; |
2242 | } | |
2243 | ||
40e56410 VS |
2244 | if (hotplug_trigger) { |
2245 | if (IS_BROXTON(dev)) | |
2246 | bxt_hpd_irq_handler(dev, hotplug_trigger, hpd_bxt); | |
2247 | else | |
2248 | ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_bdw); | |
d04a492d SS |
2249 | found = true; |
2250 | } | |
2251 | ||
9e63743e SS |
2252 | if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) { |
2253 | gmbus_irq_handler(dev); | |
2254 | found = true; | |
2255 | } | |
2256 | ||
d04a492d | 2257 | if (!found) |
38cc46d7 | 2258 | DRM_ERROR("Unexpected DE Port interrupt\n"); |
6d766f02 | 2259 | } |
38cc46d7 OM |
2260 | else |
2261 | DRM_ERROR("The master control interrupt lied (DE PORT)!\n"); | |
6d766f02 DV |
2262 | } |
2263 | ||
055e393f | 2264 | for_each_pipe(dev_priv, pipe) { |
770de83d | 2265 | uint32_t pipe_iir, flip_done = 0, fault_errors = 0; |
abd58f01 | 2266 | |
c42664cc DV |
2267 | if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) |
2268 | continue; | |
abd58f01 | 2269 | |
c42664cc | 2270 | pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe)); |
c42664cc DV |
2271 | if (pipe_iir) { |
2272 | ret = IRQ_HANDLED; | |
2273 | I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir); | |
770de83d | 2274 | |
d6bbafa1 CW |
2275 | if (pipe_iir & GEN8_PIPE_VBLANK && |
2276 | intel_pipe_handle_vblank(dev, pipe)) | |
2277 | intel_check_page_flip(dev, pipe); | |
38cc46d7 | 2278 | |
b4834a50 | 2279 | if (INTEL_INFO(dev_priv)->gen >= 9) |
770de83d DL |
2280 | flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE; |
2281 | else | |
2282 | flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE; | |
2283 | ||
2284 | if (flip_done) { | |
38cc46d7 OM |
2285 | intel_prepare_page_flip(dev, pipe); |
2286 | intel_finish_page_flip_plane(dev, pipe); | |
2287 | } | |
2288 | ||
2289 | if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE) | |
2290 | hsw_pipe_crc_irq_handler(dev, pipe); | |
2291 | ||
1f7247c0 DV |
2292 | if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) |
2293 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
2294 | pipe); | |
38cc46d7 | 2295 | |
770de83d | 2296 | |
b4834a50 | 2297 | if (INTEL_INFO(dev_priv)->gen >= 9) |
770de83d DL |
2298 | fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS; |
2299 | else | |
2300 | fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
2301 | ||
2302 | if (fault_errors) | |
38cc46d7 OM |
2303 | DRM_ERROR("Fault errors on pipe %c\n: 0x%08x", |
2304 | pipe_name(pipe), | |
2305 | pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS); | |
c42664cc | 2306 | } else |
abd58f01 BW |
2307 | DRM_ERROR("The master control interrupt lied (DE PIPE)!\n"); |
2308 | } | |
2309 | ||
266ea3d9 SS |
2310 | if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) && |
2311 | master_ctl & GEN8_DE_PCH_IRQ) { | |
92d03a80 DV |
2312 | /* |
2313 | * FIXME(BDW): Assume for now that the new interrupt handling | |
2314 | * scheme also closed the SDE interrupt handling race we've seen | |
2315 | * on older pch-split platforms. But this needs testing. | |
2316 | */ | |
2317 | u32 pch_iir = I915_READ(SDEIIR); | |
92d03a80 DV |
2318 | if (pch_iir) { |
2319 | I915_WRITE(SDEIIR, pch_iir); | |
2320 | ret = IRQ_HANDLED; | |
6dbf30ce VS |
2321 | |
2322 | if (HAS_PCH_SPT(dev_priv)) | |
2323 | spt_irq_handler(dev, pch_iir); | |
2324 | else | |
2325 | cpt_irq_handler(dev, pch_iir); | |
38cc46d7 OM |
2326 | } else |
2327 | DRM_ERROR("The master control interrupt lied (SDE)!\n"); | |
2328 | ||
92d03a80 DV |
2329 | } |
2330 | ||
cb0d205e CW |
2331 | I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); |
2332 | POSTING_READ_FW(GEN8_MASTER_IRQ); | |
abd58f01 BW |
2333 | |
2334 | return ret; | |
2335 | } | |
2336 | ||
17e1df07 DV |
2337 | static void i915_error_wake_up(struct drm_i915_private *dev_priv, |
2338 | bool reset_completed) | |
2339 | { | |
a4872ba6 | 2340 | struct intel_engine_cs *ring; |
17e1df07 DV |
2341 | int i; |
2342 | ||
2343 | /* | |
2344 | * Notify all waiters for GPU completion events that reset state has | |
2345 | * been changed, and that they need to restart their wait after | |
2346 | * checking for potential errors (and bail out to drop locks if there is | |
2347 | * a gpu reset pending so that i915_error_work_func can acquire them). | |
2348 | */ | |
2349 | ||
2350 | /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */ | |
2351 | for_each_ring(ring, dev_priv, i) | |
2352 | wake_up_all(&ring->irq_queue); | |
2353 | ||
2354 | /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */ | |
2355 | wake_up_all(&dev_priv->pending_flip_queue); | |
2356 | ||
2357 | /* | |
2358 | * Signal tasks blocked in i915_gem_wait_for_error that the pending | |
2359 | * reset state is cleared. | |
2360 | */ | |
2361 | if (reset_completed) | |
2362 | wake_up_all(&dev_priv->gpu_error.reset_queue); | |
2363 | } | |
2364 | ||
8a905236 | 2365 | /** |
b8d24a06 | 2366 | * i915_reset_and_wakeup - do process context error handling work |
8a905236 JB |
2367 | * |
2368 | * Fire an error uevent so userspace can see that a hang or error | |
2369 | * was detected. | |
2370 | */ | |
b8d24a06 | 2371 | static void i915_reset_and_wakeup(struct drm_device *dev) |
8a905236 | 2372 | { |
b8d24a06 MK |
2373 | struct drm_i915_private *dev_priv = to_i915(dev); |
2374 | struct i915_gpu_error *error = &dev_priv->gpu_error; | |
cce723ed BW |
2375 | char *error_event[] = { I915_ERROR_UEVENT "=1", NULL }; |
2376 | char *reset_event[] = { I915_RESET_UEVENT "=1", NULL }; | |
2377 | char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL }; | |
17e1df07 | 2378 | int ret; |
8a905236 | 2379 | |
5bdebb18 | 2380 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event); |
f316a42c | 2381 | |
7db0ba24 DV |
2382 | /* |
2383 | * Note that there's only one work item which does gpu resets, so we | |
2384 | * need not worry about concurrent gpu resets potentially incrementing | |
2385 | * error->reset_counter twice. We only need to take care of another | |
2386 | * racing irq/hangcheck declaring the gpu dead for a second time. A | |
2387 | * quick check for that is good enough: schedule_work ensures the | |
2388 | * correct ordering between hang detection and this work item, and since | |
2389 | * the reset in-progress bit is only ever set by code outside of this | |
2390 | * work we don't need to worry about any other races. | |
2391 | */ | |
2392 | if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) { | |
f803aa55 | 2393 | DRM_DEBUG_DRIVER("resetting chip\n"); |
5bdebb18 | 2394 | kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, |
7db0ba24 | 2395 | reset_event); |
1f83fee0 | 2396 | |
f454c694 ID |
2397 | /* |
2398 | * In most cases it's guaranteed that we get here with an RPM | |
2399 | * reference held, for example because there is a pending GPU | |
2400 | * request that won't finish until the reset is done. This | |
2401 | * isn't the case at least when we get here by doing a | |
2402 | * simulated reset via debugs, so get an RPM reference. | |
2403 | */ | |
2404 | intel_runtime_pm_get(dev_priv); | |
7514747d VS |
2405 | |
2406 | intel_prepare_reset(dev); | |
2407 | ||
17e1df07 DV |
2408 | /* |
2409 | * All state reset _must_ be completed before we update the | |
2410 | * reset counter, for otherwise waiters might miss the reset | |
2411 | * pending state and not properly drop locks, resulting in | |
2412 | * deadlocks with the reset work. | |
2413 | */ | |
f69061be DV |
2414 | ret = i915_reset(dev); |
2415 | ||
7514747d | 2416 | intel_finish_reset(dev); |
17e1df07 | 2417 | |
f454c694 ID |
2418 | intel_runtime_pm_put(dev_priv); |
2419 | ||
f69061be DV |
2420 | if (ret == 0) { |
2421 | /* | |
2422 | * After all the gem state is reset, increment the reset | |
2423 | * counter and wake up everyone waiting for the reset to | |
2424 | * complete. | |
2425 | * | |
2426 | * Since unlock operations are a one-sided barrier only, | |
2427 | * we need to insert a barrier here to order any seqno | |
2428 | * updates before | |
2429 | * the counter increment. | |
2430 | */ | |
4e857c58 | 2431 | smp_mb__before_atomic(); |
f69061be DV |
2432 | atomic_inc(&dev_priv->gpu_error.reset_counter); |
2433 | ||
5bdebb18 | 2434 | kobject_uevent_env(&dev->primary->kdev->kobj, |
f69061be | 2435 | KOBJ_CHANGE, reset_done_event); |
1f83fee0 | 2436 | } else { |
2ac0f450 | 2437 | atomic_set_mask(I915_WEDGED, &error->reset_counter); |
f316a42c | 2438 | } |
1f83fee0 | 2439 | |
17e1df07 DV |
2440 | /* |
2441 | * Note: The wake_up also serves as a memory barrier so that | |
2442 | * waiters see the update value of the reset counter atomic_t. | |
2443 | */ | |
2444 | i915_error_wake_up(dev_priv, true); | |
f316a42c | 2445 | } |
8a905236 JB |
2446 | } |
2447 | ||
35aed2e6 | 2448 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
2449 | { |
2450 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bd9854f9 | 2451 | uint32_t instdone[I915_NUM_INSTDONE_REG]; |
8a905236 | 2452 | u32 eir = I915_READ(EIR); |
050ee91f | 2453 | int pipe, i; |
8a905236 | 2454 | |
35aed2e6 CW |
2455 | if (!eir) |
2456 | return; | |
8a905236 | 2457 | |
a70491cc | 2458 | pr_err("render error detected, EIR: 0x%08x\n", eir); |
8a905236 | 2459 | |
bd9854f9 BW |
2460 | i915_get_extra_instdone(dev, instdone); |
2461 | ||
8a905236 JB |
2462 | if (IS_G4X(dev)) { |
2463 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
2464 | u32 ipeir = I915_READ(IPEIR_I965); | |
2465 | ||
a70491cc JP |
2466 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2467 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
050ee91f BW |
2468 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2469 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a70491cc | 2470 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2471 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2472 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2473 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2474 | } |
2475 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
2476 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2477 | pr_err("page table error\n"); |
2478 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2479 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2480 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2481 | } |
2482 | } | |
2483 | ||
a6c45cf0 | 2484 | if (!IS_GEN2(dev)) { |
8a905236 JB |
2485 | if (eir & I915_ERROR_PAGE_TABLE) { |
2486 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
a70491cc JP |
2487 | pr_err("page table error\n"); |
2488 | pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err); | |
8a905236 | 2489 | I915_WRITE(PGTBL_ER, pgtbl_err); |
3143a2bf | 2490 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
2491 | } |
2492 | } | |
2493 | ||
2494 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
a70491cc | 2495 | pr_err("memory refresh error:\n"); |
055e393f | 2496 | for_each_pipe(dev_priv, pipe) |
a70491cc | 2497 | pr_err("pipe %c stat: 0x%08x\n", |
9db4a9c7 | 2498 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); |
8a905236 JB |
2499 | /* pipestat has already been acked */ |
2500 | } | |
2501 | if (eir & I915_ERROR_INSTRUCTION) { | |
a70491cc JP |
2502 | pr_err("instruction error\n"); |
2503 | pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM)); | |
050ee91f BW |
2504 | for (i = 0; i < ARRAY_SIZE(instdone); i++) |
2505 | pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]); | |
a6c45cf0 | 2506 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
2507 | u32 ipeir = I915_READ(IPEIR); |
2508 | ||
a70491cc JP |
2509 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR)); |
2510 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR)); | |
a70491cc | 2511 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD)); |
8a905236 | 2512 | I915_WRITE(IPEIR, ipeir); |
3143a2bf | 2513 | POSTING_READ(IPEIR); |
8a905236 JB |
2514 | } else { |
2515 | u32 ipeir = I915_READ(IPEIR_I965); | |
2516 | ||
a70491cc JP |
2517 | pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965)); |
2518 | pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965)); | |
a70491cc | 2519 | pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS)); |
a70491cc | 2520 | pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965)); |
8a905236 | 2521 | I915_WRITE(IPEIR_I965, ipeir); |
3143a2bf | 2522 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
2523 | } |
2524 | } | |
2525 | ||
2526 | I915_WRITE(EIR, eir); | |
3143a2bf | 2527 | POSTING_READ(EIR); |
8a905236 JB |
2528 | eir = I915_READ(EIR); |
2529 | if (eir) { | |
2530 | /* | |
2531 | * some errors might have become stuck, | |
2532 | * mask them. | |
2533 | */ | |
2534 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
2535 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
2536 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
2537 | } | |
35aed2e6 CW |
2538 | } |
2539 | ||
2540 | /** | |
b8d24a06 | 2541 | * i915_handle_error - handle a gpu error |
35aed2e6 CW |
2542 | * @dev: drm device |
2543 | * | |
b8d24a06 | 2544 | * Do some basic checking of regsiter state at error time and |
35aed2e6 CW |
2545 | * dump it to the syslog. Also call i915_capture_error_state() to make |
2546 | * sure we get a record and make it available in debugfs. Fire a uevent | |
2547 | * so userspace knows something bad happened (should trigger collection | |
2548 | * of a ring dump etc.). | |
2549 | */ | |
58174462 MK |
2550 | void i915_handle_error(struct drm_device *dev, bool wedged, |
2551 | const char *fmt, ...) | |
35aed2e6 CW |
2552 | { |
2553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58174462 MK |
2554 | va_list args; |
2555 | char error_msg[80]; | |
35aed2e6 | 2556 | |
58174462 MK |
2557 | va_start(args, fmt); |
2558 | vscnprintf(error_msg, sizeof(error_msg), fmt, args); | |
2559 | va_end(args); | |
2560 | ||
2561 | i915_capture_error_state(dev, wedged, error_msg); | |
35aed2e6 | 2562 | i915_report_and_clear_eir(dev); |
8a905236 | 2563 | |
ba1234d1 | 2564 | if (wedged) { |
f69061be DV |
2565 | atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG, |
2566 | &dev_priv->gpu_error.reset_counter); | |
ba1234d1 | 2567 | |
11ed50ec | 2568 | /* |
b8d24a06 MK |
2569 | * Wakeup waiting processes so that the reset function |
2570 | * i915_reset_and_wakeup doesn't deadlock trying to grab | |
2571 | * various locks. By bumping the reset counter first, the woken | |
17e1df07 DV |
2572 | * processes will see a reset in progress and back off, |
2573 | * releasing their locks and then wait for the reset completion. | |
2574 | * We must do this for _all_ gpu waiters that might hold locks | |
2575 | * that the reset work needs to acquire. | |
2576 | * | |
2577 | * Note: The wake_up serves as the required memory barrier to | |
2578 | * ensure that the waiters see the updated value of the reset | |
2579 | * counter atomic_t. | |
11ed50ec | 2580 | */ |
17e1df07 | 2581 | i915_error_wake_up(dev_priv, false); |
11ed50ec BG |
2582 | } |
2583 | ||
b8d24a06 | 2584 | i915_reset_and_wakeup(dev); |
8a905236 JB |
2585 | } |
2586 | ||
42f52ef8 KP |
2587 | /* Called from drm generic code, passed 'crtc' which |
2588 | * we use as a pipe index | |
2589 | */ | |
f71d4af4 | 2590 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2591 | { |
2d1013dd | 2592 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2593 | unsigned long irqflags; |
71e0ffa5 | 2594 | |
1ec14ad3 | 2595 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2596 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 | 2597 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2598 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
e9d21d7f | 2599 | else |
7c463586 | 2600 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2601 | PIPE_VBLANK_INTERRUPT_STATUS); |
1ec14ad3 | 2602 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 2603 | |
0a3e67a4 JB |
2604 | return 0; |
2605 | } | |
2606 | ||
f71d4af4 | 2607 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2608 | { |
2d1013dd | 2609 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2610 | unsigned long irqflags; |
b518421f | 2611 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2612 | DE_PIPE_VBLANK(pipe); |
f796cf8f | 2613 | |
f796cf8f | 2614 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
b518421f | 2615 | ironlake_enable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2616 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2617 | ||
2618 | return 0; | |
2619 | } | |
2620 | ||
7e231dbe JB |
2621 | static int valleyview_enable_vblank(struct drm_device *dev, int pipe) |
2622 | { | |
2d1013dd | 2623 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2624 | unsigned long irqflags; |
7e231dbe | 2625 | |
7e231dbe | 2626 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
31acc7f5 | 2627 | i915_enable_pipestat(dev_priv, pipe, |
755e9019 | 2628 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2629 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2630 | ||
2631 | return 0; | |
2632 | } | |
2633 | ||
abd58f01 BW |
2634 | static int gen8_enable_vblank(struct drm_device *dev, int pipe) |
2635 | { | |
2636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2637 | unsigned long irqflags; | |
abd58f01 | 2638 | |
abd58f01 | 2639 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2640 | dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK; |
2641 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2642 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2643 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2644 | return 0; | |
2645 | } | |
2646 | ||
42f52ef8 KP |
2647 | /* Called from drm generic code, passed 'crtc' which |
2648 | * we use as a pipe index | |
2649 | */ | |
f71d4af4 | 2650 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 | 2651 | { |
2d1013dd | 2652 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9d21d7f | 2653 | unsigned long irqflags; |
0a3e67a4 | 2654 | |
1ec14ad3 | 2655 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 2656 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 ID |
2657 | PIPE_VBLANK_INTERRUPT_STATUS | |
2658 | PIPE_START_VBLANK_INTERRUPT_STATUS); | |
f796cf8f JB |
2659 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2660 | } | |
2661 | ||
f71d4af4 | 2662 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f | 2663 | { |
2d1013dd | 2664 | struct drm_i915_private *dev_priv = dev->dev_private; |
f796cf8f | 2665 | unsigned long irqflags; |
b518421f | 2666 | uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) : |
40da17c2 | 2667 | DE_PIPE_VBLANK(pipe); |
f796cf8f JB |
2668 | |
2669 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
b518421f | 2670 | ironlake_disable_display_irq(dev_priv, bit); |
b1f14ad0 JB |
2671 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2672 | } | |
2673 | ||
7e231dbe JB |
2674 | static void valleyview_disable_vblank(struct drm_device *dev, int pipe) |
2675 | { | |
2d1013dd | 2676 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 2677 | unsigned long irqflags; |
7e231dbe JB |
2678 | |
2679 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
31acc7f5 | 2680 | i915_disable_pipestat(dev_priv, pipe, |
755e9019 | 2681 | PIPE_START_VBLANK_INTERRUPT_STATUS); |
7e231dbe JB |
2682 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2683 | } | |
2684 | ||
abd58f01 BW |
2685 | static void gen8_disable_vblank(struct drm_device *dev, int pipe) |
2686 | { | |
2687 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2688 | unsigned long irqflags; | |
abd58f01 | 2689 | |
abd58f01 | 2690 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
7167d7c6 DV |
2691 | dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK; |
2692 | I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); | |
2693 | POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); | |
abd58f01 BW |
2694 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
2695 | } | |
2696 | ||
9107e9d2 | 2697 | static bool |
94f7bbe1 | 2698 | ring_idle(struct intel_engine_cs *ring, u32 seqno) |
9107e9d2 CW |
2699 | { |
2700 | return (list_empty(&ring->request_list) || | |
94f7bbe1 | 2701 | i915_seqno_passed(seqno, ring->last_submitted_seqno)); |
f65d9421 BG |
2702 | } |
2703 | ||
a028c4b0 DV |
2704 | static bool |
2705 | ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr) | |
2706 | { | |
2707 | if (INTEL_INFO(dev)->gen >= 8) { | |
a6cdb93a | 2708 | return (ipehr >> 23) == 0x1c; |
a028c4b0 DV |
2709 | } else { |
2710 | ipehr &= ~MI_SEMAPHORE_SYNC_MASK; | |
2711 | return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | | |
2712 | MI_SEMAPHORE_REGISTER); | |
2713 | } | |
2714 | } | |
2715 | ||
a4872ba6 | 2716 | static struct intel_engine_cs * |
a6cdb93a | 2717 | semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset) |
921d42ea DV |
2718 | { |
2719 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2720 | struct intel_engine_cs *signaller; |
921d42ea DV |
2721 | int i; |
2722 | ||
2723 | if (INTEL_INFO(dev_priv->dev)->gen >= 8) { | |
a6cdb93a RV |
2724 | for_each_ring(signaller, dev_priv, i) { |
2725 | if (ring == signaller) | |
2726 | continue; | |
2727 | ||
2728 | if (offset == signaller->semaphore.signal_ggtt[ring->id]) | |
2729 | return signaller; | |
2730 | } | |
921d42ea DV |
2731 | } else { |
2732 | u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK; | |
2733 | ||
2734 | for_each_ring(signaller, dev_priv, i) { | |
2735 | if(ring == signaller) | |
2736 | continue; | |
2737 | ||
ebc348b2 | 2738 | if (sync_bits == signaller->semaphore.mbox.wait[ring->id]) |
921d42ea DV |
2739 | return signaller; |
2740 | } | |
2741 | } | |
2742 | ||
a6cdb93a RV |
2743 | DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n", |
2744 | ring->id, ipehr, offset); | |
921d42ea DV |
2745 | |
2746 | return NULL; | |
2747 | } | |
2748 | ||
a4872ba6 OM |
2749 | static struct intel_engine_cs * |
2750 | semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno) | |
a24a11e6 CW |
2751 | { |
2752 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88fe429d | 2753 | u32 cmd, ipehr, head; |
a6cdb93a RV |
2754 | u64 offset = 0; |
2755 | int i, backwards; | |
a24a11e6 CW |
2756 | |
2757 | ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); | |
a028c4b0 | 2758 | if (!ipehr_is_semaphore_wait(ring->dev, ipehr)) |
6274f212 | 2759 | return NULL; |
a24a11e6 | 2760 | |
88fe429d DV |
2761 | /* |
2762 | * HEAD is likely pointing to the dword after the actual command, | |
2763 | * so scan backwards until we find the MBOX. But limit it to just 3 | |
a6cdb93a RV |
2764 | * or 4 dwords depending on the semaphore wait command size. |
2765 | * Note that we don't care about ACTHD here since that might | |
88fe429d DV |
2766 | * point at at batch, and semaphores are always emitted into the |
2767 | * ringbuffer itself. | |
a24a11e6 | 2768 | */ |
88fe429d | 2769 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
a6cdb93a | 2770 | backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4; |
88fe429d | 2771 | |
a6cdb93a | 2772 | for (i = backwards; i; --i) { |
88fe429d DV |
2773 | /* |
2774 | * Be paranoid and presume the hw has gone off into the wild - | |
2775 | * our ring is smaller than what the hardware (and hence | |
2776 | * HEAD_ADDR) allows. Also handles wrap-around. | |
2777 | */ | |
ee1b1e5e | 2778 | head &= ring->buffer->size - 1; |
88fe429d DV |
2779 | |
2780 | /* This here seems to blow up */ | |
ee1b1e5e | 2781 | cmd = ioread32(ring->buffer->virtual_start + head); |
a24a11e6 CW |
2782 | if (cmd == ipehr) |
2783 | break; | |
2784 | ||
88fe429d DV |
2785 | head -= 4; |
2786 | } | |
a24a11e6 | 2787 | |
88fe429d DV |
2788 | if (!i) |
2789 | return NULL; | |
a24a11e6 | 2790 | |
ee1b1e5e | 2791 | *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1; |
a6cdb93a RV |
2792 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2793 | offset = ioread32(ring->buffer->virtual_start + head + 12); | |
2794 | offset <<= 32; | |
2795 | offset = ioread32(ring->buffer->virtual_start + head + 8); | |
2796 | } | |
2797 | return semaphore_wait_to_signaller_ring(ring, ipehr, offset); | |
a24a11e6 CW |
2798 | } |
2799 | ||
a4872ba6 | 2800 | static int semaphore_passed(struct intel_engine_cs *ring) |
6274f212 CW |
2801 | { |
2802 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
a4872ba6 | 2803 | struct intel_engine_cs *signaller; |
a0d036b0 | 2804 | u32 seqno; |
6274f212 | 2805 | |
4be17381 | 2806 | ring->hangcheck.deadlock++; |
6274f212 CW |
2807 | |
2808 | signaller = semaphore_waits_for(ring, &seqno); | |
4be17381 CW |
2809 | if (signaller == NULL) |
2810 | return -1; | |
2811 | ||
2812 | /* Prevent pathological recursion due to driver bugs */ | |
2813 | if (signaller->hangcheck.deadlock >= I915_NUM_RINGS) | |
6274f212 CW |
2814 | return -1; |
2815 | ||
4be17381 CW |
2816 | if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno)) |
2817 | return 1; | |
2818 | ||
a0d036b0 CW |
2819 | /* cursory check for an unkickable deadlock */ |
2820 | if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE && | |
2821 | semaphore_passed(signaller) < 0) | |
4be17381 CW |
2822 | return -1; |
2823 | ||
2824 | return 0; | |
6274f212 CW |
2825 | } |
2826 | ||
2827 | static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv) | |
2828 | { | |
a4872ba6 | 2829 | struct intel_engine_cs *ring; |
6274f212 CW |
2830 | int i; |
2831 | ||
2832 | for_each_ring(ring, dev_priv, i) | |
4be17381 | 2833 | ring->hangcheck.deadlock = 0; |
6274f212 CW |
2834 | } |
2835 | ||
ad8beaea | 2836 | static enum intel_ring_hangcheck_action |
a4872ba6 | 2837 | ring_stuck(struct intel_engine_cs *ring, u64 acthd) |
1ec14ad3 CW |
2838 | { |
2839 | struct drm_device *dev = ring->dev; | |
2840 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9107e9d2 CW |
2841 | u32 tmp; |
2842 | ||
f260fe7b MK |
2843 | if (acthd != ring->hangcheck.acthd) { |
2844 | if (acthd > ring->hangcheck.max_acthd) { | |
2845 | ring->hangcheck.max_acthd = acthd; | |
2846 | return HANGCHECK_ACTIVE; | |
2847 | } | |
2848 | ||
2849 | return HANGCHECK_ACTIVE_LOOP; | |
2850 | } | |
6274f212 | 2851 | |
9107e9d2 | 2852 | if (IS_GEN2(dev)) |
f2f4d82f | 2853 | return HANGCHECK_HUNG; |
9107e9d2 CW |
2854 | |
2855 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
2856 | * If so we can simply poke the RB_WAIT bit | |
2857 | * and break the hang. This should work on | |
2858 | * all but the second generation chipsets. | |
2859 | */ | |
2860 | tmp = I915_READ_CTL(ring); | |
1ec14ad3 | 2861 | if (tmp & RING_WAIT) { |
58174462 MK |
2862 | i915_handle_error(dev, false, |
2863 | "Kicking stuck wait on %s", | |
2864 | ring->name); | |
1ec14ad3 | 2865 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2866 | return HANGCHECK_KICK; |
6274f212 CW |
2867 | } |
2868 | ||
2869 | if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) { | |
2870 | switch (semaphore_passed(ring)) { | |
2871 | default: | |
f2f4d82f | 2872 | return HANGCHECK_HUNG; |
6274f212 | 2873 | case 1: |
58174462 MK |
2874 | i915_handle_error(dev, false, |
2875 | "Kicking stuck semaphore on %s", | |
2876 | ring->name); | |
6274f212 | 2877 | I915_WRITE_CTL(ring, tmp); |
f2f4d82f | 2878 | return HANGCHECK_KICK; |
6274f212 | 2879 | case 0: |
f2f4d82f | 2880 | return HANGCHECK_WAIT; |
6274f212 | 2881 | } |
9107e9d2 | 2882 | } |
ed5cbb03 | 2883 | |
f2f4d82f | 2884 | return HANGCHECK_HUNG; |
ed5cbb03 MK |
2885 | } |
2886 | ||
737b1506 | 2887 | /* |
f65d9421 | 2888 | * This is called when the chip hasn't reported back with completed |
05407ff8 MK |
2889 | * batchbuffers in a long time. We keep track per ring seqno progress and |
2890 | * if there are no progress, hangcheck score for that ring is increased. | |
2891 | * Further, acthd is inspected to see if the ring is stuck. On stuck case | |
2892 | * we kick the ring. If we see no progress on three subsequent calls | |
2893 | * we assume chip is wedged and try to fix it by resetting the chip. | |
f65d9421 | 2894 | */ |
737b1506 | 2895 | static void i915_hangcheck_elapsed(struct work_struct *work) |
f65d9421 | 2896 | { |
737b1506 CW |
2897 | struct drm_i915_private *dev_priv = |
2898 | container_of(work, typeof(*dev_priv), | |
2899 | gpu_error.hangcheck_work.work); | |
2900 | struct drm_device *dev = dev_priv->dev; | |
a4872ba6 | 2901 | struct intel_engine_cs *ring; |
b4519513 | 2902 | int i; |
05407ff8 | 2903 | int busy_count = 0, rings_hung = 0; |
9107e9d2 CW |
2904 | bool stuck[I915_NUM_RINGS] = { 0 }; |
2905 | #define BUSY 1 | |
2906 | #define KICK 5 | |
2907 | #define HUNG 20 | |
893eead0 | 2908 | |
d330a953 | 2909 | if (!i915.enable_hangcheck) |
3e0dc6b0 BW |
2910 | return; |
2911 | ||
b4519513 | 2912 | for_each_ring(ring, dev_priv, i) { |
50877445 CW |
2913 | u64 acthd; |
2914 | u32 seqno; | |
9107e9d2 | 2915 | bool busy = true; |
05407ff8 | 2916 | |
6274f212 CW |
2917 | semaphore_clear_deadlocks(dev_priv); |
2918 | ||
05407ff8 MK |
2919 | seqno = ring->get_seqno(ring, false); |
2920 | acthd = intel_ring_get_active_head(ring); | |
b4519513 | 2921 | |
9107e9d2 | 2922 | if (ring->hangcheck.seqno == seqno) { |
94f7bbe1 | 2923 | if (ring_idle(ring, seqno)) { |
da661464 MK |
2924 | ring->hangcheck.action = HANGCHECK_IDLE; |
2925 | ||
9107e9d2 CW |
2926 | if (waitqueue_active(&ring->irq_queue)) { |
2927 | /* Issue a wake-up to catch stuck h/w. */ | |
094f9a54 | 2928 | if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) { |
f4adcd24 DV |
2929 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring))) |
2930 | DRM_ERROR("Hangcheck timer elapsed... %s idle\n", | |
2931 | ring->name); | |
2932 | else | |
2933 | DRM_INFO("Fake missed irq on %s\n", | |
2934 | ring->name); | |
094f9a54 CW |
2935 | wake_up_all(&ring->irq_queue); |
2936 | } | |
2937 | /* Safeguard against driver failure */ | |
2938 | ring->hangcheck.score += BUSY; | |
9107e9d2 CW |
2939 | } else |
2940 | busy = false; | |
05407ff8 | 2941 | } else { |
6274f212 CW |
2942 | /* We always increment the hangcheck score |
2943 | * if the ring is busy and still processing | |
2944 | * the same request, so that no single request | |
2945 | * can run indefinitely (such as a chain of | |
2946 | * batches). The only time we do not increment | |
2947 | * the hangcheck score on this ring, if this | |
2948 | * ring is in a legitimate wait for another | |
2949 | * ring. In that case the waiting ring is a | |
2950 | * victim and we want to be sure we catch the | |
2951 | * right culprit. Then every time we do kick | |
2952 | * the ring, add a small increment to the | |
2953 | * score so that we can catch a batch that is | |
2954 | * being repeatedly kicked and so responsible | |
2955 | * for stalling the machine. | |
2956 | */ | |
ad8beaea MK |
2957 | ring->hangcheck.action = ring_stuck(ring, |
2958 | acthd); | |
2959 | ||
2960 | switch (ring->hangcheck.action) { | |
da661464 | 2961 | case HANGCHECK_IDLE: |
f2f4d82f | 2962 | case HANGCHECK_WAIT: |
f2f4d82f | 2963 | case HANGCHECK_ACTIVE: |
f260fe7b MK |
2964 | break; |
2965 | case HANGCHECK_ACTIVE_LOOP: | |
ea04cb31 | 2966 | ring->hangcheck.score += BUSY; |
6274f212 | 2967 | break; |
f2f4d82f | 2968 | case HANGCHECK_KICK: |
ea04cb31 | 2969 | ring->hangcheck.score += KICK; |
6274f212 | 2970 | break; |
f2f4d82f | 2971 | case HANGCHECK_HUNG: |
ea04cb31 | 2972 | ring->hangcheck.score += HUNG; |
6274f212 CW |
2973 | stuck[i] = true; |
2974 | break; | |
2975 | } | |
05407ff8 | 2976 | } |
9107e9d2 | 2977 | } else { |
da661464 MK |
2978 | ring->hangcheck.action = HANGCHECK_ACTIVE; |
2979 | ||
9107e9d2 CW |
2980 | /* Gradually reduce the count so that we catch DoS |
2981 | * attempts across multiple batches. | |
2982 | */ | |
2983 | if (ring->hangcheck.score > 0) | |
2984 | ring->hangcheck.score--; | |
f260fe7b MK |
2985 | |
2986 | ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0; | |
d1e61e7f CW |
2987 | } |
2988 | ||
05407ff8 MK |
2989 | ring->hangcheck.seqno = seqno; |
2990 | ring->hangcheck.acthd = acthd; | |
9107e9d2 | 2991 | busy_count += busy; |
893eead0 | 2992 | } |
b9201c14 | 2993 | |
92cab734 | 2994 | for_each_ring(ring, dev_priv, i) { |
b6b0fac0 | 2995 | if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) { |
b8d88d1d DV |
2996 | DRM_INFO("%s on %s\n", |
2997 | stuck[i] ? "stuck" : "no progress", | |
2998 | ring->name); | |
a43adf07 | 2999 | rings_hung++; |
92cab734 MK |
3000 | } |
3001 | } | |
3002 | ||
05407ff8 | 3003 | if (rings_hung) |
58174462 | 3004 | return i915_handle_error(dev, true, "Ring hung"); |
f65d9421 | 3005 | |
05407ff8 MK |
3006 | if (busy_count) |
3007 | /* Reset timer case chip hangs without another request | |
3008 | * being added */ | |
10cd45b6 MK |
3009 | i915_queue_hangcheck(dev); |
3010 | } | |
3011 | ||
3012 | void i915_queue_hangcheck(struct drm_device *dev) | |
3013 | { | |
737b1506 | 3014 | struct i915_gpu_error *e = &to_i915(dev)->gpu_error; |
672e7b7c | 3015 | |
d330a953 | 3016 | if (!i915.enable_hangcheck) |
10cd45b6 MK |
3017 | return; |
3018 | ||
737b1506 CW |
3019 | /* Don't continually defer the hangcheck so that it is always run at |
3020 | * least once after work has been scheduled on any ring. Otherwise, | |
3021 | * we will ignore a hung ring if a second ring is kept busy. | |
3022 | */ | |
3023 | ||
3024 | queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work, | |
3025 | round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES)); | |
f65d9421 BG |
3026 | } |
3027 | ||
1c69eb42 | 3028 | static void ibx_irq_reset(struct drm_device *dev) |
91738a95 PZ |
3029 | { |
3030 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3031 | ||
3032 | if (HAS_PCH_NOP(dev)) | |
3033 | return; | |
3034 | ||
f86f3fb0 | 3035 | GEN5_IRQ_RESET(SDE); |
105b122e PZ |
3036 | |
3037 | if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev)) | |
3038 | I915_WRITE(SERR_INT, 0xffffffff); | |
622364b6 | 3039 | } |
105b122e | 3040 | |
622364b6 PZ |
3041 | /* |
3042 | * SDEIER is also touched by the interrupt handler to work around missed PCH | |
3043 | * interrupts. Hence we can't update it after the interrupt handler is enabled - | |
3044 | * instead we unconditionally enable all PCH interrupt sources here, but then | |
3045 | * only unmask them as needed with SDEIMR. | |
3046 | * | |
3047 | * This function needs to be called before interrupts are enabled. | |
3048 | */ | |
3049 | static void ibx_irq_pre_postinstall(struct drm_device *dev) | |
3050 | { | |
3051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3052 | ||
3053 | if (HAS_PCH_NOP(dev)) | |
3054 | return; | |
3055 | ||
3056 | WARN_ON(I915_READ(SDEIER) != 0); | |
91738a95 PZ |
3057 | I915_WRITE(SDEIER, 0xffffffff); |
3058 | POSTING_READ(SDEIER); | |
3059 | } | |
3060 | ||
7c4d664e | 3061 | static void gen5_gt_irq_reset(struct drm_device *dev) |
d18ea1b5 DV |
3062 | { |
3063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3064 | ||
f86f3fb0 | 3065 | GEN5_IRQ_RESET(GT); |
a9d356a6 | 3066 | if (INTEL_INFO(dev)->gen >= 6) |
f86f3fb0 | 3067 | GEN5_IRQ_RESET(GEN6_PM); |
d18ea1b5 DV |
3068 | } |
3069 | ||
1da177e4 LT |
3070 | /* drm_dma.h hooks |
3071 | */ | |
be30b29f | 3072 | static void ironlake_irq_reset(struct drm_device *dev) |
036a4a7d | 3073 | { |
2d1013dd | 3074 | struct drm_i915_private *dev_priv = dev->dev_private; |
036a4a7d | 3075 | |
0c841212 | 3076 | I915_WRITE(HWSTAM, 0xffffffff); |
bdfcdb63 | 3077 | |
f86f3fb0 | 3078 | GEN5_IRQ_RESET(DE); |
c6d954c1 PZ |
3079 | if (IS_GEN7(dev)) |
3080 | I915_WRITE(GEN7_ERR_INT, 0xffffffff); | |
036a4a7d | 3081 | |
7c4d664e | 3082 | gen5_gt_irq_reset(dev); |
c650156a | 3083 | |
1c69eb42 | 3084 | ibx_irq_reset(dev); |
7d99163d | 3085 | } |
c650156a | 3086 | |
70591a41 VS |
3087 | static void vlv_display_irq_reset(struct drm_i915_private *dev_priv) |
3088 | { | |
3089 | enum pipe pipe; | |
3090 | ||
0706f17c | 3091 | i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0); |
70591a41 VS |
3092 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3093 | ||
3094 | for_each_pipe(dev_priv, pipe) | |
3095 | I915_WRITE(PIPESTAT(pipe), 0xffff); | |
3096 | ||
3097 | GEN5_IRQ_RESET(VLV_); | |
3098 | } | |
3099 | ||
7e231dbe JB |
3100 | static void valleyview_irq_preinstall(struct drm_device *dev) |
3101 | { | |
2d1013dd | 3102 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe | 3103 | |
7e231dbe JB |
3104 | /* VLV magic */ |
3105 | I915_WRITE(VLV_IMR, 0); | |
3106 | I915_WRITE(RING_IMR(RENDER_RING_BASE), 0); | |
3107 | I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0); | |
3108 | I915_WRITE(RING_IMR(BLT_RING_BASE), 0); | |
3109 | ||
7c4d664e | 3110 | gen5_gt_irq_reset(dev); |
7e231dbe | 3111 | |
7c4cde39 | 3112 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); |
7e231dbe | 3113 | |
70591a41 | 3114 | vlv_display_irq_reset(dev_priv); |
7e231dbe JB |
3115 | } |
3116 | ||
d6e3cca3 DV |
3117 | static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv) |
3118 | { | |
3119 | GEN8_IRQ_RESET_NDX(GT, 0); | |
3120 | GEN8_IRQ_RESET_NDX(GT, 1); | |
3121 | GEN8_IRQ_RESET_NDX(GT, 2); | |
3122 | GEN8_IRQ_RESET_NDX(GT, 3); | |
3123 | } | |
3124 | ||
823f6b38 | 3125 | static void gen8_irq_reset(struct drm_device *dev) |
abd58f01 BW |
3126 | { |
3127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3128 | int pipe; | |
3129 | ||
abd58f01 BW |
3130 | I915_WRITE(GEN8_MASTER_IRQ, 0); |
3131 | POSTING_READ(GEN8_MASTER_IRQ); | |
3132 | ||
d6e3cca3 | 3133 | gen8_gt_irq_reset(dev_priv); |
abd58f01 | 3134 | |
055e393f | 3135 | for_each_pipe(dev_priv, pipe) |
f458ebbc DV |
3136 | if (intel_display_power_is_enabled(dev_priv, |
3137 | POWER_DOMAIN_PIPE(pipe))) | |
813bde43 | 3138 | GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); |
abd58f01 | 3139 | |
f86f3fb0 PZ |
3140 | GEN5_IRQ_RESET(GEN8_DE_PORT_); |
3141 | GEN5_IRQ_RESET(GEN8_DE_MISC_); | |
3142 | GEN5_IRQ_RESET(GEN8_PCU_); | |
abd58f01 | 3143 | |
266ea3d9 SS |
3144 | if (HAS_PCH_SPLIT(dev)) |
3145 | ibx_irq_reset(dev); | |
abd58f01 | 3146 | } |
09f2344d | 3147 | |
4c6c03be DL |
3148 | void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, |
3149 | unsigned int pipe_mask) | |
d49bdb0e | 3150 | { |
1180e206 | 3151 | uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; |
d49bdb0e | 3152 | |
13321786 | 3153 | spin_lock_irq(&dev_priv->irq_lock); |
d14c0343 DL |
3154 | if (pipe_mask & 1 << PIPE_A) |
3155 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, | |
3156 | dev_priv->de_irq_mask[PIPE_A], | |
3157 | ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); | |
4c6c03be DL |
3158 | if (pipe_mask & 1 << PIPE_B) |
3159 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, | |
3160 | dev_priv->de_irq_mask[PIPE_B], | |
3161 | ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); | |
3162 | if (pipe_mask & 1 << PIPE_C) | |
3163 | GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, | |
3164 | dev_priv->de_irq_mask[PIPE_C], | |
3165 | ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); | |
13321786 | 3166 | spin_unlock_irq(&dev_priv->irq_lock); |
d49bdb0e PZ |
3167 | } |
3168 | ||
43f328d7 VS |
3169 | static void cherryview_irq_preinstall(struct drm_device *dev) |
3170 | { | |
3171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3172 | |
3173 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3174 | POSTING_READ(GEN8_MASTER_IRQ); | |
3175 | ||
d6e3cca3 | 3176 | gen8_gt_irq_reset(dev_priv); |
43f328d7 VS |
3177 | |
3178 | GEN5_IRQ_RESET(GEN8_PCU_); | |
3179 | ||
43f328d7 VS |
3180 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV); |
3181 | ||
70591a41 | 3182 | vlv_display_irq_reset(dev_priv); |
43f328d7 VS |
3183 | } |
3184 | ||
87a02106 VS |
3185 | static u32 intel_hpd_enabled_irqs(struct drm_device *dev, |
3186 | const u32 hpd[HPD_NUM_PINS]) | |
3187 | { | |
3188 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3189 | struct intel_encoder *encoder; | |
3190 | u32 enabled_irqs = 0; | |
3191 | ||
3192 | for_each_intel_encoder(dev, encoder) | |
3193 | if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED) | |
3194 | enabled_irqs |= hpd[encoder->hpd_pin]; | |
3195 | ||
3196 | return enabled_irqs; | |
3197 | } | |
3198 | ||
82a28bcf | 3199 | static void ibx_hpd_irq_setup(struct drm_device *dev) |
7fe0b973 | 3200 | { |
2d1013dd | 3201 | struct drm_i915_private *dev_priv = dev->dev_private; |
87a02106 | 3202 | u32 hotplug_irqs, hotplug, enabled_irqs; |
82a28bcf DV |
3203 | |
3204 | if (HAS_PCH_IBX(dev)) { | |
fee884ed | 3205 | hotplug_irqs = SDE_HOTPLUG_MASK; |
87a02106 | 3206 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx); |
82a28bcf | 3207 | } else { |
fee884ed | 3208 | hotplug_irqs = SDE_HOTPLUG_MASK_CPT; |
87a02106 | 3209 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt); |
82a28bcf | 3210 | } |
7fe0b973 | 3211 | |
fee884ed | 3212 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); |
82a28bcf DV |
3213 | |
3214 | /* | |
3215 | * Enable digital hotplug on the PCH, and configure the DP short pulse | |
6dbf30ce VS |
3216 | * duration to 2ms (which is the minimum in the Display Port spec). |
3217 | * The pulse duration bits are reserved on LPT+. | |
82a28bcf | 3218 | */ |
7fe0b973 KP |
3219 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3220 | hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK); | |
3221 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms; | |
3222 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms; | |
3223 | hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms; | |
0b2eb33e VS |
3224 | /* |
3225 | * When CPU and PCH are on the same package, port A | |
3226 | * HPD must be enabled in both north and south. | |
3227 | */ | |
3228 | if (HAS_PCH_LPT_LP(dev)) | |
3229 | hotplug |= PORTA_HOTPLUG_ENABLE; | |
7fe0b973 | 3230 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
6dbf30ce | 3231 | } |
26951caf | 3232 | |
6dbf30ce VS |
3233 | static void spt_hpd_irq_setup(struct drm_device *dev) |
3234 | { | |
3235 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3236 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3237 | ||
3238 | hotplug_irqs = SDE_HOTPLUG_MASK_SPT; | |
3239 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt); | |
3240 | ||
3241 | ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs); | |
3242 | ||
3243 | /* Enable digital hotplug on the PCH */ | |
3244 | hotplug = I915_READ(PCH_PORT_HOTPLUG); | |
3245 | hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE | | |
74c0b395 | 3246 | PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE; |
6dbf30ce VS |
3247 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); |
3248 | ||
3249 | hotplug = I915_READ(PCH_PORT_HOTPLUG2); | |
3250 | hotplug |= PORTE_HOTPLUG_ENABLE; | |
3251 | I915_WRITE(PCH_PORT_HOTPLUG2, hotplug); | |
7fe0b973 KP |
3252 | } |
3253 | ||
e4ce95aa VS |
3254 | static void ilk_hpd_irq_setup(struct drm_device *dev) |
3255 | { | |
3256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3257 | u32 hotplug_irqs, hotplug, enabled_irqs; | |
3258 | ||
3a3b3c7d VS |
3259 | if (INTEL_INFO(dev)->gen >= 8) { |
3260 | hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG; | |
3261 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw); | |
3262 | ||
3263 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
3264 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
23bb4cb5 VS |
3265 | hotplug_irqs = DE_DP_A_HOTPLUG_IVB; |
3266 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb); | |
3a3b3c7d VS |
3267 | |
3268 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); | |
23bb4cb5 VS |
3269 | } else { |
3270 | hotplug_irqs = DE_DP_A_HOTPLUG; | |
3271 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk); | |
e4ce95aa | 3272 | |
3a3b3c7d VS |
3273 | ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs); |
3274 | } | |
e4ce95aa VS |
3275 | |
3276 | /* | |
3277 | * Enable digital hotplug on the CPU, and configure the DP short pulse | |
3278 | * duration to 2ms (which is the minimum in the Display Port spec) | |
23bb4cb5 | 3279 | * The pulse duration bits are reserved on HSW+. |
e4ce95aa VS |
3280 | */ |
3281 | hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL); | |
3282 | hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK; | |
3283 | hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms; | |
3284 | I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug); | |
3285 | ||
3286 | ibx_hpd_irq_setup(dev); | |
3287 | } | |
3288 | ||
e0a20ad7 SS |
3289 | static void bxt_hpd_irq_setup(struct drm_device *dev) |
3290 | { | |
3291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a52bb15b | 3292 | u32 hotplug_irqs, hotplug, enabled_irqs; |
e0a20ad7 | 3293 | |
a52bb15b VS |
3294 | enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt); |
3295 | hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK; | |
e0a20ad7 | 3296 | |
a52bb15b | 3297 | bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs); |
e0a20ad7 | 3298 | |
a52bb15b VS |
3299 | hotplug = I915_READ(PCH_PORT_HOTPLUG); |
3300 | hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE | | |
3301 | PORTA_HOTPLUG_ENABLE; | |
3302 | I915_WRITE(PCH_PORT_HOTPLUG, hotplug); | |
e0a20ad7 SS |
3303 | } |
3304 | ||
d46da437 PZ |
3305 | static void ibx_irq_postinstall(struct drm_device *dev) |
3306 | { | |
2d1013dd | 3307 | struct drm_i915_private *dev_priv = dev->dev_private; |
82a28bcf | 3308 | u32 mask; |
e5868a31 | 3309 | |
692a04cf DV |
3310 | if (HAS_PCH_NOP(dev)) |
3311 | return; | |
3312 | ||
105b122e | 3313 | if (HAS_PCH_IBX(dev)) |
5c673b60 | 3314 | mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON; |
105b122e | 3315 | else |
5c673b60 | 3316 | mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT; |
8664281b | 3317 | |
337ba017 | 3318 | GEN5_ASSERT_IIR_IS_ZERO(SDEIIR); |
d46da437 | 3319 | I915_WRITE(SDEIMR, ~mask); |
d46da437 PZ |
3320 | } |
3321 | ||
0a9a8c91 DV |
3322 | static void gen5_gt_irq_postinstall(struct drm_device *dev) |
3323 | { | |
3324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3325 | u32 pm_irqs, gt_irqs; | |
3326 | ||
3327 | pm_irqs = gt_irqs = 0; | |
3328 | ||
3329 | dev_priv->gt_irq_mask = ~0; | |
040d2baa | 3330 | if (HAS_L3_DPF(dev)) { |
0a9a8c91 | 3331 | /* L3 parity interrupt is always unmasked. */ |
35a85ac6 BW |
3332 | dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev); |
3333 | gt_irqs |= GT_PARITY_ERROR(dev); | |
0a9a8c91 DV |
3334 | } |
3335 | ||
3336 | gt_irqs |= GT_RENDER_USER_INTERRUPT; | |
3337 | if (IS_GEN5(dev)) { | |
3338 | gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT | | |
3339 | ILK_BSD_USER_INTERRUPT; | |
3340 | } else { | |
3341 | gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT; | |
3342 | } | |
3343 | ||
35079899 | 3344 | GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs); |
0a9a8c91 DV |
3345 | |
3346 | if (INTEL_INFO(dev)->gen >= 6) { | |
78e68d36 ID |
3347 | /* |
3348 | * RPS interrupts will get enabled/disabled on demand when RPS | |
3349 | * itself is enabled/disabled. | |
3350 | */ | |
0a9a8c91 DV |
3351 | if (HAS_VEBOX(dev)) |
3352 | pm_irqs |= PM_VEBOX_USER_INTERRUPT; | |
3353 | ||
605cd25b | 3354 | dev_priv->pm_irq_mask = 0xffffffff; |
35079899 | 3355 | GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs); |
0a9a8c91 DV |
3356 | } |
3357 | } | |
3358 | ||
f71d4af4 | 3359 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d | 3360 | { |
2d1013dd | 3361 | struct drm_i915_private *dev_priv = dev->dev_private; |
8e76f8dc PZ |
3362 | u32 display_mask, extra_mask; |
3363 | ||
3364 | if (INTEL_INFO(dev)->gen >= 7) { | |
3365 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
3366 | DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB | | |
3367 | DE_PLANEB_FLIP_DONE_IVB | | |
5c673b60 | 3368 | DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB); |
8e76f8dc | 3369 | extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB | |
23bb4cb5 VS |
3370 | DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB | |
3371 | DE_DP_A_HOTPLUG_IVB); | |
8e76f8dc PZ |
3372 | } else { |
3373 | display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | | |
3374 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE | | |
5b3a856b | 3375 | DE_AUX_CHANNEL_A | |
5b3a856b DV |
3376 | DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE | |
3377 | DE_POISON); | |
e4ce95aa VS |
3378 | extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT | |
3379 | DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN | | |
3380 | DE_DP_A_HOTPLUG); | |
8e76f8dc | 3381 | } |
036a4a7d | 3382 | |
1ec14ad3 | 3383 | dev_priv->irq_mask = ~display_mask; |
036a4a7d | 3384 | |
0c841212 PZ |
3385 | I915_WRITE(HWSTAM, 0xeffe); |
3386 | ||
622364b6 PZ |
3387 | ibx_irq_pre_postinstall(dev); |
3388 | ||
35079899 | 3389 | GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask); |
036a4a7d | 3390 | |
0a9a8c91 | 3391 | gen5_gt_irq_postinstall(dev); |
036a4a7d | 3392 | |
d46da437 | 3393 | ibx_irq_postinstall(dev); |
7fe0b973 | 3394 | |
f97108d1 | 3395 | if (IS_IRONLAKE_M(dev)) { |
6005ce42 DV |
3396 | /* Enable PCU event interrupts |
3397 | * | |
3398 | * spinlocking not required here for correctness since interrupt | |
4bc9d430 DV |
3399 | * setup is guaranteed to run in single-threaded context. But we |
3400 | * need it to make the assert_spin_locked happy. */ | |
d6207435 | 3401 | spin_lock_irq(&dev_priv->irq_lock); |
f97108d1 | 3402 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); |
d6207435 | 3403 | spin_unlock_irq(&dev_priv->irq_lock); |
f97108d1 JB |
3404 | } |
3405 | ||
036a4a7d ZW |
3406 | return 0; |
3407 | } | |
3408 | ||
f8b79e58 ID |
3409 | static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv) |
3410 | { | |
3411 | u32 pipestat_mask; | |
3412 | u32 iir_mask; | |
120dda4f | 3413 | enum pipe pipe; |
f8b79e58 ID |
3414 | |
3415 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3416 | PIPE_FIFO_UNDERRUN_STATUS; | |
3417 | ||
120dda4f VS |
3418 | for_each_pipe(dev_priv, pipe) |
3419 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3420 | POSTING_READ(PIPESTAT(PIPE_A)); |
3421 | ||
3422 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3423 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3424 | ||
120dda4f VS |
3425 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3426 | for_each_pipe(dev_priv, pipe) | |
3427 | i915_enable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3428 | |
3429 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3430 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3431 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; | |
120dda4f VS |
3432 | if (IS_CHERRYVIEW(dev_priv)) |
3433 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3434 | dev_priv->irq_mask &= ~iir_mask; |
3435 | ||
3436 | I915_WRITE(VLV_IIR, iir_mask); | |
3437 | I915_WRITE(VLV_IIR, iir_mask); | |
f8b79e58 | 3438 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
76e41860 VS |
3439 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
3440 | POSTING_READ(VLV_IMR); | |
f8b79e58 ID |
3441 | } |
3442 | ||
3443 | static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv) | |
3444 | { | |
3445 | u32 pipestat_mask; | |
3446 | u32 iir_mask; | |
120dda4f | 3447 | enum pipe pipe; |
f8b79e58 ID |
3448 | |
3449 | iir_mask = I915_DISPLAY_PORT_INTERRUPT | | |
3450 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
6c7fba04 | 3451 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT; |
120dda4f VS |
3452 | if (IS_CHERRYVIEW(dev_priv)) |
3453 | iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT; | |
f8b79e58 ID |
3454 | |
3455 | dev_priv->irq_mask |= iir_mask; | |
f8b79e58 | 3456 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); |
76e41860 | 3457 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); |
f8b79e58 ID |
3458 | I915_WRITE(VLV_IIR, iir_mask); |
3459 | I915_WRITE(VLV_IIR, iir_mask); | |
3460 | POSTING_READ(VLV_IIR); | |
3461 | ||
3462 | pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV | | |
3463 | PIPE_CRC_DONE_INTERRUPT_STATUS; | |
3464 | ||
120dda4f VS |
3465 | i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
3466 | for_each_pipe(dev_priv, pipe) | |
3467 | i915_disable_pipestat(dev_priv, pipe, pipestat_mask); | |
f8b79e58 ID |
3468 | |
3469 | pipestat_mask = PIPESTAT_INT_STATUS_MASK | | |
3470 | PIPE_FIFO_UNDERRUN_STATUS; | |
120dda4f VS |
3471 | |
3472 | for_each_pipe(dev_priv, pipe) | |
3473 | I915_WRITE(PIPESTAT(pipe), pipestat_mask); | |
f8b79e58 ID |
3474 | POSTING_READ(PIPESTAT(PIPE_A)); |
3475 | } | |
3476 | ||
3477 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv) | |
3478 | { | |
3479 | assert_spin_locked(&dev_priv->irq_lock); | |
3480 | ||
3481 | if (dev_priv->display_irqs_enabled) | |
3482 | return; | |
3483 | ||
3484 | dev_priv->display_irqs_enabled = true; | |
3485 | ||
950eabaf | 3486 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3487 | valleyview_display_irqs_install(dev_priv); |
3488 | } | |
3489 | ||
3490 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) | |
3491 | { | |
3492 | assert_spin_locked(&dev_priv->irq_lock); | |
3493 | ||
3494 | if (!dev_priv->display_irqs_enabled) | |
3495 | return; | |
3496 | ||
3497 | dev_priv->display_irqs_enabled = false; | |
3498 | ||
950eabaf | 3499 | if (intel_irqs_enabled(dev_priv)) |
f8b79e58 ID |
3500 | valleyview_display_irqs_uninstall(dev_priv); |
3501 | } | |
3502 | ||
0e6c9a9e | 3503 | static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv) |
7e231dbe | 3504 | { |
f8b79e58 | 3505 | dev_priv->irq_mask = ~0; |
7e231dbe | 3506 | |
0706f17c | 3507 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3508 | POSTING_READ(PORT_HOTPLUG_EN); |
3509 | ||
7e231dbe | 3510 | I915_WRITE(VLV_IIR, 0xffffffff); |
76e41860 VS |
3511 | I915_WRITE(VLV_IIR, 0xffffffff); |
3512 | I915_WRITE(VLV_IER, ~dev_priv->irq_mask); | |
3513 | I915_WRITE(VLV_IMR, dev_priv->irq_mask); | |
3514 | POSTING_READ(VLV_IMR); | |
7e231dbe | 3515 | |
b79480ba DV |
3516 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3517 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3518 | spin_lock_irq(&dev_priv->irq_lock); |
f8b79e58 ID |
3519 | if (dev_priv->display_irqs_enabled) |
3520 | valleyview_display_irqs_install(dev_priv); | |
d6207435 | 3521 | spin_unlock_irq(&dev_priv->irq_lock); |
0e6c9a9e VS |
3522 | } |
3523 | ||
3524 | static int valleyview_irq_postinstall(struct drm_device *dev) | |
3525 | { | |
3526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3527 | ||
3528 | vlv_display_irq_postinstall(dev_priv); | |
7e231dbe | 3529 | |
0a9a8c91 | 3530 | gen5_gt_irq_postinstall(dev); |
7e231dbe JB |
3531 | |
3532 | /* ack & enable invalid PTE error interrupts */ | |
3533 | #if 0 /* FIXME: add support to irq handler for checking these bits */ | |
3534 | I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK); | |
3535 | I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK); | |
3536 | #endif | |
3537 | ||
3538 | I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE); | |
20afbda2 DV |
3539 | |
3540 | return 0; | |
3541 | } | |
3542 | ||
abd58f01 BW |
3543 | static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv) |
3544 | { | |
abd58f01 BW |
3545 | /* These are interrupts we'll toggle with the ring mask register */ |
3546 | uint32_t gt_interrupts[] = { | |
3547 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT | | |
73d477f6 | 3548 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT | |
abd58f01 | 3549 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT | |
73d477f6 OM |
3550 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT | |
3551 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT, | |
abd58f01 | 3552 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
73d477f6 OM |
3553 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT | |
3554 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT | | |
3555 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT, | |
abd58f01 | 3556 | 0, |
73d477f6 OM |
3557 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
3558 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT | |
abd58f01 BW |
3559 | }; |
3560 | ||
0961021a | 3561 | dev_priv->pm_irq_mask = 0xffffffff; |
9a2d2d87 D |
3562 | GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]); |
3563 | GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]); | |
78e68d36 ID |
3564 | /* |
3565 | * RPS interrupts will get enabled/disabled on demand when RPS itself | |
3566 | * is enabled/disabled. | |
3567 | */ | |
3568 | GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0); | |
9a2d2d87 | 3569 | GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]); |
abd58f01 BW |
3570 | } |
3571 | ||
3572 | static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) | |
3573 | { | |
770de83d DL |
3574 | uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE; |
3575 | uint32_t de_pipe_enables; | |
3a3b3c7d VS |
3576 | u32 de_port_masked = GEN8_AUX_CHANNEL_A; |
3577 | u32 de_port_enables; | |
3578 | enum pipe pipe; | |
770de83d | 3579 | |
b4834a50 | 3580 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
770de83d DL |
3581 | de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | |
3582 | GEN9_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d VS |
3583 | de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | |
3584 | GEN9_AUX_CHANNEL_D; | |
9e63743e | 3585 | if (IS_BROXTON(dev_priv)) |
3a3b3c7d VS |
3586 | de_port_masked |= BXT_DE_PORT_GMBUS; |
3587 | } else { | |
770de83d DL |
3588 | de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | |
3589 | GEN8_DE_PIPE_IRQ_FAULT_ERRORS; | |
3a3b3c7d | 3590 | } |
770de83d DL |
3591 | |
3592 | de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | | |
3593 | GEN8_PIPE_FIFO_UNDERRUN; | |
3594 | ||
3a3b3c7d | 3595 | de_port_enables = de_port_masked; |
a52bb15b VS |
3596 | if (IS_BROXTON(dev_priv)) |
3597 | de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK; | |
3598 | else if (IS_BROADWELL(dev_priv)) | |
3a3b3c7d VS |
3599 | de_port_enables |= GEN8_PORT_DP_A_HOTPLUG; |
3600 | ||
13b3a0a7 DV |
3601 | dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; |
3602 | dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked; | |
3603 | dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked; | |
abd58f01 | 3604 | |
055e393f | 3605 | for_each_pipe(dev_priv, pipe) |
f458ebbc | 3606 | if (intel_display_power_is_enabled(dev_priv, |
813bde43 PZ |
3607 | POWER_DOMAIN_PIPE(pipe))) |
3608 | GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, | |
3609 | dev_priv->de_irq_mask[pipe], | |
3610 | de_pipe_enables); | |
abd58f01 | 3611 | |
3a3b3c7d | 3612 | GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables); |
abd58f01 BW |
3613 | } |
3614 | ||
3615 | static int gen8_irq_postinstall(struct drm_device *dev) | |
3616 | { | |
3617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3618 | ||
266ea3d9 SS |
3619 | if (HAS_PCH_SPLIT(dev)) |
3620 | ibx_irq_pre_postinstall(dev); | |
622364b6 | 3621 | |
abd58f01 BW |
3622 | gen8_gt_irq_postinstall(dev_priv); |
3623 | gen8_de_irq_postinstall(dev_priv); | |
3624 | ||
266ea3d9 SS |
3625 | if (HAS_PCH_SPLIT(dev)) |
3626 | ibx_irq_postinstall(dev); | |
abd58f01 BW |
3627 | |
3628 | I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL); | |
3629 | POSTING_READ(GEN8_MASTER_IRQ); | |
3630 | ||
3631 | return 0; | |
3632 | } | |
3633 | ||
43f328d7 VS |
3634 | static int cherryview_irq_postinstall(struct drm_device *dev) |
3635 | { | |
3636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 | 3637 | |
c2b66797 | 3638 | vlv_display_irq_postinstall(dev_priv); |
43f328d7 VS |
3639 | |
3640 | gen8_gt_irq_postinstall(dev_priv); | |
3641 | ||
3642 | I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE); | |
3643 | POSTING_READ(GEN8_MASTER_IRQ); | |
3644 | ||
3645 | return 0; | |
3646 | } | |
3647 | ||
abd58f01 BW |
3648 | static void gen8_irq_uninstall(struct drm_device *dev) |
3649 | { | |
3650 | struct drm_i915_private *dev_priv = dev->dev_private; | |
abd58f01 BW |
3651 | |
3652 | if (!dev_priv) | |
3653 | return; | |
3654 | ||
823f6b38 | 3655 | gen8_irq_reset(dev); |
abd58f01 BW |
3656 | } |
3657 | ||
8ea0be4f VS |
3658 | static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv) |
3659 | { | |
3660 | /* Interrupt setup is already guaranteed to be single-threaded, this is | |
3661 | * just to make the assert_spin_locked check happy. */ | |
3662 | spin_lock_irq(&dev_priv->irq_lock); | |
3663 | if (dev_priv->display_irqs_enabled) | |
3664 | valleyview_display_irqs_uninstall(dev_priv); | |
3665 | spin_unlock_irq(&dev_priv->irq_lock); | |
3666 | ||
3667 | vlv_display_irq_reset(dev_priv); | |
3668 | ||
c352d1ba | 3669 | dev_priv->irq_mask = ~0; |
8ea0be4f VS |
3670 | } |
3671 | ||
7e231dbe JB |
3672 | static void valleyview_irq_uninstall(struct drm_device *dev) |
3673 | { | |
2d1013dd | 3674 | struct drm_i915_private *dev_priv = dev->dev_private; |
7e231dbe JB |
3675 | |
3676 | if (!dev_priv) | |
3677 | return; | |
3678 | ||
843d0e7d ID |
3679 | I915_WRITE(VLV_MASTER_IER, 0); |
3680 | ||
893fce8e VS |
3681 | gen5_gt_irq_reset(dev); |
3682 | ||
7e231dbe | 3683 | I915_WRITE(HWSTAM, 0xffffffff); |
f8b79e58 | 3684 | |
8ea0be4f | 3685 | vlv_display_irq_uninstall(dev_priv); |
7e231dbe JB |
3686 | } |
3687 | ||
43f328d7 VS |
3688 | static void cherryview_irq_uninstall(struct drm_device *dev) |
3689 | { | |
3690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
43f328d7 VS |
3691 | |
3692 | if (!dev_priv) | |
3693 | return; | |
3694 | ||
3695 | I915_WRITE(GEN8_MASTER_IRQ, 0); | |
3696 | POSTING_READ(GEN8_MASTER_IRQ); | |
3697 | ||
a2c30fba | 3698 | gen8_gt_irq_reset(dev_priv); |
43f328d7 | 3699 | |
a2c30fba | 3700 | GEN5_IRQ_RESET(GEN8_PCU_); |
43f328d7 | 3701 | |
c2b66797 | 3702 | vlv_display_irq_uninstall(dev_priv); |
43f328d7 VS |
3703 | } |
3704 | ||
f71d4af4 | 3705 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d | 3706 | { |
2d1013dd | 3707 | struct drm_i915_private *dev_priv = dev->dev_private; |
4697995b JB |
3708 | |
3709 | if (!dev_priv) | |
3710 | return; | |
3711 | ||
be30b29f | 3712 | ironlake_irq_reset(dev); |
036a4a7d ZW |
3713 | } |
3714 | ||
a266c7d5 | 3715 | static void i8xx_irq_preinstall(struct drm_device * dev) |
1da177e4 | 3716 | { |
2d1013dd | 3717 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 3718 | int pipe; |
91e3738e | 3719 | |
055e393f | 3720 | for_each_pipe(dev_priv, pipe) |
9db4a9c7 | 3721 | I915_WRITE(PIPESTAT(pipe), 0); |
a266c7d5 CW |
3722 | I915_WRITE16(IMR, 0xffff); |
3723 | I915_WRITE16(IER, 0x0); | |
3724 | POSTING_READ16(IER); | |
c2798b19 CW |
3725 | } |
3726 | ||
3727 | static int i8xx_irq_postinstall(struct drm_device *dev) | |
3728 | { | |
2d1013dd | 3729 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 | 3730 | |
c2798b19 CW |
3731 | I915_WRITE16(EMR, |
3732 | ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); | |
3733 | ||
3734 | /* Unmask the interrupts that we always want on. */ | |
3735 | dev_priv->irq_mask = | |
3736 | ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3737 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3738 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3739 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
c2798b19 CW |
3740 | I915_WRITE16(IMR, dev_priv->irq_mask); |
3741 | ||
3742 | I915_WRITE16(IER, | |
3743 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3744 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
c2798b19 CW |
3745 | I915_USER_INTERRUPT); |
3746 | POSTING_READ16(IER); | |
3747 | ||
379ef82d DV |
3748 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3749 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3750 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3751 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3752 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3753 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3754 | |
c2798b19 CW |
3755 | return 0; |
3756 | } | |
3757 | ||
90a72f87 VS |
3758 | /* |
3759 | * Returns true when a page flip has completed. | |
3760 | */ | |
3761 | static bool i8xx_handle_vblank(struct drm_device *dev, | |
1f1c2e24 | 3762 | int plane, int pipe, u32 iir) |
90a72f87 | 3763 | { |
2d1013dd | 3764 | struct drm_i915_private *dev_priv = dev->dev_private; |
1f1c2e24 | 3765 | u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
90a72f87 | 3766 | |
8d7849db | 3767 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3768 | return false; |
3769 | ||
3770 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3771 | goto check_page_flip; |
90a72f87 | 3772 | |
90a72f87 VS |
3773 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3774 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3775 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3776 | * the flip is completed (no longer pending). Since this doesn't raise | |
3777 | * an interrupt per se, we watch for the change at vblank. | |
3778 | */ | |
3779 | if (I915_READ16(ISR) & flip_pending) | |
d6bbafa1 | 3780 | goto check_page_flip; |
90a72f87 | 3781 | |
7d47559e | 3782 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3783 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3784 | return true; |
d6bbafa1 CW |
3785 | |
3786 | check_page_flip: | |
3787 | intel_check_page_flip(dev, pipe); | |
3788 | return false; | |
90a72f87 VS |
3789 | } |
3790 | ||
ff1f525e | 3791 | static irqreturn_t i8xx_irq_handler(int irq, void *arg) |
c2798b19 | 3792 | { |
45a83f84 | 3793 | struct drm_device *dev = arg; |
2d1013dd | 3794 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3795 | u16 iir, new_iir; |
3796 | u32 pipe_stats[2]; | |
c2798b19 CW |
3797 | int pipe; |
3798 | u16 flip_mask = | |
3799 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3800 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
3801 | ||
2dd2a883 ID |
3802 | if (!intel_irqs_enabled(dev_priv)) |
3803 | return IRQ_NONE; | |
3804 | ||
c2798b19 CW |
3805 | iir = I915_READ16(IIR); |
3806 | if (iir == 0) | |
3807 | return IRQ_NONE; | |
3808 | ||
3809 | while (iir & ~flip_mask) { | |
3810 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3811 | * have been cleared after the pipestat interrupt was received. | |
3812 | * It doesn't set the bit in iir again, but it still produces | |
3813 | * interrupts (for non-MSI). | |
3814 | */ | |
222c7f51 | 3815 | spin_lock(&dev_priv->irq_lock); |
c2798b19 | 3816 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3817 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
c2798b19 | 3818 | |
055e393f | 3819 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3820 | int reg = PIPESTAT(pipe); |
3821 | pipe_stats[pipe] = I915_READ(reg); | |
3822 | ||
3823 | /* | |
3824 | * Clear the PIPE*STAT regs before the IIR | |
3825 | */ | |
2d9d2b0b | 3826 | if (pipe_stats[pipe] & 0x8000ffff) |
c2798b19 | 3827 | I915_WRITE(reg, pipe_stats[pipe]); |
c2798b19 | 3828 | } |
222c7f51 | 3829 | spin_unlock(&dev_priv->irq_lock); |
c2798b19 CW |
3830 | |
3831 | I915_WRITE16(IIR, iir & ~flip_mask); | |
3832 | new_iir = I915_READ16(IIR); /* Flush posted writes */ | |
3833 | ||
c2798b19 | 3834 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 3835 | notify_ring(&dev_priv->ring[RCS]); |
c2798b19 | 3836 | |
055e393f | 3837 | for_each_pipe(dev_priv, pipe) { |
1f1c2e24 | 3838 | int plane = pipe; |
3a77c4c4 | 3839 | if (HAS_FBC(dev)) |
1f1c2e24 VS |
3840 | plane = !plane; |
3841 | ||
4356d586 | 3842 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
1f1c2e24 VS |
3843 | i8xx_handle_vblank(dev, plane, pipe, iir)) |
3844 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
c2798b19 | 3845 | |
4356d586 | 3846 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) |
277de95e | 3847 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 3848 | |
1f7247c0 DV |
3849 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
3850 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
3851 | pipe); | |
4356d586 | 3852 | } |
c2798b19 CW |
3853 | |
3854 | iir = new_iir; | |
3855 | } | |
3856 | ||
3857 | return IRQ_HANDLED; | |
3858 | } | |
3859 | ||
3860 | static void i8xx_irq_uninstall(struct drm_device * dev) | |
3861 | { | |
2d1013dd | 3862 | struct drm_i915_private *dev_priv = dev->dev_private; |
c2798b19 CW |
3863 | int pipe; |
3864 | ||
055e393f | 3865 | for_each_pipe(dev_priv, pipe) { |
c2798b19 CW |
3866 | /* Clear enable bits; then clear status bits */ |
3867 | I915_WRITE(PIPESTAT(pipe), 0); | |
3868 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); | |
3869 | } | |
3870 | I915_WRITE16(IMR, 0xffff); | |
3871 | I915_WRITE16(IER, 0x0); | |
3872 | I915_WRITE16(IIR, I915_READ16(IIR)); | |
3873 | } | |
3874 | ||
a266c7d5 CW |
3875 | static void i915_irq_preinstall(struct drm_device * dev) |
3876 | { | |
2d1013dd | 3877 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
3878 | int pipe; |
3879 | ||
a266c7d5 | 3880 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 3881 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
3882 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
3883 | } | |
3884 | ||
00d98ebd | 3885 | I915_WRITE16(HWSTAM, 0xeffe); |
055e393f | 3886 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
3887 | I915_WRITE(PIPESTAT(pipe), 0); |
3888 | I915_WRITE(IMR, 0xffffffff); | |
3889 | I915_WRITE(IER, 0x0); | |
3890 | POSTING_READ(IER); | |
3891 | } | |
3892 | ||
3893 | static int i915_irq_postinstall(struct drm_device *dev) | |
3894 | { | |
2d1013dd | 3895 | struct drm_i915_private *dev_priv = dev->dev_private; |
38bde180 | 3896 | u32 enable_mask; |
a266c7d5 | 3897 | |
38bde180 CW |
3898 | I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH)); |
3899 | ||
3900 | /* Unmask the interrupts that we always want on. */ | |
3901 | dev_priv->irq_mask = | |
3902 | ~(I915_ASLE_INTERRUPT | | |
3903 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3904 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
3905 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
37ef01ab | 3906 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); |
38bde180 CW |
3907 | |
3908 | enable_mask = | |
3909 | I915_ASLE_INTERRUPT | | |
3910 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | | |
3911 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
38bde180 CW |
3912 | I915_USER_INTERRUPT; |
3913 | ||
a266c7d5 | 3914 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 3915 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
3916 | POSTING_READ(PORT_HOTPLUG_EN); |
3917 | ||
a266c7d5 CW |
3918 | /* Enable in IER... */ |
3919 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
3920 | /* and unmask in IMR */ | |
3921 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; | |
3922 | } | |
3923 | ||
a266c7d5 CW |
3924 | I915_WRITE(IMR, dev_priv->irq_mask); |
3925 | I915_WRITE(IER, enable_mask); | |
3926 | POSTING_READ(IER); | |
3927 | ||
f49e38dd | 3928 | i915_enable_asle_pipestat(dev); |
20afbda2 | 3929 | |
379ef82d DV |
3930 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
3931 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 3932 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
3933 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); |
3934 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 3935 | spin_unlock_irq(&dev_priv->irq_lock); |
379ef82d | 3936 | |
20afbda2 DV |
3937 | return 0; |
3938 | } | |
3939 | ||
90a72f87 VS |
3940 | /* |
3941 | * Returns true when a page flip has completed. | |
3942 | */ | |
3943 | static bool i915_handle_vblank(struct drm_device *dev, | |
3944 | int plane, int pipe, u32 iir) | |
3945 | { | |
2d1013dd | 3946 | struct drm_i915_private *dev_priv = dev->dev_private; |
90a72f87 VS |
3947 | u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane); |
3948 | ||
8d7849db | 3949 | if (!intel_pipe_handle_vblank(dev, pipe)) |
90a72f87 VS |
3950 | return false; |
3951 | ||
3952 | if ((iir & flip_pending) == 0) | |
d6bbafa1 | 3953 | goto check_page_flip; |
90a72f87 | 3954 | |
90a72f87 VS |
3955 | /* We detect FlipDone by looking for the change in PendingFlip from '1' |
3956 | * to '0' on the following vblank, i.e. IIR has the Pendingflip | |
3957 | * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence | |
3958 | * the flip is completed (no longer pending). Since this doesn't raise | |
3959 | * an interrupt per se, we watch for the change at vblank. | |
3960 | */ | |
3961 | if (I915_READ(ISR) & flip_pending) | |
d6bbafa1 | 3962 | goto check_page_flip; |
90a72f87 | 3963 | |
7d47559e | 3964 | intel_prepare_page_flip(dev, plane); |
90a72f87 | 3965 | intel_finish_page_flip(dev, pipe); |
90a72f87 | 3966 | return true; |
d6bbafa1 CW |
3967 | |
3968 | check_page_flip: | |
3969 | intel_check_page_flip(dev, pipe); | |
3970 | return false; | |
90a72f87 VS |
3971 | } |
3972 | ||
ff1f525e | 3973 | static irqreturn_t i915_irq_handler(int irq, void *arg) |
a266c7d5 | 3974 | { |
45a83f84 | 3975 | struct drm_device *dev = arg; |
2d1013dd | 3976 | struct drm_i915_private *dev_priv = dev->dev_private; |
8291ee90 | 3977 | u32 iir, new_iir, pipe_stats[I915_MAX_PIPES]; |
38bde180 CW |
3978 | u32 flip_mask = |
3979 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
3980 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
38bde180 | 3981 | int pipe, ret = IRQ_NONE; |
a266c7d5 | 3982 | |
2dd2a883 ID |
3983 | if (!intel_irqs_enabled(dev_priv)) |
3984 | return IRQ_NONE; | |
3985 | ||
a266c7d5 | 3986 | iir = I915_READ(IIR); |
38bde180 CW |
3987 | do { |
3988 | bool irq_received = (iir & ~flip_mask) != 0; | |
8291ee90 | 3989 | bool blc_event = false; |
a266c7d5 CW |
3990 | |
3991 | /* Can't rely on pipestat interrupt bit in iir as it might | |
3992 | * have been cleared after the pipestat interrupt was received. | |
3993 | * It doesn't set the bit in iir again, but it still produces | |
3994 | * interrupts (for non-MSI). | |
3995 | */ | |
222c7f51 | 3996 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 3997 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 3998 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 3999 | |
055e393f | 4000 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4001 | int reg = PIPESTAT(pipe); |
4002 | pipe_stats[pipe] = I915_READ(reg); | |
4003 | ||
38bde180 | 4004 | /* Clear the PIPE*STAT regs before the IIR */ |
a266c7d5 | 4005 | if (pipe_stats[pipe] & 0x8000ffff) { |
a266c7d5 | 4006 | I915_WRITE(reg, pipe_stats[pipe]); |
38bde180 | 4007 | irq_received = true; |
a266c7d5 CW |
4008 | } |
4009 | } | |
222c7f51 | 4010 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4011 | |
4012 | if (!irq_received) | |
4013 | break; | |
4014 | ||
a266c7d5 | 4015 | /* Consume port. Then clear IIR or we'll miss events */ |
16c6c56b VS |
4016 | if (I915_HAS_HOTPLUG(dev) && |
4017 | iir & I915_DISPLAY_PORT_INTERRUPT) | |
4018 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4019 | |
38bde180 | 4020 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4021 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4022 | ||
a266c7d5 | 4023 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 4024 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 4025 | |
055e393f | 4026 | for_each_pipe(dev_priv, pipe) { |
38bde180 | 4027 | int plane = pipe; |
3a77c4c4 | 4028 | if (HAS_FBC(dev)) |
38bde180 | 4029 | plane = !plane; |
90a72f87 | 4030 | |
8291ee90 | 4031 | if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4032 | i915_handle_vblank(dev, plane, pipe, iir)) |
4033 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane); | |
a266c7d5 CW |
4034 | |
4035 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4036 | blc_event = true; | |
4356d586 DV |
4037 | |
4038 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4039 | i9xx_pipe_crc_irq_handler(dev, pipe); |
2d9d2b0b | 4040 | |
1f7247c0 DV |
4041 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4042 | intel_cpu_fifo_underrun_irq_handler(dev_priv, | |
4043 | pipe); | |
a266c7d5 CW |
4044 | } |
4045 | ||
a266c7d5 CW |
4046 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) |
4047 | intel_opregion_asle_intr(dev); | |
4048 | ||
4049 | /* With MSI, interrupts are only generated when iir | |
4050 | * transitions from zero to nonzero. If another bit got | |
4051 | * set while we were handling the existing iir bits, then | |
4052 | * we would never get another interrupt. | |
4053 | * | |
4054 | * This is fine on non-MSI as well, as if we hit this path | |
4055 | * we avoid exiting the interrupt handler only to generate | |
4056 | * another one. | |
4057 | * | |
4058 | * Note that for MSI this could cause a stray interrupt report | |
4059 | * if an interrupt landed in the time between writing IIR and | |
4060 | * the posting read. This should be rare enough to never | |
4061 | * trigger the 99% of 100,000 interrupts test for disabling | |
4062 | * stray interrupts. | |
4063 | */ | |
38bde180 | 4064 | ret = IRQ_HANDLED; |
a266c7d5 | 4065 | iir = new_iir; |
38bde180 | 4066 | } while (iir & ~flip_mask); |
a266c7d5 CW |
4067 | |
4068 | return ret; | |
4069 | } | |
4070 | ||
4071 | static void i915_irq_uninstall(struct drm_device * dev) | |
4072 | { | |
2d1013dd | 4073 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4074 | int pipe; |
4075 | ||
a266c7d5 | 4076 | if (I915_HAS_HOTPLUG(dev)) { |
0706f17c | 4077 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
a266c7d5 CW |
4078 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
4079 | } | |
4080 | ||
00d98ebd | 4081 | I915_WRITE16(HWSTAM, 0xffff); |
055e393f | 4082 | for_each_pipe(dev_priv, pipe) { |
55b39755 | 4083 | /* Clear enable bits; then clear status bits */ |
a266c7d5 | 4084 | I915_WRITE(PIPESTAT(pipe), 0); |
55b39755 CW |
4085 | I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe))); |
4086 | } | |
a266c7d5 CW |
4087 | I915_WRITE(IMR, 0xffffffff); |
4088 | I915_WRITE(IER, 0x0); | |
4089 | ||
a266c7d5 CW |
4090 | I915_WRITE(IIR, I915_READ(IIR)); |
4091 | } | |
4092 | ||
4093 | static void i965_irq_preinstall(struct drm_device * dev) | |
4094 | { | |
2d1013dd | 4095 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4096 | int pipe; |
4097 | ||
0706f17c | 4098 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4099 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4100 | |
4101 | I915_WRITE(HWSTAM, 0xeffe); | |
055e393f | 4102 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4103 | I915_WRITE(PIPESTAT(pipe), 0); |
4104 | I915_WRITE(IMR, 0xffffffff); | |
4105 | I915_WRITE(IER, 0x0); | |
4106 | POSTING_READ(IER); | |
4107 | } | |
4108 | ||
4109 | static int i965_irq_postinstall(struct drm_device *dev) | |
4110 | { | |
2d1013dd | 4111 | struct drm_i915_private *dev_priv = dev->dev_private; |
bbba0a97 | 4112 | u32 enable_mask; |
a266c7d5 CW |
4113 | u32 error_mask; |
4114 | ||
a266c7d5 | 4115 | /* Unmask the interrupts that we always want on. */ |
bbba0a97 | 4116 | dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | |
adca4730 | 4117 | I915_DISPLAY_PORT_INTERRUPT | |
bbba0a97 CW |
4118 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | |
4119 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | | |
4120 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4121 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | | |
4122 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
4123 | ||
4124 | enable_mask = ~dev_priv->irq_mask; | |
21ad8330 VS |
4125 | enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | |
4126 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT); | |
bbba0a97 CW |
4127 | enable_mask |= I915_USER_INTERRUPT; |
4128 | ||
4129 | if (IS_G4X(dev)) | |
4130 | enable_mask |= I915_BSD_USER_INTERRUPT; | |
a266c7d5 | 4131 | |
b79480ba DV |
4132 | /* Interrupt setup is already guaranteed to be single-threaded, this is |
4133 | * just to make the assert_spin_locked check happy. */ | |
d6207435 | 4134 | spin_lock_irq(&dev_priv->irq_lock); |
755e9019 ID |
4135 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); |
4136 | i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
4137 | i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); | |
d6207435 | 4138 | spin_unlock_irq(&dev_priv->irq_lock); |
a266c7d5 | 4139 | |
a266c7d5 CW |
4140 | /* |
4141 | * Enable some error detection, note the instruction error mask | |
4142 | * bit is reserved, so we leave it masked. | |
4143 | */ | |
4144 | if (IS_G4X(dev)) { | |
4145 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
4146 | GM45_ERROR_MEM_PRIV | | |
4147 | GM45_ERROR_CP_PRIV | | |
4148 | I915_ERROR_MEMORY_REFRESH); | |
4149 | } else { | |
4150 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
4151 | I915_ERROR_MEMORY_REFRESH); | |
4152 | } | |
4153 | I915_WRITE(EMR, error_mask); | |
4154 | ||
4155 | I915_WRITE(IMR, dev_priv->irq_mask); | |
4156 | I915_WRITE(IER, enable_mask); | |
4157 | POSTING_READ(IER); | |
4158 | ||
0706f17c | 4159 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
20afbda2 DV |
4160 | POSTING_READ(PORT_HOTPLUG_EN); |
4161 | ||
f49e38dd | 4162 | i915_enable_asle_pipestat(dev); |
20afbda2 DV |
4163 | |
4164 | return 0; | |
4165 | } | |
4166 | ||
bac56d5b | 4167 | static void i915_hpd_irq_setup(struct drm_device *dev) |
20afbda2 | 4168 | { |
2d1013dd | 4169 | struct drm_i915_private *dev_priv = dev->dev_private; |
20afbda2 DV |
4170 | u32 hotplug_en; |
4171 | ||
b5ea2d56 DV |
4172 | assert_spin_locked(&dev_priv->irq_lock); |
4173 | ||
778eb334 VS |
4174 | /* Note HDMI and DP share hotplug bits */ |
4175 | /* enable bits are the same for all generations */ | |
0706f17c | 4176 | hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915); |
778eb334 VS |
4177 | /* Programming the CRT detection parameters tends |
4178 | to generate a spurious hotplug event about three | |
4179 | seconds later. So just do it once. | |
4180 | */ | |
4181 | if (IS_G4X(dev)) | |
4182 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
778eb334 VS |
4183 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; |
4184 | ||
4185 | /* Ignore TV since it's buggy */ | |
0706f17c EE |
4186 | i915_hotplug_interrupt_update_locked(dev_priv, |
4187 | (HOTPLUG_INT_EN_MASK | |
4188 | | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK), | |
4189 | hotplug_en); | |
a266c7d5 CW |
4190 | } |
4191 | ||
ff1f525e | 4192 | static irqreturn_t i965_irq_handler(int irq, void *arg) |
a266c7d5 | 4193 | { |
45a83f84 | 4194 | struct drm_device *dev = arg; |
2d1013dd | 4195 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4196 | u32 iir, new_iir; |
4197 | u32 pipe_stats[I915_MAX_PIPES]; | |
a266c7d5 | 4198 | int ret = IRQ_NONE, pipe; |
21ad8330 VS |
4199 | u32 flip_mask = |
4200 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | | |
4201 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; | |
a266c7d5 | 4202 | |
2dd2a883 ID |
4203 | if (!intel_irqs_enabled(dev_priv)) |
4204 | return IRQ_NONE; | |
4205 | ||
a266c7d5 CW |
4206 | iir = I915_READ(IIR); |
4207 | ||
a266c7d5 | 4208 | for (;;) { |
501e01d7 | 4209 | bool irq_received = (iir & ~flip_mask) != 0; |
2c8ba29f CW |
4210 | bool blc_event = false; |
4211 | ||
a266c7d5 CW |
4212 | /* Can't rely on pipestat interrupt bit in iir as it might |
4213 | * have been cleared after the pipestat interrupt was received. | |
4214 | * It doesn't set the bit in iir again, but it still produces | |
4215 | * interrupts (for non-MSI). | |
4216 | */ | |
222c7f51 | 4217 | spin_lock(&dev_priv->irq_lock); |
a266c7d5 | 4218 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
aaecdf61 | 4219 | DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); |
a266c7d5 | 4220 | |
055e393f | 4221 | for_each_pipe(dev_priv, pipe) { |
a266c7d5 CW |
4222 | int reg = PIPESTAT(pipe); |
4223 | pipe_stats[pipe] = I915_READ(reg); | |
4224 | ||
4225 | /* | |
4226 | * Clear the PIPE*STAT regs before the IIR | |
4227 | */ | |
4228 | if (pipe_stats[pipe] & 0x8000ffff) { | |
a266c7d5 | 4229 | I915_WRITE(reg, pipe_stats[pipe]); |
501e01d7 | 4230 | irq_received = true; |
a266c7d5 CW |
4231 | } |
4232 | } | |
222c7f51 | 4233 | spin_unlock(&dev_priv->irq_lock); |
a266c7d5 CW |
4234 | |
4235 | if (!irq_received) | |
4236 | break; | |
4237 | ||
4238 | ret = IRQ_HANDLED; | |
4239 | ||
4240 | /* Consume port. Then clear IIR or we'll miss events */ | |
16c6c56b VS |
4241 | if (iir & I915_DISPLAY_PORT_INTERRUPT) |
4242 | i9xx_hpd_irq_handler(dev); | |
a266c7d5 | 4243 | |
21ad8330 | 4244 | I915_WRITE(IIR, iir & ~flip_mask); |
a266c7d5 CW |
4245 | new_iir = I915_READ(IIR); /* Flush posted writes */ |
4246 | ||
a266c7d5 | 4247 | if (iir & I915_USER_INTERRUPT) |
74cdb337 | 4248 | notify_ring(&dev_priv->ring[RCS]); |
a266c7d5 | 4249 | if (iir & I915_BSD_USER_INTERRUPT) |
74cdb337 | 4250 | notify_ring(&dev_priv->ring[VCS]); |
a266c7d5 | 4251 | |
055e393f | 4252 | for_each_pipe(dev_priv, pipe) { |
2c8ba29f | 4253 | if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS && |
90a72f87 VS |
4254 | i915_handle_vblank(dev, pipe, pipe, iir)) |
4255 | flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe); | |
a266c7d5 CW |
4256 | |
4257 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) | |
4258 | blc_event = true; | |
4356d586 DV |
4259 | |
4260 | if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) | |
277de95e | 4261 | i9xx_pipe_crc_irq_handler(dev, pipe); |
a266c7d5 | 4262 | |
1f7247c0 DV |
4263 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) |
4264 | intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); | |
2d9d2b0b | 4265 | } |
a266c7d5 CW |
4266 | |
4267 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
4268 | intel_opregion_asle_intr(dev); | |
4269 | ||
515ac2bb DV |
4270 | if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS) |
4271 | gmbus_irq_handler(dev); | |
4272 | ||
a266c7d5 CW |
4273 | /* With MSI, interrupts are only generated when iir |
4274 | * transitions from zero to nonzero. If another bit got | |
4275 | * set while we were handling the existing iir bits, then | |
4276 | * we would never get another interrupt. | |
4277 | * | |
4278 | * This is fine on non-MSI as well, as if we hit this path | |
4279 | * we avoid exiting the interrupt handler only to generate | |
4280 | * another one. | |
4281 | * | |
4282 | * Note that for MSI this could cause a stray interrupt report | |
4283 | * if an interrupt landed in the time between writing IIR and | |
4284 | * the posting read. This should be rare enough to never | |
4285 | * trigger the 99% of 100,000 interrupts test for disabling | |
4286 | * stray interrupts. | |
4287 | */ | |
4288 | iir = new_iir; | |
4289 | } | |
4290 | ||
4291 | return ret; | |
4292 | } | |
4293 | ||
4294 | static void i965_irq_uninstall(struct drm_device * dev) | |
4295 | { | |
2d1013dd | 4296 | struct drm_i915_private *dev_priv = dev->dev_private; |
a266c7d5 CW |
4297 | int pipe; |
4298 | ||
4299 | if (!dev_priv) | |
4300 | return; | |
4301 | ||
0706f17c | 4302 | i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); |
adca4730 | 4303 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); |
a266c7d5 CW |
4304 | |
4305 | I915_WRITE(HWSTAM, 0xffffffff); | |
055e393f | 4306 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4307 | I915_WRITE(PIPESTAT(pipe), 0); |
4308 | I915_WRITE(IMR, 0xffffffff); | |
4309 | I915_WRITE(IER, 0x0); | |
4310 | ||
055e393f | 4311 | for_each_pipe(dev_priv, pipe) |
a266c7d5 CW |
4312 | I915_WRITE(PIPESTAT(pipe), |
4313 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
4314 | I915_WRITE(IIR, I915_READ(IIR)); | |
4315 | } | |
4316 | ||
fca52a55 DV |
4317 | /** |
4318 | * intel_irq_init - initializes irq support | |
4319 | * @dev_priv: i915 device instance | |
4320 | * | |
4321 | * This function initializes all the irq support including work items, timers | |
4322 | * and all the vtables. It does not setup the interrupt itself though. | |
4323 | */ | |
b963291c | 4324 | void intel_irq_init(struct drm_i915_private *dev_priv) |
f71d4af4 | 4325 | { |
b963291c | 4326 | struct drm_device *dev = dev_priv->dev; |
8b2e326d | 4327 | |
77913b39 JN |
4328 | intel_hpd_init_work(dev_priv); |
4329 | ||
c6a828d3 | 4330 | INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work); |
a4da4fa4 | 4331 | INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work); |
8b2e326d | 4332 | |
a6706b45 | 4333 | /* Let's track the enabled rps events */ |
b963291c | 4334 | if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) |
6c65a587 | 4335 | /* WaGsvRC0ResidencyMethod:vlv */ |
6f4b12f8 | 4336 | dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED; |
31685c25 D |
4337 | else |
4338 | dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS; | |
a6706b45 | 4339 | |
737b1506 CW |
4340 | INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work, |
4341 | i915_hangcheck_elapsed); | |
61bac78e | 4342 | |
97a19a24 | 4343 | pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); |
9ee32fea | 4344 | |
b963291c | 4345 | if (IS_GEN2(dev_priv)) { |
4cdb83ec VS |
4346 | dev->max_vblank_count = 0; |
4347 | dev->driver->get_vblank_counter = i8xx_get_vblank_counter; | |
b963291c | 4348 | } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) { |
f71d4af4 JB |
4349 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ |
4350 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
391f75e2 VS |
4351 | } else { |
4352 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
4353 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
f71d4af4 JB |
4354 | } |
4355 | ||
21da2700 VS |
4356 | /* |
4357 | * Opt out of the vblank disable timer on everything except gen2. | |
4358 | * Gen2 doesn't have a hardware frame counter and so depends on | |
4359 | * vblank interrupts to produce sane vblank seuquence numbers. | |
4360 | */ | |
b963291c | 4361 | if (!IS_GEN2(dev_priv)) |
21da2700 VS |
4362 | dev->vblank_disable_immediate = true; |
4363 | ||
f3a5c3f6 DV |
4364 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; |
4365 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; | |
f71d4af4 | 4366 | |
b963291c | 4367 | if (IS_CHERRYVIEW(dev_priv)) { |
43f328d7 VS |
4368 | dev->driver->irq_handler = cherryview_irq_handler; |
4369 | dev->driver->irq_preinstall = cherryview_irq_preinstall; | |
4370 | dev->driver->irq_postinstall = cherryview_irq_postinstall; | |
4371 | dev->driver->irq_uninstall = cherryview_irq_uninstall; | |
4372 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4373 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
4374 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
b963291c | 4375 | } else if (IS_VALLEYVIEW(dev_priv)) { |
7e231dbe JB |
4376 | dev->driver->irq_handler = valleyview_irq_handler; |
4377 | dev->driver->irq_preinstall = valleyview_irq_preinstall; | |
4378 | dev->driver->irq_postinstall = valleyview_irq_postinstall; | |
4379 | dev->driver->irq_uninstall = valleyview_irq_uninstall; | |
4380 | dev->driver->enable_vblank = valleyview_enable_vblank; | |
4381 | dev->driver->disable_vblank = valleyview_disable_vblank; | |
fa00abe0 | 4382 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; |
b963291c | 4383 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
abd58f01 | 4384 | dev->driver->irq_handler = gen8_irq_handler; |
723761b8 | 4385 | dev->driver->irq_preinstall = gen8_irq_reset; |
abd58f01 BW |
4386 | dev->driver->irq_postinstall = gen8_irq_postinstall; |
4387 | dev->driver->irq_uninstall = gen8_irq_uninstall; | |
4388 | dev->driver->enable_vblank = gen8_enable_vblank; | |
4389 | dev->driver->disable_vblank = gen8_disable_vblank; | |
6dbf30ce | 4390 | if (IS_BROXTON(dev)) |
e0a20ad7 | 4391 | dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup; |
6dbf30ce VS |
4392 | else if (HAS_PCH_SPT(dev)) |
4393 | dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; | |
4394 | else | |
3a3b3c7d | 4395 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 JB |
4396 | } else if (HAS_PCH_SPLIT(dev)) { |
4397 | dev->driver->irq_handler = ironlake_irq_handler; | |
723761b8 | 4398 | dev->driver->irq_preinstall = ironlake_irq_reset; |
f71d4af4 JB |
4399 | dev->driver->irq_postinstall = ironlake_irq_postinstall; |
4400 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
4401 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
4402 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
23bb4cb5 | 4403 | dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup; |
f71d4af4 | 4404 | } else { |
b963291c | 4405 | if (INTEL_INFO(dev_priv)->gen == 2) { |
c2798b19 CW |
4406 | dev->driver->irq_preinstall = i8xx_irq_preinstall; |
4407 | dev->driver->irq_postinstall = i8xx_irq_postinstall; | |
4408 | dev->driver->irq_handler = i8xx_irq_handler; | |
4409 | dev->driver->irq_uninstall = i8xx_irq_uninstall; | |
b963291c | 4410 | } else if (INTEL_INFO(dev_priv)->gen == 3) { |
a266c7d5 CW |
4411 | dev->driver->irq_preinstall = i915_irq_preinstall; |
4412 | dev->driver->irq_postinstall = i915_irq_postinstall; | |
4413 | dev->driver->irq_uninstall = i915_irq_uninstall; | |
4414 | dev->driver->irq_handler = i915_irq_handler; | |
c2798b19 | 4415 | } else { |
a266c7d5 CW |
4416 | dev->driver->irq_preinstall = i965_irq_preinstall; |
4417 | dev->driver->irq_postinstall = i965_irq_postinstall; | |
4418 | dev->driver->irq_uninstall = i965_irq_uninstall; | |
4419 | dev->driver->irq_handler = i965_irq_handler; | |
c2798b19 | 4420 | } |
778eb334 VS |
4421 | if (I915_HAS_HOTPLUG(dev_priv)) |
4422 | dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; | |
f71d4af4 JB |
4423 | dev->driver->enable_vblank = i915_enable_vblank; |
4424 | dev->driver->disable_vblank = i915_disable_vblank; | |
4425 | } | |
4426 | } | |
20afbda2 | 4427 | |
fca52a55 DV |
4428 | /** |
4429 | * intel_irq_install - enables the hardware interrupt | |
4430 | * @dev_priv: i915 device instance | |
4431 | * | |
4432 | * This function enables the hardware interrupt handling, but leaves the hotplug | |
4433 | * handling still disabled. It is called after intel_irq_init(). | |
4434 | * | |
4435 | * In the driver load and resume code we need working interrupts in a few places | |
4436 | * but don't want to deal with the hassle of concurrent probe and hotplug | |
4437 | * workers. Hence the split into this two-stage approach. | |
4438 | */ | |
2aeb7d3a DV |
4439 | int intel_irq_install(struct drm_i915_private *dev_priv) |
4440 | { | |
4441 | /* | |
4442 | * We enable some interrupt sources in our postinstall hooks, so mark | |
4443 | * interrupts as enabled _before_ actually enabling them to avoid | |
4444 | * special cases in our ordering checks. | |
4445 | */ | |
4446 | dev_priv->pm.irqs_enabled = true; | |
4447 | ||
4448 | return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq); | |
4449 | } | |
4450 | ||
fca52a55 DV |
4451 | /** |
4452 | * intel_irq_uninstall - finilizes all irq handling | |
4453 | * @dev_priv: i915 device instance | |
4454 | * | |
4455 | * This stops interrupt and hotplug handling and unregisters and frees all | |
4456 | * resources acquired in the init functions. | |
4457 | */ | |
2aeb7d3a DV |
4458 | void intel_irq_uninstall(struct drm_i915_private *dev_priv) |
4459 | { | |
4460 | drm_irq_uninstall(dev_priv->dev); | |
4461 | intel_hpd_cancel_work(dev_priv); | |
4462 | dev_priv->pm.irqs_enabled = false; | |
4463 | } | |
4464 | ||
fca52a55 DV |
4465 | /** |
4466 | * intel_runtime_pm_disable_interrupts - runtime interrupt disabling | |
4467 | * @dev_priv: i915 device instance | |
4468 | * | |
4469 | * This function is used to disable interrupts at runtime, both in the runtime | |
4470 | * pm and the system suspend/resume code. | |
4471 | */ | |
b963291c | 4472 | void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4473 | { |
b963291c | 4474 | dev_priv->dev->driver->irq_uninstall(dev_priv->dev); |
2aeb7d3a | 4475 | dev_priv->pm.irqs_enabled = false; |
2dd2a883 | 4476 | synchronize_irq(dev_priv->dev->irq); |
c67a470b PZ |
4477 | } |
4478 | ||
fca52a55 DV |
4479 | /** |
4480 | * intel_runtime_pm_enable_interrupts - runtime interrupt enabling | |
4481 | * @dev_priv: i915 device instance | |
4482 | * | |
4483 | * This function is used to enable interrupts at runtime, both in the runtime | |
4484 | * pm and the system suspend/resume code. | |
4485 | */ | |
b963291c | 4486 | void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv) |
c67a470b | 4487 | { |
2aeb7d3a | 4488 | dev_priv->pm.irqs_enabled = true; |
b963291c DV |
4489 | dev_priv->dev->driver->irq_preinstall(dev_priv->dev); |
4490 | dev_priv->dev->driver->irq_postinstall(dev_priv->dev); | |
c67a470b | 4491 | } |