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drm/i915: streamline hsw_pm_irq_handler
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 49 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 50 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
51 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
52 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
53};
54
55static const u32 hpd_mask_i915[] = {
56 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
57 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
58 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
59 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
60 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
61 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
62};
63
64static const u32 hpd_status_gen4[] = {
65 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
71};
72
e5868a31
EE		 73static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
74 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
036a4a7d 82/* For display hotplug interrupt */
995b6762 83static void
f2b115e6 84ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 85{
4bc9d430
DV		 86 assert_spin_locked(&dev_priv->irq_lock);
87
1ec14ad3
CW		 88 if ((dev_priv->irq_mask & mask) != 0) {
89 dev_priv->irq_mask &= ~mask;
90 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 91 POSTING_READ(DEIMR);
036a4a7d
ZW		 92 }
93}
94
0ff9800a 95static void
f2b115e6 96ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 97{
4bc9d430
DV		 98 assert_spin_locked(&dev_priv->irq_lock);
99
1ec14ad3
CW		 100 if ((dev_priv->irq_mask & mask) != mask) {
101 dev_priv->irq_mask |= mask;
102 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 103 POSTING_READ(DEIMR);
036a4a7d
ZW		 104 }
105}
106
8664281b
PZ		 107static bool ivb_can_enable_err_int(struct drm_device *dev)
108{
109 struct drm_i915_private *dev_priv = dev->dev_private;
110 struct intel_crtc *crtc;
111 enum pipe pipe;
112
4bc9d430
DV		 113 assert_spin_locked(&dev_priv->irq_lock);
114
8664281b
PZ		 115 for_each_pipe(pipe) {
116 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
117
118 if (crtc->cpu_fifo_underrun_disabled)
119 return false;
120 }
121
122 return true;
123}
124
125static bool cpt_can_enable_serr_int(struct drm_device *dev)
126{
127 struct drm_i915_private *dev_priv = dev->dev_private;
128 enum pipe pipe;
129 struct intel_crtc *crtc;
130
fee884ed
DV		 131 assert_spin_locked(&dev_priv->irq_lock);
132
8664281b
PZ		 133 for_each_pipe(pipe) {
134 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
135
136 if (crtc->pch_fifo_underrun_disabled)
137 return false;
138 }
139
140 return true;
141}
142
143static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
144 enum pipe pipe, bool enable)
145{
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
148 DE_PIPEB_FIFO_UNDERRUN;
149
150 if (enable)
151 ironlake_enable_display_irq(dev_priv, bit);
152 else
153 ironlake_disable_display_irq(dev_priv, bit);
154}
155
156static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 157 enum pipe pipe, bool enable)
8664281b
PZ		 158{
159 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 160 if (enable) {
7336df65
DV		 161 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
162
8664281b
PZ		 163 if (!ivb_can_enable_err_int(dev))
164 return;
165
8664281b
PZ		 166 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
167 } else {
7336df65
DV		 168 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
169
170 /* Change the state _after_ we've read out the current one. */
8664281b 171 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 172
173 if (!was_enabled &&
174 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
175 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
176 pipe_name(pipe));
177 }
8664281b
PZ		 178 }
179}
180
fee884ed
DV		 181/**
182 * ibx_display_interrupt_update - update SDEIMR
183 * @dev_priv: driver private
184 * @interrupt_mask: mask of interrupt bits to update
185 * @enabled_irq_mask: mask of interrupt bits to enable
186 */
187static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
188 uint32_t interrupt_mask,
189 uint32_t enabled_irq_mask)
190{
191 uint32_t sdeimr = I915_READ(SDEIMR);
192 sdeimr &= ~interrupt_mask;
193 sdeimr |= (~enabled_irq_mask & interrupt_mask);
194
195 assert_spin_locked(&dev_priv->irq_lock);
196
197 I915_WRITE(SDEIMR, sdeimr);
198 POSTING_READ(SDEIMR);
199}
200#define ibx_enable_display_interrupt(dev_priv, bits) \
201 ibx_display_interrupt_update((dev_priv), (bits), (bits))
202#define ibx_disable_display_interrupt(dev_priv, bits) \
203 ibx_display_interrupt_update((dev_priv), (bits), 0)
204
de28075d
DV		 205static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
206 enum transcoder pch_transcoder,
8664281b
PZ		 207 bool enable)
208{
8664281b 209 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 210 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
211 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 212
213 if (enable)
fee884ed 214 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 215 else
fee884ed 216 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 217}
218
219static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
220 enum transcoder pch_transcoder,
221 bool enable)
222{
223 struct drm_i915_private *dev_priv = dev->dev_private;
224
225 if (enable) {
1dd246fb
DV		 226 I915_WRITE(SERR_INT,
227 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
228
8664281b
PZ		 229 if (!cpt_can_enable_serr_int(dev))
230 return;
231
fee884ed 232 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 233 } else {
1dd246fb
DV		 234 uint32_t tmp = I915_READ(SERR_INT);
235 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
236
237 /* Change the state _after_ we've read out the current one. */
fee884ed 238 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 239
240 if (!was_enabled &&
241 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
242 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
243 transcoder_name(pch_transcoder));
244 }
8664281b 245 }
8664281b
PZ		 246}
247
248/**
249 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
250 * @dev: drm device
251 * @pipe: pipe
252 * @enable: true if we want to report FIFO underrun errors, false otherwise
253 *
254 * This function makes us disable or enable CPU fifo underruns for a specific
255 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
256 * reporting for one pipe may also disable all the other CPU error interruts for
257 * the other pipes, due to the fact that there's just one interrupt mask/enable
258 * bit for all the pipes.
259 *
260 * Returns the previous state of underrun reporting.
261 */
262bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
263 enum pipe pipe, bool enable)
264{
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
268 unsigned long flags;
269 bool ret;
270
271 spin_lock_irqsave(&dev_priv->irq_lock, flags);
272
273 ret = !intel_crtc->cpu_fifo_underrun_disabled;
274
275 if (enable == ret)
276 goto done;
277
278 intel_crtc->cpu_fifo_underrun_disabled = !enable;
279
280 if (IS_GEN5(dev) || IS_GEN6(dev))
281 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
282 else if (IS_GEN7(dev))
7336df65 283 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 284
285done:
286 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
287 return ret;
288}
289
290/**
291 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
292 * @dev: drm device
293 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
294 * @enable: true if we want to report FIFO underrun errors, false otherwise
295 *
296 * This function makes us disable or enable PCH fifo underruns for a specific
297 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
298 * underrun reporting for one transcoder may also disable all the other PCH
299 * error interruts for the other transcoders, due to the fact that there's just
300 * one interrupt mask/enable bit for all the transcoders.
301 *
302 * Returns the previous state of underrun reporting.
303 */
304bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
305 enum transcoder pch_transcoder,
306 bool enable)
307{
308 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 309 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 311 unsigned long flags;
312 bool ret;
313
de28075d
DV		 314 /*
315 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
316 * has only one pch transcoder A that all pipes can use. To avoid racy
317 * pch transcoder -> pipe lookups from interrupt code simply store the
318 * underrun statistics in crtc A. Since we never expose this anywhere
319 * nor use it outside of the fifo underrun code here using the "wrong"
320 * crtc on LPT won't cause issues.
321 */
8664281b
PZ		 322
323 spin_lock_irqsave(&dev_priv->irq_lock, flags);
324
325 ret = !intel_crtc->pch_fifo_underrun_disabled;
326
327 if (enable == ret)
328 goto done;
329
330 intel_crtc->pch_fifo_underrun_disabled = !enable;
331
332 if (HAS_PCH_IBX(dev))
de28075d 333 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 334 else
335 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
336
337done:
338 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
339 return ret;
340}
341
342
7c463586
KP		 343void
344i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
345{
46c06a30
VS		 346 u32 reg = PIPESTAT(pipe);
347 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 348
b79480ba
DV		 349 assert_spin_locked(&dev_priv->irq_lock);
350
46c06a30
VS		 351 if ((pipestat & mask) == mask)
352 return;
353
354 /* Enable the interrupt, clear any pending status */
355 pipestat |= mask | (mask >> 16);
356 I915_WRITE(reg, pipestat);
357 POSTING_READ(reg);
7c463586
KP		 358}
359
360void
361i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
362{
46c06a30
VS		 363 u32 reg = PIPESTAT(pipe);
364 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 365
b79480ba
DV		 366 assert_spin_locked(&dev_priv->irq_lock);
367
46c06a30
VS		 368 if ((pipestat & mask) == 0)
369 return;
370
371 pipestat &= ~mask;
372 I915_WRITE(reg, pipestat);
373 POSTING_READ(reg);
7c463586
KP		 374}
375
01c66889 376/**
f49e38dd 377 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 378 */
f49e38dd 379static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 380{
1ec14ad3
CW		 381 drm_i915_private_t *dev_priv = dev->dev_private;
382 unsigned long irqflags;
383
f49e38dd
JN		 384 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
385 return;
386
1ec14ad3 387 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 388
f898780b
JN		 389 i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
390 if (INTEL_INFO(dev)->gen >= 4)
391 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
1ec14ad3
CW		 392
393 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 394}
395
0a3e67a4
JB		 396/**
397 * i915_pipe_enabled - check if a pipe is enabled
398 * @dev: DRM device
399 * @pipe: pipe to check
400 *
401 * Reading certain registers when the pipe is disabled can hang the chip.
402 * Use this routine to make sure the PLL is running and the pipe is active
403 * before reading such registers if unsure.
404 */
405static int
406i915_pipe_enabled(struct drm_device *dev, int pipe)
407{
408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56 409
a01025af
DV		 410 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
411 /* Locking is horribly broken here, but whatever. */
412 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 414
a01025af
DV		 415 return intel_crtc->active;
416 } else {
417 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
418 }
0a3e67a4
JB		 419}
420
42f52ef8
KP		 421/* Called from drm generic code, passed a 'crtc', which
422 * we use as a pipe index
423 */
f71d4af4 424static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 425{
426 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
427 unsigned long high_frame;
428 unsigned long low_frame;
5eddb70b 429 u32 high1, high2, low;
0a3e67a4
JB		 430
431 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 432 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 433 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 434 return 0;
435 }
436
9db4a9c7
JB		 437 high_frame = PIPEFRAME(pipe);
438 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 439
0a3e67a4
JB		 440 /*
441 * High & low register fields aren't synchronized, so make sure
442 * we get a low value that's stable across two reads of the high
443 * register.
444 */
445 do {
5eddb70b
CW		 446 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
447 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
448 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 449 } while (high1 != high2);
450
5eddb70b
CW		 451 high1 >>= PIPE_FRAME_HIGH_SHIFT;
452 low >>= PIPE_FRAME_LOW_SHIFT;
453 return (high1 << 8) | low;
0a3e67a4
JB		 454}
455
f71d4af4 456static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 457{
458 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 459 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 460
461 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 462 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 463 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 464 return 0;
465 }
466
467 return I915_READ(reg);
468}
469
f71d4af4 470static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 471 int *vpos, int *hpos)
472{
473 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
474 u32 vbl = 0, position = 0;
475 int vbl_start, vbl_end, htotal, vtotal;
476 bool in_vbl = true;
477 int ret = 0;
fe2b8f9d
PZ		 478 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
479 pipe);
0af7e4df
MK		 480
481 if (!i915_pipe_enabled(dev, pipe)) {
482 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 483 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 484 return 0;
485 }
486
487 /* Get vtotal. */
fe2b8f9d 488 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 489
490 if (INTEL_INFO(dev)->gen >= 4) {
491 /* No obvious pixelcount register. Only query vertical
492 * scanout position from Display scan line register.
493 */
494 position = I915_READ(PIPEDSL(pipe));
495
496 /* Decode into vertical scanout position. Don't have
497 * horizontal scanout position.
498 */
499 *vpos = position & 0x1fff;
500 *hpos = 0;
501 } else {
502 /* Have access to pixelcount since start of frame.
503 * We can split this into vertical and horizontal
504 * scanout position.
505 */
506 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
507
fe2b8f9d 508 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 509 *vpos = position / htotal;
510 *hpos = position - (*vpos * htotal);
511 }
512
513 /* Query vblank area. */
fe2b8f9d 514 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 515
516 /* Test position against vblank region. */
517 vbl_start = vbl & 0x1fff;
518 vbl_end = (vbl >> 16) & 0x1fff;
519
520 if ((*vpos < vbl_start) || (*vpos > vbl_end))
521 in_vbl = false;
522
523 /* Inside "upper part" of vblank area? Apply corrective offset: */
524 if (in_vbl && (*vpos >= vbl_start))
525 *vpos = *vpos - vtotal;
526
527 /* Readouts valid? */
528 if (vbl > 0)
529 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
530
531 /* In vblank? */
532 if (in_vbl)
533 ret |= DRM_SCANOUTPOS_INVBL;
534
535 return ret;
536}
537
f71d4af4 538static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 539 int *max_error,
540 struct timeval *vblank_time,
541 unsigned flags)
542{
4041b853 543 struct drm_crtc *crtc;
0af7e4df 544
7eb552ae 545 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 546 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 547 return -EINVAL;
548 }
549
550 /* Get drm_crtc to timestamp: */
4041b853
CW		 551 crtc = intel_get_crtc_for_pipe(dev, pipe);
552 if (crtc == NULL) {
553 DRM_ERROR("Invalid crtc %d\n", pipe);
554 return -EINVAL;
555 }
556
557 if (!crtc->enabled) {
558 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
559 return -EBUSY;
560 }
0af7e4df
MK		 561
562 /* Helper routine in DRM core does all the work: */
4041b853
CW		 563 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
564 vblank_time, flags,
565 crtc);
0af7e4df
MK		 566}
567
321a1b30
EE		 568static int intel_hpd_irq_event(struct drm_device *dev, struct drm_connector *connector)
569{
570 enum drm_connector_status old_status;
571
572 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
573 old_status = connector->status;
574
575 connector->status = connector->funcs->detect(connector, false);
576 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %d to %d\n",
577 connector->base.id,
578 drm_get_connector_name(connector),
579 old_status, connector->status);
580 return (old_status != connector->status);
581}
582
5ca58282
JB		 583/*
584 * Handle hotplug events outside the interrupt handler proper.
585 */
ac4c16c5
EE		 586#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
587
5ca58282
JB		 588static void i915_hotplug_work_func(struct work_struct *work)
589{
590 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
591 hotplug_work);
592 struct drm_device *dev = dev_priv->dev;
c31c4ba3 593 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 594 struct intel_connector *intel_connector;
595 struct intel_encoder *intel_encoder;
596 struct drm_connector *connector;
597 unsigned long irqflags;
598 bool hpd_disabled = false;
321a1b30 599 bool changed = false;
142e2398 600 u32 hpd_event_bits;
4ef69c7a 601
52d7eced
DV		 602 /* HPD irq before everything is fully set up. */
603 if (!dev_priv->enable_hotplug_processing)
604 return;
605
a65e34c7 606 mutex_lock(&mode_config->mutex);
e67189ab
JB		 607 DRM_DEBUG_KMS("running encoder hotplug functions\n");
608
cd569aed 609 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 610
611 hpd_event_bits = dev_priv->hpd_event_bits;
612 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 613 list_for_each_entry(connector, &mode_config->connector_list, head) {
614 intel_connector = to_intel_connector(connector);
615 intel_encoder = intel_connector->encoder;
616 if (intel_encoder->hpd_pin > HPD_NONE &&
617 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
618 connector->polled == DRM_CONNECTOR_POLL_HPD) {
619 DRM_INFO("HPD interrupt storm detected on connector %s: "
620 "switching from hotplug detection to polling\n",
621 drm_get_connector_name(connector));
622 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
623 connector->polled = DRM_CONNECTOR_POLL_CONNECT
624 | DRM_CONNECTOR_POLL_DISCONNECT;
625 hpd_disabled = true;
626 }
142e2398
EE		 627 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
628 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
629 drm_get_connector_name(connector), intel_encoder->hpd_pin);
630 }
cd569aed
EE		 631 }
632 /* if there were no outputs to poll, poll was disabled,
633 * therefore make sure it's enabled when disabling HPD on
634 * some connectors */
ac4c16c5 635 if (hpd_disabled) {
cd569aed 636 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 637 mod_timer(&dev_priv->hotplug_reenable_timer,
638 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
639 }
cd569aed
EE		 640
641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
642
321a1b30
EE		 643 list_for_each_entry(connector, &mode_config->connector_list, head) {
644 intel_connector = to_intel_connector(connector);
645 intel_encoder = intel_connector->encoder;
646 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
647 if (intel_encoder->hot_plug)
648 intel_encoder->hot_plug(intel_encoder);
649 if (intel_hpd_irq_event(dev, connector))
650 changed = true;
651 }
652 }
40ee3381
KP		 653 mutex_unlock(&mode_config->mutex);
654
321a1b30
EE		 655 if (changed)
656 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 657}
658
d0ecd7e2 659static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1
JB		 660{
661 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 662 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 663 u8 new_delay;
9270388e 664
d0ecd7e2 665 spin_lock(&mchdev_lock);
f97108d1 666
73edd18f
DV		 667 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
668
20e4d407 669 new_delay = dev_priv->ips.cur_delay;
9270388e 670
7648fa99 671 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 672 busy_up = I915_READ(RCPREVBSYTUPAVG);
673 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 674 max_avg = I915_READ(RCBMAXAVG);
675 min_avg = I915_READ(RCBMINAVG);
676
677 /* Handle RCS change request from hw */
b5b72e89 678 if (busy_up > max_avg) {
20e4d407
DV		 679 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
680 new_delay = dev_priv->ips.cur_delay - 1;
681 if (new_delay < dev_priv->ips.max_delay)
682 new_delay = dev_priv->ips.max_delay;
b5b72e89 683 } else if (busy_down < min_avg) {
20e4d407
DV		 684 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
685 new_delay = dev_priv->ips.cur_delay + 1;
686 if (new_delay > dev_priv->ips.min_delay)
687 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 688 }
689
7648fa99 690 if (ironlake_set_drps(dev, new_delay))
20e4d407 691 dev_priv->ips.cur_delay = new_delay;
f97108d1 692
d0ecd7e2 693 spin_unlock(&mchdev_lock);
9270388e 694
f97108d1
JB		 695 return;
696}
697
549f7365
CW		 698static void notify_ring(struct drm_device *dev,
699 struct intel_ring_buffer *ring)
700{
701 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 702
475553de
CW		 703 if (ring->obj == NULL)
704 return;
705
b2eadbc8 706 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 707
549f7365 708 wake_up_all(&ring->irq_queue);
3e0dc6b0 709 if (i915_enable_hangcheck) {
99584db3 710 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 711 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 712 }
549f7365
CW		 713}
714
4912d041 715static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 716{
4912d041 717 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 718 rps.work);
4912d041 719 u32 pm_iir, pm_imr;
7b9e0ae6 720 u8 new_delay;
4912d041 721
c6a828d3
DV		 722 spin_lock_irq(&dev_priv->rps.lock);
723 pm_iir = dev_priv->rps.pm_iir;
724 dev_priv->rps.pm_iir = 0;
4912d041 725 pm_imr = I915_READ(GEN6_PMIMR);
4848405c
BW		 726 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
727 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS);
c6a828d3 728 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 729
4848405c 730 if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
3b8d8d91
JB		 731 return;
732
4fc688ce 733 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 734
7425034a 735 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
c6a828d3 736 new_delay = dev_priv->rps.cur_delay + 1;
7425034a
VS		 737
738 /*
739 * For better performance, jump directly
740 * to RPe if we're below it.
741 */
742 if (IS_VALLEYVIEW(dev_priv->dev) &&
743 dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
744 new_delay = dev_priv->rps.rpe_delay;
745 } else
c6a828d3 746 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 747
79249636
BW		 748 /* sysfs frequency interfaces may have snuck in while servicing the
749 * interrupt
750 */
d8289c9e
VS		 751 if (new_delay >= dev_priv->rps.min_delay &&
752 new_delay <= dev_priv->rps.max_delay) {
0a073b84
JB		 753 if (IS_VALLEYVIEW(dev_priv->dev))
754 valleyview_set_rps(dev_priv->dev, new_delay);
755 else
756 gen6_set_rps(dev_priv->dev, new_delay);
79249636 757 }
3b8d8d91 758
52ceb908
JB		 759 if (IS_VALLEYVIEW(dev_priv->dev)) {
760 /*
761 * On VLV, when we enter RC6 we may not be at the minimum
762 * voltage level, so arm a timer to check. It should only
763 * fire when there's activity or once after we've entered
764 * RC6, and then won't be re-armed until the next RPS interrupt.
765 */
766 mod_delayed_work(dev_priv->wq, &dev_priv->rps.vlv_work,
767 msecs_to_jiffies(100));
768 }
769
4fc688ce 770 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 771}
772
e3689190
BW		 773
774/**
775 * ivybridge_parity_work - Workqueue called when a parity error interrupt
776 * occurred.
777 * @work: workqueue struct
778 *
779 * Doesn't actually do anything except notify userspace. As a consequence of
780 * this event, userspace should try to remap the bad rows since statistically
781 * it is likely the same row is more likely to go bad again.
782 */
783static void ivybridge_parity_work(struct work_struct *work)
784{
785 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 786 l3_parity.error_work);
e3689190
BW		 787 u32 error_status, row, bank, subbank;
788 char *parity_event[5];
789 uint32_t misccpctl;
790 unsigned long flags;
791
792 /* We must turn off DOP level clock gating to access the L3 registers.
793 * In order to prevent a get/put style interface, acquire struct mutex
794 * any time we access those registers.
795 */
796 mutex_lock(&dev_priv->dev->struct_mutex);
797
798 misccpctl = I915_READ(GEN7_MISCCPCTL);
799 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
800 POSTING_READ(GEN7_MISCCPCTL);
801
802 error_status = I915_READ(GEN7_L3CDERRST1);
803 row = GEN7_PARITY_ERROR_ROW(error_status);
804 bank = GEN7_PARITY_ERROR_BANK(error_status);
805 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
806
807 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
808 GEN7_L3CDERRST1_ENABLE);
809 POSTING_READ(GEN7_L3CDERRST1);
810
811 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
812
813 spin_lock_irqsave(&dev_priv->irq_lock, flags);
cc609d5d 814 dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190
BW		 815 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
816 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
817
818 mutex_unlock(&dev_priv->dev->struct_mutex);
819
820 parity_event[0] = "L3_PARITY_ERROR=1";
821 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
822 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
823 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
824 parity_event[4] = NULL;
825
826 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
827 KOBJ_CHANGE, parity_event);
828
829 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
830 row, bank, subbank);
831
832 kfree(parity_event[3]);
833 kfree(parity_event[2]);
834 kfree(parity_event[1]);
835}
836
d0ecd7e2 837static void ivybridge_parity_error_irq_handler(struct drm_device *dev)
e3689190
BW		 838{
839 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e3689190 840
e1ef7cc2 841 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 842 return;
843
d0ecd7e2 844 spin_lock(&dev_priv->irq_lock);
cc609d5d 845 dev_priv->gt_irq_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
e3689190 846 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
d0ecd7e2 847 spin_unlock(&dev_priv->irq_lock);
e3689190 848
a4da4fa4 849 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 850}
851
e7b4c6b1
DV		 852static void snb_gt_irq_handler(struct drm_device *dev,
853 struct drm_i915_private *dev_priv,
854 u32 gt_iir)
855{
856
cc609d5d
BW		 857 if (gt_iir &
858 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 859 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 860 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 861 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 862 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 863 notify_ring(dev, &dev_priv->ring[BCS]);
864
cc609d5d
BW		 865 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
866 GT_BSD_CS_ERROR_INTERRUPT |
867 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
e7b4c6b1
DV		 868 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
869 i915_handle_error(dev, false);
870 }
e3689190 871
cc609d5d 872 if (gt_iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
d0ecd7e2 873 ivybridge_parity_error_irq_handler(dev);
e7b4c6b1
DV		 874}
875
baf02a1f 876/* Legacy way of handling PM interrupts */
d0ecd7e2
DV		 877static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv,
878 u32 pm_iir)
fc6826d1 879{
fc6826d1
CW		 880 /*
881 * IIR bits should never already be set because IMR should
882 * prevent an interrupt from being shown in IIR. The warning
883 * displays a case where we've unsafely cleared
c6a828d3 884 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 885 * type is not a problem, it displays a problem in the logic.
886 *
c6a828d3 887 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 888 */
889
d0ecd7e2 890 spin_lock(&dev_priv->rps.lock);
c6a828d3
DV		 891 dev_priv->rps.pm_iir |= pm_iir;
892 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 893 POSTING_READ(GEN6_PMIMR);
d0ecd7e2 894 spin_unlock(&dev_priv->rps.lock);
fc6826d1 895
c6a828d3 896 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 897}
898
b543fb04
EE		 899#define HPD_STORM_DETECT_PERIOD 1000
900#define HPD_STORM_THRESHOLD 5
901
10a504de 902static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 903 u32 hotplug_trigger,
904 const u32 *hpd)
b543fb04
EE		 905{
906 drm_i915_private_t *dev_priv = dev->dev_private;
b543fb04 907 int i;
10a504de 908 bool storm_detected = false;
b543fb04 909
91d131d2
DV		 910 if (!hotplug_trigger)
911 return;
912
b5ea2d56 913 spin_lock(&dev_priv->irq_lock);
b543fb04 914 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 915
b543fb04
EE		 916 if (!(hpd[i] & hotplug_trigger) ||
917 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
918 continue;
919
bc5ead8c 920 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 921 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
922 dev_priv->hpd_stats[i].hpd_last_jiffies
923 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
924 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
925 dev_priv->hpd_stats[i].hpd_cnt = 0;
926 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
927 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 928 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 929 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 930 storm_detected = true;
b543fb04
EE		 931 } else {
932 dev_priv->hpd_stats[i].hpd_cnt++;
933 }
934 }
935
10a504de
DV		 936 if (storm_detected)
937 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 938 spin_unlock(&dev_priv->irq_lock);
5876fa0d
DV		 939
940 queue_work(dev_priv->wq,
941 &dev_priv->hotplug_work);
b543fb04
EE		 942}
943
515ac2bb
DV		 944static void gmbus_irq_handler(struct drm_device *dev)
945{
28c70f16
DV		 946 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
947
28c70f16 948 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 949}
950
ce99c256
DV		 951static void dp_aux_irq_handler(struct drm_device *dev)
952{
9ee32fea
DV		 953 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
954
9ee32fea 955 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 956}
957
d0ecd7e2 958/* Unlike gen6_rps_irq_handler() from which this function is originally derived,
baf02a1f
BW		 959 * we must be able to deal with other PM interrupts. This is complicated because
960 * of the way in which we use the masks to defer the RPS work (which for
961 * posterity is necessary because of forcewake).
962 */
963static void hsw_pm_irq_handler(struct drm_i915_private *dev_priv,
964 u32 pm_iir)
965{
41a05a3a
DV		 966 if (pm_iir & GEN6_PM_RPS_EVENTS) {
967 spin_lock(&dev_priv->rps.lock);
968 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
baf02a1f
BW		 969 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
970 /* never want to mask useful interrupts. (also posting read) */
4848405c 971 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
baf02a1f
BW		 972 /* TODO: if queue_work is slow, move it out of the spinlock */
973 queue_work(dev_priv->wq, &dev_priv->rps.work);
41a05a3a 974 spin_unlock(&dev_priv->rps.lock);
baf02a1f 975 }
baf02a1f 976
41a05a3a
DV		 977 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
978 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 979
41a05a3a
DV		 980 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
981 DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
982 i915_handle_error(dev_priv->dev, false);
12638c57 983 }
baf02a1f
BW		 984}
985
ff1f525e 986static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 987{
988 struct drm_device *dev = (struct drm_device *) arg;
989 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
990 u32 iir, gt_iir, pm_iir;
991 irqreturn_t ret = IRQ_NONE;
992 unsigned long irqflags;
993 int pipe;
994 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 995
996 atomic_inc(&dev_priv->irq_received);
997
7e231dbe
JB		 998 while (true) {
999 iir = I915_READ(VLV_IIR);
1000 gt_iir = I915_READ(GTIIR);
1001 pm_iir = I915_READ(GEN6_PMIIR);
1002
1003 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1004 goto out;
1005
1006 ret = IRQ_HANDLED;
1007
e7b4c6b1 1008 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 1009
1010 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1011 for_each_pipe(pipe) {
1012 int reg = PIPESTAT(pipe);
1013 pipe_stats[pipe] = I915_READ(reg);
1014
1015 /*
1016 * Clear the PIPE*STAT regs before the IIR
1017 */
1018 if (pipe_stats[pipe] & 0x8000ffff) {
1019 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1020 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1021 pipe_name(pipe));
1022 I915_WRITE(reg, pipe_stats[pipe]);
1023 }
1024 }
1025 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1026
31acc7f5
JB		 1027 for_each_pipe(pipe) {
1028 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1029 drm_handle_vblank(dev, pipe);
1030
1031 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1032 intel_prepare_page_flip(dev, pipe);
1033 intel_finish_page_flip(dev, pipe);
1034 }
1035 }
1036
7e231dbe
JB		 1037 /* Consume port. Then clear IIR or we'll miss events */
1038 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1039 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 1040 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
7e231dbe
JB		 1041
1042 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1043 hotplug_status);
91d131d2
DV		 1044
1045 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1046
7e231dbe
JB		 1047 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1048 I915_READ(PORT_HOTPLUG_STAT);
1049 }
1050
515ac2bb
DV		 1051 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1052 gmbus_irq_handler(dev);
7e231dbe 1053
4848405c 1054 if (pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1055 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1056
1057 I915_WRITE(GTIIR, gt_iir);
1058 I915_WRITE(GEN6_PMIIR, pm_iir);
1059 I915_WRITE(VLV_IIR, iir);
1060 }
1061
1062out:
1063 return ret;
1064}
1065
23e81d69 1066static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 1067{
1068 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1069 int pipe;
b543fb04 1070 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1071
91d131d2
DV		 1072 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1073
cfc33bf7
VS		 1074 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1075 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1076 SDE_AUDIO_POWER_SHIFT);
776ad806 1077 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1078 port_name(port));
1079 }
776ad806 1080
ce99c256
DV		 1081 if (pch_iir & SDE_AUX_MASK)
1082 dp_aux_irq_handler(dev);
1083
776ad806 1084 if (pch_iir & SDE_GMBUS)
515ac2bb 1085 gmbus_irq_handler(dev);
776ad806
JB		 1086
1087 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1088 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1089
1090 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1091 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1092
1093 if (pch_iir & SDE_POISON)
1094 DRM_ERROR("PCH poison interrupt\n");
1095
9db4a9c7
JB		 1096 if (pch_iir & SDE_FDI_MASK)
1097 for_each_pipe(pipe)
1098 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1099 pipe_name(pipe),
1100 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1101
1102 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1103 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1104
1105 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1106 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1107
776ad806 1108 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1109 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1110 false))
1111 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1112
1113 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1114 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1115 false))
1116 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1117}
1118
1119static void ivb_err_int_handler(struct drm_device *dev)
1120{
1121 struct drm_i915_private *dev_priv = dev->dev_private;
1122 u32 err_int = I915_READ(GEN7_ERR_INT);
1123
de032bf4
PZ		 1124 if (err_int & ERR_INT_POISON)
1125 DRM_ERROR("Poison interrupt\n");
1126
8664281b
PZ		 1127 if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1128 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1129 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1130
1131 if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1132 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1133 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1134
1135 if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1136 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1137 DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1138
1139 I915_WRITE(GEN7_ERR_INT, err_int);
1140}
1141
1142static void cpt_serr_int_handler(struct drm_device *dev)
1143{
1144 struct drm_i915_private *dev_priv = dev->dev_private;
1145 u32 serr_int = I915_READ(SERR_INT);
1146
de032bf4
PZ		 1147 if (serr_int & SERR_INT_POISON)
1148 DRM_ERROR("PCH poison interrupt\n");
1149
8664281b
PZ		 1150 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1151 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1152 false))
1153 DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1154
1155 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1156 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1157 false))
1158 DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1159
1160 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1161 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1162 false))
1163 DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1164
1165 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1166}
1167
23e81d69
AJ		 1168static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1169{
1170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1171 int pipe;
b543fb04 1172 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1173
91d131d2
DV		 1174 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1175
cfc33bf7
VS		 1176 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1177 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1178 SDE_AUDIO_POWER_SHIFT_CPT);
1179 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1180 port_name(port));
1181 }
23e81d69
AJ		 1182
1183 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1184 dp_aux_irq_handler(dev);
23e81d69
AJ		 1185
1186 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1187 gmbus_irq_handler(dev);
23e81d69
AJ		 1188
1189 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1190 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1191
1192 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1193 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1194
1195 if (pch_iir & SDE_FDI_MASK_CPT)
1196 for_each_pipe(pipe)
1197 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1198 pipe_name(pipe),
1199 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1200
1201 if (pch_iir & SDE_ERROR_CPT)
1202 cpt_serr_int_handler(dev);
23e81d69
AJ		 1203}
1204
ff1f525e 1205static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1206{
1207 struct drm_device *dev = (struct drm_device *) arg;
1208 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
ab5c608b 1209 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
0e43406b
CW		 1210 irqreturn_t ret = IRQ_NONE;
1211 int i;
b1f14ad0
JB		 1212
1213 atomic_inc(&dev_priv->irq_received);
1214
8664281b
PZ		 1215 /* We get interrupts on unclaimed registers, so check for this before we
1216 * do any I915_{READ,WRITE}. */
1217 if (IS_HASWELL(dev) &&
1218 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1219 DRM_ERROR("Unclaimed register before interrupt\n");
1220 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1221 }
1222
b1f14ad0
JB		 1223 /* disable master interrupt before clearing iir */
1224 de_ier = I915_READ(DEIER);
1225 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 1226
44498aea
PZ		 1227 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1228 * interrupts will will be stored on its back queue, and then we'll be
1229 * able to process them after we restore SDEIER (as soon as we restore
1230 * it, we'll get an interrupt if SDEIIR still has something to process
1231 * due to its back queue). */
ab5c608b
BW		 1232 if (!HAS_PCH_NOP(dev)) {
1233 sde_ier = I915_READ(SDEIER);
1234 I915_WRITE(SDEIER, 0);
1235 POSTING_READ(SDEIER);
1236 }
44498aea 1237
8664281b
PZ		 1238 /* On Haswell, also mask ERR_INT because we don't want to risk
1239 * generating "unclaimed register" interrupts from inside the interrupt
1240 * handler. */
4bc9d430
DV		 1241 if (IS_HASWELL(dev)) {
1242 spin_lock(&dev_priv->irq_lock);
8664281b 1243 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
4bc9d430
DV		 1244 spin_unlock(&dev_priv->irq_lock);
1245 }
8664281b 1246
b1f14ad0 1247 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 1248 if (gt_iir) {
1249 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1250 I915_WRITE(GTIIR, gt_iir);
1251 ret = IRQ_HANDLED;
b1f14ad0
JB		 1252 }
1253
0e43406b
CW		 1254 de_iir = I915_READ(DEIIR);
1255 if (de_iir) {
8664281b
PZ		 1256 if (de_iir & DE_ERR_INT_IVB)
1257 ivb_err_int_handler(dev);
1258
ce99c256
DV		 1259 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1260 dp_aux_irq_handler(dev);
1261
0e43406b 1262 if (de_iir & DE_GSE_IVB)
81a07809 1263 intel_opregion_asle_intr(dev);
0e43406b
CW		 1264
1265 for (i = 0; i < 3; i++) {
74d44445
DV		 1266 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1267 drm_handle_vblank(dev, i);
0e43406b
CW		 1268 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1269 intel_prepare_page_flip(dev, i);
1270 intel_finish_page_flip_plane(dev, i);
1271 }
0e43406b 1272 }
b615b57a 1273
0e43406b 1274 /* check event from PCH */
ab5c608b 1275 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
0e43406b 1276 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 1277
23e81d69 1278 cpt_irq_handler(dev, pch_iir);
b1f14ad0 1279
0e43406b
CW		 1280 /* clear PCH hotplug event before clear CPU irq */
1281 I915_WRITE(SDEIIR, pch_iir);
1282 }
b615b57a 1283
0e43406b
CW		 1284 I915_WRITE(DEIIR, de_iir);
1285 ret = IRQ_HANDLED;
b1f14ad0
JB		 1286 }
1287
0e43406b
CW		 1288 pm_iir = I915_READ(GEN6_PMIIR);
1289 if (pm_iir) {
baf02a1f
BW		 1290 if (IS_HASWELL(dev))
1291 hsw_pm_irq_handler(dev_priv, pm_iir);
4848405c 1292 else if (pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1293 gen6_rps_irq_handler(dev_priv, pm_iir);
0e43406b
CW		 1294 I915_WRITE(GEN6_PMIIR, pm_iir);
1295 ret = IRQ_HANDLED;
1296 }
b1f14ad0 1297
4bc9d430
DV		 1298 if (IS_HASWELL(dev)) {
1299 spin_lock(&dev_priv->irq_lock);
1300 if (ivb_can_enable_err_int(dev))
1301 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
1302 spin_unlock(&dev_priv->irq_lock);
1303 }
8664281b 1304
b1f14ad0
JB		 1305 I915_WRITE(DEIER, de_ier);
1306 POSTING_READ(DEIER);
ab5c608b
BW		 1307 if (!HAS_PCH_NOP(dev)) {
1308 I915_WRITE(SDEIER, sde_ier);
1309 POSTING_READ(SDEIER);
1310 }
b1f14ad0
JB		 1311
1312 return ret;
1313}
1314
e7b4c6b1
DV		 1315static void ilk_gt_irq_handler(struct drm_device *dev,
1316 struct drm_i915_private *dev_priv,
1317 u32 gt_iir)
1318{
cc609d5d
BW		 1319 if (gt_iir &
1320 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1321 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1322 if (gt_iir & ILK_BSD_USER_INTERRUPT)
e7b4c6b1
DV		 1323 notify_ring(dev, &dev_priv->ring[VCS]);
1324}
1325
ff1f525e 1326static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 1327{
4697995b 1328 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 1329 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1330 int ret = IRQ_NONE;
44498aea 1331 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 1332
4697995b
JB		 1333 atomic_inc(&dev_priv->irq_received);
1334
2d109a84
ZN		 1335 /* disable master interrupt before clearing iir */
1336 de_ier = I915_READ(DEIER);
1337 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 1338 POSTING_READ(DEIER);
2d109a84 1339
44498aea
PZ		 1340 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1341 * interrupts will will be stored on its back queue, and then we'll be
1342 * able to process them after we restore SDEIER (as soon as we restore
1343 * it, we'll get an interrupt if SDEIIR still has something to process
1344 * due to its back queue). */
1345 sde_ier = I915_READ(SDEIER);
1346 I915_WRITE(SDEIER, 0);
1347 POSTING_READ(SDEIER);
1348
036a4a7d
ZW		 1349 de_iir = I915_READ(DEIIR);
1350 gt_iir = I915_READ(GTIIR);
3b8d8d91 1351 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 1352
acd15b6c 1353 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 1354 goto done;
036a4a7d 1355
c7c85101 1356 ret = IRQ_HANDLED;
036a4a7d 1357
e7b4c6b1
DV		 1358 if (IS_GEN5(dev))
1359 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1360 else
1361 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 1362
ce99c256
DV		 1363 if (de_iir & DE_AUX_CHANNEL_A)
1364 dp_aux_irq_handler(dev);
1365
c7c85101 1366 if (de_iir & DE_GSE)
81a07809 1367 intel_opregion_asle_intr(dev);
c650156a 1368
74d44445
DV		 1369 if (de_iir & DE_PIPEA_VBLANK)
1370 drm_handle_vblank(dev, 0);
1371
1372 if (de_iir & DE_PIPEB_VBLANK)
1373 drm_handle_vblank(dev, 1);
1374
de032bf4
PZ		 1375 if (de_iir & DE_POISON)
1376 DRM_ERROR("Poison interrupt\n");
1377
8664281b
PZ		 1378 if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1379 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1380 DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1381
1382 if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1383 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1384 DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1385
f072d2e7 1386 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 1387 intel_prepare_page_flip(dev, 0);
2bbda389 1388 intel_finish_page_flip_plane(dev, 0);
f072d2e7 1389 }
013d5aa2 1390
f072d2e7 1391 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 1392 intel_prepare_page_flip(dev, 1);
2bbda389 1393 intel_finish_page_flip_plane(dev, 1);
f072d2e7 1394 }
013d5aa2 1395
c7c85101 1396 /* check event from PCH */
776ad806 1397 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 1398 u32 pch_iir = I915_READ(SDEIIR);
1399
23e81d69
AJ		 1400 if (HAS_PCH_CPT(dev))
1401 cpt_irq_handler(dev, pch_iir);
1402 else
1403 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 1404
1405 /* should clear PCH hotplug event before clear CPU irq */
1406 I915_WRITE(SDEIIR, pch_iir);
776ad806 1407 }
036a4a7d 1408
73edd18f 1409 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
d0ecd7e2 1410 ironlake_rps_change_irq_handler(dev);
f97108d1 1411
4848405c 1412 if (IS_GEN6(dev) && pm_iir & GEN6_PM_RPS_EVENTS)
d0ecd7e2 1413 gen6_rps_irq_handler(dev_priv, pm_iir);
3b8d8d91 1414
c7c85101
ZN		 1415 I915_WRITE(GTIIR, gt_iir);
1416 I915_WRITE(DEIIR, de_iir);
4912d041 1417 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 1418
1419done:
2d109a84 1420 I915_WRITE(DEIER, de_ier);
3143a2bf 1421 POSTING_READ(DEIER);
44498aea
PZ		 1422 I915_WRITE(SDEIER, sde_ier);
1423 POSTING_READ(SDEIER);
2d109a84 1424
036a4a7d
ZW		 1425 return ret;
1426}
1427
8a905236
JB		 1428/**
1429 * i915_error_work_func - do process context error handling work
1430 * @work: work struct
1431 *
1432 * Fire an error uevent so userspace can see that a hang or error
1433 * was detected.
1434 */
1435static void i915_error_work_func(struct work_struct *work)
1436{
1f83fee0
DV		 1437 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1438 work);
1439 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1440 gpu_error);
8a905236 1441 struct drm_device *dev = dev_priv->dev;
f69061be 1442 struct intel_ring_buffer *ring;
f316a42c
BG		 1443 char *error_event[] = { "ERROR=1", NULL };
1444 char *reset_event[] = { "RESET=1", NULL };
1445 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 1446 int i, ret;
8a905236 1447
f316a42c
BG		 1448 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1449
7db0ba24
DV		 1450 /*
1451 * Note that there's only one work item which does gpu resets, so we
1452 * need not worry about concurrent gpu resets potentially incrementing
1453 * error->reset_counter twice. We only need to take care of another
1454 * racing irq/hangcheck declaring the gpu dead for a second time. A
1455 * quick check for that is good enough: schedule_work ensures the
1456 * correct ordering between hang detection and this work item, and since
1457 * the reset in-progress bit is only ever set by code outside of this
1458 * work we don't need to worry about any other races.
1459 */
1460 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 1461 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 1462 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1463 reset_event);
1f83fee0 1464
f69061be
DV		 1465 ret = i915_reset(dev);
1466
1467 if (ret == 0) {
1468 /*
1469 * After all the gem state is reset, increment the reset
1470 * counter and wake up everyone waiting for the reset to
1471 * complete.
1472 *
1473 * Since unlock operations are a one-sided barrier only,
1474 * we need to insert a barrier here to order any seqno
1475 * updates before
1476 * the counter increment.
1477 */
1478 smp_mb__before_atomic_inc();
1479 atomic_inc(&dev_priv->gpu_error.reset_counter);
1480
1481 kobject_uevent_env(&dev->primary->kdev.kobj,
1482 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 1483 } else {
1484 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 1485 }
1f83fee0 1486
f69061be
DV		 1487 for_each_ring(ring, dev_priv, i)
1488 wake_up_all(&ring->irq_queue);
1489
96a02917
VS		 1490 intel_display_handle_reset(dev);
1491
1f83fee0 1492 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 1493 }
8a905236
JB		 1494}
1495
85f9e50d
DV		 1496/* NB: please notice the memset */
1497static void i915_get_extra_instdone(struct drm_device *dev,
1498 uint32_t *instdone)
1499{
1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1502
1503 switch(INTEL_INFO(dev)->gen) {
1504 case 2:
1505 case 3:
1506 instdone[0] = I915_READ(INSTDONE);
1507 break;
1508 case 4:
1509 case 5:
1510 case 6:
1511 instdone[0] = I915_READ(INSTDONE_I965);
1512 instdone[1] = I915_READ(INSTDONE1);
1513 break;
1514 default:
1515 WARN_ONCE(1, "Unsupported platform\n");
1516 case 7:
1517 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1518 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1519 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1520 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1521 break;
1522 }
1523}
1524
3bd3c932 1525#ifdef CONFIG_DEBUG_FS
9df30794 1526static struct drm_i915_error_object *
d0d045e8
BW		 1527i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1528 struct drm_i915_gem_object *src,
1529 const int num_pages)
9df30794
CW		 1530{
1531 struct drm_i915_error_object *dst;
d0d045e8 1532 int i;
e56660dd 1533 u32 reloc_offset;
9df30794 1534
05394f39 1535 if (src == NULL || src->pages == NULL)
9df30794
CW		 1536 return NULL;
1537
d0d045e8 1538 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1539 if (dst == NULL)
1540 return NULL;
1541
f343c5f6 1542 reloc_offset = dst->gtt_offset = i915_gem_obj_ggtt_offset(src);
d0d045e8 1543 for (i = 0; i < num_pages; i++) {
788885ae 1544 unsigned long flags;
e56660dd 1545 void *d;
788885ae 1546
e56660dd 1547 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1548 if (d == NULL)
1549 goto unwind;
e56660dd 1550
788885ae 1551 local_irq_save(flags);
5d4545ae 1552 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1553 src->has_global_gtt_mapping) {
172975aa
CW		 1554 void __iomem *s;
1555
1556 /* Simply ignore tiling or any overlapping fence.
1557 * It's part of the error state, and this hopefully
1558 * captures what the GPU read.
1559 */
1560
5d4545ae 1561 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1562 reloc_offset);
1563 memcpy_fromio(d, s, PAGE_SIZE);
1564 io_mapping_unmap_atomic(s);
960e3564
CW		 1565 } else if (src->stolen) {
1566 unsigned long offset;
1567
1568 offset = dev_priv->mm.stolen_base;
1569 offset += src->stolen->start;
1570 offset += i << PAGE_SHIFT;
1571
1a240d4d 1572 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1573 } else {
9da3da66 1574 struct page *page;
172975aa
CW		 1575 void *s;
1576
9da3da66 1577 page = i915_gem_object_get_page(src, i);
172975aa 1578
9da3da66
CW		 1579 drm_clflush_pages(&page, 1);
1580
1581 s = kmap_atomic(page);
172975aa
CW		 1582 memcpy(d, s, PAGE_SIZE);
1583 kunmap_atomic(s);
1584
9da3da66 1585 drm_clflush_pages(&page, 1);
172975aa 1586 }
788885ae 1587 local_irq_restore(flags);
e56660dd 1588
9da3da66 1589 dst->pages[i] = d;
e56660dd
CW		 1590
1591 reloc_offset += PAGE_SIZE;
9df30794 1592 }
d0d045e8 1593 dst->page_count = num_pages;
9df30794
CW		 1594
1595 return dst;
1596
1597unwind:
9da3da66
CW		 1598 while (i--)
1599 kfree(dst->pages[i]);
9df30794
CW		 1600 kfree(dst);
1601 return NULL;
1602}
d0d045e8
BW		 1603#define i915_error_object_create(dev_priv, src) \
1604 i915_error_object_create_sized((dev_priv), (src), \
1605 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1606
1607static void
1608i915_error_object_free(struct drm_i915_error_object *obj)
1609{
1610 int page;
1611
1612 if (obj == NULL)
1613 return;
1614
1615 for (page = 0; page < obj->page_count; page++)
1616 kfree(obj->pages[page]);
1617
1618 kfree(obj);
1619}
1620
742cbee8
DV		 1621void
1622i915_error_state_free(struct kref *error_ref)
9df30794 1623{
742cbee8
DV		 1624 struct drm_i915_error_state *error = container_of(error_ref,
1625 typeof(*error), ref);
e2f973d5
CW		 1626 int i;
1627
52d39a21
CW		 1628 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1629 i915_error_object_free(error->ring[i].batchbuffer);
1630 i915_error_object_free(error->ring[i].ringbuffer);
7ed73da0 1631 i915_error_object_free(error->ring[i].ctx);
52d39a21
CW		 1632 kfree(error->ring[i].requests);
1633 }
e2f973d5 1634
9df30794 1635 kfree(error->active_bo);
6ef3d427 1636 kfree(error->overlay);
7ed73da0 1637 kfree(error->display);
9df30794
CW		 1638 kfree(error);
1639}
1b50247a
CW		 1640static void capture_bo(struct drm_i915_error_buffer *err,
1641 struct drm_i915_gem_object *obj)
1642{
1643 err->size = obj->base.size;
1644 err->name = obj->base.name;
0201f1ec
CW		 1645 err->rseqno = obj->last_read_seqno;
1646 err->wseqno = obj->last_write_seqno;
f343c5f6 1647 err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
1b50247a
CW		 1648 err->read_domains = obj->base.read_domains;
1649 err->write_domain = obj->base.write_domain;
1650 err->fence_reg = obj->fence_reg;
1651 err->pinned = 0;
1652 if (obj->pin_count > 0)
1653 err->pinned = 1;
1654 if (obj->user_pin_count > 0)
1655 err->pinned = -1;
1656 err->tiling = obj->tiling_mode;
1657 err->dirty = obj->dirty;
1658 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1659 err->ring = obj->ring ? obj->ring->id : -1;
1660 err->cache_level = obj->cache_level;
1661}
9df30794 1662
1b50247a
CW		 1663static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1664 int count, struct list_head *head)
c724e8a9
CW		 1665{
1666 struct drm_i915_gem_object *obj;
1667 int i = 0;
1668
1669 list_for_each_entry(obj, head, mm_list) {
1b50247a 1670 capture_bo(err++, obj);
c724e8a9
CW		 1671 if (++i == count)
1672 break;
1b50247a
CW		 1673 }
1674
1675 return i;
1676}
1677
1678static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1679 int count, struct list_head *head)
1680{
1681 struct drm_i915_gem_object *obj;
1682 int i = 0;
1683
35c20a60 1684 list_for_each_entry(obj, head, global_list) {
1b50247a
CW		 1685 if (obj->pin_count == 0)
1686 continue;
c724e8a9 1687
1b50247a
CW		 1688 capture_bo(err++, obj);
1689 if (++i == count)
1690 break;
c724e8a9
CW		 1691 }
1692
1693 return i;
1694}
1695
748ebc60
CW		 1696static void i915_gem_record_fences(struct drm_device *dev,
1697 struct drm_i915_error_state *error)
1698{
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 int i;
1701
1702 /* Fences */
1703 switch (INTEL_INFO(dev)->gen) {
775d17b6 1704 case 7:
748ebc60 1705 case 6:
42b5aeab 1706 for (i = 0; i < dev_priv->num_fence_regs; i++)
748ebc60
CW		 1707 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1708 break;
1709 case 5:
1710 case 4:
1711 for (i = 0; i < 16; i++)
1712 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1713 break;
1714 case 3:
1715 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1716 for (i = 0; i < 8; i++)
1717 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1718 case 2:
1719 for (i = 0; i < 8; i++)
1720 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1721 break;
1722
7dbf9d6e
BW		 1723 default:
1724 BUG();
748ebc60
CW		 1725 }
1726}
1727
bcfb2e28
CW		 1728static struct drm_i915_error_object *
1729i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1730 struct intel_ring_buffer *ring)
1731{
1732 struct drm_i915_gem_object *obj;
1733 u32 seqno;
1734
1735 if (!ring->get_seqno)
1736 return NULL;
1737
b45305fc
DV		 1738 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1739 u32 acthd = I915_READ(ACTHD);
1740
1741 if (WARN_ON(ring->id != RCS))
1742 return NULL;
1743
1744 obj = ring->private;
f343c5f6
BW		 1745 if (acthd >= i915_gem_obj_ggtt_offset(obj) &&
1746 acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
b45305fc
DV		 1747 return i915_error_object_create(dev_priv, obj);
1748 }
1749
b2eadbc8 1750 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1751 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1752 if (obj->ring != ring)
1753 continue;
1754
0201f1ec 1755 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1756 continue;
1757
1758 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1759 continue;
1760
1761 /* We need to copy these to an anonymous buffer as the simplest
1762 * method to avoid being overwritten by userspace.
1763 */
1764 return i915_error_object_create(dev_priv, obj);
1765 }
1766
1767 return NULL;
1768}
1769
d27b1e0e
DV		 1770static void i915_record_ring_state(struct drm_device *dev,
1771 struct drm_i915_error_state *error,
1772 struct intel_ring_buffer *ring)
1773{
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775
33f3f518 1776 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1777 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1778 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1779 error->semaphore_mboxes[ring->id][0]
1780 = I915_READ(RING_SYNC_0(ring->mmio_base));
1781 error->semaphore_mboxes[ring->id][1]
1782 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1783 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1784 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1785 }
c1cd90ed 1786
d27b1e0e 1787 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1788 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1789 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1790 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1791 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1792 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1793 if (ring->id == RCS)
d27b1e0e 1794 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1795 } else {
9d2f41fa 1796 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1797 error->ipeir[ring->id] = I915_READ(IPEIR);
1798 error->ipehr[ring->id] = I915_READ(IPEHR);
1799 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1800 }
1801
9574b3fe 1802 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1803 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1804 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1805 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1806 error->head[ring->id] = I915_READ_HEAD(ring);
1807 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1808 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1809
1810 error->cpu_ring_head[ring->id] = ring->head;
1811 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1812}
1813
8c123e54
BW		 1814
1815static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1816 struct drm_i915_error_state *error,
1817 struct drm_i915_error_ring *ering)
1818{
1819 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1820 struct drm_i915_gem_object *obj;
1821
1822 /* Currently render ring is the only HW context user */
1823 if (ring->id != RCS || !error->ccid)
1824 return;
1825
35c20a60 1826 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
f343c5f6 1827 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
8c123e54
BW		 1828 ering->ctx = i915_error_object_create_sized(dev_priv,
1829 obj, 1);
3ef8fb5a 1830 break;
8c123e54
BW		 1831 }
1832 }
1833}
1834
52d39a21
CW		 1835static void i915_gem_record_rings(struct drm_device *dev,
1836 struct drm_i915_error_state *error)
1837{
1838 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1839 struct intel_ring_buffer *ring;
52d39a21
CW		 1840 struct drm_i915_gem_request *request;
1841 int i, count;
1842
b4519513 1843 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1844 i915_record_ring_state(dev, error, ring);
1845
1846 error->ring[i].batchbuffer =
1847 i915_error_first_batchbuffer(dev_priv, ring);
1848
1849 error->ring[i].ringbuffer =
1850 i915_error_object_create(dev_priv, ring->obj);
1851
8c123e54
BW		 1852
1853 i915_gem_record_active_context(ring, error, &error->ring[i]);
1854
52d39a21
CW		 1855 count = 0;
1856 list_for_each_entry(request, &ring->request_list, list)
1857 count++;
1858
1859 error->ring[i].num_requests = count;
1860 error->ring[i].requests =
1861 kmalloc(count*sizeof(struct drm_i915_error_request),
1862 GFP_ATOMIC);
1863 if (error->ring[i].requests == NULL) {
1864 error->ring[i].num_requests = 0;
1865 continue;
1866 }
1867
1868 count = 0;
1869 list_for_each_entry(request, &ring->request_list, list) {
1870 struct drm_i915_error_request *erq;
1871
1872 erq = &error->ring[i].requests[count++];
1873 erq->seqno = request->seqno;
1874 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1875 erq->tail = request->tail;
52d39a21
CW		 1876 }
1877 }
1878}
1879
26b7c224
BW		 1880static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1881 struct drm_i915_error_state *error)
1882{
1883 struct drm_i915_gem_object *obj;
1884 int i;
1885
1886 i = 0;
1887 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1888 i++;
1889 error->active_bo_count = i;
1890 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1891 if (obj->pin_count)
1892 i++;
1893 error->pinned_bo_count = i - error->active_bo_count;
1894
1895 if (i) {
1896 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1897 GFP_ATOMIC);
1898 if (error->active_bo)
1899 error->pinned_bo =
1900 error->active_bo + error->active_bo_count;
1901 }
1902
1903 if (error->active_bo)
1904 error->active_bo_count =
1905 capture_active_bo(error->active_bo,
1906 error->active_bo_count,
1907 &dev_priv->mm.active_list);
1908
1909 if (error->pinned_bo)
1910 error->pinned_bo_count =
1911 capture_pinned_bo(error->pinned_bo,
1912 error->pinned_bo_count,
1913 &dev_priv->mm.bound_list);
1914}
1915
8a905236
JB		 1916/**
1917 * i915_capture_error_state - capture an error record for later analysis
1918 * @dev: drm device
1919 *
1920 * Should be called when an error is detected (either a hang or an error
1921 * interrupt) to capture error state from the time of the error. Fills
1922 * out a structure which becomes available in debugfs for user level tools
1923 * to pick up.
1924 */
63eeaf38
JB		 1925static void i915_capture_error_state(struct drm_device *dev)
1926{
1927 struct drm_i915_private *dev_priv = dev->dev_private;
1928 struct drm_i915_error_state *error;
1929 unsigned long flags;
26b7c224 1930 int pipe;
63eeaf38 1931
99584db3
DV		 1932 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1933 error = dev_priv->gpu_error.first_error;
1934 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1935 if (error)
1936 return;
63eeaf38 1937
9db4a9c7 1938 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1939 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1940 if (!error) {
9df30794
CW		 1941 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1942 return;
63eeaf38
JB		 1943 }
1944
5d83d294 1945 DRM_INFO("capturing error event; look for more information in "
ef86ddce 1946 "/sys/class/drm/card%d/error\n", dev->primary->index);
2fa772f3 1947
742cbee8 1948 kref_init(&error->ref);
63eeaf38
JB		 1949 error->eir = I915_READ(EIR);
1950 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1951 if (HAS_HW_CONTEXTS(dev))
1952 error->ccid = I915_READ(CCID);
be998e2e
BW		 1953
1954 if (HAS_PCH_SPLIT(dev))
1955 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1956 else if (IS_VALLEYVIEW(dev))
1957 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1958 else if (IS_GEN2(dev))
1959 error->ier = I915_READ16(IER);
1960 else
1961 error->ier = I915_READ(IER);
1962
0f3b6849
CW		 1963 if (INTEL_INFO(dev)->gen >= 6)
1964 error->derrmr = I915_READ(DERRMR);
1965
1966 if (IS_VALLEYVIEW(dev))
1967 error->forcewake = I915_READ(FORCEWAKE_VLV);
1968 else if (INTEL_INFO(dev)->gen >= 7)
1969 error->forcewake = I915_READ(FORCEWAKE_MT);
1970 else if (INTEL_INFO(dev)->gen == 6)
1971 error->forcewake = I915_READ(FORCEWAKE);
1972
4f3308b9
PZ		 1973 if (!HAS_PCH_SPLIT(dev))
1974 for_each_pipe(pipe)
1975 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1976
33f3f518 1977 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1978 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1979 error->done_reg = I915_READ(DONE_REG);
1980 }
d27b1e0e 1981
71e172e8
BW		 1982 if (INTEL_INFO(dev)->gen == 7)
1983 error->err_int = I915_READ(GEN7_ERR_INT);
1984
050ee91f
BW		 1985 i915_get_extra_instdone(dev, error->extra_instdone);
1986
26b7c224 1987 i915_gem_capture_buffers(dev_priv, error);
748ebc60 1988 i915_gem_record_fences(dev, error);
52d39a21 1989 i915_gem_record_rings(dev, error);
9df30794 1990
9df30794
CW		 1991 do_gettimeofday(&error->time);
1992
6ef3d427 1993 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1994 error->display = intel_display_capture_error_state(dev);
6ef3d427 1995
99584db3
DV		 1996 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1997 if (dev_priv->gpu_error.first_error == NULL) {
1998 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1999 error = NULL;
2000 }
99584db3 2001 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 2002
2003 if (error)
742cbee8 2004 i915_error_state_free(&error->ref);
9df30794
CW		 2005}
2006
2007void i915_destroy_error_state(struct drm_device *dev)
2008{
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 struct drm_i915_error_state *error;
6dc0e816 2011 unsigned long flags;
9df30794 2012
99584db3
DV		 2013 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
2014 error = dev_priv->gpu_error.first_error;
2015 dev_priv->gpu_error.first_error = NULL;
2016 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 2017
2018 if (error)
742cbee8 2019 kref_put(&error->ref, i915_error_state_free);
63eeaf38 2020}
3bd3c932
CW		 2021#else
2022#define i915_capture_error_state(x)
2023#endif
63eeaf38 2024
35aed2e6 2025static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2028 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2029 u32 eir = I915_READ(EIR);
050ee91f 2030 int pipe, i;
8a905236 2031
35aed2e6
CW		 2032 if (!eir)
2033 return;
8a905236 2034
a70491cc 2035 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2036
bd9854f9
BW		 2037 i915_get_extra_instdone(dev, instdone);
2038
8a905236
JB		 2039 if (IS_G4X(dev)) {
2040 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2041 u32 ipeir = I915_READ(IPEIR_I965);
2042
a70491cc
JP		 2043 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2044 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2045 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2046 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2047 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2048 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2049 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2050 POSTING_READ(IPEIR_I965);
8a905236
JB		 2051 }
2052 if (eir & GM45_ERROR_PAGE_TABLE) {
2053 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2054 pr_err("page table error\n");
2055 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2056 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2057 POSTING_READ(PGTBL_ER);
8a905236
JB		 2058 }
2059 }
2060
a6c45cf0 2061 if (!IS_GEN2(dev)) {
8a905236
JB		 2062 if (eir & I915_ERROR_PAGE_TABLE) {
2063 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2064 pr_err("page table error\n");
2065 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2066 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2067 POSTING_READ(PGTBL_ER);
8a905236
JB		 2068 }
2069 }
2070
2071 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2072 pr_err("memory refresh error:\n");
9db4a9c7 2073 for_each_pipe(pipe)
a70491cc 2074 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2075 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2076 /* pipestat has already been acked */
2077 }
2078 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2079 pr_err("instruction error\n");
2080 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2081 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2082 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2083 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2084 u32 ipeir = I915_READ(IPEIR);
2085
a70491cc
JP		 2086 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2087 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2088 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2089 I915_WRITE(IPEIR, ipeir);
3143a2bf 2090 POSTING_READ(IPEIR);
8a905236
JB		 2091 } else {
2092 u32 ipeir = I915_READ(IPEIR_I965);
2093
a70491cc
JP		 2094 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2095 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2096 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2097 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2098 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2099 POSTING_READ(IPEIR_I965);
8a905236
JB		 2100 }
2101 }
2102
2103 I915_WRITE(EIR, eir);
3143a2bf 2104 POSTING_READ(EIR);
8a905236
JB		 2105 eir = I915_READ(EIR);
2106 if (eir) {
2107 /*
2108 * some errors might have become stuck,
2109 * mask them.
2110 */
2111 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2112 I915_WRITE(EMR, I915_READ(EMR) | eir);
2113 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2114 }
35aed2e6
CW		 2115}
2116
2117/**
2118 * i915_handle_error - handle an error interrupt
2119 * @dev: drm device
2120 *
2121 * Do some basic checking of regsiter state at error interrupt time and
2122 * dump it to the syslog. Also call i915_capture_error_state() to make
2123 * sure we get a record and make it available in debugfs. Fire a uevent
2124 * so userspace knows something bad happened (should trigger collection
2125 * of a ring dump etc.).
2126 */
527f9e90 2127void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 2128{
2129 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 2130 struct intel_ring_buffer *ring;
2131 int i;
35aed2e6
CW		 2132
2133 i915_capture_error_state(dev);
2134 i915_report_and_clear_eir(dev);
8a905236 2135
ba1234d1 2136 if (wedged) {
f69061be
DV		 2137 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2138 &dev_priv->gpu_error.reset_counter);
ba1234d1 2139
11ed50ec 2140 /*
1f83fee0
DV		 2141 * Wakeup waiting processes so that the reset work item
2142 * doesn't deadlock trying to grab various locks.
11ed50ec 2143 */
b4519513
CW		 2144 for_each_ring(ring, dev_priv, i)
2145 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 2146 }
2147
99584db3 2148 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 2149}
2150
21ad8330 2151static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 2152{
2153 drm_i915_private_t *dev_priv = dev->dev_private;
2154 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2156 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2157 struct intel_unpin_work *work;
2158 unsigned long flags;
2159 bool stall_detected;
2160
2161 /* Ignore early vblank irqs */
2162 if (intel_crtc == NULL)
2163 return;
2164
2165 spin_lock_irqsave(&dev->event_lock, flags);
2166 work = intel_crtc->unpin_work;
2167
e7d841ca
CW		 2168 if (work == NULL ||
2169 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2170 !work->enable_stall_check) {
4e5359cd
SF		 2171 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2172 spin_unlock_irqrestore(&dev->event_lock, flags);
2173 return;
2174 }
2175
2176 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2177 obj = work->pending_flip_obj;
a6c45cf0 2178 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2179 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2180 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2181 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2182 } else {
9db4a9c7 2183 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2184 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 2185 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2186 crtc->x * crtc->fb->bits_per_pixel/8);
2187 }
2188
2189 spin_unlock_irqrestore(&dev->event_lock, flags);
2190
2191 if (stall_detected) {
2192 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2193 intel_prepare_page_flip(dev, intel_crtc->plane);
2194 }
2195}
2196
42f52ef8
KP		 2197/* Called from drm generic code, passed 'crtc' which
2198 * we use as a pipe index
2199 */
f71d4af4 2200static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2201{
2202 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2203 unsigned long irqflags;
71e0ffa5 2204
5eddb70b 2205 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2206 return -EINVAL;
0a3e67a4 2207
1ec14ad3 2208 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2209 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 2210 i915_enable_pipestat(dev_priv, pipe,
2211 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 2212 else
7c463586
KP		 2213 i915_enable_pipestat(dev_priv, pipe,
2214 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 2215
2216 /* maintain vblank delivery even in deep C-states */
2217 if (dev_priv->info->gen == 3)
6b26c86d 2218 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2219 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2220
0a3e67a4
JB		 2221 return 0;
2222}
2223
f71d4af4 2224static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2225{
2226 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2227 unsigned long irqflags;
2228
2229 if (!i915_pipe_enabled(dev, pipe))
2230 return -EINVAL;
2231
2232 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2233 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2234 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 2235 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2236
2237 return 0;
2238}
2239
f71d4af4 2240static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2241{
2242 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2243 unsigned long irqflags;
2244
2245 if (!i915_pipe_enabled(dev, pipe))
2246 return -EINVAL;
2247
2248 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2249 ironlake_enable_display_irq(dev_priv,
2250 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 2251 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2252
2253 return 0;
2254}
2255
7e231dbe
JB		 2256static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2257{
2258 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2259 unsigned long irqflags;
31acc7f5 2260 u32 imr;
7e231dbe
JB		 2261
2262 if (!i915_pipe_enabled(dev, pipe))
2263 return -EINVAL;
2264
2265 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 2266 imr = I915_READ(VLV_IMR);
31acc7f5 2267 if (pipe == 0)
7e231dbe 2268 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2269 else
7e231dbe 2270 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2271 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 2272 i915_enable_pipestat(dev_priv, pipe,
2273 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 2274 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2275
2276 return 0;
2277}
2278
42f52ef8
KP		 2279/* Called from drm generic code, passed 'crtc' which
2280 * we use as a pipe index
2281 */
f71d4af4 2282static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 2283{
2284 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 2285 unsigned long irqflags;
0a3e67a4 2286
1ec14ad3 2287 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 2288 if (dev_priv->info->gen == 3)
6b26c86d 2289 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2290
f796cf8f
JB		 2291 i915_disable_pipestat(dev_priv, pipe,
2292 PIPE_VBLANK_INTERRUPT_ENABLE |
2293 PIPE_START_VBLANK_INTERRUPT_ENABLE);
2294 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2295}
2296
f71d4af4 2297static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 2298{
2299 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2300 unsigned long irqflags;
2301
2302 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2303 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 2304 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 2305 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 2306}
2307
f71d4af4 2308static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 2309{
2310 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2311 unsigned long irqflags;
2312
2313 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 2314 ironlake_disable_display_irq(dev_priv,
2315 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 2316 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2317}
2318
7e231dbe
JB		 2319static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2320{
2321 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2322 unsigned long irqflags;
31acc7f5 2323 u32 imr;
7e231dbe
JB		 2324
2325 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 2326 i915_disable_pipestat(dev_priv, pipe,
2327 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 2328 imr = I915_READ(VLV_IMR);
31acc7f5 2329 if (pipe == 0)
7e231dbe 2330 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 2331 else
7e231dbe 2332 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2333 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 2334 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2335}
2336
893eead0
CW		 2337static u32
2338ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2339{
893eead0
CW		 2340 return list_entry(ring->request_list.prev,
2341 struct drm_i915_gem_request, list)->seqno;
2342}
2343
9107e9d2
CW		 2344static bool
2345ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2346{
2347 return (list_empty(&ring->request_list) ||
2348 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2349}
2350
6274f212
CW		 2351static struct intel_ring_buffer *
2352semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2353{
2354 struct drm_i915_private *dev_priv = ring->dev->dev_private;
6274f212 2355 u32 cmd, ipehr, acthd, acthd_min;
a24a11e6
CW		 2356
2357 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
2358 if ((ipehr & ~(0x3 << 16)) !=
2359 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
6274f212 2360 return NULL;
a24a11e6
CW		 2361
2362 /* ACTHD is likely pointing to the dword after the actual command,
2363 * so scan backwards until we find the MBOX.
2364 */
6274f212 2365 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
a24a11e6
CW		 2366 acthd_min = max((int)acthd - 3 * 4, 0);
2367 do {
2368 cmd = ioread32(ring->virtual_start + acthd);
2369 if (cmd == ipehr)
2370 break;
2371
2372 acthd -= 4;
2373 if (acthd < acthd_min)
6274f212 2374 return NULL;
a24a11e6
CW		 2375 } while (1);
2376
6274f212
CW		 2377 *seqno = ioread32(ring->virtual_start+acthd+4)+1;
2378 return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
a24a11e6
CW		 2379}
2380
6274f212
CW		 2381static int semaphore_passed(struct intel_ring_buffer *ring)
2382{
2383 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2384 struct intel_ring_buffer *signaller;
2385 u32 seqno, ctl;
2386
2387 ring->hangcheck.deadlock = true;
2388
2389 signaller = semaphore_waits_for(ring, &seqno);
2390 if (signaller == NULL || signaller->hangcheck.deadlock)
2391 return -1;
2392
2393 /* cursory check for an unkickable deadlock */
2394 ctl = I915_READ_CTL(signaller);
2395 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2396 return -1;
2397
2398 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2399}
2400
2401static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2402{
2403 struct intel_ring_buffer *ring;
2404 int i;
2405
2406 for_each_ring(ring, dev_priv, i)
2407 ring->hangcheck.deadlock = false;
2408}
2409
ad8beaea
MK		 2410static enum intel_ring_hangcheck_action
2411ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1ec14ad3
CW		 2412{
2413 struct drm_device *dev = ring->dev;
2414 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2415 u32 tmp;
2416
6274f212
CW		 2417 if (ring->hangcheck.acthd != acthd)
2418 return active;
2419
9107e9d2 2420 if (IS_GEN2(dev))
6274f212 2421 return hung;
9107e9d2
CW		 2422
2423 /* Is the chip hanging on a WAIT_FOR_EVENT?
2424 * If so we can simply poke the RB_WAIT bit
2425 * and break the hang. This should work on
2426 * all but the second generation chipsets.
2427 */
2428 tmp = I915_READ_CTL(ring);
1ec14ad3
CW		 2429 if (tmp & RING_WAIT) {
2430 DRM_ERROR("Kicking stuck wait on %s\n",
2431 ring->name);
2432 I915_WRITE_CTL(ring, tmp);
6274f212
CW		 2433 return kick;
2434 }
2435
2436 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2437 switch (semaphore_passed(ring)) {
2438 default:
2439 return hung;
2440 case 1:
2441 DRM_ERROR("Kicking stuck semaphore on %s\n",
2442 ring->name);
2443 I915_WRITE_CTL(ring, tmp);
2444 return kick;
2445 case 0:
2446 return wait;
2447 }
9107e9d2 2448 }
ed5cbb03 2449
6274f212 2450 return hung;
ed5cbb03
MK		 2451}
2452
f65d9421
BG		 2453/**
2454 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2455 * batchbuffers in a long time. We keep track per ring seqno progress and
2456 * if there are no progress, hangcheck score for that ring is increased.
2457 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2458 * we kick the ring. If we see no progress on three subsequent calls
2459 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421
BG		 2460 */
2461void i915_hangcheck_elapsed(unsigned long data)
2462{
2463 struct drm_device *dev = (struct drm_device *)data;
2464 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513 2465 struct intel_ring_buffer *ring;
b4519513 2466 int i;
05407ff8 2467 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2468 bool stuck[I915_NUM_RINGS] = { 0 };
2469#define BUSY 1
2470#define KICK 5
2471#define HUNG 20
2472#define FIRE 30
893eead0 2473
3e0dc6b0
BW		 2474 if (!i915_enable_hangcheck)
2475 return;
2476
b4519513 2477 for_each_ring(ring, dev_priv, i) {
05407ff8 2478 u32 seqno, acthd;
9107e9d2 2479 bool busy = true;
05407ff8 2480
6274f212
CW		 2481 semaphore_clear_deadlocks(dev_priv);
2482
05407ff8
MK		 2483 seqno = ring->get_seqno(ring, false);
2484 acthd = intel_ring_get_active_head(ring);
b4519513 2485
9107e9d2
CW		 2486 if (ring->hangcheck.seqno == seqno) {
2487 if (ring_idle(ring, seqno)) {
2488 if (waitqueue_active(&ring->irq_queue)) {
2489 /* Issue a wake-up to catch stuck h/w. */
2490 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2491 ring->name);
2492 wake_up_all(&ring->irq_queue);
2493 ring->hangcheck.score += HUNG;
2494 } else
2495 busy = false;
05407ff8 2496 } else {
9107e9d2
CW		 2497 int score;
2498
6274f212
CW		 2499 /* We always increment the hangcheck score
2500 * if the ring is busy and still processing
2501 * the same request, so that no single request
2502 * can run indefinitely (such as a chain of
2503 * batches). The only time we do not increment
2504 * the hangcheck score on this ring, if this
2505 * ring is in a legitimate wait for another
2506 * ring. In that case the waiting ring is a
2507 * victim and we want to be sure we catch the
2508 * right culprit. Then every time we do kick
2509 * the ring, add a small increment to the
2510 * score so that we can catch a batch that is
2511 * being repeatedly kicked and so responsible
2512 * for stalling the machine.
2513 */
ad8beaea
MK		 2514 ring->hangcheck.action = ring_stuck(ring,
2515 acthd);
2516
2517 switch (ring->hangcheck.action) {
6274f212
CW		 2518 case wait:
2519 score = 0;
2520 break;
2521 case active:
9107e9d2 2522 score = BUSY;
6274f212
CW		 2523 break;
2524 case kick:
2525 score = KICK;
2526 break;
2527 case hung:
2528 score = HUNG;
2529 stuck[i] = true;
2530 break;
2531 }
9107e9d2 2532 ring->hangcheck.score += score;
05407ff8 2533 }
9107e9d2
CW		 2534 } else {
2535 /* Gradually reduce the count so that we catch DoS
2536 * attempts across multiple batches.
2537 */
2538 if (ring->hangcheck.score > 0)
2539 ring->hangcheck.score--;
d1e61e7f
CW		 2540 }
2541
05407ff8
MK		 2542 ring->hangcheck.seqno = seqno;
2543 ring->hangcheck.acthd = acthd;
9107e9d2 2544 busy_count += busy;
893eead0 2545 }
b9201c14 2546
92cab734 2547 for_each_ring(ring, dev_priv, i) {
9107e9d2 2548 if (ring->hangcheck.score > FIRE) {
acd78c11 2549 DRM_ERROR("%s on %s\n",
05407ff8 2550 stuck[i] ? "stuck" : "no progress",
a43adf07
CW		 2551 ring->name);
2552 rings_hung++;
92cab734
MK		 2553 }
2554 }
2555
05407ff8
MK		 2556 if (rings_hung)
2557 return i915_handle_error(dev, true);
f65d9421 2558
05407ff8
MK		 2559 if (busy_count)
2560 /* Reset timer case chip hangs without another request
2561 * being added */
2562 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2563 round_jiffies_up(jiffies +
2564 DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2565}
2566
91738a95
PZ		 2567static void ibx_irq_preinstall(struct drm_device *dev)
2568{
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570
2571 if (HAS_PCH_NOP(dev))
2572 return;
2573
2574 /* south display irq */
2575 I915_WRITE(SDEIMR, 0xffffffff);
2576 /*
2577 * SDEIER is also touched by the interrupt handler to work around missed
2578 * PCH interrupts. Hence we can't update it after the interrupt handler
2579 * is enabled - instead we unconditionally enable all PCH interrupt
2580 * sources here, but then only unmask them as needed with SDEIMR.
2581 */
2582 I915_WRITE(SDEIER, 0xffffffff);
2583 POSTING_READ(SDEIER);
2584}
2585
1da177e4
LT		 2586/* drm_dma.h hooks
2587*/
f71d4af4 2588static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2589{
2590 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2591
4697995b
JB		 2592 atomic_set(&dev_priv->irq_received, 0);
2593
036a4a7d 2594 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2595
036a4a7d
ZW		 2596 /* XXX hotplug from PCH */
2597
2598 I915_WRITE(DEIMR, 0xffffffff);
2599 I915_WRITE(DEIER, 0x0);
3143a2bf 2600 POSTING_READ(DEIER);
036a4a7d
ZW		 2601
2602 /* and GT */
2603 I915_WRITE(GTIMR, 0xffffffff);
2604 I915_WRITE(GTIER, 0x0);
3143a2bf 2605 POSTING_READ(GTIER);
c650156a 2606
91738a95 2607 ibx_irq_preinstall(dev);
7d99163d
BW		 2608}
2609
2610static void ivybridge_irq_preinstall(struct drm_device *dev)
2611{
2612 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2613
2614 atomic_set(&dev_priv->irq_received, 0);
2615
2616 I915_WRITE(HWSTAM, 0xeffe);
2617
2618 /* XXX hotplug from PCH */
2619
2620 I915_WRITE(DEIMR, 0xffffffff);
2621 I915_WRITE(DEIER, 0x0);
2622 POSTING_READ(DEIER);
2623
2624 /* and GT */
2625 I915_WRITE(GTIMR, 0xffffffff);
2626 I915_WRITE(GTIER, 0x0);
2627 POSTING_READ(GTIER);
2628
eda63ffb
BW		 2629 /* Power management */
2630 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2631 I915_WRITE(GEN6_PMIER, 0x0);
2632 POSTING_READ(GEN6_PMIER);
2633
91738a95 2634 ibx_irq_preinstall(dev);
036a4a7d
ZW		 2635}
2636
7e231dbe
JB		 2637static void valleyview_irq_preinstall(struct drm_device *dev)
2638{
2639 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2640 int pipe;
2641
2642 atomic_set(&dev_priv->irq_received, 0);
2643
7e231dbe
JB		 2644 /* VLV magic */
2645 I915_WRITE(VLV_IMR, 0);
2646 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2647 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2648 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2649
7e231dbe
JB		 2650 /* and GT */
2651 I915_WRITE(GTIIR, I915_READ(GTIIR));
2652 I915_WRITE(GTIIR, I915_READ(GTIIR));
2653 I915_WRITE(GTIMR, 0xffffffff);
2654 I915_WRITE(GTIER, 0x0);
2655 POSTING_READ(GTIER);
2656
2657 I915_WRITE(DPINVGTT, 0xff);
2658
2659 I915_WRITE(PORT_HOTPLUG_EN, 0);
2660 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2661 for_each_pipe(pipe)
2662 I915_WRITE(PIPESTAT(pipe), 0xffff);
2663 I915_WRITE(VLV_IIR, 0xffffffff);
2664 I915_WRITE(VLV_IMR, 0xffffffff);
2665 I915_WRITE(VLV_IER, 0x0);
2666 POSTING_READ(VLV_IER);
2667}
2668
82a28bcf 2669static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2670{
2671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2672 struct drm_mode_config *mode_config = &dev->mode_config;
2673 struct intel_encoder *intel_encoder;
fee884ed 2674 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2675
2676 if (HAS_PCH_IBX(dev)) {
fee884ed 2677 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2678 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2679 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2680 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2681 } else {
fee884ed 2682 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2683 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2684 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2685 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2686 }
7fe0b973 2687
fee884ed 2688 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2689
2690 /*
2691 * Enable digital hotplug on the PCH, and configure the DP short pulse
2692 * duration to 2ms (which is the minimum in the Display Port spec)
2693 *
2694 * This register is the same on all known PCH chips.
2695 */
7fe0b973
KP		 2696 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2697 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2698 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2699 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2700 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2701 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2702}
2703
d46da437
PZ		 2704static void ibx_irq_postinstall(struct drm_device *dev)
2705{
2706 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2707 u32 mask;
e5868a31 2708
692a04cf
DV		 2709 if (HAS_PCH_NOP(dev))
2710 return;
2711
8664281b
PZ		 2712 if (HAS_PCH_IBX(dev)) {
2713 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
de032bf4 2714 SDE_TRANSA_FIFO_UNDER | SDE_POISON;
8664281b
PZ		 2715 } else {
2716 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2717
2718 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2719 }
ab5c608b 2720
d46da437
PZ		 2721 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2722 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2723}
2724
f71d4af4 2725static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 2726{
4bc9d430
DV		 2727 unsigned long irqflags;
2728
036a4a7d
ZW		 2729 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2730 /* enable kind of interrupts always enabled */
013d5aa2 2731 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256 2732 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
8664281b 2733 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
de032bf4 2734 DE_PIPEA_FIFO_UNDERRUN | DE_POISON;
cc609d5d 2735 u32 gt_irqs;
036a4a7d 2736
1ec14ad3 2737 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2738
2739 /* should always can generate irq */
2740 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3 2741 I915_WRITE(DEIMR, dev_priv->irq_mask);
6005ce42
DV		 2742 I915_WRITE(DEIER, display_mask |
2743 DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT);
3143a2bf 2744 POSTING_READ(DEIER);
036a4a7d 2745
1ec14ad3 2746 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2747
2748 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2749 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2750
cc609d5d
BW		 2751 gt_irqs = GT_RENDER_USER_INTERRUPT;
2752
1ec14ad3 2753 if (IS_GEN6(dev))
cc609d5d 2754 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
1ec14ad3 2755 else
cc609d5d
BW		 2756 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2757 ILK_BSD_USER_INTERRUPT;
2758
2759 I915_WRITE(GTIER, gt_irqs);
3143a2bf 2760 POSTING_READ(GTIER);
036a4a7d 2761
d46da437 2762 ibx_irq_postinstall(dev);
7fe0b973 2763
f97108d1 2764 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 2765 /* Enable PCU event interrupts
2766 *
2767 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 2768 * setup is guaranteed to run in single-threaded context. But we
2769 * need it to make the assert_spin_locked happy. */
2770 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 2771 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 2772 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 2773 }
2774
036a4a7d
ZW		 2775 return 0;
2776}
2777
f71d4af4 2778static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2779{
2780 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2781 /* enable kind of interrupts always enabled */
b615b57a
CW		 2782 u32 display_mask =
2783 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2784 DE_PLANEC_FLIP_DONE_IVB |
2785 DE_PLANEB_FLIP_DONE_IVB |
ce99c256 2786 DE_PLANEA_FLIP_DONE_IVB |
8664281b
PZ		 2787 DE_AUX_CHANNEL_A_IVB |
2788 DE_ERR_INT_IVB;
12638c57 2789 u32 pm_irqs = GEN6_PM_RPS_EVENTS;
cc609d5d 2790 u32 gt_irqs;
b1f14ad0 2791
b1f14ad0
JB		 2792 dev_priv->irq_mask = ~display_mask;
2793
2794 /* should always can generate irq */
8664281b 2795 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
b1f14ad0
JB		 2796 I915_WRITE(DEIIR, I915_READ(DEIIR));
2797 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2798 I915_WRITE(DEIER,
2799 display_mask |
2800 DE_PIPEC_VBLANK_IVB |
2801 DE_PIPEB_VBLANK_IVB |
2802 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2803 POSTING_READ(DEIER);
2804
cc609d5d 2805 dev_priv->gt_irq_mask = ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2806
2807 I915_WRITE(GTIIR, I915_READ(GTIIR));
2808 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2809
cc609d5d
BW		 2810 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2811 GT_BLT_USER_INTERRUPT | GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2812 I915_WRITE(GTIER, gt_irqs);
b1f14ad0
JB		 2813 POSTING_READ(GTIER);
2814
12638c57
BW		 2815 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2816 if (HAS_VEBOX(dev))
2817 pm_irqs |= PM_VEBOX_USER_INTERRUPT |
2818 PM_VEBOX_CS_ERROR_INTERRUPT;
2819
2820 /* Our enable/disable rps functions may touch these registers so
2821 * make sure to set a known state for only the non-RPS bits.
2822 * The RMW is extra paranoia since this should be called after being set
2823 * to a known state in preinstall.
2824 * */
2825 I915_WRITE(GEN6_PMIMR,
2826 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs);
2827 I915_WRITE(GEN6_PMIER,
2828 (I915_READ(GEN6_PMIER) & GEN6_PM_RPS_EVENTS) | pm_irqs);
2829 POSTING_READ(GEN6_PMIER);
eda63ffb 2830
d46da437 2831 ibx_irq_postinstall(dev);
7fe0b973 2832
b1f14ad0
JB		 2833 return 0;
2834}
2835
7e231dbe
JB		 2836static int valleyview_irq_postinstall(struct drm_device *dev)
2837{
2838 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
cc609d5d 2839 u32 gt_irqs;
7e231dbe 2840 u32 enable_mask;
31acc7f5 2841 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
b79480ba 2842 unsigned long irqflags;
7e231dbe
JB		 2843
2844 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2845 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2846 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2847 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2848 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2849
31acc7f5
JB		 2850 /*
2851 *Leave vblank interrupts masked initially. enable/disable will
2852 * toggle them based on usage.
2853 */
2854 dev_priv->irq_mask = (~enable_mask) |
2855 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2856 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2857
20afbda2
DV		 2858 I915_WRITE(PORT_HOTPLUG_EN, 0);
2859 POSTING_READ(PORT_HOTPLUG_EN);
2860
7e231dbe
JB		 2861 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2862 I915_WRITE(VLV_IER, enable_mask);
2863 I915_WRITE(VLV_IIR, 0xffffffff);
2864 I915_WRITE(PIPESTAT(0), 0xffff);
2865 I915_WRITE(PIPESTAT(1), 0xffff);
2866 POSTING_READ(VLV_IER);
2867
b79480ba
DV		 2868 /* Interrupt setup is already guaranteed to be single-threaded, this is
2869 * just to make the assert_spin_locked check happy. */
2870 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2871 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2872 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5 2873 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
b79480ba 2874 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 2875
7e231dbe
JB		 2876 I915_WRITE(VLV_IIR, 0xffffffff);
2877 I915_WRITE(VLV_IIR, 0xffffffff);
2878
7e231dbe 2879 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2880 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5 2881
cc609d5d
BW		 2882 gt_irqs = GT_RENDER_USER_INTERRUPT | GT_BSD_USER_INTERRUPT |
2883 GT_BLT_USER_INTERRUPT;
2884 I915_WRITE(GTIER, gt_irqs);
7e231dbe
JB		 2885 POSTING_READ(GTIER);
2886
2887 /* ack & enable invalid PTE error interrupts */
2888#if 0 /* FIXME: add support to irq handler for checking these bits */
2889 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2890 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2891#endif
2892
2893 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2894
2895 return 0;
2896}
2897
7e231dbe
JB		 2898static void valleyview_irq_uninstall(struct drm_device *dev)
2899{
2900 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2901 int pipe;
2902
2903 if (!dev_priv)
2904 return;
2905
ac4c16c5
EE		 2906 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2907
7e231dbe
JB		 2908 for_each_pipe(pipe)
2909 I915_WRITE(PIPESTAT(pipe), 0xffff);
2910
2911 I915_WRITE(HWSTAM, 0xffffffff);
2912 I915_WRITE(PORT_HOTPLUG_EN, 0);
2913 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2914 for_each_pipe(pipe)
2915 I915_WRITE(PIPESTAT(pipe), 0xffff);
2916 I915_WRITE(VLV_IIR, 0xffffffff);
2917 I915_WRITE(VLV_IMR, 0xffffffff);
2918 I915_WRITE(VLV_IER, 0x0);
2919 POSTING_READ(VLV_IER);
2920}
2921
f71d4af4 2922static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2923{
2924 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2925
2926 if (!dev_priv)
2927 return;
2928
ac4c16c5
EE		 2929 del_timer_sync(&dev_priv->hotplug_reenable_timer);
2930
036a4a7d
ZW		 2931 I915_WRITE(HWSTAM, 0xffffffff);
2932
2933 I915_WRITE(DEIMR, 0xffffffff);
2934 I915_WRITE(DEIER, 0x0);
2935 I915_WRITE(DEIIR, I915_READ(DEIIR));
8664281b
PZ		 2936 if (IS_GEN7(dev))
2937 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
036a4a7d
ZW		 2938
2939 I915_WRITE(GTIMR, 0xffffffff);
2940 I915_WRITE(GTIER, 0x0);
2941 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f 2942
ab5c608b
BW		 2943 if (HAS_PCH_NOP(dev))
2944 return;
2945
192aac1f
KP		 2946 I915_WRITE(SDEIMR, 0xffffffff);
2947 I915_WRITE(SDEIER, 0x0);
2948 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
8664281b
PZ		 2949 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2950 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
036a4a7d
ZW		 2951}
2952
a266c7d5 2953static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2954{
2955 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2956 int pipe;
91e3738e 2957
a266c7d5 2958 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2959
9db4a9c7
JB		 2960 for_each_pipe(pipe)
2961 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2962 I915_WRITE16(IMR, 0xffff);
2963 I915_WRITE16(IER, 0x0);
2964 POSTING_READ16(IER);
c2798b19
CW		 2965}
2966
2967static int i8xx_irq_postinstall(struct drm_device *dev)
2968{
2969 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2970
c2798b19
CW		 2971 I915_WRITE16(EMR,
2972 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2973
2974 /* Unmask the interrupts that we always want on. */
2975 dev_priv->irq_mask =
2976 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2977 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2978 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2979 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2980 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2981 I915_WRITE16(IMR, dev_priv->irq_mask);
2982
2983 I915_WRITE16(IER,
2984 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2985 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2986 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2987 I915_USER_INTERRUPT);
2988 POSTING_READ16(IER);
2989
2990 return 0;
2991}
2992
90a72f87
VS		 2993/*
2994 * Returns true when a page flip has completed.
2995 */
2996static bool i8xx_handle_vblank(struct drm_device *dev,
2997 int pipe, u16 iir)
2998{
2999 drm_i915_private_t *dev_priv = dev->dev_private;
3000 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
3001
3002 if (!drm_handle_vblank(dev, pipe))
3003 return false;
3004
3005 if ((iir & flip_pending) == 0)
3006 return false;
3007
3008 intel_prepare_page_flip(dev, pipe);
3009
3010 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3011 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3012 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3013 * the flip is completed (no longer pending). Since this doesn't raise
3014 * an interrupt per se, we watch for the change at vblank.
3015 */
3016 if (I915_READ16(ISR) & flip_pending)
3017 return false;
3018
3019 intel_finish_page_flip(dev, pipe);
3020
3021 return true;
3022}
3023
ff1f525e 3024static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3025{
3026 struct drm_device *dev = (struct drm_device *) arg;
3027 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 3028 u16 iir, new_iir;
3029 u32 pipe_stats[2];
3030 unsigned long irqflags;
3031 int irq_received;
3032 int pipe;
3033 u16 flip_mask =
3034 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3035 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3036
3037 atomic_inc(&dev_priv->irq_received);
3038
3039 iir = I915_READ16(IIR);
3040 if (iir == 0)
3041 return IRQ_NONE;
3042
3043 while (iir & ~flip_mask) {
3044 /* Can't rely on pipestat interrupt bit in iir as it might
3045 * have been cleared after the pipestat interrupt was received.
3046 * It doesn't set the bit in iir again, but it still produces
3047 * interrupts (for non-MSI).
3048 */
3049 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3050 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3051 i915_handle_error(dev, false);
3052
3053 for_each_pipe(pipe) {
3054 int reg = PIPESTAT(pipe);
3055 pipe_stats[pipe] = I915_READ(reg);
3056
3057 /*
3058 * Clear the PIPE*STAT regs before the IIR
3059 */
3060 if (pipe_stats[pipe] & 0x8000ffff) {
3061 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3062 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3063 pipe_name(pipe));
3064 I915_WRITE(reg, pipe_stats[pipe]);
3065 irq_received = 1;
3066 }
3067 }
3068 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3069
3070 I915_WRITE16(IIR, iir & ~flip_mask);
3071 new_iir = I915_READ16(IIR); /* Flush posted writes */
3072
d05c617e 3073 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3074
3075 if (iir & I915_USER_INTERRUPT)
3076 notify_ring(dev, &dev_priv->ring[RCS]);
3077
3078 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3079 i8xx_handle_vblank(dev, 0, iir))
3080 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 3081
3082 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3083 i8xx_handle_vblank(dev, 1, iir))
3084 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 3085
3086 iir = new_iir;
3087 }
3088
3089 return IRQ_HANDLED;
3090}
3091
3092static void i8xx_irq_uninstall(struct drm_device * dev)
3093{
3094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3095 int pipe;
3096
c2798b19
CW		 3097 for_each_pipe(pipe) {
3098 /* Clear enable bits; then clear status bits */
3099 I915_WRITE(PIPESTAT(pipe), 0);
3100 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3101 }
3102 I915_WRITE16(IMR, 0xffff);
3103 I915_WRITE16(IER, 0x0);
3104 I915_WRITE16(IIR, I915_READ16(IIR));
3105}
3106
a266c7d5
CW		 3107static void i915_irq_preinstall(struct drm_device * dev)
3108{
3109 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3110 int pipe;
3111
3112 atomic_set(&dev_priv->irq_received, 0);
3113
3114 if (I915_HAS_HOTPLUG(dev)) {
3115 I915_WRITE(PORT_HOTPLUG_EN, 0);
3116 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3117 }
3118
00d98ebd 3119 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3120 for_each_pipe(pipe)
3121 I915_WRITE(PIPESTAT(pipe), 0);
3122 I915_WRITE(IMR, 0xffffffff);
3123 I915_WRITE(IER, 0x0);
3124 POSTING_READ(IER);
3125}
3126
3127static int i915_irq_postinstall(struct drm_device *dev)
3128{
3129 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 3130 u32 enable_mask;
a266c7d5 3131
38bde180
CW		 3132 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3133
3134 /* Unmask the interrupts that we always want on. */
3135 dev_priv->irq_mask =
3136 ~(I915_ASLE_INTERRUPT |
3137 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3138 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3139 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3140 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3141 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3142
3143 enable_mask =
3144 I915_ASLE_INTERRUPT |
3145 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3146 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3147 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3148 I915_USER_INTERRUPT;
3149
a266c7d5 3150 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3151 I915_WRITE(PORT_HOTPLUG_EN, 0);
3152 POSTING_READ(PORT_HOTPLUG_EN);
3153
a266c7d5
CW		 3154 /* Enable in IER... */
3155 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3156 /* and unmask in IMR */
3157 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3158 }
3159
a266c7d5
CW		 3160 I915_WRITE(IMR, dev_priv->irq_mask);
3161 I915_WRITE(IER, enable_mask);
3162 POSTING_READ(IER);
3163
f49e38dd 3164 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3165
3166 return 0;
3167}
3168
90a72f87
VS		 3169/*
3170 * Returns true when a page flip has completed.
3171 */
3172static bool i915_handle_vblank(struct drm_device *dev,
3173 int plane, int pipe, u32 iir)
3174{
3175 drm_i915_private_t *dev_priv = dev->dev_private;
3176 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3177
3178 if (!drm_handle_vblank(dev, pipe))
3179 return false;
3180
3181 if ((iir & flip_pending) == 0)
3182 return false;
3183
3184 intel_prepare_page_flip(dev, plane);
3185
3186 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3187 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3188 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3189 * the flip is completed (no longer pending). Since this doesn't raise
3190 * an interrupt per se, we watch for the change at vblank.
3191 */
3192 if (I915_READ(ISR) & flip_pending)
3193 return false;
3194
3195 intel_finish_page_flip(dev, pipe);
3196
3197 return true;
3198}
3199
ff1f525e 3200static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3201{
3202 struct drm_device *dev = (struct drm_device *) arg;
3203 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 3204 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3205 unsigned long irqflags;
38bde180
CW		 3206 u32 flip_mask =
3207 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3208 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3209 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 3210
3211 atomic_inc(&dev_priv->irq_received);
3212
3213 iir = I915_READ(IIR);
38bde180
CW		 3214 do {
3215 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3216 bool blc_event = false;
a266c7d5
CW		 3217
3218 /* Can't rely on pipestat interrupt bit in iir as it might
3219 * have been cleared after the pipestat interrupt was received.
3220 * It doesn't set the bit in iir again, but it still produces
3221 * interrupts (for non-MSI).
3222 */
3223 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3224 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3225 i915_handle_error(dev, false);
3226
3227 for_each_pipe(pipe) {
3228 int reg = PIPESTAT(pipe);
3229 pipe_stats[pipe] = I915_READ(reg);
3230
38bde180 3231 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 3232 if (pipe_stats[pipe] & 0x8000ffff) {
3233 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3234 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3235 pipe_name(pipe));
3236 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3237 irq_received = true;
a266c7d5
CW		 3238 }
3239 }
3240 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3241
3242 if (!irq_received)
3243 break;
3244
a266c7d5
CW		 3245 /* Consume port. Then clear IIR or we'll miss events */
3246 if ((I915_HAS_HOTPLUG(dev)) &&
3247 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
3248 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04 3249 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
a266c7d5
CW		 3250
3251 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3252 hotplug_status);
91d131d2
DV		 3253
3254 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
3255
a266c7d5 3256 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 3257 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 3258 }
3259
38bde180 3260 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3261 new_iir = I915_READ(IIR); /* Flush posted writes */
3262
a266c7d5
CW		 3263 if (iir & I915_USER_INTERRUPT)
3264 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3265
a266c7d5 3266 for_each_pipe(pipe) {
38bde180
CW		 3267 int plane = pipe;
3268 if (IS_MOBILE(dev))
3269 plane = !plane;
90a72f87 3270
8291ee90 3271 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3272 i915_handle_vblank(dev, plane, pipe, iir))
3273 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3274
3275 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3276 blc_event = true;
3277 }
3278
a266c7d5
CW		 3279 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3280 intel_opregion_asle_intr(dev);
3281
3282 /* With MSI, interrupts are only generated when iir
3283 * transitions from zero to nonzero. If another bit got
3284 * set while we were handling the existing iir bits, then
3285 * we would never get another interrupt.
3286 *
3287 * This is fine on non-MSI as well, as if we hit this path
3288 * we avoid exiting the interrupt handler only to generate
3289 * another one.
3290 *
3291 * Note that for MSI this could cause a stray interrupt report
3292 * if an interrupt landed in the time between writing IIR and
3293 * the posting read. This should be rare enough to never
3294 * trigger the 99% of 100,000 interrupts test for disabling
3295 * stray interrupts.
3296 */
38bde180 3297 ret = IRQ_HANDLED;
a266c7d5 3298 iir = new_iir;
38bde180 3299 } while (iir & ~flip_mask);
a266c7d5 3300
d05c617e 3301 i915_update_dri1_breadcrumb(dev);
8291ee90 3302
a266c7d5
CW		 3303 return ret;
3304}
3305
3306static void i915_irq_uninstall(struct drm_device * dev)
3307{
3308 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3309 int pipe;
3310
ac4c16c5
EE		 3311 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3312
a266c7d5
CW		 3313 if (I915_HAS_HOTPLUG(dev)) {
3314 I915_WRITE(PORT_HOTPLUG_EN, 0);
3315 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3316 }
3317
00d98ebd 3318 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3319 for_each_pipe(pipe) {
3320 /* Clear enable bits; then clear status bits */
a266c7d5 3321 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3322 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3323 }
a266c7d5
CW		 3324 I915_WRITE(IMR, 0xffffffff);
3325 I915_WRITE(IER, 0x0);
3326
a266c7d5
CW		 3327 I915_WRITE(IIR, I915_READ(IIR));
3328}
3329
3330static void i965_irq_preinstall(struct drm_device * dev)
3331{
3332 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3333 int pipe;
3334
3335 atomic_set(&dev_priv->irq_received, 0);
3336
adca4730
CW		 3337 I915_WRITE(PORT_HOTPLUG_EN, 0);
3338 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3339
3340 I915_WRITE(HWSTAM, 0xeffe);
3341 for_each_pipe(pipe)
3342 I915_WRITE(PIPESTAT(pipe), 0);
3343 I915_WRITE(IMR, 0xffffffff);
3344 I915_WRITE(IER, 0x0);
3345 POSTING_READ(IER);
3346}
3347
3348static int i965_irq_postinstall(struct drm_device *dev)
3349{
3350 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 3351 u32 enable_mask;
a266c7d5 3352 u32 error_mask;
b79480ba 3353 unsigned long irqflags;
a266c7d5 3354
a266c7d5 3355 /* Unmask the interrupts that we always want on. */
bbba0a97 3356 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3357 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3358 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3359 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3360 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3361 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3362 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3363
3364 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3365 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3366 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3367 enable_mask |= I915_USER_INTERRUPT;
3368
3369 if (IS_G4X(dev))
3370 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3371
b79480ba
DV		 3372 /* Interrupt setup is already guaranteed to be single-threaded, this is
3373 * just to make the assert_spin_locked check happy. */
3374 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
515ac2bb 3375 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
b79480ba 3376 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3377
a266c7d5
CW		 3378 /*
3379 * Enable some error detection, note the instruction error mask
3380 * bit is reserved, so we leave it masked.
3381 */
3382 if (IS_G4X(dev)) {
3383 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3384 GM45_ERROR_MEM_PRIV |
3385 GM45_ERROR_CP_PRIV |
3386 I915_ERROR_MEMORY_REFRESH);
3387 } else {
3388 error_mask = ~(I915_ERROR_PAGE_TABLE |
3389 I915_ERROR_MEMORY_REFRESH);
3390 }
3391 I915_WRITE(EMR, error_mask);
3392
3393 I915_WRITE(IMR, dev_priv->irq_mask);
3394 I915_WRITE(IER, enable_mask);
3395 POSTING_READ(IER);
3396
20afbda2
DV		 3397 I915_WRITE(PORT_HOTPLUG_EN, 0);
3398 POSTING_READ(PORT_HOTPLUG_EN);
3399
f49e38dd 3400 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3401
3402 return 0;
3403}
3404
bac56d5b 3405static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2
DV		 3406{
3407 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31 3408 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3409 struct intel_encoder *intel_encoder;
20afbda2
DV		 3410 u32 hotplug_en;
3411
b5ea2d56
DV		 3412 assert_spin_locked(&dev_priv->irq_lock);
3413
bac56d5b
EE		 3414 if (I915_HAS_HOTPLUG(dev)) {
3415 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3416 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3417 /* Note HDMI and DP share hotplug bits */
e5868a31 3418 /* enable bits are the same for all generations */
cd569aed
EE		 3419 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3420 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3421 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3422 /* Programming the CRT detection parameters tends
3423 to generate a spurious hotplug event about three
3424 seconds later. So just do it once.
3425 */
3426 if (IS_G4X(dev))
3427 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3428 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3429 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3430
bac56d5b
EE		 3431 /* Ignore TV since it's buggy */
3432 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3433 }
a266c7d5
CW		 3434}
3435
ff1f525e 3436static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3437{
3438 struct drm_device *dev = (struct drm_device *) arg;
3439 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 3440 u32 iir, new_iir;
3441 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 3442 unsigned long irqflags;
3443 int irq_received;
3444 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3445 u32 flip_mask =
3446 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3447 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 3448
3449 atomic_inc(&dev_priv->irq_received);
3450
3451 iir = I915_READ(IIR);
3452
a266c7d5 3453 for (;;) {
2c8ba29f
CW		 3454 bool blc_event = false;
3455
21ad8330 3456 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 3457
3458 /* Can't rely on pipestat interrupt bit in iir as it might
3459 * have been cleared after the pipestat interrupt was received.
3460 * It doesn't set the bit in iir again, but it still produces
3461 * interrupts (for non-MSI).
3462 */
3463 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3464 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3465 i915_handle_error(dev, false);
3466
3467 for_each_pipe(pipe) {
3468 int reg = PIPESTAT(pipe);
3469 pipe_stats[pipe] = I915_READ(reg);
3470
3471 /*
3472 * Clear the PIPE*STAT regs before the IIR
3473 */
3474 if (pipe_stats[pipe] & 0x8000ffff) {
3475 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3476 DRM_DEBUG_DRIVER("pipe %c underrun\n",
3477 pipe_name(pipe));
3478 I915_WRITE(reg, pipe_stats[pipe]);
3479 irq_received = 1;
3480 }
3481 }
3482 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3483
3484 if (!irq_received)
3485 break;
3486
3487 ret = IRQ_HANDLED;
3488
3489 /* Consume port. Then clear IIR or we'll miss events */
adca4730 3490 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5 3491 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
b543fb04
EE		 3492 u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3493 HOTPLUG_INT_STATUS_G4X :
4f7fd709 3494 HOTPLUG_INT_STATUS_I915);
a266c7d5
CW		 3495
3496 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3497 hotplug_status);
91d131d2
DV		 3498
3499 intel_hpd_irq_handler(dev, hotplug_trigger,
3500 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3501
a266c7d5
CW		 3502 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3503 I915_READ(PORT_HOTPLUG_STAT);
3504 }
3505
21ad8330 3506 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3507 new_iir = I915_READ(IIR); /* Flush posted writes */
3508
a266c7d5
CW		 3509 if (iir & I915_USER_INTERRUPT)
3510 notify_ring(dev, &dev_priv->ring[RCS]);
3511 if (iir & I915_BSD_USER_INTERRUPT)
3512 notify_ring(dev, &dev_priv->ring[VCS]);
3513
a266c7d5 3514 for_each_pipe(pipe) {
2c8ba29f 3515 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3516 i915_handle_vblank(dev, pipe, pipe, iir))
3517 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3518
3519 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3520 blc_event = true;
3521 }
3522
3523
3524 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3525 intel_opregion_asle_intr(dev);
3526
515ac2bb
DV		 3527 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3528 gmbus_irq_handler(dev);
3529
a266c7d5
CW		 3530 /* With MSI, interrupts are only generated when iir
3531 * transitions from zero to nonzero. If another bit got
3532 * set while we were handling the existing iir bits, then
3533 * we would never get another interrupt.
3534 *
3535 * This is fine on non-MSI as well, as if we hit this path
3536 * we avoid exiting the interrupt handler only to generate
3537 * another one.
3538 *
3539 * Note that for MSI this could cause a stray interrupt report
3540 * if an interrupt landed in the time between writing IIR and
3541 * the posting read. This should be rare enough to never
3542 * trigger the 99% of 100,000 interrupts test for disabling
3543 * stray interrupts.
3544 */
3545 iir = new_iir;
3546 }
3547
d05c617e 3548 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3549
a266c7d5
CW		 3550 return ret;
3551}
3552
3553static void i965_irq_uninstall(struct drm_device * dev)
3554{
3555 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3556 int pipe;
3557
3558 if (!dev_priv)
3559 return;
3560
ac4c16c5
EE		 3561 del_timer_sync(&dev_priv->hotplug_reenable_timer);
3562
adca4730
CW		 3563 I915_WRITE(PORT_HOTPLUG_EN, 0);
3564 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3565
3566 I915_WRITE(HWSTAM, 0xffffffff);
3567 for_each_pipe(pipe)
3568 I915_WRITE(PIPESTAT(pipe), 0);
3569 I915_WRITE(IMR, 0xffffffff);
3570 I915_WRITE(IER, 0x0);
3571
3572 for_each_pipe(pipe)
3573 I915_WRITE(PIPESTAT(pipe),
3574 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3575 I915_WRITE(IIR, I915_READ(IIR));
3576}
3577
ac4c16c5
EE		 3578static void i915_reenable_hotplug_timer_func(unsigned long data)
3579{
3580 drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3581 struct drm_device *dev = dev_priv->dev;
3582 struct drm_mode_config *mode_config = &dev->mode_config;
3583 unsigned long irqflags;
3584 int i;
3585
3586 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3587 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3588 struct drm_connector *connector;
3589
3590 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3591 continue;
3592
3593 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3594
3595 list_for_each_entry(connector, &mode_config->connector_list, head) {
3596 struct intel_connector *intel_connector = to_intel_connector(connector);
3597
3598 if (intel_connector->encoder->hpd_pin == i) {
3599 if (connector->polled != intel_connector->polled)
3600 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3601 drm_get_connector_name(connector));
3602 connector->polled = intel_connector->polled;
3603 if (!connector->polled)
3604 connector->polled = DRM_CONNECTOR_POLL_HPD;
3605 }
3606 }
3607 }
3608 if (dev_priv->display.hpd_irq_setup)
3609 dev_priv->display.hpd_irq_setup(dev);
3610 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3611}
3612
f71d4af4
JB		 3613void intel_irq_init(struct drm_device *dev)
3614{
8b2e326d
CW		 3615 struct drm_i915_private *dev_priv = dev->dev_private;
3616
3617 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 3618 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 3619 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 3620 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 3621
99584db3
DV		 3622 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3623 i915_hangcheck_elapsed,
61bac78e 3624 (unsigned long) dev);
ac4c16c5
EE		 3625 setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3626 (unsigned long) dev_priv);
61bac78e 3627
97a19a24 3628 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 3629
f71d4af4
JB		 3630 dev->driver->get_vblank_counter = i915_get_vblank_counter;
3631 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 3632 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 3633 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3634 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3635 }
3636
c3613de9
KP		 3637 if (drm_core_check_feature(dev, DRIVER_MODESET))
3638 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3639 else
3640 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 3641 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3642
7e231dbe
JB		 3643 if (IS_VALLEYVIEW(dev)) {
3644 dev->driver->irq_handler = valleyview_irq_handler;
3645 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3646 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3647 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3648 dev->driver->enable_vblank = valleyview_enable_vblank;
3649 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 3650 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 3651 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
7d99163d 3652 /* Share uninstall handlers with ILK/SNB */
f71d4af4 3653 dev->driver->irq_handler = ivybridge_irq_handler;
7d99163d 3654 dev->driver->irq_preinstall = ivybridge_irq_preinstall;
f71d4af4
JB		 3655 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3656 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3657 dev->driver->enable_vblank = ivybridge_enable_vblank;
3658 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 3659 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 3660 } else if (HAS_PCH_SPLIT(dev)) {
3661 dev->driver->irq_handler = ironlake_irq_handler;
3662 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3663 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3664 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3665 dev->driver->enable_vblank = ironlake_enable_vblank;
3666 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 3667 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 3668 } else {
c2798b19
CW		 3669 if (INTEL_INFO(dev)->gen == 2) {
3670 dev->driver->irq_preinstall = i8xx_irq_preinstall;
3671 dev->driver->irq_postinstall = i8xx_irq_postinstall;
3672 dev->driver->irq_handler = i8xx_irq_handler;
3673 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3674 } else if (INTEL_INFO(dev)->gen == 3) {
3675 dev->driver->irq_preinstall = i915_irq_preinstall;
3676 dev->driver->irq_postinstall = i915_irq_postinstall;
3677 dev->driver->irq_uninstall = i915_irq_uninstall;
3678 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3679 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3680 } else {
a266c7d5
CW		 3681 dev->driver->irq_preinstall = i965_irq_preinstall;
3682 dev->driver->irq_postinstall = i965_irq_postinstall;
3683 dev->driver->irq_uninstall = i965_irq_uninstall;
3684 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 3685 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3686 }
f71d4af4
JB		 3687 dev->driver->enable_vblank = i915_enable_vblank;
3688 dev->driver->disable_vblank = i915_disable_vblank;
3689 }
3690}
20afbda2
DV		 3691
3692void intel_hpd_init(struct drm_device *dev)
3693{
3694 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 3695 struct drm_mode_config *mode_config = &dev->mode_config;
3696 struct drm_connector *connector;
b5ea2d56 3697 unsigned long irqflags;
821450c6 3698 int i;
20afbda2 3699
821450c6
EE		 3700 for (i = 1; i < HPD_NUM_PINS; i++) {
3701 dev_priv->hpd_stats[i].hpd_cnt = 0;
3702 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3703 }
3704 list_for_each_entry(connector, &mode_config->connector_list, head) {
3705 struct intel_connector *intel_connector = to_intel_connector(connector);
3706 connector->polled = intel_connector->polled;
3707 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3708 connector->polled = DRM_CONNECTOR_POLL_HPD;
3709 }
b5ea2d56
DV		 3710
3711 /* Interrupt setup is already guaranteed to be single-threaded, this is
3712 * just to make the assert_spin_locked checks happy. */
3713 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 3714 if (dev_priv->display.hpd_irq_setup)
3715 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 3716 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 3717}
Linux kernel - Deliverables
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