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drm/i915: Update VBT fields for child devices
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
fca52a55
DV		 40/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
e4ce95aa
VS		 48static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
50};
51
23bb4cb5
VS		 52static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
54};
55
3a3b3c7d
VS		 56static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
58};
59
7c7e10db 60static const u32 hpd_ibx[HPD_NUM_PINS] = {
e5868a31
EE		 61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
66};
67
7c7e10db 68static const u32 hpd_cpt[HPD_NUM_PINS] = {
e5868a31 69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
74};
75
26951caf 76static const u32 hpd_spt[HPD_NUM_PINS] = {
74c0b395 77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
26951caf
XZ		 78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
82};
83
7c7e10db 84static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
e5868a31
EE		 85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
91};
92
7c7e10db 93static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
e5868a31
EE		 94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
100};
101
4bca26d0 102static const u32 hpd_status_i915[HPD_NUM_PINS] = {
e5868a31
EE		 103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
109};
110
e0a20ad7
SS		 111/* BXT hpd list */
112static const u32 hpd_bxt[HPD_NUM_PINS] = {
7f3561be 113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
e0a20ad7
SS		 114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
116};
117
5c502442 118/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 119#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
127} while (0)
128
f86f3fb0 129#define GEN5_IRQ_RESET(type) do { \
a9d356a6 130 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 131 POSTING_READ(type##IMR); \
a9d356a6 132 I915_WRITE(type##IER, 0); \
5c502442
PZ		 133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
a9d356a6
PZ		 137} while (0)
138
337ba017
PZ		 139/*
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
141 */
f0f59a00
VS		 142static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
143 i915_reg_t reg)
b51a2842
VS		 144{
145 u32 val = I915_READ(reg);
146
147 if (val == 0)
148 return;
149
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
f0f59a00 151 i915_mmio_reg_offset(reg), val);
b51a2842
VS		 152 I915_WRITE(reg, 0xffffffff);
153 POSTING_READ(reg);
154 I915_WRITE(reg, 0xffffffff);
155 POSTING_READ(reg);
156}
337ba017 157
35079899 158#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
b51a2842 159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
35079899 160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
7d1bd539
VS		 161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
35079899
PZ		 163} while (0)
164
165#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
b51a2842 166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
35079899 167 I915_WRITE(type##IER, (ier_val)); \
7d1bd539
VS		 168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
35079899
PZ		 170} while (0)
171
c9a9a268
ID		 172static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
173
0706f17c
EE		 174/* For display hotplug interrupt */
175static inline void
176i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
177 uint32_t mask,
178 uint32_t bits)
179{
180 uint32_t val;
181
182 assert_spin_locked(&dev_priv->irq_lock);
183 WARN_ON(bits & ~mask);
184
185 val = I915_READ(PORT_HOTPLUG_EN);
186 val &= ~mask;
187 val |= bits;
188 I915_WRITE(PORT_HOTPLUG_EN, val);
189}
190
191/**
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
202 */
203void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
204 uint32_t mask,
205 uint32_t bits)
206{
207 spin_lock_irq(&dev_priv->irq_lock);
208 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209 spin_unlock_irq(&dev_priv->irq_lock);
210}
211
d9dc34f1
VS		 212/**
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
217 */
fbdedaea
VS		 218void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
036a4a7d 221{
d9dc34f1
VS		 222 uint32_t new_val;
223
4bc9d430
DV		 224 assert_spin_locked(&dev_priv->irq_lock);
225
d9dc34f1
VS		 226 WARN_ON(enabled_irq_mask & ~interrupt_mask);
227
9df7575f 228 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 229 return;
c67a470b 230
d9dc34f1
VS		 231 new_val = dev_priv->irq_mask;
232 new_val &= ~interrupt_mask;
233 new_val |= (~enabled_irq_mask & interrupt_mask);
234
235 if (new_val != dev_priv->irq_mask) {
236 dev_priv->irq_mask = new_val;
1ec14ad3 237 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 238 POSTING_READ(DEIMR);
036a4a7d
ZW		 239 }
240}
241
43eaea13
PZ		 242/**
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
247 */
248static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249 uint32_t interrupt_mask,
250 uint32_t enabled_irq_mask)
251{
252 assert_spin_locked(&dev_priv->irq_lock);
253
15a17aae
DV		 254 WARN_ON(enabled_irq_mask & ~interrupt_mask);
255
9df7575f 256 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 257 return;
c67a470b 258
43eaea13
PZ		 259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
262 POSTING_READ(GTIMR);
263}
264
480c8033 265void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 266{
267 ilk_update_gt_irq(dev_priv, mask, mask);
268}
269
480c8033 270void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
43eaea13
PZ		 271{
272 ilk_update_gt_irq(dev_priv, mask, 0);
273}
274
f0f59a00 275static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
b900b949
ID		 276{
277 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
278}
279
f0f59a00 280static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
a72fbc3a
ID		 281{
282 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
283}
284
f0f59a00 285static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
b900b949
ID		 286{
287 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
288}
289
edbfdb45 290/**
81fd874e
VS		 291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
295 */
edbfdb45
PZ		 296static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297 uint32_t interrupt_mask,
298 uint32_t enabled_irq_mask)
299{
605cd25b 300 uint32_t new_val;
edbfdb45 301
15a17aae
DV		 302 WARN_ON(enabled_irq_mask & ~interrupt_mask);
303
edbfdb45
PZ		 304 assert_spin_locked(&dev_priv->irq_lock);
305
605cd25b 306 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 307 new_val &= ~interrupt_mask;
308 new_val |= (~enabled_irq_mask & interrupt_mask);
309
605cd25b
PZ		 310 if (new_val != dev_priv->pm_irq_mask) {
311 dev_priv->pm_irq_mask = new_val;
a72fbc3a
ID		 312 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313 POSTING_READ(gen6_pm_imr(dev_priv));
f52ecbcf 314 }
edbfdb45
PZ		 315}
316
480c8033 317void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
edbfdb45 318{
9939fba2
ID		 319 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
320 return;
321
edbfdb45
PZ		 322 snb_update_pm_irq(dev_priv, mask, mask);
323}
324
9939fba2
ID		 325static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
326 uint32_t mask)
edbfdb45
PZ		 327{
328 snb_update_pm_irq(dev_priv, mask, 0);
329}
330
9939fba2
ID		 331void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
332{
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
334 return;
335
336 __gen6_disable_pm_irq(dev_priv, mask);
337}
338
3cc134e3
ID		 339void gen6_reset_rps_interrupts(struct drm_device *dev)
340{
341 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 342 i915_reg_t reg = gen6_pm_iir(dev_priv);
3cc134e3
ID		 343
344 spin_lock_irq(&dev_priv->irq_lock);
345 I915_WRITE(reg, dev_priv->pm_rps_events);
346 I915_WRITE(reg, dev_priv->pm_rps_events);
347 POSTING_READ(reg);
096fad9e 348 dev_priv->rps.pm_iir = 0;
3cc134e3
ID		 349 spin_unlock_irq(&dev_priv->irq_lock);
350}
351
b900b949
ID		 352void gen6_enable_rps_interrupts(struct drm_device *dev)
353{
354 struct drm_i915_private *dev_priv = dev->dev_private;
355
356 spin_lock_irq(&dev_priv->irq_lock);
78e68d36 357
b900b949 358 WARN_ON(dev_priv->rps.pm_iir);
3cc134e3 359 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
d4d70aa5 360 dev_priv->rps.interrupts_enabled = true;
78e68d36
ID		 361 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
362 dev_priv->pm_rps_events);
b900b949 363 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
78e68d36 364
b900b949
ID		 365 spin_unlock_irq(&dev_priv->irq_lock);
366}
367
59d02a1f
ID		 368u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
369{
370 /*
f24eeb19 371 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
59d02a1f 372 * if GEN6_PM_UP_EI_EXPIRED is masked.
f24eeb19
ID		 373 *
374 * TODO: verify if this can be reproduced on VLV,CHV.
59d02a1f
ID		 375 */
376 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
377 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
378
379 if (INTEL_INFO(dev_priv)->gen >= 8)
380 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
381
382 return mask;
383}
384
b900b949
ID		 385void gen6_disable_rps_interrupts(struct drm_device *dev)
386{
387 struct drm_i915_private *dev_priv = dev->dev_private;
388
d4d70aa5
ID		 389 spin_lock_irq(&dev_priv->irq_lock);
390 dev_priv->rps.interrupts_enabled = false;
391 spin_unlock_irq(&dev_priv->irq_lock);
392
393 cancel_work_sync(&dev_priv->rps.work);
394
9939fba2
ID		 395 spin_lock_irq(&dev_priv->irq_lock);
396
59d02a1f 397 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
9939fba2
ID		 398
399 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
b900b949
ID		 400 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
401 ~dev_priv->pm_rps_events);
58072ccb
ID		 402
403 spin_unlock_irq(&dev_priv->irq_lock);
404
405 synchronize_irq(dev->irq);
b900b949
ID		 406}
407
3a3b3c7d 408/**
81fd874e
VS		 409 * bdw_update_port_irq - update DE port interrupt
410 * @dev_priv: driver private
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
413 */
3a3b3c7d
VS		 414static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
415 uint32_t interrupt_mask,
416 uint32_t enabled_irq_mask)
417{
418 uint32_t new_val;
419 uint32_t old_val;
420
421 assert_spin_locked(&dev_priv->irq_lock);
422
423 WARN_ON(enabled_irq_mask & ~interrupt_mask);
424
425 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
426 return;
427
428 old_val = I915_READ(GEN8_DE_PORT_IMR);
429
430 new_val = old_val;
431 new_val &= ~interrupt_mask;
432 new_val |= (~enabled_irq_mask & interrupt_mask);
433
434 if (new_val != old_val) {
435 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
436 POSTING_READ(GEN8_DE_PORT_IMR);
437 }
438}
439
013d3752
VS		 440/**
441 * bdw_update_pipe_irq - update DE pipe interrupt
442 * @dev_priv: driver private
443 * @pipe: pipe whose interrupt to update
444 * @interrupt_mask: mask of interrupt bits to update
445 * @enabled_irq_mask: mask of interrupt bits to enable
446 */
447void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
448 enum pipe pipe,
449 uint32_t interrupt_mask,
450 uint32_t enabled_irq_mask)
451{
452 uint32_t new_val;
453
454 assert_spin_locked(&dev_priv->irq_lock);
455
456 WARN_ON(enabled_irq_mask & ~interrupt_mask);
457
458 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
459 return;
460
461 new_val = dev_priv->de_irq_mask[pipe];
462 new_val &= ~interrupt_mask;
463 new_val |= (~enabled_irq_mask & interrupt_mask);
464
465 if (new_val != dev_priv->de_irq_mask[pipe]) {
466 dev_priv->de_irq_mask[pipe] = new_val;
467 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
468 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
469 }
470}
471
fee884ed
DV		 472/**
473 * ibx_display_interrupt_update - update SDEIMR
474 * @dev_priv: driver private
475 * @interrupt_mask: mask of interrupt bits to update
476 * @enabled_irq_mask: mask of interrupt bits to enable
477 */
47339cd9
DV		 478void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
479 uint32_t interrupt_mask,
480 uint32_t enabled_irq_mask)
fee884ed
DV		 481{
482 uint32_t sdeimr = I915_READ(SDEIMR);
483 sdeimr &= ~interrupt_mask;
484 sdeimr |= (~enabled_irq_mask & interrupt_mask);
485
15a17aae
DV		 486 WARN_ON(enabled_irq_mask & ~interrupt_mask);
487
fee884ed
DV		 488 assert_spin_locked(&dev_priv->irq_lock);
489
9df7575f 490 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
c67a470b 491 return;
c67a470b 492
fee884ed
DV		 493 I915_WRITE(SDEIMR, sdeimr);
494 POSTING_READ(SDEIMR);
495}
8664281b 496
b5ea642a 497static void
755e9019
ID		 498__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
499 u32 enable_mask, u32 status_mask)
7c463586 500{
f0f59a00 501 i915_reg_t reg = PIPESTAT(pipe);
755e9019 502 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 503
b79480ba 504 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 505 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 506
04feced9
VS		 507 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
508 status_mask & ~PIPESTAT_INT_STATUS_MASK,
509 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
510 pipe_name(pipe), enable_mask, status_mask))
755e9019
ID		 511 return;
512
513 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 514 return;
515
91d181dd
ID		 516 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
517
46c06a30 518 /* Enable the interrupt, clear any pending status */
755e9019 519 pipestat |= enable_mask | status_mask;
46c06a30
VS		 520 I915_WRITE(reg, pipestat);
521 POSTING_READ(reg);
7c463586
KP		 522}
523
b5ea642a 524static void
755e9019
ID		 525__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
526 u32 enable_mask, u32 status_mask)
7c463586 527{
f0f59a00 528 i915_reg_t reg = PIPESTAT(pipe);
755e9019 529 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 530
b79480ba 531 assert_spin_locked(&dev_priv->irq_lock);
d518ce50 532 WARN_ON(!intel_irqs_enabled(dev_priv));
b79480ba 533
04feced9
VS		 534 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
535 status_mask & ~PIPESTAT_INT_STATUS_MASK,
536 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
537 pipe_name(pipe), enable_mask, status_mask))
46c06a30
VS		 538 return;
539
755e9019
ID		 540 if ((pipestat & enable_mask) == 0)
541 return;
542
91d181dd
ID		 543 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
544
755e9019 545 pipestat &= ~enable_mask;
46c06a30
VS		 546 I915_WRITE(reg, pipestat);
547 POSTING_READ(reg);
7c463586
KP		 548}
549
10c59c51
ID		 550static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
551{
552 u32 enable_mask = status_mask << 16;
553
554 /*
724a6905
VS		 555 * On pipe A we don't support the PSR interrupt yet,
556 * on pipe B and C the same bit MBZ.
10c59c51
ID		 557 */
558 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
559 return 0;
724a6905
VS		 560 /*
561 * On pipe B and C we don't support the PSR interrupt yet, on pipe
562 * A the same bit is for perf counters which we don't use either.
563 */
564 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
565 return 0;
10c59c51
ID		 566
567 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
568 SPRITE0_FLIP_DONE_INT_EN_VLV |
569 SPRITE1_FLIP_DONE_INT_EN_VLV);
570 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
571 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
572 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
573 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
574
575 return enable_mask;
576}
577
755e9019
ID		 578void
579i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
580 u32 status_mask)
581{
582 u32 enable_mask;
583
666a4537 584 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10c59c51
ID		 585 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
586 status_mask);
587 else
588 enable_mask = status_mask << 16;
755e9019
ID		 589 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
590}
591
592void
593i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
594 u32 status_mask)
595{
596 u32 enable_mask;
597
666a4537 598 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
10c59c51
ID		 599 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
600 status_mask);
601 else
602 enable_mask = status_mask << 16;
755e9019
ID		 603 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
604}
605
01c66889 606/**
f49e38dd 607 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
468f9d29 608 * @dev: drm device
01c66889 609 */
f49e38dd 610static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 611{
2d1013dd 612 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3 613
f49e38dd
JN		 614 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
615 return;
616
13321786 617 spin_lock_irq(&dev_priv->irq_lock);
01c66889 618
755e9019 619 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 620 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 621 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 622 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3 623
13321786 624 spin_unlock_irq(&dev_priv->irq_lock);
01c66889
ZY		 625}
626
f75f3746
VS		 627/*
628 * This timing diagram depicts the video signal in and
629 * around the vertical blanking period.
630 *
631 * Assumptions about the fictitious mode used in this example:
632 * vblank_start >= 3
633 * vsync_start = vblank_start + 1
634 * vsync_end = vblank_start + 2
635 * vtotal = vblank_start + 3
636 *
637 * start of vblank:
638 * latch double buffered registers
639 * increment frame counter (ctg+)
640 * generate start of vblank interrupt (gen4+)
641 * |
642 * | frame start:
643 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
644 * | may be shifted forward 1-3 extra lines via PIPECONF
645 * | |
646 * | | start of vsync:
647 * | | generate vsync interrupt
648 * | | |
649 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
650 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
651 * ----va---> <-----------------vb--------------------> <--------va-------------
652 * | | <----vs-----> |
653 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
654 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
655 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
656 * | | |
657 * last visible pixel first visible pixel
658 * | increment frame counter (gen3/4)
659 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
660 *
661 * x = horizontal active
662 * _ = horizontal blanking
663 * hs = horizontal sync
664 * va = vertical active
665 * vb = vertical blanking
666 * vs = vertical sync
667 * vbs = vblank_start (number)
668 *
669 * Summary:
670 * - most events happen at the start of horizontal sync
671 * - frame start happens at the start of horizontal blank, 1-4 lines
672 * (depending on PIPECONF settings) after the start of vblank
673 * - gen3/4 pixel and frame counter are synchronized with the start
674 * of horizontal active on the first line of vertical active
675 */
676
88e72717 677static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
4cdb83ec
VS		 678{
679 /* Gen2 doesn't have a hardware frame counter */
680 return 0;
681}
682
42f52ef8
KP		 683/* Called from drm generic code, passed a 'crtc', which
684 * we use as a pipe index
685 */
88e72717 686static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
0a3e67a4 687{
2d1013dd 688 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 689 i915_reg_t high_frame, low_frame;
0b2a8e09 690 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
f3a5c3f6
DV		 691 struct intel_crtc *intel_crtc =
692 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
fc467a22 693 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
0a3e67a4 694
f3a5c3f6
DV		 695 htotal = mode->crtc_htotal;
696 hsync_start = mode->crtc_hsync_start;
697 vbl_start = mode->crtc_vblank_start;
698 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
699 vbl_start = DIV_ROUND_UP(vbl_start, 2);
391f75e2 700
0b2a8e09
VS		 701 /* Convert to pixel count */
702 vbl_start *= htotal;
703
704 /* Start of vblank event occurs at start of hsync */
705 vbl_start -= htotal - hsync_start;
706
9db4a9c7
JB		 707 high_frame = PIPEFRAME(pipe);
708 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 709
0a3e67a4
JB		 710 /*
711 * High & low register fields aren't synchronized, so make sure
712 * we get a low value that's stable across two reads of the high
713 * register.
714 */
715 do {
5eddb70b 716 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 717 low = I915_READ(low_frame);
5eddb70b 718 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 719 } while (high1 != high2);
720
5eddb70b 721 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 722 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 723 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 724
725 /*
726 * The frame counter increments at beginning of active.
727 * Cook up a vblank counter by also checking the pixel
728 * counter against vblank start.
729 */
edc08d0a 730 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 731}
732
974e59ba 733static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
9880b7a5 734{
2d1013dd 735 struct drm_i915_private *dev_priv = dev->dev_private;
9880b7a5 736
649636ef 737 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
9880b7a5
JB		 738}
739
75aa3f63 740/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
a225f079
VS		 741static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
742{
743 struct drm_device *dev = crtc->base.dev;
744 struct drm_i915_private *dev_priv = dev->dev_private;
fc467a22 745 const struct drm_display_mode *mode = &crtc->base.hwmode;
a225f079 746 enum pipe pipe = crtc->pipe;
80715b2f 747 int position, vtotal;
a225f079 748
80715b2f 749 vtotal = mode->crtc_vtotal;
a225f079
VS		 750 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
751 vtotal /= 2;
752
753 if (IS_GEN2(dev))
75aa3f63 754 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
a225f079 755 else
75aa3f63 756 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
a225f079 757
41b578fb
JB		 758 /*
759 * On HSW, the DSL reg (0x70000) appears to return 0 if we
760 * read it just before the start of vblank. So try it again
761 * so we don't accidentally end up spanning a vblank frame
762 * increment, causing the pipe_update_end() code to squak at us.
763 *
764 * The nature of this problem means we can't simply check the ISR
765 * bit and return the vblank start value; nor can we use the scanline
766 * debug register in the transcoder as it appears to have the same
767 * problem. We may need to extend this to include other platforms,
768 * but so far testing only shows the problem on HSW.
769 */
b2916819 770 if (HAS_DDI(dev) && !position) {
41b578fb
JB		 771 int i, temp;
772
773 for (i = 0; i < 100; i++) {
774 udelay(1);
775 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
776 DSL_LINEMASK_GEN3;
777 if (temp != position) {
778 position = temp;
779 break;
780 }
781 }
782 }
783
a225f079 784 /*
80715b2f
VS		 785 * See update_scanline_offset() for the details on the
786 * scanline_offset adjustment.
a225f079 787 */
80715b2f 788 return (position + crtc->scanline_offset) % vtotal;
a225f079
VS		 789}
790
88e72717 791static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
abca9e45 792 unsigned int flags, int *vpos, int *hpos,
3bb403bf
VS		 793 ktime_t *stime, ktime_t *etime,
794 const struct drm_display_mode *mode)
0af7e4df 795{
c2baf4b7
VS		 796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3aa18df8 799 int position;
78e8fc6b 800 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
0af7e4df
MK		 801 bool in_vbl = true;
802 int ret = 0;
ad3543ed 803 unsigned long irqflags;
0af7e4df 804
fc467a22 805 if (WARN_ON(!mode->crtc_clock)) {
0af7e4df 806 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 807 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 808 return 0;
809 }
810
c2baf4b7 811 htotal = mode->crtc_htotal;
78e8fc6b 812 hsync_start = mode->crtc_hsync_start;
c2baf4b7
VS		 813 vtotal = mode->crtc_vtotal;
814 vbl_start = mode->crtc_vblank_start;
815 vbl_end = mode->crtc_vblank_end;
0af7e4df 816
d31faf65
VS		 817 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
818 vbl_start = DIV_ROUND_UP(vbl_start, 2);
819 vbl_end /= 2;
820 vtotal /= 2;
821 }
822
c2baf4b7
VS		 823 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
824
ad3543ed
MK		 825 /*
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
829 */
830 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
78e8fc6b 831
ad3543ed
MK		 832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
833
834 /* Get optional system timestamp before query. */
835 if (stime)
836 *stime = ktime_get();
837
7c06b08a 838 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
841 */
a225f079 842 position = __intel_get_crtc_scanline(intel_crtc);
0af7e4df
MK		 843 } else {
844 /* Have access to pixelcount since start of frame.
845 * We can split this into vertical and horizontal
846 * scanout position.
847 */
75aa3f63 848 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 849
3aa18df8
VS		 850 /* convert to pixel counts */
851 vbl_start *= htotal;
852 vbl_end *= htotal;
853 vtotal *= htotal;
78e8fc6b 854
7e78f1cb
VS		 855 /*
856 * In interlaced modes, the pixel counter counts all pixels,
857 * so one field will have htotal more pixels. In order to avoid
858 * the reported position from jumping backwards when the pixel
859 * counter is beyond the length of the shorter field, just
860 * clamp the position the length of the shorter field. This
861 * matches how the scanline counter based position works since
862 * the scanline counter doesn't count the two half lines.
863 */
864 if (position >= vtotal)
865 position = vtotal - 1;
866
78e8fc6b
VS		 867 /*
868 * Start of vblank interrupt is triggered at start of hsync,
869 * just prior to the first active line of vblank. However we
870 * consider lines to start at the leading edge of horizontal
871 * active. So, should we get here before we've crossed into
872 * the horizontal active of the first line in vblank, we would
873 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
874 * always add htotal-hsync_start to the current pixel position.
875 */
876 position = (position + htotal - hsync_start) % vtotal;
0af7e4df
MK		 877 }
878
ad3543ed
MK		 879 /* Get optional system timestamp after query. */
880 if (etime)
881 *etime = ktime_get();
882
883 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
884
885 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
886
3aa18df8
VS		 887 in_vbl = position >= vbl_start && position < vbl_end;
888
889 /*
890 * While in vblank, position will be negative
891 * counting up towards 0 at vbl_end. And outside
892 * vblank, position will be positive counting
893 * up since vbl_end.
894 */
895 if (position >= vbl_start)
896 position -= vbl_end;
897 else
898 position += vtotal - vbl_end;
0af7e4df 899
7c06b08a 900 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 901 *vpos = position;
902 *hpos = 0;
903 } else {
904 *vpos = position / htotal;
905 *hpos = position - (*vpos * htotal);
906 }
0af7e4df 907
0af7e4df
MK		 908 /* In vblank? */
909 if (in_vbl)
3d3cbd84 910 ret |= DRM_SCANOUTPOS_IN_VBLANK;
0af7e4df
MK		 911
912 return ret;
913}
914
a225f079
VS		 915int intel_get_crtc_scanline(struct intel_crtc *crtc)
916{
917 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
918 unsigned long irqflags;
919 int position;
920
921 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
922 position = __intel_get_crtc_scanline(crtc);
923 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924
925 return position;
926}
927
88e72717 928static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
0af7e4df
MK		 929 int *max_error,
930 struct timeval *vblank_time,
931 unsigned flags)
932{
4041b853 933 struct drm_crtc *crtc;
0af7e4df 934
88e72717
TR		 935 if (pipe >= INTEL_INFO(dev)->num_pipes) {
936 DRM_ERROR("Invalid crtc %u\n", pipe);
0af7e4df
MK		 937 return -EINVAL;
938 }
939
940 /* Get drm_crtc to timestamp: */
4041b853
CW		 941 crtc = intel_get_crtc_for_pipe(dev, pipe);
942 if (crtc == NULL) {
88e72717 943 DRM_ERROR("Invalid crtc %u\n", pipe);
4041b853
CW		 944 return -EINVAL;
945 }
946
fc467a22 947 if (!crtc->hwmode.crtc_clock) {
88e72717 948 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
4041b853
CW		 949 return -EBUSY;
950 }
0af7e4df
MK		 951
952 /* Helper routine in DRM core does all the work: */
4041b853
CW		 953 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
954 vblank_time, flags,
fc467a22 955 &crtc->hwmode);
0af7e4df
MK		 956}
957
d0ecd7e2 958static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 959{
2d1013dd 960 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 961 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 962 u8 new_delay;
9270388e 963
d0ecd7e2 964 spin_lock(&mchdev_lock);
f97108d1 965
73edd18f
DV		 966 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
967
20e4d407 968 new_delay = dev_priv->ips.cur_delay;
9270388e 969
7648fa99 970 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 971 busy_up = I915_READ(RCPREVBSYTUPAVG);
972 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 973 max_avg = I915_READ(RCBMAXAVG);
974 min_avg = I915_READ(RCBMINAVG);
975
976 /* Handle RCS change request from hw */
b5b72e89 977 if (busy_up > max_avg) {
20e4d407
DV		 978 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
979 new_delay = dev_priv->ips.cur_delay - 1;
980 if (new_delay < dev_priv->ips.max_delay)
981 new_delay = dev_priv->ips.max_delay;
b5b72e89 982 } else if (busy_down < min_avg) {
20e4d407
DV		 983 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
984 new_delay = dev_priv->ips.cur_delay + 1;
985 if (new_delay > dev_priv->ips.min_delay)
986 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 987 }
988
7648fa99 989 if (ironlake_set_drps(dev, new_delay))
20e4d407 990 dev_priv->ips.cur_delay = new_delay;
f97108d1 991
d0ecd7e2 992 spin_unlock(&mchdev_lock);
9270388e 993
f97108d1
JB		 994 return;
995}
996
0bc40be8 997static void notify_ring(struct intel_engine_cs *engine)
549f7365 998{
117897f4 999 if (!intel_engine_initialized(engine))
475553de
CW		 1000 return;
1001
0bc40be8 1002 trace_i915_gem_request_notify(engine);
9862e600 1003
0bc40be8 1004 wake_up_all(&engine->irq_queue);
549f7365
CW		 1005}
1006
43cf3bf0
CW		 1007static void vlv_c0_read(struct drm_i915_private *dev_priv,
1008 struct intel_rps_ei *ei)
31685c25 1009{
43cf3bf0
CW		 1010 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1011 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1012 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1013}
31685c25 1014
43cf3bf0
CW		 1015static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1016 const struct intel_rps_ei *old,
1017 const struct intel_rps_ei *now,
1018 int threshold)
1019{
1020 u64 time, c0;
7bad74d5 1021 unsigned int mul = 100;
31685c25 1022
43cf3bf0
CW		 1023 if (old->cz_clock == 0)
1024 return false;
31685c25 1025
7bad74d5
VS		 1026 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1027 mul <<= 8;
1028
43cf3bf0 1029 time = now->cz_clock - old->cz_clock;
7bad74d5 1030 time *= threshold * dev_priv->czclk_freq;
31685c25 1031
43cf3bf0
CW		 1032 /* Workload can be split between render + media, e.g. SwapBuffers
1033 * being blitted in X after being rendered in mesa. To account for
1034 * this we need to combine both engines into our activity counter.
31685c25 1035 */
43cf3bf0
CW		 1036 c0 = now->render_c0 - old->render_c0;
1037 c0 += now->media_c0 - old->media_c0;
7bad74d5 1038 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
31685c25 1039
43cf3bf0 1040 return c0 >= time;
31685c25
D		 1041}
1042
43cf3bf0 1043void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
31685c25 1044{
43cf3bf0
CW		 1045 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1046 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
43cf3bf0 1047}
31685c25 1048
43cf3bf0
CW		 1049static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1050{
1051 struct intel_rps_ei now;
1052 u32 events = 0;
31685c25 1053
6f4b12f8 1054 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
43cf3bf0 1055 return 0;
31685c25 1056
43cf3bf0
CW		 1057 vlv_c0_read(dev_priv, &now);
1058 if (now.cz_clock == 0)
1059 return 0;
31685c25 1060
43cf3bf0
CW		 1061 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1062 if (!vlv_c0_above(dev_priv,
1063 &dev_priv->rps.down_ei, &now,
8fb55197 1064 dev_priv->rps.down_threshold))
43cf3bf0
CW		 1065 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1066 dev_priv->rps.down_ei = now;
1067 }
31685c25 1068
43cf3bf0
CW		 1069 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1070 if (vlv_c0_above(dev_priv,
1071 &dev_priv->rps.up_ei, &now,
8fb55197 1072 dev_priv->rps.up_threshold))
43cf3bf0
CW		 1073 events |= GEN6_PM_RP_UP_THRESHOLD;
1074 dev_priv->rps.up_ei = now;
31685c25
D		 1075 }
1076
43cf3bf0 1077 return events;
31685c25
D		 1078}
1079
f5a4c67d
CW		 1080static bool any_waiters(struct drm_i915_private *dev_priv)
1081{
e2f80391 1082 struct intel_engine_cs *engine;
f5a4c67d 1083
b4ac5afc 1084 for_each_engine(engine, dev_priv)
e2f80391 1085 if (engine->irq_refcount)
f5a4c67d
CW		 1086 return true;
1087
1088 return false;
1089}
1090
4912d041 1091static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1092{
2d1013dd
JN		 1093 struct drm_i915_private *dev_priv =
1094 container_of(work, struct drm_i915_private, rps.work);
8d3afd7d
CW		 1095 bool client_boost;
1096 int new_delay, adj, min, max;
edbfdb45 1097 u32 pm_iir;
4912d041 1098
59cdb63d 1099 spin_lock_irq(&dev_priv->irq_lock);
d4d70aa5
ID		 1100 /* Speed up work cancelation during disabling rps interrupts. */
1101 if (!dev_priv->rps.interrupts_enabled) {
1102 spin_unlock_irq(&dev_priv->irq_lock);
1103 return;
1104 }
1f814dac
ID		 1105
1106 /*
1107 * The RPS work is synced during runtime suspend, we don't require a
1108 * wakeref. TODO: instead of disabling the asserts make sure that we
1109 * always hold an RPM reference while the work is running.
1110 */
1111 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1112
c6a828d3
DV		 1113 pm_iir = dev_priv->rps.pm_iir;
1114 dev_priv->rps.pm_iir = 0;
a72fbc3a
ID		 1115 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1116 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
8d3afd7d
CW		 1117 client_boost = dev_priv->rps.client_boost;
1118 dev_priv->rps.client_boost = false;
59cdb63d 1119 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1120
60611c13 1121 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1122 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1123
8d3afd7d 1124 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1f814dac 1125 goto out;
3b8d8d91 1126
4fc688ce 1127 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1128
43cf3bf0
CW		 1129 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1130
dd75fdc8 1131 adj = dev_priv->rps.last_adj;
edcf284b 1132 new_delay = dev_priv->rps.cur_freq;
8d3afd7d
CW		 1133 min = dev_priv->rps.min_freq_softlimit;
1134 max = dev_priv->rps.max_freq_softlimit;
1135
1136 if (client_boost) {
1137 new_delay = dev_priv->rps.max_freq_softlimit;
1138 adj = 0;
1139 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1140 if (adj > 0)
1141 adj *= 2;
edcf284b
CW		 1142 else /* CHV needs even encode values */
1143 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
7425034a
VS		 1144 /*
1145 * For better performance, jump directly
1146 * to RPe if we're below it.
1147 */
edcf284b 1148 if (new_delay < dev_priv->rps.efficient_freq - adj) {
b39fb297 1149 new_delay = dev_priv->rps.efficient_freq;
edcf284b
CW		 1150 adj = 0;
1151 }
f5a4c67d
CW		 1152 } else if (any_waiters(dev_priv)) {
1153 adj = 0;
dd75fdc8 1154 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1155 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1156 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1157 else
b39fb297 1158 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8
CW		 1159 adj = 0;
1160 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1161 if (adj < 0)
1162 adj *= 2;
edcf284b
CW		 1163 else /* CHV needs even encode values */
1164 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
dd75fdc8 1165 } else { /* unknown event */
edcf284b 1166 adj = 0;
dd75fdc8 1167 }
3b8d8d91 1168
edcf284b
CW		 1169 dev_priv->rps.last_adj = adj;
1170
79249636
BW		 1171 /* sysfs frequency interfaces may have snuck in while servicing the
1172 * interrupt
1173 */
edcf284b 1174 new_delay += adj;
8d3afd7d 1175 new_delay = clamp_t(int, new_delay, min, max);
27544369 1176
ffe02b40 1177 intel_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1178
4fc688ce 1179 mutex_unlock(&dev_priv->rps.hw_lock);
1f814dac
ID		 1180out:
1181 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3b8d8d91
JB		 1182}
1183
e3689190
BW		 1184
1185/**
1186 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1187 * occurred.
1188 * @work: workqueue struct
1189 *
1190 * Doesn't actually do anything except notify userspace. As a consequence of
1191 * this event, userspace should try to remap the bad rows since statistically
1192 * it is likely the same row is more likely to go bad again.
1193 */
1194static void ivybridge_parity_work(struct work_struct *work)
1195{
2d1013dd
JN		 1196 struct drm_i915_private *dev_priv =
1197 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1198 u32 error_status, row, bank, subbank;
35a85ac6 1199 char *parity_event[6];
e3689190 1200 uint32_t misccpctl;
35a85ac6 1201 uint8_t slice = 0;
e3689190
BW		 1202
1203 /* We must turn off DOP level clock gating to access the L3 registers.
1204 * In order to prevent a get/put style interface, acquire struct mutex
1205 * any time we access those registers.
1206 */
1207 mutex_lock(&dev_priv->dev->struct_mutex);
1208
35a85ac6
BW		 1209 /* If we've screwed up tracking, just let the interrupt fire again */
1210 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1211 goto out;
1212
e3689190
BW		 1213 misccpctl = I915_READ(GEN7_MISCCPCTL);
1214 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1215 POSTING_READ(GEN7_MISCCPCTL);
1216
35a85ac6 1217 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
f0f59a00 1218 i915_reg_t reg;
e3689190 1219
35a85ac6
BW		 1220 slice--;
1221 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1222 break;
e3689190 1223
35a85ac6 1224 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1225
6fa1c5f1 1226 reg = GEN7_L3CDERRST1(slice);
e3689190 1227
35a85ac6
BW		 1228 error_status = I915_READ(reg);
1229 row = GEN7_PARITY_ERROR_ROW(error_status);
1230 bank = GEN7_PARITY_ERROR_BANK(error_status);
1231 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1232
1233 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1234 POSTING_READ(reg);
1235
1236 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1237 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1238 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1239 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1240 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1241 parity_event[5] = NULL;
1242
5bdebb18 1243 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1244 KOBJ_CHANGE, parity_event);
e3689190 1245
35a85ac6
BW		 1246 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1247 slice, row, bank, subbank);
e3689190 1248
35a85ac6
BW		 1249 kfree(parity_event[4]);
1250 kfree(parity_event[3]);
1251 kfree(parity_event[2]);
1252 kfree(parity_event[1]);
1253 }
e3689190 1254
35a85ac6 1255 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1256
35a85ac6
BW		 1257out:
1258 WARN_ON(dev_priv->l3_parity.which_slice);
4cb21832 1259 spin_lock_irq(&dev_priv->irq_lock);
480c8033 1260 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
4cb21832 1261 spin_unlock_irq(&dev_priv->irq_lock);
35a85ac6
BW		 1262
1263 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1264}
1265
35a85ac6 1266static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1267{
2d1013dd 1268 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1269
040d2baa 1270 if (!HAS_L3_DPF(dev))
e3689190
BW		 1271 return;
1272
d0ecd7e2 1273 spin_lock(&dev_priv->irq_lock);
480c8033 1274 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1275 spin_unlock(&dev_priv->irq_lock);
e3689190 1276
35a85ac6
BW		 1277 iir &= GT_PARITY_ERROR(dev);
1278 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1279 dev_priv->l3_parity.which_slice |= 1 << 1;
1280
1281 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1282 dev_priv->l3_parity.which_slice |= 1 << 0;
1283
a4da4fa4 1284 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1285}
1286
f1af8fc1
PZ		 1287static void ilk_gt_irq_handler(struct drm_device *dev,
1288 struct drm_i915_private *dev_priv,
1289 u32 gt_iir)
1290{
1291 if (gt_iir &
1292 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
4a570db5 1293 notify_ring(&dev_priv->engine[RCS]);
f1af8fc1 1294 if (gt_iir & ILK_BSD_USER_INTERRUPT)
4a570db5 1295 notify_ring(&dev_priv->engine[VCS]);
f1af8fc1
PZ		 1296}
1297
e7b4c6b1
DV		 1298static void snb_gt_irq_handler(struct drm_device *dev,
1299 struct drm_i915_private *dev_priv,
1300 u32 gt_iir)
1301{
1302
cc609d5d
BW		 1303 if (gt_iir &
1304 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
4a570db5 1305 notify_ring(&dev_priv->engine[RCS]);
cc609d5d 1306 if (gt_iir & GT_BSD_USER_INTERRUPT)
4a570db5 1307 notify_ring(&dev_priv->engine[VCS]);
cc609d5d 1308 if (gt_iir & GT_BLT_USER_INTERRUPT)
4a570db5 1309 notify_ring(&dev_priv->engine[BCS]);
e7b4c6b1 1310
cc609d5d
BW		 1311 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1312 GT_BSD_CS_ERROR_INTERRUPT |
aaecdf61
DV		 1313 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1314 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
e3689190 1315
35a85ac6
BW		 1316 if (gt_iir & GT_PARITY_ERROR(dev))
1317 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1318}
1319
fbcc1a0c 1320static __always_inline void
0bc40be8 1321gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
fbcc1a0c
NH		 1322{
1323 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
0bc40be8 1324 notify_ring(engine);
fbcc1a0c 1325 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
27af5eea 1326 tasklet_schedule(&engine->irq_tasklet);
fbcc1a0c
NH		 1327}
1328
74cdb337 1329static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
abd58f01
BW		 1330 u32 master_ctl)
1331{
abd58f01
BW		 1332 irqreturn_t ret = IRQ_NONE;
1333
1334 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
5dd280b0
NH		 1335 u32 iir = I915_READ_FW(GEN8_GT_IIR(0));
1336 if (iir) {
1337 I915_WRITE_FW(GEN8_GT_IIR(0), iir);
abd58f01 1338 ret = IRQ_HANDLED;
e981e7b1 1339
4a570db5
TU		 1340 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1341 iir, GEN8_RCS_IRQ_SHIFT);
74cdb337 1342
4a570db5
TU		 1343 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1344 iir, GEN8_BCS_IRQ_SHIFT);
abd58f01
BW		 1345 } else
1346 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1347 }
1348
85f9b5f9 1349 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
5dd280b0
NH		 1350 u32 iir = I915_READ_FW(GEN8_GT_IIR(1));
1351 if (iir) {
1352 I915_WRITE_FW(GEN8_GT_IIR(1), iir);
abd58f01 1353 ret = IRQ_HANDLED;
e981e7b1 1354
4a570db5
TU		 1355 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1356 iir, GEN8_VCS1_IRQ_SHIFT);
abd58f01 1357
4a570db5
TU		 1358 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1359 iir, GEN8_VCS2_IRQ_SHIFT);
0961021a 1360 } else
abd58f01 1361 DRM_ERROR("The master control interrupt lied (GT1)!\n");
0961021a
BW		 1362 }
1363
abd58f01 1364 if (master_ctl & GEN8_GT_VECS_IRQ) {
5dd280b0
NH		 1365 u32 iir = I915_READ_FW(GEN8_GT_IIR(3));
1366 if (iir) {
1367 I915_WRITE_FW(GEN8_GT_IIR(3), iir);
abd58f01 1368 ret = IRQ_HANDLED;
e981e7b1 1369
4a570db5
TU		 1370 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1371 iir, GEN8_VECS_IRQ_SHIFT);
abd58f01
BW		 1372 } else
1373 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1374 }
1375
0961021a 1376 if (master_ctl & GEN8_GT_PM_IRQ) {
5dd280b0
NH		 1377 u32 iir = I915_READ_FW(GEN8_GT_IIR(2));
1378 if (iir & dev_priv->pm_rps_events) {
cb0d205e 1379 I915_WRITE_FW(GEN8_GT_IIR(2),
5dd280b0 1380 iir & dev_priv->pm_rps_events);
38cc46d7 1381 ret = IRQ_HANDLED;
5dd280b0 1382 gen6_rps_irq_handler(dev_priv, iir);
0961021a
BW		 1383 } else
1384 DRM_ERROR("The master control interrupt lied (PM)!\n");
1385 }
1386
abd58f01
BW		 1387 return ret;
1388}
1389
63c88d22
ID		 1390static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1391{
1392 switch (port) {
1393 case PORT_A:
195baa06 1394 return val & PORTA_HOTPLUG_LONG_DETECT;
63c88d22
ID		 1395 case PORT_B:
1396 return val & PORTB_HOTPLUG_LONG_DETECT;
1397 case PORT_C:
1398 return val & PORTC_HOTPLUG_LONG_DETECT;
63c88d22
ID		 1399 default:
1400 return false;
1401 }
1402}
1403
6dbf30ce
VS		 1404static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1405{
1406 switch (port) {
1407 case PORT_E:
1408 return val & PORTE_HOTPLUG_LONG_DETECT;
1409 default:
1410 return false;
1411 }
1412}
1413
74c0b395
VS		 1414static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1415{
1416 switch (port) {
1417 case PORT_A:
1418 return val & PORTA_HOTPLUG_LONG_DETECT;
1419 case PORT_B:
1420 return val & PORTB_HOTPLUG_LONG_DETECT;
1421 case PORT_C:
1422 return val & PORTC_HOTPLUG_LONG_DETECT;
1423 case PORT_D:
1424 return val & PORTD_HOTPLUG_LONG_DETECT;
1425 default:
1426 return false;
1427 }
1428}
1429
e4ce95aa
VS		 1430static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1431{
1432 switch (port) {
1433 case PORT_A:
1434 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1435 default:
1436 return false;
1437 }
1438}
1439
676574df 1440static bool pch_port_hotplug_long_detect(enum port port, u32 val)
13cf5504
DA		 1441{
1442 switch (port) {
13cf5504 1443 case PORT_B:
676574df 1444 return val & PORTB_HOTPLUG_LONG_DETECT;
13cf5504 1445 case PORT_C:
676574df 1446 return val & PORTC_HOTPLUG_LONG_DETECT;
13cf5504 1447 case PORT_D:
676574df
JN		 1448 return val & PORTD_HOTPLUG_LONG_DETECT;
1449 default:
1450 return false;
13cf5504
DA		 1451 }
1452}
1453
676574df 1454static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
13cf5504
DA		 1455{
1456 switch (port) {
13cf5504 1457 case PORT_B:
676574df 1458 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
13cf5504 1459 case PORT_C:
676574df 1460 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
13cf5504 1461 case PORT_D:
676574df
JN		 1462 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1463 default:
1464 return false;
13cf5504
DA		 1465 }
1466}
1467
42db67d6
VS		 1468/*
1469 * Get a bit mask of pins that have triggered, and which ones may be long.
1470 * This can be called multiple times with the same masks to accumulate
1471 * hotplug detection results from several registers.
1472 *
1473 * Note that the caller is expected to zero out the masks initially.
1474 */
fd63e2a9 1475static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
8c841e57 1476 u32 hotplug_trigger, u32 dig_hotplug_reg,
fd63e2a9
ID		 1477 const u32 hpd[HPD_NUM_PINS],
1478 bool long_pulse_detect(enum port port, u32 val))
676574df 1479{
8c841e57 1480 enum port port;
676574df
JN		 1481 int i;
1482
676574df 1483 for_each_hpd_pin(i) {
8c841e57
JN		 1484 if ((hpd[i] & hotplug_trigger) == 0)
1485 continue;
676574df 1486
8c841e57
JN		 1487 *pin_mask |= BIT(i);
1488
cc24fcdc
ID		 1489 if (!intel_hpd_pin_to_port(i, &port))
1490 continue;
1491
fd63e2a9 1492 if (long_pulse_detect(port, dig_hotplug_reg))
8c841e57 1493 *long_mask |= BIT(i);
676574df
JN		 1494 }
1495
1496 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1497 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1498
1499}
1500
515ac2bb
DV		 1501static void gmbus_irq_handler(struct drm_device *dev)
1502{
2d1013dd 1503 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1504
28c70f16 1505 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1506}
1507
ce99c256
DV		 1508static void dp_aux_irq_handler(struct drm_device *dev)
1509{
2d1013dd 1510 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1511
9ee32fea 1512 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1513}
1514
8bf1e9f1 1515#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1516static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1517 uint32_t crc0, uint32_t crc1,
1518 uint32_t crc2, uint32_t crc3,
1519 uint32_t crc4)
8bf1e9f1
SH		 1520{
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1523 struct intel_pipe_crc_entry *entry;
ac2300d4 1524 int head, tail;
b2c88f5b 1525
d538bbdf
DL		 1526 spin_lock(&pipe_crc->lock);
1527
0c912c79 1528 if (!pipe_crc->entries) {
d538bbdf 1529 spin_unlock(&pipe_crc->lock);
34273620 1530 DRM_DEBUG_KMS("spurious interrupt\n");
0c912c79
DL		 1531 return;
1532 }
1533
d538bbdf
DL		 1534 head = pipe_crc->head;
1535 tail = pipe_crc->tail;
b2c88f5b
DL		 1536
1537 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1538 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1539 DRM_ERROR("CRC buffer overflowing\n");
1540 return;
1541 }
1542
1543 entry = &pipe_crc->entries[head];
8bf1e9f1 1544
8bc5e955 1545 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1546 entry->crc[0] = crc0;
1547 entry->crc[1] = crc1;
1548 entry->crc[2] = crc2;
1549 entry->crc[3] = crc3;
1550 entry->crc[4] = crc4;
b2c88f5b
DL		 1551
1552 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1553 pipe_crc->head = head;
1554
1555 spin_unlock(&pipe_crc->lock);
07144428
DL		 1556
1557 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1558}
277de95e
DV		 1559#else
1560static inline void
1561display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1562 uint32_t crc0, uint32_t crc1,
1563 uint32_t crc2, uint32_t crc3,
1564 uint32_t crc4) {}
1565#endif
1566
eba94eb9 1567
277de95e 1568static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1569{
1570 struct drm_i915_private *dev_priv = dev->dev_private;
1571
277de95e
DV		 1572 display_pipe_crc_irq_handler(dev, pipe,
1573 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1574 0, 0, 0, 0);
5a69b89f
DV		 1575}
1576
277de95e 1577static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1578{
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
277de95e
DV		 1581 display_pipe_crc_irq_handler(dev, pipe,
1582 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1583 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1584 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1585 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1586 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1587}
5b3a856b 1588
277de95e 1589static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1590{
1591 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1592 uint32_t res1, res2;
1593
1594 if (INTEL_INFO(dev)->gen >= 3)
1595 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1596 else
1597 res1 = 0;
1598
1599 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1600 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1601 else
1602 res2 = 0;
5b3a856b 1603
277de95e
DV		 1604 display_pipe_crc_irq_handler(dev, pipe,
1605 I915_READ(PIPE_CRC_RES_RED(pipe)),
1606 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1607 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1608 res1, res2);
5b3a856b 1609}
8bf1e9f1 1610
1403c0d4
PZ		 1611/* The RPS events need forcewake, so we add them to a work queue and mask their
1612 * IMR bits until the work is done. Other interrupts can be processed without
1613 * the work queue. */
1614static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1615{
a6706b45 1616 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1617 spin_lock(&dev_priv->irq_lock);
480c8033 1618 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
d4d70aa5
ID		 1619 if (dev_priv->rps.interrupts_enabled) {
1620 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1621 queue_work(dev_priv->wq, &dev_priv->rps.work);
1622 }
59cdb63d 1623 spin_unlock(&dev_priv->irq_lock);
baf02a1f 1624 }
baf02a1f 1625
c9a9a268
ID		 1626 if (INTEL_INFO(dev_priv)->gen >= 8)
1627 return;
1628
1403c0d4
PZ		 1629 if (HAS_VEBOX(dev_priv->dev)) {
1630 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
4a570db5 1631 notify_ring(&dev_priv->engine[VECS]);
12638c57 1632
aaecdf61
DV		 1633 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1634 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
12638c57 1635 }
baf02a1f
BW		 1636}
1637
8d7849db
VS		 1638static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1639{
8d7849db
VS		 1640 if (!drm_handle_vblank(dev, pipe))
1641 return false;
1642
8d7849db
VS		 1643 return true;
1644}
1645
c1874ed7
ID		 1646static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1647{
1648 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1649 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1650 int pipe;
1651
58ead0d7 1652 spin_lock(&dev_priv->irq_lock);
1ca993d2
VS		 1653
1654 if (!dev_priv->display_irqs_enabled) {
1655 spin_unlock(&dev_priv->irq_lock);
1656 return;
1657 }
1658
055e393f 1659 for_each_pipe(dev_priv, pipe) {
f0f59a00 1660 i915_reg_t reg;
bbb5eebf 1661 u32 mask, iir_bit = 0;
91d181dd 1662
bbb5eebf
DV		 1663 /*
1664 * PIPESTAT bits get signalled even when the interrupt is
1665 * disabled with the mask bits, and some of the status bits do
1666 * not generate interrupts at all (like the underrun bit). Hence
1667 * we need to be careful that we only handle what we want to
1668 * handle.
1669 */
0f239f4c
DV		 1670
1671 /* fifo underruns are filterered in the underrun handler. */
1672 mask = PIPE_FIFO_UNDERRUN_STATUS;
bbb5eebf
DV		 1673
1674 switch (pipe) {
1675 case PIPE_A:
1676 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1677 break;
1678 case PIPE_B:
1679 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1680 break;
3278f67f
VS		 1681 case PIPE_C:
1682 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1683 break;
bbb5eebf
DV		 1684 }
1685 if (iir & iir_bit)
1686 mask |= dev_priv->pipestat_irq_mask[pipe];
1687
1688 if (!mask)
91d181dd
ID		 1689 continue;
1690
1691 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1692 mask |= PIPESTAT_INT_ENABLE_MASK;
1693 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1694
1695 /*
1696 * Clear the PIPE*STAT regs before the IIR
1697 */
91d181dd
ID		 1698 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1699 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1700 I915_WRITE(reg, pipe_stats[pipe]);
1701 }
58ead0d7 1702 spin_unlock(&dev_priv->irq_lock);
c1874ed7 1703
055e393f 1704 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 1705 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1706 intel_pipe_handle_vblank(dev, pipe))
1707 intel_check_page_flip(dev, pipe);
c1874ed7 1708
579a9b0e 1709 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1710 intel_prepare_page_flip(dev, pipe);
1711 intel_finish_page_flip(dev, pipe);
1712 }
1713
1714 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1715 i9xx_pipe_crc_irq_handler(dev, pipe);
1716
1f7247c0
DV		 1717 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1718 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
c1874ed7
ID		 1719 }
1720
1721 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1722 gmbus_irq_handler(dev);
1723}
1724
16c6c56b
VS		 1725static void i9xx_hpd_irq_handler(struct drm_device *dev)
1726{
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
42db67d6 1729 u32 pin_mask = 0, long_mask = 0;
16c6c56b 1730
0d2e4297
JN		 1731 if (!hotplug_status)
1732 return;
16c6c56b 1733
0d2e4297
JN		 1734 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1735 /*
1736 * Make sure hotplug status is cleared before we clear IIR, or else we
1737 * may miss hotplug events.
1738 */
1739 POSTING_READ(PORT_HOTPLUG_STAT);
16c6c56b 1740
666a4537 1741 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
0d2e4297 1742 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
16c6c56b 1743
58f2cf24
VS		 1744 if (hotplug_trigger) {
1745 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1746 hotplug_trigger, hpd_status_g4x,
1747 i9xx_port_hotplug_long_detect);
1748
1749 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1750 }
369712e8
JN		 1751
1752 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1753 dp_aux_irq_handler(dev);
0d2e4297
JN		 1754 } else {
1755 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
16c6c56b 1756
58f2cf24
VS		 1757 if (hotplug_trigger) {
1758 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
44cc6c08 1759 hotplug_trigger, hpd_status_i915,
58f2cf24 1760 i9xx_port_hotplug_long_detect);
58f2cf24
VS		 1761 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1762 }
3ff60f89 1763 }
16c6c56b
VS		 1764}
1765
ff1f525e 1766static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe 1767{
45a83f84 1768 struct drm_device *dev = arg;
2d1013dd 1769 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1770 u32 iir, gt_iir, pm_iir;
1771 irqreturn_t ret = IRQ_NONE;
7e231dbe 1772
2dd2a883
ID		 1773 if (!intel_irqs_enabled(dev_priv))
1774 return IRQ_NONE;
1775
1f814dac
ID		 1776 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1777 disable_rpm_wakeref_asserts(dev_priv);
1778
7e231dbe 1779 while (true) {
3ff60f89
OM		 1780 /* Find, clear, then process each source of interrupt */
1781
7e231dbe 1782 gt_iir = I915_READ(GTIIR);
3ff60f89
OM		 1783 if (gt_iir)
1784 I915_WRITE(GTIIR, gt_iir);
1785
7e231dbe 1786 pm_iir = I915_READ(GEN6_PMIIR);
3ff60f89
OM		 1787 if (pm_iir)
1788 I915_WRITE(GEN6_PMIIR, pm_iir);
1789
1790 iir = I915_READ(VLV_IIR);
1791 if (iir) {
1792 /* Consume port before clearing IIR or we'll miss events */
1793 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1794 i9xx_hpd_irq_handler(dev);
1795 I915_WRITE(VLV_IIR, iir);
1796 }
7e231dbe
JB		 1797
1798 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1799 goto out;
1800
1801 ret = IRQ_HANDLED;
1802
3ff60f89
OM		 1803 if (gt_iir)
1804 snb_gt_irq_handler(dev, dev_priv, gt_iir);
60611c13 1805 if (pm_iir)
d0ecd7e2 1806 gen6_rps_irq_handler(dev_priv, pm_iir);
3ff60f89
OM		 1807 /* Call regardless, as some status bits might not be
1808 * signalled in iir */
1809 valleyview_pipestat_irq_handler(dev, iir);
7e231dbe
JB		 1810 }
1811
1812out:
1f814dac
ID		 1813 enable_rpm_wakeref_asserts(dev_priv);
1814
7e231dbe
JB		 1815 return ret;
1816}
1817
43f328d7
VS		 1818static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1819{
45a83f84 1820 struct drm_device *dev = arg;
43f328d7
VS		 1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 u32 master_ctl, iir;
1823 irqreturn_t ret = IRQ_NONE;
43f328d7 1824
2dd2a883
ID		 1825 if (!intel_irqs_enabled(dev_priv))
1826 return IRQ_NONE;
1827
1f814dac
ID		 1828 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1829 disable_rpm_wakeref_asserts(dev_priv);
1830
579de73b 1831 do {
8e5fd599
VS		 1832 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1833 iir = I915_READ(VLV_IIR);
43f328d7 1834
8e5fd599
VS		 1835 if (master_ctl == 0 && iir == 0)
1836 break;
43f328d7 1837
27b6c122
OM		 1838 ret = IRQ_HANDLED;
1839
8e5fd599 1840 I915_WRITE(GEN8_MASTER_IRQ, 0);
43f328d7 1841
27b6c122 1842 /* Find, clear, then process each source of interrupt */
43f328d7 1843
27b6c122
OM		 1844 if (iir) {
1845 /* Consume port before clearing IIR or we'll miss events */
1846 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1847 i9xx_hpd_irq_handler(dev);
1848 I915_WRITE(VLV_IIR, iir);
1849 }
43f328d7 1850
74cdb337 1851 gen8_gt_irq_handler(dev_priv, master_ctl);
43f328d7 1852
27b6c122
OM		 1853 /* Call regardless, as some status bits might not be
1854 * signalled in iir */
1855 valleyview_pipestat_irq_handler(dev, iir);
43f328d7 1856
8e5fd599
VS		 1857 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1858 POSTING_READ(GEN8_MASTER_IRQ);
579de73b 1859 } while (0);
3278f67f 1860
1f814dac
ID		 1861 enable_rpm_wakeref_asserts(dev_priv);
1862
43f328d7
VS		 1863 return ret;
1864}
1865
40e56410
VS		 1866static void ibx_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
1867 const u32 hpd[HPD_NUM_PINS])
1868{
1869 struct drm_i915_private *dev_priv = to_i915(dev);
1870 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1871
6a39d7c9
JN		 1872 /*
1873 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1874 * unless we touch the hotplug register, even if hotplug_trigger is
1875 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1876 * errors.
1877 */
40e56410 1878 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
6a39d7c9
JN		 1879 if (!hotplug_trigger) {
1880 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1881 PORTD_HOTPLUG_STATUS_MASK |
1882 PORTC_HOTPLUG_STATUS_MASK |
1883 PORTB_HOTPLUG_STATUS_MASK;
1884 dig_hotplug_reg &= ~mask;
1885 }
1886
40e56410 1887 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
6a39d7c9
JN		 1888 if (!hotplug_trigger)
1889 return;
40e56410
VS		 1890
1891 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1892 dig_hotplug_reg, hpd,
1893 pch_port_hotplug_long_detect);
1894
1895 intel_hpd_irq_handler(dev, pin_mask, long_mask);
1896}
1897
23e81d69 1898static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1899{
2d1013dd 1900 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1901 int pipe;
b543fb04 1902 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
13cf5504 1903
6a39d7c9 1904 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
91d131d2 1905
cfc33bf7
VS		 1906 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1907 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1908 SDE_AUDIO_POWER_SHIFT);
776ad806 1909 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1910 port_name(port));
1911 }
776ad806 1912
ce99c256
DV		 1913 if (pch_iir & SDE_AUX_MASK)
1914 dp_aux_irq_handler(dev);
1915
776ad806 1916 if (pch_iir & SDE_GMBUS)
515ac2bb 1917 gmbus_irq_handler(dev);
776ad806
JB		 1918
1919 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1920 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1921
1922 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1923 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1924
1925 if (pch_iir & SDE_POISON)
1926 DRM_ERROR("PCH poison interrupt\n");
1927
9db4a9c7 1928 if (pch_iir & SDE_FDI_MASK)
055e393f 1929 for_each_pipe(dev_priv, pipe)
9db4a9c7
JB		 1930 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1931 pipe_name(pipe),
1932 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1933
1934 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1935 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1936
1937 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1938 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1939
776ad806 1940 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1f7247c0 1941 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1942
1943 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1f7247c0 1944 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1945}
1946
1947static void ivb_err_int_handler(struct drm_device *dev)
1948{
1949 struct drm_i915_private *dev_priv = dev->dev_private;
1950 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1951 enum pipe pipe;
8664281b 1952
de032bf4
PZ		 1953 if (err_int & ERR_INT_POISON)
1954 DRM_ERROR("Poison interrupt\n");
1955
055e393f 1956 for_each_pipe(dev_priv, pipe) {
1f7247c0
DV		 1957 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1958 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
8bf1e9f1 1959
5a69b89f
DV		 1960 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1961 if (IS_IVYBRIDGE(dev))
277de95e 1962 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1963 else
277de95e 1964 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1965 }
1966 }
8bf1e9f1 1967
8664281b
PZ		 1968 I915_WRITE(GEN7_ERR_INT, err_int);
1969}
1970
1971static void cpt_serr_int_handler(struct drm_device *dev)
1972{
1973 struct drm_i915_private *dev_priv = dev->dev_private;
1974 u32 serr_int = I915_READ(SERR_INT);
1975
de032bf4
PZ		 1976 if (serr_int & SERR_INT_POISON)
1977 DRM_ERROR("PCH poison interrupt\n");
1978
8664281b 1979 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1f7247c0 1980 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
8664281b
PZ		 1981
1982 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1f7247c0 1983 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
8664281b
PZ		 1984
1985 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1f7247c0 1986 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
8664281b
PZ		 1987
1988 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1989}
1990
23e81d69
AJ		 1991static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1992{
2d1013dd 1993 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 1994 int pipe;
6dbf30ce 1995 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
13cf5504 1996
6a39d7c9 1997 ibx_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
91d131d2 1998
cfc33bf7
VS		 1999 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2000 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2001 SDE_AUDIO_POWER_SHIFT_CPT);
2002 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2003 port_name(port));
2004 }
23e81d69
AJ		 2005
2006 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 2007 dp_aux_irq_handler(dev);
23e81d69
AJ		 2008
2009 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 2010 gmbus_irq_handler(dev);
23e81d69
AJ		 2011
2012 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2013 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2014
2015 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2016 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2017
2018 if (pch_iir & SDE_FDI_MASK_CPT)
055e393f 2019 for_each_pipe(dev_priv, pipe)
23e81d69
AJ		 2020 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2021 pipe_name(pipe),
2022 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 2023
2024 if (pch_iir & SDE_ERROR_CPT)
2025 cpt_serr_int_handler(dev);
23e81d69
AJ		 2026}
2027
6dbf30ce
VS		 2028static void spt_irq_handler(struct drm_device *dev, u32 pch_iir)
2029{
2030 struct drm_i915_private *dev_priv = dev->dev_private;
2031 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2032 ~SDE_PORTE_HOTPLUG_SPT;
2033 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2034 u32 pin_mask = 0, long_mask = 0;
2035
2036 if (hotplug_trigger) {
2037 u32 dig_hotplug_reg;
2038
2039 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2040 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2041
2042 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2043 dig_hotplug_reg, hpd_spt,
74c0b395 2044 spt_port_hotplug_long_detect);
6dbf30ce
VS		 2045 }
2046
2047 if (hotplug2_trigger) {
2048 u32 dig_hotplug_reg;
2049
2050 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2051 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2052
2053 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2054 dig_hotplug_reg, hpd_spt,
2055 spt_port_hotplug2_long_detect);
2056 }
2057
2058 if (pin_mask)
2059 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2060
2061 if (pch_iir & SDE_GMBUS_CPT)
2062 gmbus_irq_handler(dev);
2063}
2064
40e56410
VS		 2065static void ilk_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2066 const u32 hpd[HPD_NUM_PINS])
2067{
2068 struct drm_i915_private *dev_priv = to_i915(dev);
2069 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2070
2071 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2072 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2073
2074 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2075 dig_hotplug_reg, hpd,
2076 ilk_port_hotplug_long_detect);
2077
2078 intel_hpd_irq_handler(dev, pin_mask, long_mask);
2079}
2080
c008bc6e
PZ		 2081static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2082{
2083 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 2084 enum pipe pipe;
e4ce95aa
VS		 2085 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2086
40e56410
VS		 2087 if (hotplug_trigger)
2088 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ilk);
c008bc6e
PZ		 2089
2090 if (de_iir & DE_AUX_CHANNEL_A)
2091 dp_aux_irq_handler(dev);
2092
2093 if (de_iir & DE_GSE)
2094 intel_opregion_asle_intr(dev);
2095
c008bc6e
PZ		 2096 if (de_iir & DE_POISON)
2097 DRM_ERROR("Poison interrupt\n");
2098
055e393f 2099 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2100 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2101 intel_pipe_handle_vblank(dev, pipe))
2102 intel_check_page_flip(dev, pipe);
5b3a856b 2103
40da17c2 2104 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1f7247c0 2105 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
5b3a856b 2106
40da17c2
DV		 2107 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2108 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 2109
40da17c2
DV		 2110 /* plane/pipes map 1:1 on ilk+ */
2111 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2112 intel_prepare_page_flip(dev, pipe);
2113 intel_finish_page_flip_plane(dev, pipe);
2114 }
c008bc6e
PZ		 2115 }
2116
2117 /* check event from PCH */
2118 if (de_iir & DE_PCH_EVENT) {
2119 u32 pch_iir = I915_READ(SDEIIR);
2120
2121 if (HAS_PCH_CPT(dev))
2122 cpt_irq_handler(dev, pch_iir);
2123 else
2124 ibx_irq_handler(dev, pch_iir);
2125
2126 /* should clear PCH hotplug event before clear CPU irq */
2127 I915_WRITE(SDEIIR, pch_iir);
2128 }
2129
2130 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2131 ironlake_rps_change_irq_handler(dev);
2132}
2133
9719fb98
PZ		 2134static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2135{
2136 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 2137 enum pipe pipe;
23bb4cb5
VS		 2138 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2139
40e56410
VS		 2140 if (hotplug_trigger)
2141 ilk_hpd_irq_handler(dev, hotplug_trigger, hpd_ivb);
9719fb98
PZ		 2142
2143 if (de_iir & DE_ERR_INT_IVB)
2144 ivb_err_int_handler(dev);
2145
2146 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2147 dp_aux_irq_handler(dev);
2148
2149 if (de_iir & DE_GSE_IVB)
2150 intel_opregion_asle_intr(dev);
2151
055e393f 2152 for_each_pipe(dev_priv, pipe) {
d6bbafa1
CW		 2153 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2154 intel_pipe_handle_vblank(dev, pipe))
2155 intel_check_page_flip(dev, pipe);
40da17c2
DV		 2156
2157 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 2158 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2159 intel_prepare_page_flip(dev, pipe);
2160 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 2161 }
2162 }
2163
2164 /* check event from PCH */
2165 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2166 u32 pch_iir = I915_READ(SDEIIR);
2167
2168 cpt_irq_handler(dev, pch_iir);
2169
2170 /* clear PCH hotplug event before clear CPU irq */
2171 I915_WRITE(SDEIIR, pch_iir);
2172 }
2173}
2174
72c90f62
OM		 2175/*
2176 * To handle irqs with the minimum potential races with fresh interrupts, we:
2177 * 1 - Disable Master Interrupt Control.
2178 * 2 - Find the source(s) of the interrupt.
2179 * 3 - Clear the Interrupt Identity bits (IIR).
2180 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2181 * 5 - Re-enable Master Interrupt Control.
2182 */
f1af8fc1 2183static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0 2184{
45a83f84 2185 struct drm_device *dev = arg;
2d1013dd 2186 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 2187 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 2188 irqreturn_t ret = IRQ_NONE;
b1f14ad0 2189
2dd2a883
ID		 2190 if (!intel_irqs_enabled(dev_priv))
2191 return IRQ_NONE;
2192
1f814dac
ID		 2193 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2194 disable_rpm_wakeref_asserts(dev_priv);
2195
b1f14ad0
JB		 2196 /* disable master interrupt before clearing iir */
2197 de_ier = I915_READ(DEIER);
2198 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 2199 POSTING_READ(DEIER);
b1f14ad0 2200
44498aea
PZ		 2201 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2202 * interrupts will will be stored on its back queue, and then we'll be
2203 * able to process them after we restore SDEIER (as soon as we restore
2204 * it, we'll get an interrupt if SDEIIR still has something to process
2205 * due to its back queue). */
ab5c608b
BW		 2206 if (!HAS_PCH_NOP(dev)) {
2207 sde_ier = I915_READ(SDEIER);
2208 I915_WRITE(SDEIER, 0);
2209 POSTING_READ(SDEIER);
2210 }
44498aea 2211
72c90f62
OM		 2212 /* Find, clear, then process each source of interrupt */
2213
b1f14ad0 2214 gt_iir = I915_READ(GTIIR);
0e43406b 2215 if (gt_iir) {
72c90f62
OM		 2216 I915_WRITE(GTIIR, gt_iir);
2217 ret = IRQ_HANDLED;
d8fc8a47 2218 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 2219 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 2220 else
2221 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 2222 }
2223
0e43406b
CW		 2224 de_iir = I915_READ(DEIIR);
2225 if (de_iir) {
72c90f62
OM		 2226 I915_WRITE(DEIIR, de_iir);
2227 ret = IRQ_HANDLED;
f1af8fc1
PZ		 2228 if (INTEL_INFO(dev)->gen >= 7)
2229 ivb_display_irq_handler(dev, de_iir);
2230 else
2231 ilk_display_irq_handler(dev, de_iir);
b1f14ad0
JB		 2232 }
2233
f1af8fc1
PZ		 2234 if (INTEL_INFO(dev)->gen >= 6) {
2235 u32 pm_iir = I915_READ(GEN6_PMIIR);
2236 if (pm_iir) {
f1af8fc1
PZ		 2237 I915_WRITE(GEN6_PMIIR, pm_iir);
2238 ret = IRQ_HANDLED;
72c90f62 2239 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1 2240 }
0e43406b 2241 }
b1f14ad0 2242
b1f14ad0
JB		 2243 I915_WRITE(DEIER, de_ier);
2244 POSTING_READ(DEIER);
ab5c608b
BW		 2245 if (!HAS_PCH_NOP(dev)) {
2246 I915_WRITE(SDEIER, sde_ier);
2247 POSTING_READ(SDEIER);
2248 }
b1f14ad0 2249
1f814dac
ID		 2250 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2251 enable_rpm_wakeref_asserts(dev_priv);
2252
b1f14ad0
JB		 2253 return ret;
2254}
2255
40e56410
VS		 2256static void bxt_hpd_irq_handler(struct drm_device *dev, u32 hotplug_trigger,
2257 const u32 hpd[HPD_NUM_PINS])
d04a492d 2258{
cebd87a0
VS		 2259 struct drm_i915_private *dev_priv = to_i915(dev);
2260 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
d04a492d 2261
a52bb15b
VS		 2262 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2263 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
d04a492d 2264
cebd87a0 2265 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
40e56410 2266 dig_hotplug_reg, hpd,
cebd87a0 2267 bxt_port_hotplug_long_detect);
40e56410 2268
676574df 2269 intel_hpd_irq_handler(dev, pin_mask, long_mask);
d04a492d
SS		 2270}
2271
f11a0f46
TU		 2272static irqreturn_t
2273gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
abd58f01 2274{
f11a0f46 2275 struct drm_device *dev = dev_priv->dev;
abd58f01 2276 irqreturn_t ret = IRQ_NONE;
f11a0f46 2277 u32 iir;
c42664cc 2278 enum pipe pipe;
88e04703 2279
abd58f01 2280 if (master_ctl & GEN8_DE_MISC_IRQ) {
e32192e1
TU		 2281 iir = I915_READ(GEN8_DE_MISC_IIR);
2282 if (iir) {
2283 I915_WRITE(GEN8_DE_MISC_IIR, iir);
abd58f01 2284 ret = IRQ_HANDLED;
e32192e1 2285 if (iir & GEN8_DE_MISC_GSE)
38cc46d7
OM		 2286 intel_opregion_asle_intr(dev);
2287 else
2288 DRM_ERROR("Unexpected DE Misc interrupt\n");
abd58f01 2289 }
38cc46d7
OM		 2290 else
2291 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
abd58f01
BW		 2292 }
2293
6d766f02 2294 if (master_ctl & GEN8_DE_PORT_IRQ) {
e32192e1
TU		 2295 iir = I915_READ(GEN8_DE_PORT_IIR);
2296 if (iir) {
2297 u32 tmp_mask;
d04a492d 2298 bool found = false;
cebd87a0 2299
e32192e1 2300 I915_WRITE(GEN8_DE_PORT_IIR, iir);
6d766f02 2301 ret = IRQ_HANDLED;
88e04703 2302
e32192e1
TU		 2303 tmp_mask = GEN8_AUX_CHANNEL_A;
2304 if (INTEL_INFO(dev_priv)->gen >= 9)
2305 tmp_mask |= GEN9_AUX_CHANNEL_B |
2306 GEN9_AUX_CHANNEL_C |
2307 GEN9_AUX_CHANNEL_D;
2308
2309 if (iir & tmp_mask) {
38cc46d7 2310 dp_aux_irq_handler(dev);
d04a492d
SS		 2311 found = true;
2312 }
2313
e32192e1
TU		 2314 if (IS_BROXTON(dev_priv)) {
2315 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2316 if (tmp_mask) {
2317 bxt_hpd_irq_handler(dev, tmp_mask, hpd_bxt);
2318 found = true;
2319 }
2320 } else if (IS_BROADWELL(dev_priv)) {
2321 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2322 if (tmp_mask) {
2323 ilk_hpd_irq_handler(dev, tmp_mask, hpd_bdw);
2324 found = true;
2325 }
d04a492d
SS		 2326 }
2327
e32192e1 2328 if (IS_BROXTON(dev) && (iir & BXT_DE_PORT_GMBUS)) {
9e63743e
SS		 2329 gmbus_irq_handler(dev);
2330 found = true;
2331 }
2332
d04a492d 2333 if (!found)
38cc46d7 2334 DRM_ERROR("Unexpected DE Port interrupt\n");
6d766f02 2335 }
38cc46d7
OM		 2336 else
2337 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
6d766f02
DV		 2338 }
2339
055e393f 2340 for_each_pipe(dev_priv, pipe) {
e32192e1 2341 u32 flip_done, fault_errors;
abd58f01 2342
c42664cc
DV		 2343 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2344 continue;
abd58f01 2345
e32192e1
TU		 2346 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2347 if (!iir) {
2348 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2349 continue;
2350 }
770de83d 2351
e32192e1
TU		 2352 ret = IRQ_HANDLED;
2353 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
38cc46d7 2354
e32192e1
TU		 2355 if (iir & GEN8_PIPE_VBLANK &&
2356 intel_pipe_handle_vblank(dev, pipe))
2357 intel_check_page_flip(dev, pipe);
770de83d 2358
e32192e1
TU		 2359 flip_done = iir;
2360 if (INTEL_INFO(dev_priv)->gen >= 9)
2361 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2362 else
2363 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
38cc46d7 2364
e32192e1
TU		 2365 if (flip_done) {
2366 intel_prepare_page_flip(dev, pipe);
2367 intel_finish_page_flip_plane(dev, pipe);
2368 }
38cc46d7 2369
e32192e1
TU		 2370 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2371 hsw_pipe_crc_irq_handler(dev, pipe);
38cc46d7 2372
e32192e1
TU		 2373 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2374 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
770de83d 2375
e32192e1
TU		 2376 fault_errors = iir;
2377 if (INTEL_INFO(dev_priv)->gen >= 9)
2378 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2379 else
2380 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
770de83d 2381
e32192e1
TU		 2382 if (fault_errors)
2383 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2384 pipe_name(pipe),
2385 fault_errors);
abd58f01
BW		 2386 }
2387
266ea3d9
SS		 2388 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2389 master_ctl & GEN8_DE_PCH_IRQ) {
92d03a80
DV		 2390 /*
2391 * FIXME(BDW): Assume for now that the new interrupt handling
2392 * scheme also closed the SDE interrupt handling race we've seen
2393 * on older pch-split platforms. But this needs testing.
2394 */
e32192e1
TU		 2395 iir = I915_READ(SDEIIR);
2396 if (iir) {
2397 I915_WRITE(SDEIIR, iir);
92d03a80 2398 ret = IRQ_HANDLED;
6dbf30ce
VS		 2399
2400 if (HAS_PCH_SPT(dev_priv))
e32192e1 2401 spt_irq_handler(dev, iir);
6dbf30ce 2402 else
e32192e1 2403 cpt_irq_handler(dev, iir);
2dfb0b81
JN		 2404 } else {
2405 /*
2406 * Like on previous PCH there seems to be something
2407 * fishy going on with forwarding PCH interrupts.
2408 */
2409 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2410 }
92d03a80
DV		 2411 }
2412
f11a0f46
TU		 2413 return ret;
2414}
2415
2416static irqreturn_t gen8_irq_handler(int irq, void *arg)
2417{
2418 struct drm_device *dev = arg;
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 u32 master_ctl;
2421 irqreturn_t ret;
2422
2423 if (!intel_irqs_enabled(dev_priv))
2424 return IRQ_NONE;
2425
2426 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2427 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2428 if (!master_ctl)
2429 return IRQ_NONE;
2430
2431 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2432
2433 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2434 disable_rpm_wakeref_asserts(dev_priv);
2435
2436 /* Find, clear, then process each source of interrupt */
2437 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
2438 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2439
cb0d205e
CW		 2440 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2441 POSTING_READ_FW(GEN8_MASTER_IRQ);
abd58f01 2442
1f814dac
ID		 2443 enable_rpm_wakeref_asserts(dev_priv);
2444
abd58f01
BW		 2445 return ret;
2446}
2447
17e1df07
DV		 2448static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2449 bool reset_completed)
2450{
e2f80391 2451 struct intel_engine_cs *engine;
17e1df07
DV		 2452
2453 /*
2454 * Notify all waiters for GPU completion events that reset state has
2455 * been changed, and that they need to restart their wait after
2456 * checking for potential errors (and bail out to drop locks if there is
2457 * a gpu reset pending so that i915_error_work_func can acquire them).
2458 */
2459
2460 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
b4ac5afc 2461 for_each_engine(engine, dev_priv)
e2f80391 2462 wake_up_all(&engine->irq_queue);
17e1df07
DV		 2463
2464 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2465 wake_up_all(&dev_priv->pending_flip_queue);
2466
2467 /*
2468 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2469 * reset state is cleared.
2470 */
2471 if (reset_completed)
2472 wake_up_all(&dev_priv->gpu_error.reset_queue);
2473}
2474
8a905236 2475/**
b8d24a06 2476 * i915_reset_and_wakeup - do process context error handling work
468f9d29 2477 * @dev: drm device
8a905236
JB		 2478 *
2479 * Fire an error uevent so userspace can see that a hang or error
2480 * was detected.
2481 */
b8d24a06 2482static void i915_reset_and_wakeup(struct drm_device *dev)
8a905236 2483{
b8d24a06
MK		 2484 struct drm_i915_private *dev_priv = to_i915(dev);
2485 struct i915_gpu_error *error = &dev_priv->gpu_error;
cce723ed
BW		 2486 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2487 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2488 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2489 int ret;
8a905236 2490
5bdebb18 2491 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2492
7db0ba24
DV		 2493 /*
2494 * Note that there's only one work item which does gpu resets, so we
2495 * need not worry about concurrent gpu resets potentially incrementing
2496 * error->reset_counter twice. We only need to take care of another
2497 * racing irq/hangcheck declaring the gpu dead for a second time. A
2498 * quick check for that is good enough: schedule_work ensures the
2499 * correct ordering between hang detection and this work item, and since
2500 * the reset in-progress bit is only ever set by code outside of this
2501 * work we don't need to worry about any other races.
2502 */
2503 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2504 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2505 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2506 reset_event);
1f83fee0 2507
f454c694
ID		 2508 /*
2509 * In most cases it's guaranteed that we get here with an RPM
2510 * reference held, for example because there is a pending GPU
2511 * request that won't finish until the reset is done. This
2512 * isn't the case at least when we get here by doing a
2513 * simulated reset via debugs, so get an RPM reference.
2514 */
2515 intel_runtime_pm_get(dev_priv);
7514747d
VS		 2516
2517 intel_prepare_reset(dev);
2518
17e1df07
DV		 2519 /*
2520 * All state reset _must_ be completed before we update the
2521 * reset counter, for otherwise waiters might miss the reset
2522 * pending state and not properly drop locks, resulting in
2523 * deadlocks with the reset work.
2524 */
f69061be
DV		 2525 ret = i915_reset(dev);
2526
7514747d 2527 intel_finish_reset(dev);
17e1df07 2528
f454c694
ID		 2529 intel_runtime_pm_put(dev_priv);
2530
f69061be
DV		 2531 if (ret == 0) {
2532 /*
2533 * After all the gem state is reset, increment the reset
2534 * counter and wake up everyone waiting for the reset to
2535 * complete.
2536 *
2537 * Since unlock operations are a one-sided barrier only,
2538 * we need to insert a barrier here to order any seqno
2539 * updates before
2540 * the counter increment.
2541 */
4e857c58 2542 smp_mb__before_atomic();
f69061be
DV		 2543 atomic_inc(&dev_priv->gpu_error.reset_counter);
2544
5bdebb18 2545 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2546 KOBJ_CHANGE, reset_done_event);
1f83fee0 2547 } else {
805de8f4 2548 atomic_or(I915_WEDGED, &error->reset_counter);
f316a42c 2549 }
1f83fee0 2550
17e1df07
DV		 2551 /*
2552 * Note: The wake_up also serves as a memory barrier so that
2553 * waiters see the update value of the reset counter atomic_t.
2554 */
2555 i915_error_wake_up(dev_priv, true);
f316a42c 2556 }
8a905236
JB		 2557}
2558
35aed2e6 2559static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2560{
2561 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2562 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2563 u32 eir = I915_READ(EIR);
050ee91f 2564 int pipe, i;
8a905236 2565
35aed2e6
CW		 2566 if (!eir)
2567 return;
8a905236 2568
a70491cc 2569 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2570
bd9854f9
BW		 2571 i915_get_extra_instdone(dev, instdone);
2572
8a905236
JB		 2573 if (IS_G4X(dev)) {
2574 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2575 u32 ipeir = I915_READ(IPEIR_I965);
2576
a70491cc
JP		 2577 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2578 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2579 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2580 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2581 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2582 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2583 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2584 POSTING_READ(IPEIR_I965);
8a905236
JB		 2585 }
2586 if (eir & GM45_ERROR_PAGE_TABLE) {
2587 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2588 pr_err("page table error\n");
2589 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2590 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2591 POSTING_READ(PGTBL_ER);
8a905236
JB		 2592 }
2593 }
2594
a6c45cf0 2595 if (!IS_GEN2(dev)) {
8a905236
JB		 2596 if (eir & I915_ERROR_PAGE_TABLE) {
2597 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2598 pr_err("page table error\n");
2599 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2600 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2601 POSTING_READ(PGTBL_ER);
8a905236
JB		 2602 }
2603 }
2604
2605 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2606 pr_err("memory refresh error:\n");
055e393f 2607 for_each_pipe(dev_priv, pipe)
a70491cc 2608 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2609 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2610 /* pipestat has already been acked */
2611 }
2612 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2613 pr_err("instruction error\n");
2614 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2615 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2616 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2617 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2618 u32 ipeir = I915_READ(IPEIR);
2619
a70491cc
JP		 2620 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2621 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2622 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2623 I915_WRITE(IPEIR, ipeir);
3143a2bf 2624 POSTING_READ(IPEIR);
8a905236
JB		 2625 } else {
2626 u32 ipeir = I915_READ(IPEIR_I965);
2627
a70491cc
JP		 2628 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2629 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2630 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2631 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2632 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2633 POSTING_READ(IPEIR_I965);
8a905236
JB		 2634 }
2635 }
2636
2637 I915_WRITE(EIR, eir);
3143a2bf 2638 POSTING_READ(EIR);
8a905236
JB		 2639 eir = I915_READ(EIR);
2640 if (eir) {
2641 /*
2642 * some errors might have become stuck,
2643 * mask them.
2644 */
2645 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2646 I915_WRITE(EMR, I915_READ(EMR) | eir);
2647 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2648 }
35aed2e6
CW		 2649}
2650
2651/**
b8d24a06 2652 * i915_handle_error - handle a gpu error
35aed2e6 2653 * @dev: drm device
14b730fc 2654 * @engine_mask: mask representing engines that are hung
aafd8581 2655 * Do some basic checking of register state at error time and
35aed2e6
CW		 2656 * dump it to the syslog. Also call i915_capture_error_state() to make
2657 * sure we get a record and make it available in debugfs. Fire a uevent
2658 * so userspace knows something bad happened (should trigger collection
2659 * of a ring dump etc.).
2660 */
14b730fc 2661void i915_handle_error(struct drm_device *dev, u32 engine_mask,
58174462 2662 const char *fmt, ...)
35aed2e6
CW		 2663{
2664 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2665 va_list args;
2666 char error_msg[80];
35aed2e6 2667
58174462
MK		 2668 va_start(args, fmt);
2669 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2670 va_end(args);
2671
14b730fc 2672 i915_capture_error_state(dev, engine_mask, error_msg);
35aed2e6 2673 i915_report_and_clear_eir(dev);
8a905236 2674
14b730fc 2675 if (engine_mask) {
805de8f4 2676 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
f69061be 2677 &dev_priv->gpu_error.reset_counter);
ba1234d1 2678
11ed50ec 2679 /*
b8d24a06
MK		 2680 * Wakeup waiting processes so that the reset function
2681 * i915_reset_and_wakeup doesn't deadlock trying to grab
2682 * various locks. By bumping the reset counter first, the woken
17e1df07
DV		 2683 * processes will see a reset in progress and back off,
2684 * releasing their locks and then wait for the reset completion.
2685 * We must do this for _all_ gpu waiters that might hold locks
2686 * that the reset work needs to acquire.
2687 *
2688 * Note: The wake_up serves as the required memory barrier to
2689 * ensure that the waiters see the updated value of the reset
2690 * counter atomic_t.
11ed50ec 2691 */
17e1df07 2692 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2693 }
2694
b8d24a06 2695 i915_reset_and_wakeup(dev);
8a905236
JB		 2696}
2697
42f52ef8
KP		 2698/* Called from drm generic code, passed 'crtc' which
2699 * we use as a pipe index
2700 */
88e72717 2701static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
0a3e67a4 2702{
2d1013dd 2703 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2704 unsigned long irqflags;
71e0ffa5 2705
1ec14ad3 2706 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2707 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2708 i915_enable_pipestat(dev_priv, pipe,
755e9019 2709 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2710 else
7c463586 2711 i915_enable_pipestat(dev_priv, pipe,
755e9019 2712 PIPE_VBLANK_INTERRUPT_STATUS);
1ec14ad3 2713 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2714
0a3e67a4
JB		 2715 return 0;
2716}
2717
88e72717 2718static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
f796cf8f 2719{
2d1013dd 2720 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2721 unsigned long irqflags;
b518421f 2722 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2723 DE_PIPE_VBLANK(pipe);
f796cf8f 2724
f796cf8f 2725 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
fbdedaea 2726 ilk_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2727 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2728
2729 return 0;
2730}
2731
88e72717 2732static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
7e231dbe 2733{
2d1013dd 2734 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2735 unsigned long irqflags;
7e231dbe 2736
7e231dbe 2737 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2738 i915_enable_pipestat(dev_priv, pipe,
755e9019 2739 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2740 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2741
2742 return 0;
2743}
2744
88e72717 2745static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
abd58f01
BW		 2746{
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 unsigned long irqflags;
abd58f01 2749
abd58f01 2750 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
013d3752 2751 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
abd58f01 2752 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
013d3752 2753
abd58f01
BW		 2754 return 0;
2755}
2756
42f52ef8
KP		 2757/* Called from drm generic code, passed 'crtc' which
2758 * we use as a pipe index
2759 */
88e72717 2760static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
0a3e67a4 2761{
2d1013dd 2762 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2763 unsigned long irqflags;
0a3e67a4 2764
1ec14ad3 2765 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2766 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2767 PIPE_VBLANK_INTERRUPT_STATUS |
2768 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2769 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2770}
2771
88e72717 2772static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
f796cf8f 2773{
2d1013dd 2774 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2775 unsigned long irqflags;
b518421f 2776 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2777 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2778
2779 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
fbdedaea 2780 ilk_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2781 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2782}
2783
88e72717 2784static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
7e231dbe 2785{
2d1013dd 2786 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2787 unsigned long irqflags;
7e231dbe
JB		 2788
2789 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2790 i915_disable_pipestat(dev_priv, pipe,
755e9019 2791 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2792 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2793}
2794
88e72717 2795static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
abd58f01
BW		 2796{
2797 struct drm_i915_private *dev_priv = dev->dev_private;
2798 unsigned long irqflags;
abd58f01 2799
abd58f01 2800 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
013d3752 2801 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
abd58f01
BW		 2802 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2803}
2804
9107e9d2 2805static bool
0bc40be8 2806ring_idle(struct intel_engine_cs *engine, u32 seqno)
9107e9d2 2807{
0bc40be8
TU		 2808 return (list_empty(&engine->request_list) ||
2809 i915_seqno_passed(seqno, engine->last_submitted_seqno));
f65d9421
BG		 2810}
2811
a028c4b0
DV		 2812static bool
2813ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2814{
2815 if (INTEL_INFO(dev)->gen >= 8) {
a6cdb93a 2816 return (ipehr >> 23) == 0x1c;
a028c4b0
DV		 2817 } else {
2818 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2819 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2820 MI_SEMAPHORE_REGISTER);
2821 }
2822}
2823
a4872ba6 2824static struct intel_engine_cs *
0bc40be8
TU		 2825semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2826 u64 offset)
921d42ea 2827{
0bc40be8 2828 struct drm_i915_private *dev_priv = engine->dev->dev_private;
a4872ba6 2829 struct intel_engine_cs *signaller;
921d42ea
DV		 2830
2831 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
b4ac5afc 2832 for_each_engine(signaller, dev_priv) {
0bc40be8 2833 if (engine == signaller)
a6cdb93a
RV		 2834 continue;
2835
0bc40be8 2836 if (offset == signaller->semaphore.signal_ggtt[engine->id])
a6cdb93a
RV		 2837 return signaller;
2838 }
921d42ea
DV		 2839 } else {
2840 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2841
b4ac5afc 2842 for_each_engine(signaller, dev_priv) {
0bc40be8 2843 if(engine == signaller)
921d42ea
DV		 2844 continue;
2845
0bc40be8 2846 if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
921d42ea
DV		 2847 return signaller;
2848 }
2849 }
2850
a6cdb93a 2851 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
0bc40be8 2852 engine->id, ipehr, offset);
921d42ea
DV		 2853
2854 return NULL;
2855}
2856
a4872ba6 2857static struct intel_engine_cs *
0bc40be8 2858semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
a24a11e6 2859{
0bc40be8 2860 struct drm_i915_private *dev_priv = engine->dev->dev_private;
88fe429d 2861 u32 cmd, ipehr, head;
a6cdb93a
RV		 2862 u64 offset = 0;
2863 int i, backwards;
a24a11e6 2864
381e8ae3
TE		 2865 /*
2866 * This function does not support execlist mode - any attempt to
2867 * proceed further into this function will result in a kernel panic
2868 * when dereferencing ring->buffer, which is not set up in execlist
2869 * mode.
2870 *
2871 * The correct way of doing it would be to derive the currently
2872 * executing ring buffer from the current context, which is derived
2873 * from the currently running request. Unfortunately, to get the
2874 * current request we would have to grab the struct_mutex before doing
2875 * anything else, which would be ill-advised since some other thread
2876 * might have grabbed it already and managed to hang itself, causing
2877 * the hang checker to deadlock.
2878 *
2879 * Therefore, this function does not support execlist mode in its
2880 * current form. Just return NULL and move on.
2881 */
0bc40be8 2882 if (engine->buffer == NULL)
381e8ae3
TE		 2883 return NULL;
2884
0bc40be8
TU		 2885 ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2886 if (!ipehr_is_semaphore_wait(engine->dev, ipehr))
6274f212 2887 return NULL;
a24a11e6 2888
88fe429d
DV		 2889 /*
2890 * HEAD is likely pointing to the dword after the actual command,
2891 * so scan backwards until we find the MBOX. But limit it to just 3
a6cdb93a
RV		 2892 * or 4 dwords depending on the semaphore wait command size.
2893 * Note that we don't care about ACTHD here since that might
88fe429d
DV		 2894 * point at at batch, and semaphores are always emitted into the
2895 * ringbuffer itself.
a24a11e6 2896 */
0bc40be8
TU		 2897 head = I915_READ_HEAD(engine) & HEAD_ADDR;
2898 backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
88fe429d 2899
a6cdb93a 2900 for (i = backwards; i; --i) {
88fe429d
DV		 2901 /*
2902 * Be paranoid and presume the hw has gone off into the wild -
2903 * our ring is smaller than what the hardware (and hence
2904 * HEAD_ADDR) allows. Also handles wrap-around.
2905 */
0bc40be8 2906 head &= engine->buffer->size - 1;
88fe429d
DV		 2907
2908 /* This here seems to blow up */
0bc40be8 2909 cmd = ioread32(engine->buffer->virtual_start + head);
a24a11e6
CW		 2910 if (cmd == ipehr)
2911 break;
2912
88fe429d
DV		 2913 head -= 4;
2914 }
a24a11e6 2915
88fe429d
DV		 2916 if (!i)
2917 return NULL;
a24a11e6 2918
0bc40be8
TU		 2919 *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2920 if (INTEL_INFO(engine->dev)->gen >= 8) {
2921 offset = ioread32(engine->buffer->virtual_start + head + 12);
a6cdb93a 2922 offset <<= 32;
0bc40be8 2923 offset = ioread32(engine->buffer->virtual_start + head + 8);
a6cdb93a 2924 }
0bc40be8 2925 return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
a24a11e6
CW		 2926}
2927
0bc40be8 2928static int semaphore_passed(struct intel_engine_cs *engine)
6274f212 2929{
0bc40be8 2930 struct drm_i915_private *dev_priv = engine->dev->dev_private;
a4872ba6 2931 struct intel_engine_cs *signaller;
a0d036b0 2932 u32 seqno;
6274f212 2933
0bc40be8 2934 engine->hangcheck.deadlock++;
6274f212 2935
0bc40be8 2936 signaller = semaphore_waits_for(engine, &seqno);
4be17381
CW		 2937 if (signaller == NULL)
2938 return -1;
2939
2940 /* Prevent pathological recursion due to driver bugs */
666796da 2941 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
6274f212
CW		 2942 return -1;
2943
4be17381
CW		 2944 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2945 return 1;
2946
a0d036b0
CW		 2947 /* cursory check for an unkickable deadlock */
2948 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2949 semaphore_passed(signaller) < 0)
4be17381
CW		 2950 return -1;
2951
2952 return 0;
6274f212
CW		 2953}
2954
2955static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2956{
e2f80391 2957 struct intel_engine_cs *engine;
6274f212 2958
b4ac5afc 2959 for_each_engine(engine, dev_priv)
e2f80391 2960 engine->hangcheck.deadlock = 0;
6274f212
CW		 2961}
2962
0bc40be8 2963static bool subunits_stuck(struct intel_engine_cs *engine)
1ec14ad3 2964{
61642ff0
MK		 2965 u32 instdone[I915_NUM_INSTDONE_REG];
2966 bool stuck;
2967 int i;
2968
0bc40be8 2969 if (engine->id != RCS)
61642ff0
MK		 2970 return true;
2971
0bc40be8 2972 i915_get_extra_instdone(engine->dev, instdone);
9107e9d2 2973
61642ff0
MK		 2974 /* There might be unstable subunit states even when
2975 * actual head is not moving. Filter out the unstable ones by
2976 * accumulating the undone -> done transitions and only
2977 * consider those as progress.
2978 */
2979 stuck = true;
2980 for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
0bc40be8 2981 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
61642ff0 2982
0bc40be8 2983 if (tmp != engine->hangcheck.instdone[i])
61642ff0
MK		 2984 stuck = false;
2985
0bc40be8 2986 engine->hangcheck.instdone[i] |= tmp;
61642ff0
MK		 2987 }
2988
2989 return stuck;
2990}
2991
2992static enum intel_ring_hangcheck_action
0bc40be8 2993head_stuck(struct intel_engine_cs *engine, u64 acthd)
61642ff0 2994{
0bc40be8 2995 if (acthd != engine->hangcheck.acthd) {
61642ff0
MK		 2996
2997 /* Clear subunit states on head movement */
0bc40be8
TU		 2998 memset(engine->hangcheck.instdone, 0,
2999 sizeof(engine->hangcheck.instdone));
61642ff0 3000
24a65e62 3001 return HANGCHECK_ACTIVE;
f260fe7b 3002 }
6274f212 3003
0bc40be8 3004 if (!subunits_stuck(engine))
61642ff0
MK		 3005 return HANGCHECK_ACTIVE;
3006
3007 return HANGCHECK_HUNG;
3008}
3009
3010static enum intel_ring_hangcheck_action
0bc40be8 3011ring_stuck(struct intel_engine_cs *engine, u64 acthd)
61642ff0 3012{
0bc40be8 3013 struct drm_device *dev = engine->dev;
61642ff0
MK		 3014 struct drm_i915_private *dev_priv = dev->dev_private;
3015 enum intel_ring_hangcheck_action ha;
3016 u32 tmp;
3017
0bc40be8 3018 ha = head_stuck(engine, acthd);
61642ff0
MK		 3019 if (ha != HANGCHECK_HUNG)
3020 return ha;
3021
9107e9d2 3022 if (IS_GEN2(dev))
f2f4d82f 3023 return HANGCHECK_HUNG;
9107e9d2
CW		 3024
3025 /* Is the chip hanging on a WAIT_FOR_EVENT?
3026 * If so we can simply poke the RB_WAIT bit
3027 * and break the hang. This should work on
3028 * all but the second generation chipsets.
3029 */
0bc40be8 3030 tmp = I915_READ_CTL(engine);
1ec14ad3 3031 if (tmp & RING_WAIT) {
14b730fc 3032 i915_handle_error(dev, 0,
58174462 3033 "Kicking stuck wait on %s",
0bc40be8
TU		 3034 engine->name);
3035 I915_WRITE_CTL(engine, tmp);
f2f4d82f 3036 return HANGCHECK_KICK;
6274f212
CW		 3037 }
3038
3039 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
0bc40be8 3040 switch (semaphore_passed(engine)) {
6274f212 3041 default:
f2f4d82f 3042 return HANGCHECK_HUNG;
6274f212 3043 case 1:
14b730fc 3044 i915_handle_error(dev, 0,
58174462 3045 "Kicking stuck semaphore on %s",
0bc40be8
TU		 3046 engine->name);
3047 I915_WRITE_CTL(engine, tmp);
f2f4d82f 3048 return HANGCHECK_KICK;
6274f212 3049 case 0:
f2f4d82f 3050 return HANGCHECK_WAIT;
6274f212 3051 }
9107e9d2 3052 }
ed5cbb03 3053
f2f4d82f 3054 return HANGCHECK_HUNG;
ed5cbb03
MK		 3055}
3056
737b1506 3057/*
f65d9421 3058 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 3059 * batchbuffers in a long time. We keep track per ring seqno progress and
3060 * if there are no progress, hangcheck score for that ring is increased.
3061 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3062 * we kick the ring. If we see no progress on three subsequent calls
3063 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 3064 */
737b1506 3065static void i915_hangcheck_elapsed(struct work_struct *work)
f65d9421 3066{
737b1506
CW		 3067 struct drm_i915_private *dev_priv =
3068 container_of(work, typeof(*dev_priv),
3069 gpu_error.hangcheck_work.work);
3070 struct drm_device *dev = dev_priv->dev;
e2f80391 3071 struct intel_engine_cs *engine;
c3232b18 3072 enum intel_engine_id id;
05407ff8 3073 int busy_count = 0, rings_hung = 0;
666796da 3074 bool stuck[I915_NUM_ENGINES] = { 0 };
9107e9d2
CW		 3075#define BUSY 1
3076#define KICK 5
3077#define HUNG 20
24a65e62 3078#define ACTIVE_DECAY 15
893eead0 3079
d330a953 3080 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 3081 return;
3082
1f814dac
ID		 3083 /*
3084 * The hangcheck work is synced during runtime suspend, we don't
3085 * require a wakeref. TODO: instead of disabling the asserts make
3086 * sure that we hold a reference when this work is running.
3087 */
3088 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3089
75714940
MK		 3090 /* As enabling the GPU requires fairly extensive mmio access,
3091 * periodically arm the mmio checker to see if we are triggering
3092 * any invalid access.
3093 */
3094 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3095
c3232b18 3096 for_each_engine_id(engine, dev_priv, id) {
50877445
CW		 3097 u64 acthd;
3098 u32 seqno;
9107e9d2 3099 bool busy = true;
05407ff8 3100
6274f212
CW		 3101 semaphore_clear_deadlocks(dev_priv);
3102
e2f80391
TU		 3103 seqno = engine->get_seqno(engine, false);
3104 acthd = intel_ring_get_active_head(engine);
b4519513 3105
e2f80391
TU		 3106 if (engine->hangcheck.seqno == seqno) {
3107 if (ring_idle(engine, seqno)) {
3108 engine->hangcheck.action = HANGCHECK_IDLE;
da661464 3109
e2f80391 3110 if (waitqueue_active(&engine->irq_queue)) {
9107e9d2 3111 /* Issue a wake-up to catch stuck h/w. */
e2f80391 3112 if (!test_and_set_bit(engine->id, &dev_priv->gpu_error.missed_irq_rings)) {
666796da 3113 if (!(dev_priv->gpu_error.test_irq_rings & intel_engine_flag(engine)))
f4adcd24 3114 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
e2f80391 3115 engine->name);
f4adcd24
DV		 3116 else
3117 DRM_INFO("Fake missed irq on %s\n",
e2f80391
TU		 3118 engine->name);
3119 wake_up_all(&engine->irq_queue);
094f9a54
CW		 3120 }
3121 /* Safeguard against driver failure */
e2f80391 3122 engine->hangcheck.score += BUSY;
9107e9d2
CW		 3123 } else
3124 busy = false;
05407ff8 3125 } else {
6274f212
CW		 3126 /* We always increment the hangcheck score
3127 * if the ring is busy and still processing
3128 * the same request, so that no single request
3129 * can run indefinitely (such as a chain of
3130 * batches). The only time we do not increment
3131 * the hangcheck score on this ring, if this
3132 * ring is in a legitimate wait for another
3133 * ring. In that case the waiting ring is a
3134 * victim and we want to be sure we catch the
3135 * right culprit. Then every time we do kick
3136 * the ring, add a small increment to the
3137 * score so that we can catch a batch that is
3138 * being repeatedly kicked and so responsible
3139 * for stalling the machine.
3140 */
e2f80391
TU		 3141 engine->hangcheck.action = ring_stuck(engine,
3142 acthd);
ad8beaea 3143
e2f80391 3144 switch (engine->hangcheck.action) {
da661464 3145 case HANGCHECK_IDLE:
f2f4d82f 3146 case HANGCHECK_WAIT:
f260fe7b 3147 break;
24a65e62 3148 case HANGCHECK_ACTIVE:
e2f80391 3149 engine->hangcheck.score += BUSY;
6274f212 3150 break;
f2f4d82f 3151 case HANGCHECK_KICK:
e2f80391 3152 engine->hangcheck.score += KICK;
6274f212 3153 break;
f2f4d82f 3154 case HANGCHECK_HUNG:
e2f80391 3155 engine->hangcheck.score += HUNG;
c3232b18 3156 stuck[id] = true;
6274f212
CW		 3157 break;
3158 }
05407ff8 3159 }
9107e9d2 3160 } else {
e2f80391 3161 engine->hangcheck.action = HANGCHECK_ACTIVE;
da661464 3162
9107e9d2
CW		 3163 /* Gradually reduce the count so that we catch DoS
3164 * attempts across multiple batches.
3165 */
e2f80391
TU		 3166 if (engine->hangcheck.score > 0)
3167 engine->hangcheck.score -= ACTIVE_DECAY;
3168 if (engine->hangcheck.score < 0)
3169 engine->hangcheck.score = 0;
f260fe7b 3170
61642ff0 3171 /* Clear head and subunit states on seqno movement */
e2f80391 3172 engine->hangcheck.acthd = 0;
61642ff0 3173
e2f80391
TU		 3174 memset(engine->hangcheck.instdone, 0,
3175 sizeof(engine->hangcheck.instdone));
d1e61e7f
CW		 3176 }
3177
e2f80391
TU		 3178 engine->hangcheck.seqno = seqno;
3179 engine->hangcheck.acthd = acthd;
9107e9d2 3180 busy_count += busy;
893eead0 3181 }
b9201c14 3182
c3232b18 3183 for_each_engine_id(engine, dev_priv, id) {
e2f80391 3184 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d 3185 DRM_INFO("%s on %s\n",
c3232b18 3186 stuck[id] ? "stuck" : "no progress",
e2f80391 3187 engine->name);
14b730fc 3188 rings_hung |= intel_engine_flag(engine);
92cab734
MK		 3189 }
3190 }
3191
1f814dac 3192 if (rings_hung) {
14b730fc 3193 i915_handle_error(dev, rings_hung, "Engine(s) hung");
1f814dac
ID		 3194 goto out;
3195 }
f65d9421 3196
05407ff8
MK		 3197 if (busy_count)
3198 /* Reset timer case chip hangs without another request
3199 * being added */
10cd45b6 3200 i915_queue_hangcheck(dev);
1f814dac
ID		 3201
3202out:
3203 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
10cd45b6
MK		 3204}
3205
3206void i915_queue_hangcheck(struct drm_device *dev)
3207{
737b1506 3208 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
672e7b7c 3209
d330a953 3210 if (!i915.enable_hangcheck)
10cd45b6
MK		 3211 return;
3212
737b1506
CW		 3213 /* Don't continually defer the hangcheck so that it is always run at
3214 * least once after work has been scheduled on any ring. Otherwise,
3215 * we will ignore a hung ring if a second ring is kept busy.
3216 */
3217
3218 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3219 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 3220}
3221
1c69eb42 3222static void ibx_irq_reset(struct drm_device *dev)
91738a95
PZ		 3223{
3224 struct drm_i915_private *dev_priv = dev->dev_private;
3225
3226 if (HAS_PCH_NOP(dev))
3227 return;
3228
f86f3fb0 3229 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 3230
3231 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3232 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 3233}
105b122e 3234
622364b6
PZ		 3235/*
3236 * SDEIER is also touched by the interrupt handler to work around missed PCH
3237 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3238 * instead we unconditionally enable all PCH interrupt sources here, but then
3239 * only unmask them as needed with SDEIMR.
3240 *
3241 * This function needs to be called before interrupts are enabled.
3242 */
3243static void ibx_irq_pre_postinstall(struct drm_device *dev)
3244{
3245 struct drm_i915_private *dev_priv = dev->dev_private;
3246
3247 if (HAS_PCH_NOP(dev))
3248 return;
3249
3250 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 3251 I915_WRITE(SDEIER, 0xffffffff);
3252 POSTING_READ(SDEIER);
3253}
3254
7c4d664e 3255static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 3256{
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258
f86f3fb0 3259 GEN5_IRQ_RESET(GT);
a9d356a6 3260 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 3261 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 3262}
3263
1da177e4
LT		 3264/* drm_dma.h hooks
3265*/
be30b29f 3266static void ironlake_irq_reset(struct drm_device *dev)
036a4a7d 3267{
2d1013dd 3268 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d 3269
0c841212 3270 I915_WRITE(HWSTAM, 0xffffffff);
bdfcdb63 3271
f86f3fb0 3272 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 3273 if (IS_GEN7(dev))
3274 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 3275
7c4d664e 3276 gen5_gt_irq_reset(dev);
c650156a 3277
1c69eb42 3278 ibx_irq_reset(dev);
7d99163d 3279}
c650156a 3280
70591a41
VS		 3281static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3282{
3283 enum pipe pipe;
3284
0706f17c 3285 i915_hotplug_interrupt_update(dev_priv, 0xFFFFFFFF, 0);
70591a41
VS		 3286 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3287
3288 for_each_pipe(dev_priv, pipe)
3289 I915_WRITE(PIPESTAT(pipe), 0xffff);
3290
3291 GEN5_IRQ_RESET(VLV_);
3292}
3293
7e231dbe
JB		 3294static void valleyview_irq_preinstall(struct drm_device *dev)
3295{
2d1013dd 3296 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 3297
7e231dbe
JB		 3298 /* VLV magic */
3299 I915_WRITE(VLV_IMR, 0);
3300 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3301 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3302 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3303
7c4d664e 3304 gen5_gt_irq_reset(dev);
7e231dbe 3305
7c4cde39 3306 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
7e231dbe 3307
70591a41 3308 vlv_display_irq_reset(dev_priv);
7e231dbe
JB		 3309}
3310
d6e3cca3
DV		 3311static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3312{
3313 GEN8_IRQ_RESET_NDX(GT, 0);
3314 GEN8_IRQ_RESET_NDX(GT, 1);
3315 GEN8_IRQ_RESET_NDX(GT, 2);
3316 GEN8_IRQ_RESET_NDX(GT, 3);
3317}
3318
823f6b38 3319static void gen8_irq_reset(struct drm_device *dev)
abd58f01
BW		 3320{
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 int pipe;
3323
abd58f01
BW		 3324 I915_WRITE(GEN8_MASTER_IRQ, 0);
3325 POSTING_READ(GEN8_MASTER_IRQ);
3326
d6e3cca3 3327 gen8_gt_irq_reset(dev_priv);
abd58f01 3328
055e393f 3329 for_each_pipe(dev_priv, pipe)
f458ebbc
DV		 3330 if (intel_display_power_is_enabled(dev_priv,
3331 POWER_DOMAIN_PIPE(pipe)))
813bde43 3332 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 3333
f86f3fb0
PZ		 3334 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3335 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3336 GEN5_IRQ_RESET(GEN8_PCU_);
abd58f01 3337
266ea3d9
SS		 3338 if (HAS_PCH_SPLIT(dev))
3339 ibx_irq_reset(dev);
abd58f01 3340}
09f2344d 3341
4c6c03be
DL		 3342void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3343 unsigned int pipe_mask)
d49bdb0e 3344{
1180e206 3345 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
6831f3e3 3346 enum pipe pipe;
d49bdb0e 3347
13321786 3348 spin_lock_irq(&dev_priv->irq_lock);
6831f3e3
VS		 3349 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3350 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3351 dev_priv->de_irq_mask[pipe],
3352 ~dev_priv->de_irq_mask[pipe] | extra_ier);
13321786 3353 spin_unlock_irq(&dev_priv->irq_lock);
d49bdb0e
PZ		 3354}
3355
aae8ba84
VS		 3356void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3357 unsigned int pipe_mask)
3358{
6831f3e3
VS		 3359 enum pipe pipe;
3360
aae8ba84 3361 spin_lock_irq(&dev_priv->irq_lock);
6831f3e3
VS		 3362 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3363 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
aae8ba84
VS		 3364 spin_unlock_irq(&dev_priv->irq_lock);
3365
3366 /* make sure we're done processing display irqs */
3367 synchronize_irq(dev_priv->dev->irq);
3368}
3369
43f328d7
VS		 3370static void cherryview_irq_preinstall(struct drm_device *dev)
3371{
3372 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3373
3374 I915_WRITE(GEN8_MASTER_IRQ, 0);
3375 POSTING_READ(GEN8_MASTER_IRQ);
3376
d6e3cca3 3377 gen8_gt_irq_reset(dev_priv);
43f328d7
VS		 3378
3379 GEN5_IRQ_RESET(GEN8_PCU_);
3380
43f328d7
VS		 3381 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3382
70591a41 3383 vlv_display_irq_reset(dev_priv);
43f328d7
VS		 3384}
3385
87a02106
VS		 3386static u32 intel_hpd_enabled_irqs(struct drm_device *dev,
3387 const u32 hpd[HPD_NUM_PINS])
3388{
3389 struct drm_i915_private *dev_priv = to_i915(dev);
3390 struct intel_encoder *encoder;
3391 u32 enabled_irqs = 0;
3392
3393 for_each_intel_encoder(dev, encoder)
3394 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3395 enabled_irqs |= hpd[encoder->hpd_pin];
3396
3397 return enabled_irqs;
3398}
3399
82a28bcf 3400static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 3401{
2d1013dd 3402 struct drm_i915_private *dev_priv = dev->dev_private;
87a02106 3403 u32 hotplug_irqs, hotplug, enabled_irqs;
82a28bcf
DV		 3404
3405 if (HAS_PCH_IBX(dev)) {
fee884ed 3406 hotplug_irqs = SDE_HOTPLUG_MASK;
87a02106 3407 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ibx);
82a28bcf 3408 } else {
fee884ed 3409 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
87a02106 3410 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_cpt);
82a28bcf 3411 }
7fe0b973 3412
fee884ed 3413 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 3414
3415 /*
3416 * Enable digital hotplug on the PCH, and configure the DP short pulse
6dbf30ce
VS		 3417 * duration to 2ms (which is the minimum in the Display Port spec).
3418 * The pulse duration bits are reserved on LPT+.
82a28bcf 3419 */
7fe0b973
KP		 3420 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3421 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3422 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3423 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3424 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
0b2eb33e
VS		 3425 /*
3426 * When CPU and PCH are on the same package, port A
3427 * HPD must be enabled in both north and south.
3428 */
3429 if (HAS_PCH_LPT_LP(dev))
3430 hotplug |= PORTA_HOTPLUG_ENABLE;
7fe0b973 3431 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
6dbf30ce 3432}
26951caf 3433
6dbf30ce
VS		 3434static void spt_hpd_irq_setup(struct drm_device *dev)
3435{
3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437 u32 hotplug_irqs, hotplug, enabled_irqs;
3438
3439 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3440 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_spt);
3441
3442 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3443
3444 /* Enable digital hotplug on the PCH */
3445 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3446 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
74c0b395 3447 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
6dbf30ce
VS		 3448 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3449
3450 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3451 hotplug |= PORTE_HOTPLUG_ENABLE;
3452 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
7fe0b973
KP		 3453}
3454
e4ce95aa
VS		 3455static void ilk_hpd_irq_setup(struct drm_device *dev)
3456{
3457 struct drm_i915_private *dev_priv = dev->dev_private;
3458 u32 hotplug_irqs, hotplug, enabled_irqs;
3459
3a3b3c7d
VS		 3460 if (INTEL_INFO(dev)->gen >= 8) {
3461 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3462 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bdw);
3463
3464 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3465 } else if (INTEL_INFO(dev)->gen >= 7) {
23bb4cb5
VS		 3466 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3467 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ivb);
3a3b3c7d
VS		 3468
3469 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
23bb4cb5
VS		 3470 } else {
3471 hotplug_irqs = DE_DP_A_HOTPLUG;
3472 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_ilk);
e4ce95aa 3473
3a3b3c7d
VS		 3474 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3475 }
e4ce95aa
VS		 3476
3477 /*
3478 * Enable digital hotplug on the CPU, and configure the DP short pulse
3479 * duration to 2ms (which is the minimum in the Display Port spec)
23bb4cb5 3480 * The pulse duration bits are reserved on HSW+.
e4ce95aa
VS		 3481 */
3482 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3483 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3484 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3485 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3486
3487 ibx_hpd_irq_setup(dev);
3488}
3489
e0a20ad7
SS		 3490static void bxt_hpd_irq_setup(struct drm_device *dev)
3491{
3492 struct drm_i915_private *dev_priv = dev->dev_private;
a52bb15b 3493 u32 hotplug_irqs, hotplug, enabled_irqs;
e0a20ad7 3494
a52bb15b
VS		 3495 enabled_irqs = intel_hpd_enabled_irqs(dev, hpd_bxt);
3496 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
e0a20ad7 3497
a52bb15b 3498 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
e0a20ad7 3499
a52bb15b
VS		 3500 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3501 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3502 PORTA_HOTPLUG_ENABLE;
3503 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
e0a20ad7
SS		 3504}
3505
d46da437
PZ		 3506static void ibx_irq_postinstall(struct drm_device *dev)
3507{
2d1013dd 3508 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3509 u32 mask;
e5868a31 3510
692a04cf
DV		 3511 if (HAS_PCH_NOP(dev))
3512 return;
3513
105b122e 3514 if (HAS_PCH_IBX(dev))
5c673b60 3515 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3516 else
5c673b60 3517 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3518
b51a2842 3519 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
d46da437 3520 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3521}
3522
0a9a8c91
DV		 3523static void gen5_gt_irq_postinstall(struct drm_device *dev)
3524{
3525 struct drm_i915_private *dev_priv = dev->dev_private;
3526 u32 pm_irqs, gt_irqs;
3527
3528 pm_irqs = gt_irqs = 0;
3529
3530 dev_priv->gt_irq_mask = ~0;
040d2baa 3531 if (HAS_L3_DPF(dev)) {
0a9a8c91 3532 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3533 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3534 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3535 }
3536
3537 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3538 if (IS_GEN5(dev)) {
3539 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3540 ILK_BSD_USER_INTERRUPT;
3541 } else {
3542 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3543 }
3544
35079899 3545 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3546
3547 if (INTEL_INFO(dev)->gen >= 6) {
78e68d36
ID		 3548 /*
3549 * RPS interrupts will get enabled/disabled on demand when RPS
3550 * itself is enabled/disabled.
3551 */
0a9a8c91
DV		 3552 if (HAS_VEBOX(dev))
3553 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3554
605cd25b 3555 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3556 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3557 }
3558}
3559
f71d4af4 3560static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3561{
2d1013dd 3562 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3563 u32 display_mask, extra_mask;
3564
3565 if (INTEL_INFO(dev)->gen >= 7) {
3566 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3567 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3568 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3569 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3570 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
23bb4cb5
VS		 3571 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3572 DE_DP_A_HOTPLUG_IVB);
8e76f8dc
PZ		 3573 } else {
3574 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3575 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3576 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3577 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3578 DE_POISON);
e4ce95aa
VS		 3579 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3580 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3581 DE_DP_A_HOTPLUG);
8e76f8dc 3582 }
036a4a7d 3583
1ec14ad3 3584 dev_priv->irq_mask = ~display_mask;
036a4a7d 3585
0c841212
PZ		 3586 I915_WRITE(HWSTAM, 0xeffe);
3587
622364b6
PZ		 3588 ibx_irq_pre_postinstall(dev);
3589
35079899 3590 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3591
0a9a8c91 3592 gen5_gt_irq_postinstall(dev);
036a4a7d 3593
d46da437 3594 ibx_irq_postinstall(dev);
7fe0b973 3595
f97108d1 3596 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3597 /* Enable PCU event interrupts
3598 *
3599 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3600 * setup is guaranteed to run in single-threaded context. But we
3601 * need it to make the assert_spin_locked happy. */
d6207435 3602 spin_lock_irq(&dev_priv->irq_lock);
fbdedaea 3603 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
d6207435 3604 spin_unlock_irq(&dev_priv->irq_lock);
f97108d1
JB		 3605 }
3606
036a4a7d
ZW		 3607 return 0;
3608}
3609
f8b79e58
ID		 3610static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3611{
3612 u32 pipestat_mask;
3613 u32 iir_mask;
120dda4f 3614 enum pipe pipe;
f8b79e58
ID		 3615
3616 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3617 PIPE_FIFO_UNDERRUN_STATUS;
3618
120dda4f
VS		 3619 for_each_pipe(dev_priv, pipe)
3620 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3621 POSTING_READ(PIPESTAT(PIPE_A));
3622
3623 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3624 PIPE_CRC_DONE_INTERRUPT_STATUS;
3625
120dda4f
VS		 3626 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3627 for_each_pipe(dev_priv, pipe)
3628 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3629
3630 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3631 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3632 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3633 if (IS_CHERRYVIEW(dev_priv))
3634 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3635 dev_priv->irq_mask &= ~iir_mask;
3636
3637 I915_WRITE(VLV_IIR, iir_mask);
3638 I915_WRITE(VLV_IIR, iir_mask);
f8b79e58 3639 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
76e41860
VS		 3640 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3641 POSTING_READ(VLV_IMR);
f8b79e58
ID		 3642}
3643
3644static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3645{
3646 u32 pipestat_mask;
3647 u32 iir_mask;
120dda4f 3648 enum pipe pipe;
f8b79e58
ID		 3649
3650 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3651 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3652 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
120dda4f
VS		 3653 if (IS_CHERRYVIEW(dev_priv))
3654 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
f8b79e58
ID		 3655
3656 dev_priv->irq_mask |= iir_mask;
f8b79e58 3657 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
76e41860 3658 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
f8b79e58
ID		 3659 I915_WRITE(VLV_IIR, iir_mask);
3660 I915_WRITE(VLV_IIR, iir_mask);
3661 POSTING_READ(VLV_IIR);
3662
3663 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3664 PIPE_CRC_DONE_INTERRUPT_STATUS;
3665
120dda4f
VS		 3666 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3667 for_each_pipe(dev_priv, pipe)
3668 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
f8b79e58
ID		 3669
3670 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3671 PIPE_FIFO_UNDERRUN_STATUS;
120dda4f
VS		 3672
3673 for_each_pipe(dev_priv, pipe)
3674 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
f8b79e58
ID		 3675 POSTING_READ(PIPESTAT(PIPE_A));
3676}
3677
3678void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3679{
3680 assert_spin_locked(&dev_priv->irq_lock);
3681
3682 if (dev_priv->display_irqs_enabled)
3683 return;
3684
3685 dev_priv->display_irqs_enabled = true;
3686
950eabaf 3687 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3688 valleyview_display_irqs_install(dev_priv);
3689}
3690
3691void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3692{
3693 assert_spin_locked(&dev_priv->irq_lock);
3694
3695 if (!dev_priv->display_irqs_enabled)
3696 return;
3697
3698 dev_priv->display_irqs_enabled = false;
3699
950eabaf 3700 if (intel_irqs_enabled(dev_priv))
f8b79e58
ID		 3701 valleyview_display_irqs_uninstall(dev_priv);
3702}
3703
0e6c9a9e 3704static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
7e231dbe 3705{
f8b79e58 3706 dev_priv->irq_mask = ~0;
7e231dbe 3707
0706f17c 3708 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
20afbda2
DV		 3709 POSTING_READ(PORT_HOTPLUG_EN);
3710
7e231dbe 3711 I915_WRITE(VLV_IIR, 0xffffffff);
76e41860
VS		 3712 I915_WRITE(VLV_IIR, 0xffffffff);
3713 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3714 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3715 POSTING_READ(VLV_IMR);
7e231dbe 3716
b79480ba
DV		 3717 /* Interrupt setup is already guaranteed to be single-threaded, this is
3718 * just to make the assert_spin_locked check happy. */
d6207435 3719 spin_lock_irq(&dev_priv->irq_lock);
f8b79e58
ID		 3720 if (dev_priv->display_irqs_enabled)
3721 valleyview_display_irqs_install(dev_priv);
d6207435 3722 spin_unlock_irq(&dev_priv->irq_lock);
0e6c9a9e
VS		 3723}
3724
3725static int valleyview_irq_postinstall(struct drm_device *dev)
3726{
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728
3729 vlv_display_irq_postinstall(dev_priv);
7e231dbe 3730
0a9a8c91 3731 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3732
3733 /* ack & enable invalid PTE error interrupts */
3734#if 0 /* FIXME: add support to irq handler for checking these bits */
3735 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3736 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3737#endif
3738
3739 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3740
3741 return 0;
3742}
3743
abd58f01
BW		 3744static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3745{
abd58f01
BW		 3746 /* These are interrupts we'll toggle with the ring mask register */
3747 uint32_t gt_interrupts[] = {
3748 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
73d477f6 3749 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
abd58f01 3750 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
73d477f6
OM		 3751 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3752 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
abd58f01 3753 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
73d477f6
OM		 3754 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3755 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3756 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
abd58f01 3757 0,
73d477f6
OM		 3758 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3759 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
abd58f01
BW		 3760 };
3761
0961021a 3762 dev_priv->pm_irq_mask = 0xffffffff;
9a2d2d87
D		 3763 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3764 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
78e68d36
ID		 3765 /*
3766 * RPS interrupts will get enabled/disabled on demand when RPS itself
3767 * is enabled/disabled.
3768 */
3769 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
9a2d2d87 3770 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
abd58f01
BW		 3771}
3772
3773static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3774{
770de83d
DL		 3775 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3776 uint32_t de_pipe_enables;
3a3b3c7d
VS		 3777 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3778 u32 de_port_enables;
3779 enum pipe pipe;
770de83d 3780
b4834a50 3781 if (INTEL_INFO(dev_priv)->gen >= 9) {
770de83d
DL		 3782 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3783 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3a3b3c7d
VS		 3784 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3785 GEN9_AUX_CHANNEL_D;
9e63743e 3786 if (IS_BROXTON(dev_priv))
3a3b3c7d
VS		 3787 de_port_masked |= BXT_DE_PORT_GMBUS;
3788 } else {
770de83d
DL		 3789 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3790 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3a3b3c7d 3791 }
770de83d
DL		 3792
3793 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3794 GEN8_PIPE_FIFO_UNDERRUN;
3795
3a3b3c7d 3796 de_port_enables = de_port_masked;
a52bb15b
VS		 3797 if (IS_BROXTON(dev_priv))
3798 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3799 else if (IS_BROADWELL(dev_priv))
3a3b3c7d
VS		 3800 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3801
13b3a0a7
DV		 3802 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3803 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3804 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3805
055e393f 3806 for_each_pipe(dev_priv, pipe)
f458ebbc 3807 if (intel_display_power_is_enabled(dev_priv,
813bde43
PZ		 3808 POWER_DOMAIN_PIPE(pipe)))
3809 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3810 dev_priv->de_irq_mask[pipe],
3811 de_pipe_enables);
abd58f01 3812
3a3b3c7d 3813 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
abd58f01
BW		 3814}
3815
3816static int gen8_irq_postinstall(struct drm_device *dev)
3817{
3818 struct drm_i915_private *dev_priv = dev->dev_private;
3819
266ea3d9
SS		 3820 if (HAS_PCH_SPLIT(dev))
3821 ibx_irq_pre_postinstall(dev);
622364b6 3822
abd58f01
BW		 3823 gen8_gt_irq_postinstall(dev_priv);
3824 gen8_de_irq_postinstall(dev_priv);
3825
266ea3d9
SS		 3826 if (HAS_PCH_SPLIT(dev))
3827 ibx_irq_postinstall(dev);
abd58f01
BW		 3828
3829 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3830 POSTING_READ(GEN8_MASTER_IRQ);
3831
3832 return 0;
3833}
3834
43f328d7
VS		 3835static int cherryview_irq_postinstall(struct drm_device *dev)
3836{
3837 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7 3838
c2b66797 3839 vlv_display_irq_postinstall(dev_priv);
43f328d7
VS		 3840
3841 gen8_gt_irq_postinstall(dev_priv);
3842
3843 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3844 POSTING_READ(GEN8_MASTER_IRQ);
3845
3846 return 0;
3847}
3848
abd58f01
BW		 3849static void gen8_irq_uninstall(struct drm_device *dev)
3850{
3851 struct drm_i915_private *dev_priv = dev->dev_private;
abd58f01
BW		 3852
3853 if (!dev_priv)
3854 return;
3855
823f6b38 3856 gen8_irq_reset(dev);
abd58f01
BW		 3857}
3858
8ea0be4f
VS		 3859static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3860{
3861 /* Interrupt setup is already guaranteed to be single-threaded, this is
3862 * just to make the assert_spin_locked check happy. */
3863 spin_lock_irq(&dev_priv->irq_lock);
3864 if (dev_priv->display_irqs_enabled)
3865 valleyview_display_irqs_uninstall(dev_priv);
3866 spin_unlock_irq(&dev_priv->irq_lock);
3867
3868 vlv_display_irq_reset(dev_priv);
3869
c352d1ba 3870 dev_priv->irq_mask = ~0;
8ea0be4f
VS		 3871}
3872
7e231dbe
JB		 3873static void valleyview_irq_uninstall(struct drm_device *dev)
3874{
2d1013dd 3875 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 3876
3877 if (!dev_priv)
3878 return;
3879
843d0e7d
ID		 3880 I915_WRITE(VLV_MASTER_IER, 0);
3881
893fce8e
VS		 3882 gen5_gt_irq_reset(dev);
3883
7e231dbe 3884 I915_WRITE(HWSTAM, 0xffffffff);
f8b79e58 3885
8ea0be4f 3886 vlv_display_irq_uninstall(dev_priv);
7e231dbe
JB		 3887}
3888
43f328d7
VS		 3889static void cherryview_irq_uninstall(struct drm_device *dev)
3890{
3891 struct drm_i915_private *dev_priv = dev->dev_private;
43f328d7
VS		 3892
3893 if (!dev_priv)
3894 return;
3895
3896 I915_WRITE(GEN8_MASTER_IRQ, 0);
3897 POSTING_READ(GEN8_MASTER_IRQ);
3898
a2c30fba 3899 gen8_gt_irq_reset(dev_priv);
43f328d7 3900
a2c30fba 3901 GEN5_IRQ_RESET(GEN8_PCU_);
43f328d7 3902
c2b66797 3903 vlv_display_irq_uninstall(dev_priv);
43f328d7
VS		 3904}
3905
f71d4af4 3906static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3907{
2d1013dd 3908 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3909
3910 if (!dev_priv)
3911 return;
3912
be30b29f 3913 ironlake_irq_reset(dev);
036a4a7d
ZW		 3914}
3915
a266c7d5 3916static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3917{
2d1013dd 3918 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3919 int pipe;
91e3738e 3920
055e393f 3921 for_each_pipe(dev_priv, pipe)
9db4a9c7 3922 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3923 I915_WRITE16(IMR, 0xffff);
3924 I915_WRITE16(IER, 0x0);
3925 POSTING_READ16(IER);
c2798b19
CW		 3926}
3927
3928static int i8xx_irq_postinstall(struct drm_device *dev)
3929{
2d1013dd 3930 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19 3931
c2798b19
CW		 3932 I915_WRITE16(EMR,
3933 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3934
3935 /* Unmask the interrupts that we always want on. */
3936 dev_priv->irq_mask =
3937 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3938 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3939 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
37ef01ab 3940 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
c2798b19
CW		 3941 I915_WRITE16(IMR, dev_priv->irq_mask);
3942
3943 I915_WRITE16(IER,
3944 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3945 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
c2798b19
CW		 3946 I915_USER_INTERRUPT);
3947 POSTING_READ16(IER);
3948
379ef82d
DV		 3949 /* Interrupt setup is already guaranteed to be single-threaded, this is
3950 * just to make the assert_spin_locked check happy. */
d6207435 3951 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 3952 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3953 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 3954 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 3955
c2798b19
CW		 3956 return 0;
3957}
3958
90a72f87
VS		 3959/*
3960 * Returns true when a page flip has completed.
3961 */
3962static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3963 int plane, int pipe, u32 iir)
90a72f87 3964{
2d1013dd 3965 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3966 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87 3967
8d7849db 3968 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 3969 return false;
3970
3971 if ((iir & flip_pending) == 0)
d6bbafa1 3972 goto check_page_flip;
90a72f87 3973
90a72f87
VS		 3974 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3975 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3976 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3977 * the flip is completed (no longer pending). Since this doesn't raise
3978 * an interrupt per se, we watch for the change at vblank.
3979 */
3980 if (I915_READ16(ISR) & flip_pending)
d6bbafa1 3981 goto check_page_flip;
90a72f87 3982
7d47559e 3983 intel_prepare_page_flip(dev, plane);
90a72f87 3984 intel_finish_page_flip(dev, pipe);
90a72f87 3985 return true;
d6bbafa1
CW		 3986
3987check_page_flip:
3988 intel_check_page_flip(dev, pipe);
3989 return false;
90a72f87
VS		 3990}
3991
ff1f525e 3992static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19 3993{
45a83f84 3994 struct drm_device *dev = arg;
2d1013dd 3995 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3996 u16 iir, new_iir;
3997 u32 pipe_stats[2];
c2798b19
CW		 3998 int pipe;
3999 u16 flip_mask =
4000 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4001 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
1f814dac 4002 irqreturn_t ret;
c2798b19 4003
2dd2a883
ID		 4004 if (!intel_irqs_enabled(dev_priv))
4005 return IRQ_NONE;
4006
1f814dac
ID		 4007 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4008 disable_rpm_wakeref_asserts(dev_priv);
4009
4010 ret = IRQ_NONE;
c2798b19
CW		 4011 iir = I915_READ16(IIR);
4012 if (iir == 0)
1f814dac 4013 goto out;
c2798b19
CW		 4014
4015 while (iir & ~flip_mask) {
4016 /* Can't rely on pipestat interrupt bit in iir as it might
4017 * have been cleared after the pipestat interrupt was received.
4018 * It doesn't set the bit in iir again, but it still produces
4019 * interrupts (for non-MSI).
4020 */
222c7f51 4021 spin_lock(&dev_priv->irq_lock);
c2798b19 4022 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 4023 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
c2798b19 4024
055e393f 4025 for_each_pipe(dev_priv, pipe) {
f0f59a00 4026 i915_reg_t reg = PIPESTAT(pipe);
c2798b19
CW		 4027 pipe_stats[pipe] = I915_READ(reg);
4028
4029 /*
4030 * Clear the PIPE*STAT regs before the IIR
4031 */
2d9d2b0b 4032 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 4033 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19 4034 }
222c7f51 4035 spin_unlock(&dev_priv->irq_lock);
c2798b19
CW		 4036
4037 I915_WRITE16(IIR, iir & ~flip_mask);
4038 new_iir = I915_READ16(IIR); /* Flush posted writes */
4039
c2798b19 4040 if (iir & I915_USER_INTERRUPT)
4a570db5 4041 notify_ring(&dev_priv->engine[RCS]);
c2798b19 4042
055e393f 4043 for_each_pipe(dev_priv, pipe) {
1f1c2e24 4044 int plane = pipe;
3a77c4c4 4045 if (HAS_FBC(dev))
1f1c2e24
VS		 4046 plane = !plane;
4047
4356d586 4048 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 4049 i8xx_handle_vblank(dev, plane, pipe, iir))
4050 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 4051
4356d586 4052 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4053 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 4054
1f7247c0
DV		 4055 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4056 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4057 pipe);
4356d586 4058 }
c2798b19
CW		 4059
4060 iir = new_iir;
4061 }
1f814dac
ID		 4062 ret = IRQ_HANDLED;
4063
4064out:
4065 enable_rpm_wakeref_asserts(dev_priv);
c2798b19 4066
1f814dac 4067 return ret;
c2798b19
CW		 4068}
4069
4070static void i8xx_irq_uninstall(struct drm_device * dev)
4071{
2d1013dd 4072 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 4073 int pipe;
4074
055e393f 4075 for_each_pipe(dev_priv, pipe) {
c2798b19
CW		 4076 /* Clear enable bits; then clear status bits */
4077 I915_WRITE(PIPESTAT(pipe), 0);
4078 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4079 }
4080 I915_WRITE16(IMR, 0xffff);
4081 I915_WRITE16(IER, 0x0);
4082 I915_WRITE16(IIR, I915_READ16(IIR));
4083}
4084
a266c7d5
CW		 4085static void i915_irq_preinstall(struct drm_device * dev)
4086{
2d1013dd 4087 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4088 int pipe;
4089
a266c7d5 4090 if (I915_HAS_HOTPLUG(dev)) {
0706f17c 4091 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
a266c7d5
CW		 4092 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4093 }
4094
00d98ebd 4095 I915_WRITE16(HWSTAM, 0xeffe);
055e393f 4096 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4097 I915_WRITE(PIPESTAT(pipe), 0);
4098 I915_WRITE(IMR, 0xffffffff);
4099 I915_WRITE(IER, 0x0);
4100 POSTING_READ(IER);
4101}
4102
4103static int i915_irq_postinstall(struct drm_device *dev)
4104{
2d1013dd 4105 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 4106 u32 enable_mask;
a266c7d5 4107
38bde180
CW		 4108 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4109
4110 /* Unmask the interrupts that we always want on. */
4111 dev_priv->irq_mask =
4112 ~(I915_ASLE_INTERRUPT |
4113 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4114 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4115 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
37ef01ab 4116 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
38bde180
CW		 4117
4118 enable_mask =
4119 I915_ASLE_INTERRUPT |
4120 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4121 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
38bde180
CW		 4122 I915_USER_INTERRUPT;
4123
a266c7d5 4124 if (I915_HAS_HOTPLUG(dev)) {
0706f17c 4125 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
20afbda2
DV		 4126 POSTING_READ(PORT_HOTPLUG_EN);
4127
a266c7d5
CW		 4128 /* Enable in IER... */
4129 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4130 /* and unmask in IMR */
4131 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4132 }
4133
a266c7d5
CW		 4134 I915_WRITE(IMR, dev_priv->irq_mask);
4135 I915_WRITE(IER, enable_mask);
4136 POSTING_READ(IER);
4137
f49e38dd 4138 i915_enable_asle_pipestat(dev);
20afbda2 4139
379ef82d
DV		 4140 /* Interrupt setup is already guaranteed to be single-threaded, this is
4141 * just to make the assert_spin_locked check happy. */
d6207435 4142 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 4143 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4144 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 4145 spin_unlock_irq(&dev_priv->irq_lock);
379ef82d 4146
20afbda2
DV		 4147 return 0;
4148}
4149
90a72f87
VS		 4150/*
4151 * Returns true when a page flip has completed.
4152 */
4153static bool i915_handle_vblank(struct drm_device *dev,
4154 int plane, int pipe, u32 iir)
4155{
2d1013dd 4156 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 4157 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4158
8d7849db 4159 if (!intel_pipe_handle_vblank(dev, pipe))
90a72f87
VS		 4160 return false;
4161
4162 if ((iir & flip_pending) == 0)
d6bbafa1 4163 goto check_page_flip;
90a72f87 4164
90a72f87
VS		 4165 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4166 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4167 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4168 * the flip is completed (no longer pending). Since this doesn't raise
4169 * an interrupt per se, we watch for the change at vblank.
4170 */
4171 if (I915_READ(ISR) & flip_pending)
d6bbafa1 4172 goto check_page_flip;
90a72f87 4173
7d47559e 4174 intel_prepare_page_flip(dev, plane);
90a72f87 4175 intel_finish_page_flip(dev, pipe);
90a72f87 4176 return true;
d6bbafa1
CW		 4177
4178check_page_flip:
4179 intel_check_page_flip(dev, pipe);
4180 return false;
90a72f87
VS		 4181}
4182
ff1f525e 4183static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5 4184{
45a83f84 4185 struct drm_device *dev = arg;
2d1013dd 4186 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 4187 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
38bde180
CW		 4188 u32 flip_mask =
4189 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4190 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 4191 int pipe, ret = IRQ_NONE;
a266c7d5 4192
2dd2a883
ID		 4193 if (!intel_irqs_enabled(dev_priv))
4194 return IRQ_NONE;
4195
1f814dac
ID		 4196 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4197 disable_rpm_wakeref_asserts(dev_priv);
4198
a266c7d5 4199 iir = I915_READ(IIR);
38bde180
CW		 4200 do {
4201 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 4202 bool blc_event = false;
a266c7d5
CW		 4203
4204 /* Can't rely on pipestat interrupt bit in iir as it might
4205 * have been cleared after the pipestat interrupt was received.
4206 * It doesn't set the bit in iir again, but it still produces
4207 * interrupts (for non-MSI).
4208 */
222c7f51 4209 spin_lock(&dev_priv->irq_lock);
a266c7d5 4210 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 4211 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 4212
055e393f 4213 for_each_pipe(dev_priv, pipe) {
f0f59a00 4214 i915_reg_t reg = PIPESTAT(pipe);
a266c7d5
CW		 4215 pipe_stats[pipe] = I915_READ(reg);
4216
38bde180 4217 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 4218 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4219 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 4220 irq_received = true;
a266c7d5
CW		 4221 }
4222 }
222c7f51 4223 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 4224
4225 if (!irq_received)
4226 break;
4227
a266c7d5 4228 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4229 if (I915_HAS_HOTPLUG(dev) &&
4230 iir & I915_DISPLAY_PORT_INTERRUPT)
4231 i9xx_hpd_irq_handler(dev);
a266c7d5 4232
38bde180 4233 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4234 new_iir = I915_READ(IIR); /* Flush posted writes */
4235
a266c7d5 4236 if (iir & I915_USER_INTERRUPT)
4a570db5 4237 notify_ring(&dev_priv->engine[RCS]);
a266c7d5 4238
055e393f 4239 for_each_pipe(dev_priv, pipe) {
38bde180 4240 int plane = pipe;
3a77c4c4 4241 if (HAS_FBC(dev))
38bde180 4242 plane = !plane;
90a72f87 4243
8291ee90 4244 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4245 i915_handle_vblank(dev, plane, pipe, iir))
4246 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 4247
4248 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4249 blc_event = true;
4356d586
DV		 4250
4251 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4252 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b 4253
1f7247c0
DV		 4254 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4255 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4256 pipe);
a266c7d5
CW		 4257 }
4258
a266c7d5
CW		 4259 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4260 intel_opregion_asle_intr(dev);
4261
4262 /* With MSI, interrupts are only generated when iir
4263 * transitions from zero to nonzero. If another bit got
4264 * set while we were handling the existing iir bits, then
4265 * we would never get another interrupt.
4266 *
4267 * This is fine on non-MSI as well, as if we hit this path
4268 * we avoid exiting the interrupt handler only to generate
4269 * another one.
4270 *
4271 * Note that for MSI this could cause a stray interrupt report
4272 * if an interrupt landed in the time between writing IIR and
4273 * the posting read. This should be rare enough to never
4274 * trigger the 99% of 100,000 interrupts test for disabling
4275 * stray interrupts.
4276 */
38bde180 4277 ret = IRQ_HANDLED;
a266c7d5 4278 iir = new_iir;
38bde180 4279 } while (iir & ~flip_mask);
a266c7d5 4280
1f814dac
ID		 4281 enable_rpm_wakeref_asserts(dev_priv);
4282
a266c7d5
CW		 4283 return ret;
4284}
4285
4286static void i915_irq_uninstall(struct drm_device * dev)
4287{
2d1013dd 4288 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4289 int pipe;
4290
a266c7d5 4291 if (I915_HAS_HOTPLUG(dev)) {
0706f17c 4292 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
a266c7d5
CW		 4293 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4294 }
4295
00d98ebd 4296 I915_WRITE16(HWSTAM, 0xffff);
055e393f 4297 for_each_pipe(dev_priv, pipe) {
55b39755 4298 /* Clear enable bits; then clear status bits */
a266c7d5 4299 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 4300 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4301 }
a266c7d5
CW		 4302 I915_WRITE(IMR, 0xffffffff);
4303 I915_WRITE(IER, 0x0);
4304
a266c7d5
CW		 4305 I915_WRITE(IIR, I915_READ(IIR));
4306}
4307
4308static void i965_irq_preinstall(struct drm_device * dev)
4309{
2d1013dd 4310 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4311 int pipe;
4312
0706f17c 4313 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
adca4730 4314 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4315
4316 I915_WRITE(HWSTAM, 0xeffe);
055e393f 4317 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4318 I915_WRITE(PIPESTAT(pipe), 0);
4319 I915_WRITE(IMR, 0xffffffff);
4320 I915_WRITE(IER, 0x0);
4321 POSTING_READ(IER);
4322}
4323
4324static int i965_irq_postinstall(struct drm_device *dev)
4325{
2d1013dd 4326 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 4327 u32 enable_mask;
a266c7d5
CW		 4328 u32 error_mask;
4329
a266c7d5 4330 /* Unmask the interrupts that we always want on. */
bbba0a97 4331 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 4332 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 4333 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4334 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4335 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4336 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4337 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4338
4339 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 4340 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4341 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 4342 enable_mask |= I915_USER_INTERRUPT;
4343
4344 if (IS_G4X(dev))
4345 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 4346
b79480ba
DV		 4347 /* Interrupt setup is already guaranteed to be single-threaded, this is
4348 * just to make the assert_spin_locked check happy. */
d6207435 4349 spin_lock_irq(&dev_priv->irq_lock);
755e9019
ID		 4350 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4351 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4352 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
d6207435 4353 spin_unlock_irq(&dev_priv->irq_lock);
a266c7d5 4354
a266c7d5
CW		 4355 /*
4356 * Enable some error detection, note the instruction error mask
4357 * bit is reserved, so we leave it masked.
4358 */
4359 if (IS_G4X(dev)) {
4360 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4361 GM45_ERROR_MEM_PRIV |
4362 GM45_ERROR_CP_PRIV |
4363 I915_ERROR_MEMORY_REFRESH);
4364 } else {
4365 error_mask = ~(I915_ERROR_PAGE_TABLE |
4366 I915_ERROR_MEMORY_REFRESH);
4367 }
4368 I915_WRITE(EMR, error_mask);
4369
4370 I915_WRITE(IMR, dev_priv->irq_mask);
4371 I915_WRITE(IER, enable_mask);
4372 POSTING_READ(IER);
4373
0706f17c 4374 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
20afbda2
DV		 4375 POSTING_READ(PORT_HOTPLUG_EN);
4376
f49e38dd 4377 i915_enable_asle_pipestat(dev);
20afbda2
DV		 4378
4379 return 0;
4380}
4381
bac56d5b 4382static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 4383{
2d1013dd 4384 struct drm_i915_private *dev_priv = dev->dev_private;
20afbda2
DV		 4385 u32 hotplug_en;
4386
b5ea2d56
DV		 4387 assert_spin_locked(&dev_priv->irq_lock);
4388
778eb334
VS		 4389 /* Note HDMI and DP share hotplug bits */
4390 /* enable bits are the same for all generations */
0706f17c 4391 hotplug_en = intel_hpd_enabled_irqs(dev, hpd_mask_i915);
778eb334
VS		 4392 /* Programming the CRT detection parameters tends
4393 to generate a spurious hotplug event about three
4394 seconds later. So just do it once.
4395 */
4396 if (IS_G4X(dev))
4397 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
778eb334
VS		 4398 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4399
4400 /* Ignore TV since it's buggy */
0706f17c 4401 i915_hotplug_interrupt_update_locked(dev_priv,
f9e3dc78
JN		 4402 HOTPLUG_INT_EN_MASK |
4403 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4404 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4405 hotplug_en);
a266c7d5
CW		 4406}
4407
ff1f525e 4408static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5 4409{
45a83f84 4410 struct drm_device *dev = arg;
2d1013dd 4411 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4412 u32 iir, new_iir;
4413 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 4414 int ret = IRQ_NONE, pipe;
21ad8330
VS		 4415 u32 flip_mask =
4416 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4417 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 4418
2dd2a883
ID		 4419 if (!intel_irqs_enabled(dev_priv))
4420 return IRQ_NONE;
4421
1f814dac
ID		 4422 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4423 disable_rpm_wakeref_asserts(dev_priv);
4424
a266c7d5
CW		 4425 iir = I915_READ(IIR);
4426
a266c7d5 4427 for (;;) {
501e01d7 4428 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 4429 bool blc_event = false;
4430
a266c7d5
CW		 4431 /* Can't rely on pipestat interrupt bit in iir as it might
4432 * have been cleared after the pipestat interrupt was received.
4433 * It doesn't set the bit in iir again, but it still produces
4434 * interrupts (for non-MSI).
4435 */
222c7f51 4436 spin_lock(&dev_priv->irq_lock);
a266c7d5 4437 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
aaecdf61 4438 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
a266c7d5 4439
055e393f 4440 for_each_pipe(dev_priv, pipe) {
f0f59a00 4441 i915_reg_t reg = PIPESTAT(pipe);
a266c7d5
CW		 4442 pipe_stats[pipe] = I915_READ(reg);
4443
4444 /*
4445 * Clear the PIPE*STAT regs before the IIR
4446 */
4447 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 4448 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 4449 irq_received = true;
a266c7d5
CW		 4450 }
4451 }
222c7f51 4452 spin_unlock(&dev_priv->irq_lock);
a266c7d5
CW		 4453
4454 if (!irq_received)
4455 break;
4456
4457 ret = IRQ_HANDLED;
4458
4459 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 4460 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4461 i9xx_hpd_irq_handler(dev);
a266c7d5 4462
21ad8330 4463 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 4464 new_iir = I915_READ(IIR); /* Flush posted writes */
4465
a266c7d5 4466 if (iir & I915_USER_INTERRUPT)
4a570db5 4467 notify_ring(&dev_priv->engine[RCS]);
a266c7d5 4468 if (iir & I915_BSD_USER_INTERRUPT)
4a570db5 4469 notify_ring(&dev_priv->engine[VCS]);
a266c7d5 4470
055e393f 4471 for_each_pipe(dev_priv, pipe) {
2c8ba29f 4472 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 4473 i915_handle_vblank(dev, pipe, pipe, iir))
4474 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 4475
4476 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4477 blc_event = true;
4356d586
DV		 4478
4479 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 4480 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 4481
1f7247c0
DV		 4482 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4483 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2d9d2b0b 4484 }
a266c7d5
CW		 4485
4486 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4487 intel_opregion_asle_intr(dev);
4488
515ac2bb
DV		 4489 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4490 gmbus_irq_handler(dev);
4491
a266c7d5
CW		 4492 /* With MSI, interrupts are only generated when iir
4493 * transitions from zero to nonzero. If another bit got
4494 * set while we were handling the existing iir bits, then
4495 * we would never get another interrupt.
4496 *
4497 * This is fine on non-MSI as well, as if we hit this path
4498 * we avoid exiting the interrupt handler only to generate
4499 * another one.
4500 *
4501 * Note that for MSI this could cause a stray interrupt report
4502 * if an interrupt landed in the time between writing IIR and
4503 * the posting read. This should be rare enough to never
4504 * trigger the 99% of 100,000 interrupts test for disabling
4505 * stray interrupts.
4506 */
4507 iir = new_iir;
4508 }
4509
1f814dac
ID		 4510 enable_rpm_wakeref_asserts(dev_priv);
4511
a266c7d5
CW		 4512 return ret;
4513}
4514
4515static void i965_irq_uninstall(struct drm_device * dev)
4516{
2d1013dd 4517 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 4518 int pipe;
4519
4520 if (!dev_priv)
4521 return;
4522
0706f17c 4523 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
adca4730 4524 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 4525
4526 I915_WRITE(HWSTAM, 0xffffffff);
055e393f 4527 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4528 I915_WRITE(PIPESTAT(pipe), 0);
4529 I915_WRITE(IMR, 0xffffffff);
4530 I915_WRITE(IER, 0x0);
4531
055e393f 4532 for_each_pipe(dev_priv, pipe)
a266c7d5
CW		 4533 I915_WRITE(PIPESTAT(pipe),
4534 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4535 I915_WRITE(IIR, I915_READ(IIR));
4536}
4537
fca52a55
DV		 4538/**
4539 * intel_irq_init - initializes irq support
4540 * @dev_priv: i915 device instance
4541 *
4542 * This function initializes all the irq support including work items, timers
4543 * and all the vtables. It does not setup the interrupt itself though.
4544 */
b963291c 4545void intel_irq_init(struct drm_i915_private *dev_priv)
f71d4af4 4546{
b963291c 4547 struct drm_device *dev = dev_priv->dev;
8b2e326d 4548
77913b39
JN		 4549 intel_hpd_init_work(dev_priv);
4550
c6a828d3 4551 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4552 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4553
a6706b45 4554 /* Let's track the enabled rps events */
666a4537 4555 if (IS_VALLEYVIEW(dev_priv))
6c65a587 4556 /* WaGsvRC0ResidencyMethod:vlv */
6f4b12f8 4557 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
31685c25
D		 4558 else
4559 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
a6706b45 4560
737b1506
CW		 4561 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4562 i915_hangcheck_elapsed);
61bac78e 4563
b963291c 4564 if (IS_GEN2(dev_priv)) {
4cdb83ec
VS		 4565 dev->max_vblank_count = 0;
4566 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
b963291c 4567 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
f71d4af4 4568 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
fd8f507c 4569 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
391f75e2
VS		 4570 } else {
4571 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4572 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4573 }
4574
21da2700
VS		 4575 /*
4576 * Opt out of the vblank disable timer on everything except gen2.
4577 * Gen2 doesn't have a hardware frame counter and so depends on
4578 * vblank interrupts to produce sane vblank seuquence numbers.
4579 */
b963291c 4580 if (!IS_GEN2(dev_priv))
21da2700
VS		 4581 dev->vblank_disable_immediate = true;
4582
f3a5c3f6
DV		 4583 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4584 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
f71d4af4 4585
b963291c 4586 if (IS_CHERRYVIEW(dev_priv)) {
43f328d7
VS		 4587 dev->driver->irq_handler = cherryview_irq_handler;
4588 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4589 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4590 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4591 dev->driver->enable_vblank = valleyview_enable_vblank;
4592 dev->driver->disable_vblank = valleyview_disable_vblank;
4593 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4594 } else if (IS_VALLEYVIEW(dev_priv)) {
7e231dbe
JB		 4595 dev->driver->irq_handler = valleyview_irq_handler;
4596 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4597 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4598 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4599 dev->driver->enable_vblank = valleyview_enable_vblank;
4600 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4601 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
b963291c 4602 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
abd58f01 4603 dev->driver->irq_handler = gen8_irq_handler;
723761b8 4604 dev->driver->irq_preinstall = gen8_irq_reset;
abd58f01
BW		 4605 dev->driver->irq_postinstall = gen8_irq_postinstall;
4606 dev->driver->irq_uninstall = gen8_irq_uninstall;
4607 dev->driver->enable_vblank = gen8_enable_vblank;
4608 dev->driver->disable_vblank = gen8_disable_vblank;
6dbf30ce 4609 if (IS_BROXTON(dev))
e0a20ad7 4610 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
6dbf30ce
VS		 4611 else if (HAS_PCH_SPT(dev))
4612 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4613 else
3a3b3c7d 4614 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
f71d4af4
JB		 4615 } else if (HAS_PCH_SPLIT(dev)) {
4616 dev->driver->irq_handler = ironlake_irq_handler;
723761b8 4617 dev->driver->irq_preinstall = ironlake_irq_reset;
f71d4af4
JB		 4618 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4619 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4620 dev->driver->enable_vblank = ironlake_enable_vblank;
4621 dev->driver->disable_vblank = ironlake_disable_vblank;
23bb4cb5 4622 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
f71d4af4 4623 } else {
b963291c 4624 if (INTEL_INFO(dev_priv)->gen == 2) {
c2798b19
CW		 4625 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4626 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4627 dev->driver->irq_handler = i8xx_irq_handler;
4628 dev->driver->irq_uninstall = i8xx_irq_uninstall;
b963291c 4629 } else if (INTEL_INFO(dev_priv)->gen == 3) {
a266c7d5
CW		 4630 dev->driver->irq_preinstall = i915_irq_preinstall;
4631 dev->driver->irq_postinstall = i915_irq_postinstall;
4632 dev->driver->irq_uninstall = i915_irq_uninstall;
4633 dev->driver->irq_handler = i915_irq_handler;
c2798b19 4634 } else {
a266c7d5
CW		 4635 dev->driver->irq_preinstall = i965_irq_preinstall;
4636 dev->driver->irq_postinstall = i965_irq_postinstall;
4637 dev->driver->irq_uninstall = i965_irq_uninstall;
4638 dev->driver->irq_handler = i965_irq_handler;
c2798b19 4639 }
778eb334
VS		 4640 if (I915_HAS_HOTPLUG(dev_priv))
4641 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
f71d4af4
JB		 4642 dev->driver->enable_vblank = i915_enable_vblank;
4643 dev->driver->disable_vblank = i915_disable_vblank;
4644 }
4645}
20afbda2 4646
fca52a55
DV		 4647/**
4648 * intel_irq_install - enables the hardware interrupt
4649 * @dev_priv: i915 device instance
4650 *
4651 * This function enables the hardware interrupt handling, but leaves the hotplug
4652 * handling still disabled. It is called after intel_irq_init().
4653 *
4654 * In the driver load and resume code we need working interrupts in a few places
4655 * but don't want to deal with the hassle of concurrent probe and hotplug
4656 * workers. Hence the split into this two-stage approach.
4657 */
2aeb7d3a
DV		 4658int intel_irq_install(struct drm_i915_private *dev_priv)
4659{
4660 /*
4661 * We enable some interrupt sources in our postinstall hooks, so mark
4662 * interrupts as enabled _before_ actually enabling them to avoid
4663 * special cases in our ordering checks.
4664 */
4665 dev_priv->pm.irqs_enabled = true;
4666
4667 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4668}
4669
fca52a55
DV		 4670/**
4671 * intel_irq_uninstall - finilizes all irq handling
4672 * @dev_priv: i915 device instance
4673 *
4674 * This stops interrupt and hotplug handling and unregisters and frees all
4675 * resources acquired in the init functions.
4676 */
2aeb7d3a
DV		 4677void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4678{
4679 drm_irq_uninstall(dev_priv->dev);
4680 intel_hpd_cancel_work(dev_priv);
4681 dev_priv->pm.irqs_enabled = false;
4682}
4683
fca52a55
DV		 4684/**
4685 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4686 * @dev_priv: i915 device instance
4687 *
4688 * This function is used to disable interrupts at runtime, both in the runtime
4689 * pm and the system suspend/resume code.
4690 */
b963291c 4691void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4692{
b963291c 4693 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
2aeb7d3a 4694 dev_priv->pm.irqs_enabled = false;
2dd2a883 4695 synchronize_irq(dev_priv->dev->irq);
c67a470b
PZ		 4696}
4697
fca52a55
DV		 4698/**
4699 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4700 * @dev_priv: i915 device instance
4701 *
4702 * This function is used to enable interrupts at runtime, both in the runtime
4703 * pm and the system suspend/resume code.
4704 */
b963291c 4705void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
c67a470b 4706{
2aeb7d3a 4707 dev_priv->pm.irqs_enabled = true;
b963291c
DV		 4708 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4709 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
c67a470b 4710}
Linux kernel - Deliverables
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