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drm/i915: rename some HDMI bit definitions
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
46c06a30
VS		 63 u32 reg = PIPESTAT(pipe);
64 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 65
46c06a30
VS		 66 if ((pipestat & mask) == mask)
67 return;
68
69 /* Enable the interrupt, clear any pending status */
70 pipestat |= mask | (mask >> 16);
71 I915_WRITE(reg, pipestat);
72 POSTING_READ(reg);
7c463586
KP		 73}
74
75void
76i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
77{
46c06a30
VS		 78 u32 reg = PIPESTAT(pipe);
79 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 80
46c06a30
VS		 81 if ((pipestat & mask) == 0)
82 return;
83
84 pipestat &= ~mask;
85 I915_WRITE(reg, pipestat);
86 POSTING_READ(reg);
7c463586
KP		 87}
88
01c66889
ZY		 89/**
90 * intel_enable_asle - enable ASLE interrupt for OpRegion
91 */
1ec14ad3 92void intel_enable_asle(struct drm_device *dev)
01c66889 93{
1ec14ad3
CW		 94 drm_i915_private_t *dev_priv = dev->dev_private;
95 unsigned long irqflags;
96
7e231dbe
JB		 97 /* FIXME: opregion/asle for VLV */
98 if (IS_VALLEYVIEW(dev))
99 return;
100
1ec14ad3 101 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 102
c619eed4 103 if (HAS_PCH_SPLIT(dev))
f2b115e6 104 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 105 else {
01c66889 106 i915_enable_pipestat(dev_priv, 1,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 108 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 109 i915_enable_pipestat(dev_priv, 0,
d874bcff 110 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 111 }
1ec14ad3
CW		 112
113 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 114}
115
0a3e67a4
JB		 116/**
117 * i915_pipe_enabled - check if a pipe is enabled
118 * @dev: DRM device
119 * @pipe: pipe to check
120 *
121 * Reading certain registers when the pipe is disabled can hang the chip.
122 * Use this routine to make sure the PLL is running and the pipe is active
123 * before reading such registers if unsure.
124 */
125static int
126i915_pipe_enabled(struct drm_device *dev, int pipe)
127{
128 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 129 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
130 pipe);
131
132 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 133}
134
42f52ef8
KP		 135/* Called from drm generic code, passed a 'crtc', which
136 * we use as a pipe index
137 */
f71d4af4 138static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 139{
140 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
141 unsigned long high_frame;
142 unsigned long low_frame;
5eddb70b 143 u32 high1, high2, low;
0a3e67a4
JB		 144
145 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 146 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 147 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 148 return 0;
149 }
150
9db4a9c7
JB		 151 high_frame = PIPEFRAME(pipe);
152 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 153
0a3e67a4
JB		 154 /*
155 * High & low register fields aren't synchronized, so make sure
156 * we get a low value that's stable across two reads of the high
157 * register.
158 */
159 do {
5eddb70b
CW		 160 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
161 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
162 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 163 } while (high1 != high2);
164
5eddb70b
CW		 165 high1 >>= PIPE_FRAME_HIGH_SHIFT;
166 low >>= PIPE_FRAME_LOW_SHIFT;
167 return (high1 << 8) | low;
0a3e67a4
JB		 168}
169
f71d4af4 170static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 171{
172 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 173 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 174
175 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 176 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 177 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 178 return 0;
179 }
180
181 return I915_READ(reg);
182}
183
f71d4af4 184static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 185 int *vpos, int *hpos)
186{
187 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
188 u32 vbl = 0, position = 0;
189 int vbl_start, vbl_end, htotal, vtotal;
190 bool in_vbl = true;
191 int ret = 0;
fe2b8f9d
PZ		 192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
193 pipe);
0af7e4df
MK		 194
195 if (!i915_pipe_enabled(dev, pipe)) {
196 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 197 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 198 return 0;
199 }
200
201 /* Get vtotal. */
fe2b8f9d 202 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 203
204 if (INTEL_INFO(dev)->gen >= 4) {
205 /* No obvious pixelcount register. Only query vertical
206 * scanout position from Display scan line register.
207 */
208 position = I915_READ(PIPEDSL(pipe));
209
210 /* Decode into vertical scanout position. Don't have
211 * horizontal scanout position.
212 */
213 *vpos = position & 0x1fff;
214 *hpos = 0;
215 } else {
216 /* Have access to pixelcount since start of frame.
217 * We can split this into vertical and horizontal
218 * scanout position.
219 */
220 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
221
fe2b8f9d 222 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 223 *vpos = position / htotal;
224 *hpos = position - (*vpos * htotal);
225 }
226
227 /* Query vblank area. */
fe2b8f9d 228 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 229
230 /* Test position against vblank region. */
231 vbl_start = vbl & 0x1fff;
232 vbl_end = (vbl >> 16) & 0x1fff;
233
234 if ((*vpos < vbl_start) || (*vpos > vbl_end))
235 in_vbl = false;
236
237 /* Inside "upper part" of vblank area? Apply corrective offset: */
238 if (in_vbl && (*vpos >= vbl_start))
239 *vpos = *vpos - vtotal;
240
241 /* Readouts valid? */
242 if (vbl > 0)
243 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
244
245 /* In vblank? */
246 if (in_vbl)
247 ret |= DRM_SCANOUTPOS_INVBL;
248
249 return ret;
250}
251
f71d4af4 252static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 253 int *max_error,
254 struct timeval *vblank_time,
255 unsigned flags)
256{
4041b853
CW		 257 struct drm_i915_private *dev_priv = dev->dev_private;
258 struct drm_crtc *crtc;
0af7e4df 259
4041b853
CW		 260 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
261 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 262 return -EINVAL;
263 }
264
265 /* Get drm_crtc to timestamp: */
4041b853
CW		 266 crtc = intel_get_crtc_for_pipe(dev, pipe);
267 if (crtc == NULL) {
268 DRM_ERROR("Invalid crtc %d\n", pipe);
269 return -EINVAL;
270 }
271
272 if (!crtc->enabled) {
273 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
274 return -EBUSY;
275 }
0af7e4df
MK		 276
277 /* Helper routine in DRM core does all the work: */
4041b853
CW		 278 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
279 vblank_time, flags,
280 crtc);
0af7e4df
MK		 281}
282
5ca58282
JB		 283/*
284 * Handle hotplug events outside the interrupt handler proper.
285 */
286static void i915_hotplug_work_func(struct work_struct *work)
287{
288 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
289 hotplug_work);
290 struct drm_device *dev = dev_priv->dev;
c31c4ba3 291 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 292 struct intel_encoder *encoder;
293
52d7eced
DV		 294 /* HPD irq before everything is fully set up. */
295 if (!dev_priv->enable_hotplug_processing)
296 return;
297
a65e34c7 298 mutex_lock(&mode_config->mutex);
e67189ab
JB		 299 DRM_DEBUG_KMS("running encoder hotplug functions\n");
300
4ef69c7a
CW		 301 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
302 if (encoder->hot_plug)
303 encoder->hot_plug(encoder);
304
40ee3381
KP		 305 mutex_unlock(&mode_config->mutex);
306
5ca58282 307 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 308 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 309}
310
73edd18f 311static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 312{
313 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 314 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 315 u8 new_delay;
316 unsigned long flags;
317
318 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 319
73edd18f
DV		 320 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
321
20e4d407 322 new_delay = dev_priv->ips.cur_delay;
9270388e 323
7648fa99 324 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 325 busy_up = I915_READ(RCPREVBSYTUPAVG);
326 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 327 max_avg = I915_READ(RCBMAXAVG);
328 min_avg = I915_READ(RCBMINAVG);
329
330 /* Handle RCS change request from hw */
b5b72e89 331 if (busy_up > max_avg) {
20e4d407
DV		 332 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
333 new_delay = dev_priv->ips.cur_delay - 1;
334 if (new_delay < dev_priv->ips.max_delay)
335 new_delay = dev_priv->ips.max_delay;
b5b72e89 336 } else if (busy_down < min_avg) {
20e4d407
DV		 337 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
338 new_delay = dev_priv->ips.cur_delay + 1;
339 if (new_delay > dev_priv->ips.min_delay)
340 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 341 }
342
7648fa99 343 if (ironlake_set_drps(dev, new_delay))
20e4d407 344 dev_priv->ips.cur_delay = new_delay;
f97108d1 345
9270388e
DV		 346 spin_unlock_irqrestore(&mchdev_lock, flags);
347
f97108d1
JB		 348 return;
349}
350
549f7365
CW		 351static void notify_ring(struct drm_device *dev,
352 struct intel_ring_buffer *ring)
353{
354 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 355
475553de
CW		 356 if (ring->obj == NULL)
357 return;
358
b2eadbc8 359 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 360
549f7365 361 wake_up_all(&ring->irq_queue);
3e0dc6b0 362 if (i915_enable_hangcheck) {
99584db3
DV		 363 dev_priv->gpu_error.hangcheck_count = 0;
364 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 365 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 366 }
549f7365
CW		 367}
368
4912d041 369static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 370{
4912d041 371 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 372 rps.work);
4912d041 373 u32 pm_iir, pm_imr;
7b9e0ae6 374 u8 new_delay;
4912d041 375
c6a828d3
DV		 376 spin_lock_irq(&dev_priv->rps.lock);
377 pm_iir = dev_priv->rps.pm_iir;
378 dev_priv->rps.pm_iir = 0;
4912d041 379 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 380 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 381 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 382
7b9e0ae6 383 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 384 return;
385
4fc688ce 386 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 387
388 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 389 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 390 else
c6a828d3 391 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 392
79249636
BW		 393 /* sysfs frequency interfaces may have snuck in while servicing the
394 * interrupt
395 */
396 if (!(new_delay > dev_priv->rps.max_delay ||
397 new_delay < dev_priv->rps.min_delay)) {
398 gen6_set_rps(dev_priv->dev, new_delay);
399 }
3b8d8d91 400
4fc688ce 401 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 402}
403
e3689190
BW		 404
405/**
406 * ivybridge_parity_work - Workqueue called when a parity error interrupt
407 * occurred.
408 * @work: workqueue struct
409 *
410 * Doesn't actually do anything except notify userspace. As a consequence of
411 * this event, userspace should try to remap the bad rows since statistically
412 * it is likely the same row is more likely to go bad again.
413 */
414static void ivybridge_parity_work(struct work_struct *work)
415{
416 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 417 l3_parity.error_work);
e3689190
BW		 418 u32 error_status, row, bank, subbank;
419 char *parity_event[5];
420 uint32_t misccpctl;
421 unsigned long flags;
422
423 /* We must turn off DOP level clock gating to access the L3 registers.
424 * In order to prevent a get/put style interface, acquire struct mutex
425 * any time we access those registers.
426 */
427 mutex_lock(&dev_priv->dev->struct_mutex);
428
429 misccpctl = I915_READ(GEN7_MISCCPCTL);
430 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
431 POSTING_READ(GEN7_MISCCPCTL);
432
433 error_status = I915_READ(GEN7_L3CDERRST1);
434 row = GEN7_PARITY_ERROR_ROW(error_status);
435 bank = GEN7_PARITY_ERROR_BANK(error_status);
436 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
437
438 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
439 GEN7_L3CDERRST1_ENABLE);
440 POSTING_READ(GEN7_L3CDERRST1);
441
442 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
443
444 spin_lock_irqsave(&dev_priv->irq_lock, flags);
445 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
446 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
447 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
448
449 mutex_unlock(&dev_priv->dev->struct_mutex);
450
451 parity_event[0] = "L3_PARITY_ERROR=1";
452 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
453 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
454 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
455 parity_event[4] = NULL;
456
457 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
458 KOBJ_CHANGE, parity_event);
459
460 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
461 row, bank, subbank);
462
463 kfree(parity_event[3]);
464 kfree(parity_event[2]);
465 kfree(parity_event[1]);
466}
467
d2ba8470 468static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 469{
470 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
471 unsigned long flags;
472
e1ef7cc2 473 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 474 return;
475
476 spin_lock_irqsave(&dev_priv->irq_lock, flags);
477 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
478 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
479 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
480
a4da4fa4 481 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 482}
483
e7b4c6b1
DV		 484static void snb_gt_irq_handler(struct drm_device *dev,
485 struct drm_i915_private *dev_priv,
486 u32 gt_iir)
487{
488
489 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
490 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
491 notify_ring(dev, &dev_priv->ring[RCS]);
492 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
493 notify_ring(dev, &dev_priv->ring[VCS]);
494 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
495 notify_ring(dev, &dev_priv->ring[BCS]);
496
497 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
498 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
499 GT_RENDER_CS_ERROR_INTERRUPT)) {
500 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
501 i915_handle_error(dev, false);
502 }
e3689190
BW		 503
504 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
505 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 506}
507
fc6826d1
CW		 508static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
509 u32 pm_iir)
510{
511 unsigned long flags;
512
513 /*
514 * IIR bits should never already be set because IMR should
515 * prevent an interrupt from being shown in IIR. The warning
516 * displays a case where we've unsafely cleared
c6a828d3 517 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 518 * type is not a problem, it displays a problem in the logic.
519 *
c6a828d3 520 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 521 */
522
c6a828d3 523 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 524 dev_priv->rps.pm_iir |= pm_iir;
525 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 526 POSTING_READ(GEN6_PMIMR);
c6a828d3 527 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 528
c6a828d3 529 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 530}
531
515ac2bb
DV		 532static void gmbus_irq_handler(struct drm_device *dev)
533{
28c70f16
DV		 534 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
535
28c70f16 536 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 537}
538
ce99c256
DV		 539static void dp_aux_irq_handler(struct drm_device *dev)
540{
9ee32fea
DV		 541 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
542
9ee32fea 543 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 544}
545
ff1f525e 546static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 547{
548 struct drm_device *dev = (struct drm_device *) arg;
549 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
550 u32 iir, gt_iir, pm_iir;
551 irqreturn_t ret = IRQ_NONE;
552 unsigned long irqflags;
553 int pipe;
554 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 555
556 atomic_inc(&dev_priv->irq_received);
557
7e231dbe
JB		 558 while (true) {
559 iir = I915_READ(VLV_IIR);
560 gt_iir = I915_READ(GTIIR);
561 pm_iir = I915_READ(GEN6_PMIIR);
562
563 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
564 goto out;
565
566 ret = IRQ_HANDLED;
567
e7b4c6b1 568 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 569
570 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
571 for_each_pipe(pipe) {
572 int reg = PIPESTAT(pipe);
573 pipe_stats[pipe] = I915_READ(reg);
574
575 /*
576 * Clear the PIPE*STAT regs before the IIR
577 */
578 if (pipe_stats[pipe] & 0x8000ffff) {
579 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
580 DRM_DEBUG_DRIVER("pipe %c underrun\n",
581 pipe_name(pipe));
582 I915_WRITE(reg, pipe_stats[pipe]);
583 }
584 }
585 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
586
31acc7f5
JB		 587 for_each_pipe(pipe) {
588 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
589 drm_handle_vblank(dev, pipe);
590
591 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
592 intel_prepare_page_flip(dev, pipe);
593 intel_finish_page_flip(dev, pipe);
594 }
595 }
596
7e231dbe
JB		 597 /* Consume port. Then clear IIR or we'll miss events */
598 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
599 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
600
601 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
602 hotplug_status);
603 if (hotplug_status & dev_priv->hotplug_supported_mask)
604 queue_work(dev_priv->wq,
605 &dev_priv->hotplug_work);
606
607 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
608 I915_READ(PORT_HOTPLUG_STAT);
609 }
610
515ac2bb
DV		 611 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
612 gmbus_irq_handler(dev);
7e231dbe 613
fc6826d1
CW		 614 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
615 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 616
617 I915_WRITE(GTIIR, gt_iir);
618 I915_WRITE(GEN6_PMIIR, pm_iir);
619 I915_WRITE(VLV_IIR, iir);
620 }
621
622out:
623 return ret;
624}
625
23e81d69 626static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 627{
628 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 629 int pipe;
776ad806 630
76e43830
DV		 631 if (pch_iir & SDE_HOTPLUG_MASK)
632 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
633
776ad806
JB		 634 if (pch_iir & SDE_AUDIO_POWER_MASK)
635 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
636 (pch_iir & SDE_AUDIO_POWER_MASK) >>
637 SDE_AUDIO_POWER_SHIFT);
638
ce99c256
DV		 639 if (pch_iir & SDE_AUX_MASK)
640 dp_aux_irq_handler(dev);
641
776ad806 642 if (pch_iir & SDE_GMBUS)
515ac2bb 643 gmbus_irq_handler(dev);
776ad806
JB		 644
645 if (pch_iir & SDE_AUDIO_HDCP_MASK)
646 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
647
648 if (pch_iir & SDE_AUDIO_TRANS_MASK)
649 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
650
651 if (pch_iir & SDE_POISON)
652 DRM_ERROR("PCH poison interrupt\n");
653
9db4a9c7
JB		 654 if (pch_iir & SDE_FDI_MASK)
655 for_each_pipe(pipe)
656 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
657 pipe_name(pipe),
658 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 659
660 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
661 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
662
663 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
664 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
665
666 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
667 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
668 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
669 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
670}
671
23e81d69
AJ		 672static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
673{
674 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
675 int pipe;
676
76e43830
DV		 677 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
678 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
679
23e81d69
AJ		 680 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
681 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
682 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
683 SDE_AUDIO_POWER_SHIFT_CPT);
684
685 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 686 dp_aux_irq_handler(dev);
23e81d69
AJ		 687
688 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 689 gmbus_irq_handler(dev);
23e81d69
AJ		 690
691 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
692 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
693
694 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
695 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
696
697 if (pch_iir & SDE_FDI_MASK_CPT)
698 for_each_pipe(pipe)
699 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
700 pipe_name(pipe),
701 I915_READ(FDI_RX_IIR(pipe)));
702}
703
ff1f525e 704static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 705{
706 struct drm_device *dev = (struct drm_device *) arg;
707 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 708 u32 de_iir, gt_iir, de_ier, pm_iir;
709 irqreturn_t ret = IRQ_NONE;
710 int i;
b1f14ad0
JB		 711
712 atomic_inc(&dev_priv->irq_received);
713
714 /* disable master interrupt before clearing iir */
715 de_ier = I915_READ(DEIER);
716 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 717
b1f14ad0 718 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 719 if (gt_iir) {
720 snb_gt_irq_handler(dev, dev_priv, gt_iir);
721 I915_WRITE(GTIIR, gt_iir);
722 ret = IRQ_HANDLED;
b1f14ad0
JB		 723 }
724
0e43406b
CW		 725 de_iir = I915_READ(DEIIR);
726 if (de_iir) {
ce99c256
DV		 727 if (de_iir & DE_AUX_CHANNEL_A_IVB)
728 dp_aux_irq_handler(dev);
729
0e43406b
CW		 730 if (de_iir & DE_GSE_IVB)
731 intel_opregion_gse_intr(dev);
732
733 for (i = 0; i < 3; i++) {
74d44445
DV		 734 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
735 drm_handle_vblank(dev, i);
0e43406b
CW		 736 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
737 intel_prepare_page_flip(dev, i);
738 intel_finish_page_flip_plane(dev, i);
739 }
0e43406b 740 }
b615b57a 741
0e43406b
CW		 742 /* check event from PCH */
743 if (de_iir & DE_PCH_EVENT_IVB) {
744 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 745
23e81d69 746 cpt_irq_handler(dev, pch_iir);
b1f14ad0 747
0e43406b
CW		 748 /* clear PCH hotplug event before clear CPU irq */
749 I915_WRITE(SDEIIR, pch_iir);
750 }
b615b57a 751
0e43406b
CW		 752 I915_WRITE(DEIIR, de_iir);
753 ret = IRQ_HANDLED;
b1f14ad0
JB		 754 }
755
0e43406b
CW		 756 pm_iir = I915_READ(GEN6_PMIIR);
757 if (pm_iir) {
758 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
759 gen6_queue_rps_work(dev_priv, pm_iir);
760 I915_WRITE(GEN6_PMIIR, pm_iir);
761 ret = IRQ_HANDLED;
762 }
b1f14ad0 763
b1f14ad0
JB		 764 I915_WRITE(DEIER, de_ier);
765 POSTING_READ(DEIER);
766
767 return ret;
768}
769
e7b4c6b1
DV		 770static void ilk_gt_irq_handler(struct drm_device *dev,
771 struct drm_i915_private *dev_priv,
772 u32 gt_iir)
773{
774 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
775 notify_ring(dev, &dev_priv->ring[RCS]);
776 if (gt_iir & GT_BSD_USER_INTERRUPT)
777 notify_ring(dev, &dev_priv->ring[VCS]);
778}
779
ff1f525e 780static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 781{
4697995b 782 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 783 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
784 int ret = IRQ_NONE;
acd15b6c 785 u32 de_iir, gt_iir, de_ier, pm_iir;
881f47b6 786
4697995b
JB		 787 atomic_inc(&dev_priv->irq_received);
788
2d109a84
ZN		 789 /* disable master interrupt before clearing iir */
790 de_ier = I915_READ(DEIER);
791 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 792 POSTING_READ(DEIER);
2d109a84 793
036a4a7d
ZW		 794 de_iir = I915_READ(DEIIR);
795 gt_iir = I915_READ(GTIIR);
3b8d8d91 796 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 797
acd15b6c 798 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 799 goto done;
036a4a7d 800
c7c85101 801 ret = IRQ_HANDLED;
036a4a7d 802
e7b4c6b1
DV		 803 if (IS_GEN5(dev))
804 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
805 else
806 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 807
ce99c256
DV		 808 if (de_iir & DE_AUX_CHANNEL_A)
809 dp_aux_irq_handler(dev);
810
c7c85101 811 if (de_iir & DE_GSE)
3b617967 812 intel_opregion_gse_intr(dev);
c650156a 813
74d44445
DV		 814 if (de_iir & DE_PIPEA_VBLANK)
815 drm_handle_vblank(dev, 0);
816
817 if (de_iir & DE_PIPEB_VBLANK)
818 drm_handle_vblank(dev, 1);
819
f072d2e7 820 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 821 intel_prepare_page_flip(dev, 0);
2bbda389 822 intel_finish_page_flip_plane(dev, 0);
f072d2e7 823 }
013d5aa2 824
f072d2e7 825 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 826 intel_prepare_page_flip(dev, 1);
2bbda389 827 intel_finish_page_flip_plane(dev, 1);
f072d2e7 828 }
013d5aa2 829
c7c85101 830 /* check event from PCH */
776ad806 831 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 832 u32 pch_iir = I915_READ(SDEIIR);
833
23e81d69
AJ		 834 if (HAS_PCH_CPT(dev))
835 cpt_irq_handler(dev, pch_iir);
836 else
837 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 838
839 /* should clear PCH hotplug event before clear CPU irq */
840 I915_WRITE(SDEIIR, pch_iir);
776ad806 841 }
036a4a7d 842
73edd18f
DV		 843 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
844 ironlake_handle_rps_change(dev);
f97108d1 845
fc6826d1
CW		 846 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
847 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 848
c7c85101
ZN		 849 I915_WRITE(GTIIR, gt_iir);
850 I915_WRITE(DEIIR, de_iir);
4912d041 851 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 852
853done:
2d109a84 854 I915_WRITE(DEIER, de_ier);
3143a2bf 855 POSTING_READ(DEIER);
2d109a84 856
036a4a7d
ZW		 857 return ret;
858}
859
8a905236
JB		 860/**
861 * i915_error_work_func - do process context error handling work
862 * @work: work struct
863 *
864 * Fire an error uevent so userspace can see that a hang or error
865 * was detected.
866 */
867static void i915_error_work_func(struct work_struct *work)
868{
1f83fee0
DV		 869 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
870 work);
871 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
872 gpu_error);
8a905236 873 struct drm_device *dev = dev_priv->dev;
f69061be 874 struct intel_ring_buffer *ring;
f316a42c
BG		 875 char *error_event[] = { "ERROR=1", NULL };
876 char *reset_event[] = { "RESET=1", NULL };
877 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 878 int i, ret;
8a905236 879
f316a42c
BG		 880 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
881
7db0ba24
DV		 882 /*
883 * Note that there's only one work item which does gpu resets, so we
884 * need not worry about concurrent gpu resets potentially incrementing
885 * error->reset_counter twice. We only need to take care of another
886 * racing irq/hangcheck declaring the gpu dead for a second time. A
887 * quick check for that is good enough: schedule_work ensures the
888 * correct ordering between hang detection and this work item, and since
889 * the reset in-progress bit is only ever set by code outside of this
890 * work we don't need to worry about any other races.
891 */
892 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 893 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 894 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
895 reset_event);
1f83fee0 896
f69061be
DV		 897 ret = i915_reset(dev);
898
899 if (ret == 0) {
900 /*
901 * After all the gem state is reset, increment the reset
902 * counter and wake up everyone waiting for the reset to
903 * complete.
904 *
905 * Since unlock operations are a one-sided barrier only,
906 * we need to insert a barrier here to order any seqno
907 * updates before
908 * the counter increment.
909 */
910 smp_mb__before_atomic_inc();
911 atomic_inc(&dev_priv->gpu_error.reset_counter);
912
913 kobject_uevent_env(&dev->primary->kdev.kobj,
914 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 915 } else {
916 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 917 }
1f83fee0 918
f69061be
DV		 919 for_each_ring(ring, dev_priv, i)
920 wake_up_all(&ring->irq_queue);
921
96a02917
VS		 922 intel_display_handle_reset(dev);
923
1f83fee0 924 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 925 }
8a905236
JB		 926}
927
85f9e50d
DV		 928/* NB: please notice the memset */
929static void i915_get_extra_instdone(struct drm_device *dev,
930 uint32_t *instdone)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
934
935 switch(INTEL_INFO(dev)->gen) {
936 case 2:
937 case 3:
938 instdone[0] = I915_READ(INSTDONE);
939 break;
940 case 4:
941 case 5:
942 case 6:
943 instdone[0] = I915_READ(INSTDONE_I965);
944 instdone[1] = I915_READ(INSTDONE1);
945 break;
946 default:
947 WARN_ONCE(1, "Unsupported platform\n");
948 case 7:
949 instdone[0] = I915_READ(GEN7_INSTDONE_1);
950 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
951 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
952 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
953 break;
954 }
955}
956
3bd3c932 957#ifdef CONFIG_DEBUG_FS
9df30794 958static struct drm_i915_error_object *
d0d045e8
BW		 959i915_error_object_create_sized(struct drm_i915_private *dev_priv,
960 struct drm_i915_gem_object *src,
961 const int num_pages)
9df30794
CW		 962{
963 struct drm_i915_error_object *dst;
d0d045e8 964 int i;
e56660dd 965 u32 reloc_offset;
9df30794 966
05394f39 967 if (src == NULL || src->pages == NULL)
9df30794
CW		 968 return NULL;
969
d0d045e8 970 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 971 if (dst == NULL)
972 return NULL;
973
05394f39 974 reloc_offset = src->gtt_offset;
d0d045e8 975 for (i = 0; i < num_pages; i++) {
788885ae 976 unsigned long flags;
e56660dd 977 void *d;
788885ae 978
e56660dd 979 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 980 if (d == NULL)
981 goto unwind;
e56660dd 982
788885ae 983 local_irq_save(flags);
5d4545ae 984 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 985 src->has_global_gtt_mapping) {
172975aa
CW		 986 void __iomem *s;
987
988 /* Simply ignore tiling or any overlapping fence.
989 * It's part of the error state, and this hopefully
990 * captures what the GPU read.
991 */
992
5d4545ae 993 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 994 reloc_offset);
995 memcpy_fromio(d, s, PAGE_SIZE);
996 io_mapping_unmap_atomic(s);
960e3564
CW		 997 } else if (src->stolen) {
998 unsigned long offset;
999
1000 offset = dev_priv->mm.stolen_base;
1001 offset += src->stolen->start;
1002 offset += i << PAGE_SHIFT;
1003
1a240d4d 1004 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1005 } else {
9da3da66 1006 struct page *page;
172975aa
CW		 1007 void *s;
1008
9da3da66 1009 page = i915_gem_object_get_page(src, i);
172975aa 1010
9da3da66
CW		 1011 drm_clflush_pages(&page, 1);
1012
1013 s = kmap_atomic(page);
172975aa
CW		 1014 memcpy(d, s, PAGE_SIZE);
1015 kunmap_atomic(s);
1016
9da3da66 1017 drm_clflush_pages(&page, 1);
172975aa 1018 }
788885ae 1019 local_irq_restore(flags);
e56660dd 1020
9da3da66 1021 dst->pages[i] = d;
e56660dd
CW		 1022
1023 reloc_offset += PAGE_SIZE;
9df30794 1024 }
d0d045e8 1025 dst->page_count = num_pages;
05394f39 1026 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1027
1028 return dst;
1029
1030unwind:
9da3da66
CW		 1031 while (i--)
1032 kfree(dst->pages[i]);
9df30794
CW		 1033 kfree(dst);
1034 return NULL;
1035}
d0d045e8
BW		 1036#define i915_error_object_create(dev_priv, src) \
1037 i915_error_object_create_sized((dev_priv), (src), \
1038 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1039
1040static void
1041i915_error_object_free(struct drm_i915_error_object *obj)
1042{
1043 int page;
1044
1045 if (obj == NULL)
1046 return;
1047
1048 for (page = 0; page < obj->page_count; page++)
1049 kfree(obj->pages[page]);
1050
1051 kfree(obj);
1052}
1053
742cbee8
DV		 1054void
1055i915_error_state_free(struct kref *error_ref)
9df30794 1056{
742cbee8
DV		 1057 struct drm_i915_error_state *error = container_of(error_ref,
1058 typeof(*error), ref);
e2f973d5
CW		 1059 int i;
1060
52d39a21
CW		 1061 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1062 i915_error_object_free(error->ring[i].batchbuffer);
1063 i915_error_object_free(error->ring[i].ringbuffer);
1064 kfree(error->ring[i].requests);
1065 }
e2f973d5 1066
9df30794 1067 kfree(error->active_bo);
6ef3d427 1068 kfree(error->overlay);
9df30794
CW		 1069 kfree(error);
1070}
1b50247a
CW		 1071static void capture_bo(struct drm_i915_error_buffer *err,
1072 struct drm_i915_gem_object *obj)
1073{
1074 err->size = obj->base.size;
1075 err->name = obj->base.name;
0201f1ec
CW		 1076 err->rseqno = obj->last_read_seqno;
1077 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1078 err->gtt_offset = obj->gtt_offset;
1079 err->read_domains = obj->base.read_domains;
1080 err->write_domain = obj->base.write_domain;
1081 err->fence_reg = obj->fence_reg;
1082 err->pinned = 0;
1083 if (obj->pin_count > 0)
1084 err->pinned = 1;
1085 if (obj->user_pin_count > 0)
1086 err->pinned = -1;
1087 err->tiling = obj->tiling_mode;
1088 err->dirty = obj->dirty;
1089 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1090 err->ring = obj->ring ? obj->ring->id : -1;
1091 err->cache_level = obj->cache_level;
1092}
9df30794 1093
1b50247a
CW		 1094static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1095 int count, struct list_head *head)
c724e8a9
CW		 1096{
1097 struct drm_i915_gem_object *obj;
1098 int i = 0;
1099
1100 list_for_each_entry(obj, head, mm_list) {
1b50247a 1101 capture_bo(err++, obj);
c724e8a9
CW		 1102 if (++i == count)
1103 break;
1b50247a
CW		 1104 }
1105
1106 return i;
1107}
1108
1109static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1110 int count, struct list_head *head)
1111{
1112 struct drm_i915_gem_object *obj;
1113 int i = 0;
1114
1115 list_for_each_entry(obj, head, gtt_list) {
1116 if (obj->pin_count == 0)
1117 continue;
c724e8a9 1118
1b50247a
CW		 1119 capture_bo(err++, obj);
1120 if (++i == count)
1121 break;
c724e8a9
CW		 1122 }
1123
1124 return i;
1125}
1126
748ebc60
CW		 1127static void i915_gem_record_fences(struct drm_device *dev,
1128 struct drm_i915_error_state *error)
1129{
1130 struct drm_i915_private *dev_priv = dev->dev_private;
1131 int i;
1132
1133 /* Fences */
1134 switch (INTEL_INFO(dev)->gen) {
775d17b6 1135 case 7:
748ebc60
CW		 1136 case 6:
1137 for (i = 0; i < 16; i++)
1138 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1139 break;
1140 case 5:
1141 case 4:
1142 for (i = 0; i < 16; i++)
1143 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1144 break;
1145 case 3:
1146 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1147 for (i = 0; i < 8; i++)
1148 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1149 case 2:
1150 for (i = 0; i < 8; i++)
1151 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1152 break;
1153
7dbf9d6e
BW		 1154 default:
1155 BUG();
748ebc60
CW		 1156 }
1157}
1158
bcfb2e28
CW		 1159static struct drm_i915_error_object *
1160i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1161 struct intel_ring_buffer *ring)
1162{
1163 struct drm_i915_gem_object *obj;
1164 u32 seqno;
1165
1166 if (!ring->get_seqno)
1167 return NULL;
1168
b45305fc
DV		 1169 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1170 u32 acthd = I915_READ(ACTHD);
1171
1172 if (WARN_ON(ring->id != RCS))
1173 return NULL;
1174
1175 obj = ring->private;
1176 if (acthd >= obj->gtt_offset &&
1177 acthd < obj->gtt_offset + obj->base.size)
1178 return i915_error_object_create(dev_priv, obj);
1179 }
1180
b2eadbc8 1181 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1182 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1183 if (obj->ring != ring)
1184 continue;
1185
0201f1ec 1186 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1187 continue;
1188
1189 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1190 continue;
1191
1192 /* We need to copy these to an anonymous buffer as the simplest
1193 * method to avoid being overwritten by userspace.
1194 */
1195 return i915_error_object_create(dev_priv, obj);
1196 }
1197
1198 return NULL;
1199}
1200
d27b1e0e
DV		 1201static void i915_record_ring_state(struct drm_device *dev,
1202 struct drm_i915_error_state *error,
1203 struct intel_ring_buffer *ring)
1204{
1205 struct drm_i915_private *dev_priv = dev->dev_private;
1206
33f3f518 1207 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1208 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1209 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1210 error->semaphore_mboxes[ring->id][0]
1211 = I915_READ(RING_SYNC_0(ring->mmio_base));
1212 error->semaphore_mboxes[ring->id][1]
1213 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1214 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1215 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1216 }
c1cd90ed 1217
d27b1e0e 1218 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1219 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1220 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1221 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1222 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1223 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1224 if (ring->id == RCS)
d27b1e0e 1225 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1226 } else {
9d2f41fa 1227 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1228 error->ipeir[ring->id] = I915_READ(IPEIR);
1229 error->ipehr[ring->id] = I915_READ(IPEHR);
1230 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1231 }
1232
9574b3fe 1233 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1234 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1235 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1236 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1237 error->head[ring->id] = I915_READ_HEAD(ring);
1238 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1239 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1240
1241 error->cpu_ring_head[ring->id] = ring->head;
1242 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1243}
1244
52d39a21
CW		 1245static void i915_gem_record_rings(struct drm_device *dev,
1246 struct drm_i915_error_state *error)
1247{
1248 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1249 struct intel_ring_buffer *ring;
52d39a21
CW		 1250 struct drm_i915_gem_request *request;
1251 int i, count;
1252
b4519513 1253 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1254 i915_record_ring_state(dev, error, ring);
1255
1256 error->ring[i].batchbuffer =
1257 i915_error_first_batchbuffer(dev_priv, ring);
1258
1259 error->ring[i].ringbuffer =
1260 i915_error_object_create(dev_priv, ring->obj);
1261
1262 count = 0;
1263 list_for_each_entry(request, &ring->request_list, list)
1264 count++;
1265
1266 error->ring[i].num_requests = count;
1267 error->ring[i].requests =
1268 kmalloc(count*sizeof(struct drm_i915_error_request),
1269 GFP_ATOMIC);
1270 if (error->ring[i].requests == NULL) {
1271 error->ring[i].num_requests = 0;
1272 continue;
1273 }
1274
1275 count = 0;
1276 list_for_each_entry(request, &ring->request_list, list) {
1277 struct drm_i915_error_request *erq;
1278
1279 erq = &error->ring[i].requests[count++];
1280 erq->seqno = request->seqno;
1281 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1282 erq->tail = request->tail;
52d39a21
CW		 1283 }
1284 }
1285}
1286
8a905236
JB		 1287/**
1288 * i915_capture_error_state - capture an error record for later analysis
1289 * @dev: drm device
1290 *
1291 * Should be called when an error is detected (either a hang or an error
1292 * interrupt) to capture error state from the time of the error. Fills
1293 * out a structure which becomes available in debugfs for user level tools
1294 * to pick up.
1295 */
63eeaf38
JB		 1296static void i915_capture_error_state(struct drm_device *dev)
1297{
1298 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1299 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1300 struct drm_i915_error_state *error;
1301 unsigned long flags;
9db4a9c7 1302 int i, pipe;
63eeaf38 1303
99584db3
DV		 1304 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1305 error = dev_priv->gpu_error.first_error;
1306 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1307 if (error)
1308 return;
63eeaf38 1309
9db4a9c7 1310 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1311 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1312 if (!error) {
9df30794
CW		 1313 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1314 return;
63eeaf38
JB		 1315 }
1316
2f86f191
BW		 1317 DRM_INFO("capturing error event; look for more information in"
1318 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1319 dev->primary->index);
2fa772f3 1320
742cbee8 1321 kref_init(&error->ref);
63eeaf38
JB		 1322 error->eir = I915_READ(EIR);
1323 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1324 if (HAS_HW_CONTEXTS(dev))
1325 error->ccid = I915_READ(CCID);
be998e2e
BW		 1326
1327 if (HAS_PCH_SPLIT(dev))
1328 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1329 else if (IS_VALLEYVIEW(dev))
1330 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1331 else if (IS_GEN2(dev))
1332 error->ier = I915_READ16(IER);
1333 else
1334 error->ier = I915_READ(IER);
1335
0f3b6849
CW		 1336 if (INTEL_INFO(dev)->gen >= 6)
1337 error->derrmr = I915_READ(DERRMR);
1338
1339 if (IS_VALLEYVIEW(dev))
1340 error->forcewake = I915_READ(FORCEWAKE_VLV);
1341 else if (INTEL_INFO(dev)->gen >= 7)
1342 error->forcewake = I915_READ(FORCEWAKE_MT);
1343 else if (INTEL_INFO(dev)->gen == 6)
1344 error->forcewake = I915_READ(FORCEWAKE);
1345
9db4a9c7
JB		 1346 for_each_pipe(pipe)
1347 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1348
33f3f518 1349 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1350 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1351 error->done_reg = I915_READ(DONE_REG);
1352 }
d27b1e0e 1353
71e172e8
BW		 1354 if (INTEL_INFO(dev)->gen == 7)
1355 error->err_int = I915_READ(GEN7_ERR_INT);
1356
050ee91f
BW		 1357 i915_get_extra_instdone(dev, error->extra_instdone);
1358
748ebc60 1359 i915_gem_record_fences(dev, error);
52d39a21 1360 i915_gem_record_rings(dev, error);
9df30794 1361
c724e8a9 1362 /* Record buffers on the active and pinned lists. */
9df30794 1363 error->active_bo = NULL;
c724e8a9 1364 error->pinned_bo = NULL;
9df30794 1365
bcfb2e28
CW		 1366 i = 0;
1367 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1368 i++;
1369 error->active_bo_count = i;
6c085a72 1370 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1371 if (obj->pin_count)
1372 i++;
bcfb2e28 1373 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1374
8e934dbf
CW		 1375 error->active_bo = NULL;
1376 error->pinned_bo = NULL;
bcfb2e28
CW		 1377 if (i) {
1378 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1379 GFP_ATOMIC);
c724e8a9
CW		 1380 if (error->active_bo)
1381 error->pinned_bo =
1382 error->active_bo + error->active_bo_count;
9df30794
CW		 1383 }
1384
c724e8a9
CW		 1385 if (error->active_bo)
1386 error->active_bo_count =
1b50247a
CW		 1387 capture_active_bo(error->active_bo,
1388 error->active_bo_count,
1389 &dev_priv->mm.active_list);
c724e8a9
CW		 1390
1391 if (error->pinned_bo)
1392 error->pinned_bo_count =
1b50247a
CW		 1393 capture_pinned_bo(error->pinned_bo,
1394 error->pinned_bo_count,
6c085a72 1395 &dev_priv->mm.bound_list);
c724e8a9 1396
9df30794
CW		 1397 do_gettimeofday(&error->time);
1398
6ef3d427 1399 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1400 error->display = intel_display_capture_error_state(dev);
6ef3d427 1401
99584db3
DV		 1402 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1403 if (dev_priv->gpu_error.first_error == NULL) {
1404 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1405 error = NULL;
1406 }
99584db3 1407 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1408
1409 if (error)
742cbee8 1410 i915_error_state_free(&error->ref);
9df30794
CW		 1411}
1412
1413void i915_destroy_error_state(struct drm_device *dev)
1414{
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 struct drm_i915_error_state *error;
6dc0e816 1417 unsigned long flags;
9df30794 1418
99584db3
DV		 1419 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1420 error = dev_priv->gpu_error.first_error;
1421 dev_priv->gpu_error.first_error = NULL;
1422 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1423
1424 if (error)
742cbee8 1425 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1426}
3bd3c932
CW		 1427#else
1428#define i915_capture_error_state(x)
1429#endif
63eeaf38 1430
35aed2e6 1431static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1432{
1433 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1434 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1435 u32 eir = I915_READ(EIR);
050ee91f 1436 int pipe, i;
8a905236 1437
35aed2e6
CW		 1438 if (!eir)
1439 return;
8a905236 1440
a70491cc 1441 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1442
bd9854f9
BW		 1443 i915_get_extra_instdone(dev, instdone);
1444
8a905236
JB		 1445 if (IS_G4X(dev)) {
1446 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1447 u32 ipeir = I915_READ(IPEIR_I965);
1448
a70491cc
JP		 1449 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1450 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1451 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1452 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1453 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1454 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1455 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1456 POSTING_READ(IPEIR_I965);
8a905236
JB		 1457 }
1458 if (eir & GM45_ERROR_PAGE_TABLE) {
1459 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1460 pr_err("page table error\n");
1461 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1462 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1463 POSTING_READ(PGTBL_ER);
8a905236
JB		 1464 }
1465 }
1466
a6c45cf0 1467 if (!IS_GEN2(dev)) {
8a905236
JB		 1468 if (eir & I915_ERROR_PAGE_TABLE) {
1469 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1470 pr_err("page table error\n");
1471 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1472 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1473 POSTING_READ(PGTBL_ER);
8a905236
JB		 1474 }
1475 }
1476
1477 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1478 pr_err("memory refresh error:\n");
9db4a9c7 1479 for_each_pipe(pipe)
a70491cc 1480 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1481 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1482 /* pipestat has already been acked */
1483 }
1484 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1485 pr_err("instruction error\n");
1486 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1487 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1488 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1489 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1490 u32 ipeir = I915_READ(IPEIR);
1491
a70491cc
JP		 1492 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1493 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1494 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1495 I915_WRITE(IPEIR, ipeir);
3143a2bf 1496 POSTING_READ(IPEIR);
8a905236
JB		 1497 } else {
1498 u32 ipeir = I915_READ(IPEIR_I965);
1499
a70491cc
JP		 1500 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1501 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1502 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1503 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1504 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1505 POSTING_READ(IPEIR_I965);
8a905236
JB		 1506 }
1507 }
1508
1509 I915_WRITE(EIR, eir);
3143a2bf 1510 POSTING_READ(EIR);
8a905236
JB		 1511 eir = I915_READ(EIR);
1512 if (eir) {
1513 /*
1514 * some errors might have become stuck,
1515 * mask them.
1516 */
1517 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1518 I915_WRITE(EMR, I915_READ(EMR) | eir);
1519 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1520 }
35aed2e6
CW		 1521}
1522
1523/**
1524 * i915_handle_error - handle an error interrupt
1525 * @dev: drm device
1526 *
1527 * Do some basic checking of regsiter state at error interrupt time and
1528 * dump it to the syslog. Also call i915_capture_error_state() to make
1529 * sure we get a record and make it available in debugfs. Fire a uevent
1530 * so userspace knows something bad happened (should trigger collection
1531 * of a ring dump etc.).
1532 */
527f9e90 1533void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1534{
1535 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1536 struct intel_ring_buffer *ring;
1537 int i;
35aed2e6
CW		 1538
1539 i915_capture_error_state(dev);
1540 i915_report_and_clear_eir(dev);
8a905236 1541
ba1234d1 1542 if (wedged) {
f69061be
DV		 1543 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1544 &dev_priv->gpu_error.reset_counter);
ba1234d1 1545
11ed50ec 1546 /*
1f83fee0
DV		 1547 * Wakeup waiting processes so that the reset work item
1548 * doesn't deadlock trying to grab various locks.
11ed50ec 1549 */
b4519513
CW		 1550 for_each_ring(ring, dev_priv, i)
1551 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1552 }
1553
99584db3 1554 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1555}
1556
21ad8330 1557static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1558{
1559 drm_i915_private_t *dev_priv = dev->dev_private;
1560 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1562 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1563 struct intel_unpin_work *work;
1564 unsigned long flags;
1565 bool stall_detected;
1566
1567 /* Ignore early vblank irqs */
1568 if (intel_crtc == NULL)
1569 return;
1570
1571 spin_lock_irqsave(&dev->event_lock, flags);
1572 work = intel_crtc->unpin_work;
1573
e7d841ca
CW		 1574 if (work == NULL ||
1575 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1576 !work->enable_stall_check) {
4e5359cd
SF		 1577 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1578 spin_unlock_irqrestore(&dev->event_lock, flags);
1579 return;
1580 }
1581
1582 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1583 obj = work->pending_flip_obj;
a6c45cf0 1584 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1585 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1586 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1587 obj->gtt_offset;
4e5359cd 1588 } else {
9db4a9c7 1589 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1590 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1591 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1592 crtc->x * crtc->fb->bits_per_pixel/8);
1593 }
1594
1595 spin_unlock_irqrestore(&dev->event_lock, flags);
1596
1597 if (stall_detected) {
1598 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1599 intel_prepare_page_flip(dev, intel_crtc->plane);
1600 }
1601}
1602
42f52ef8
KP		 1603/* Called from drm generic code, passed 'crtc' which
1604 * we use as a pipe index
1605 */
f71d4af4 1606static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1607{
1608 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1609 unsigned long irqflags;
71e0ffa5 1610
5eddb70b 1611 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1612 return -EINVAL;
0a3e67a4 1613
1ec14ad3 1614 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1615 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1616 i915_enable_pipestat(dev_priv, pipe,
1617 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1618 else
7c463586
KP		 1619 i915_enable_pipestat(dev_priv, pipe,
1620 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1621
1622 /* maintain vblank delivery even in deep C-states */
1623 if (dev_priv->info->gen == 3)
6b26c86d 1624 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1625 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1626
0a3e67a4
JB		 1627 return 0;
1628}
1629
f71d4af4 1630static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1631{
1632 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1633 unsigned long irqflags;
1634
1635 if (!i915_pipe_enabled(dev, pipe))
1636 return -EINVAL;
1637
1638 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1639 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1640 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1641 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1642
1643 return 0;
1644}
1645
f71d4af4 1646static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1647{
1648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1649 unsigned long irqflags;
1650
1651 if (!i915_pipe_enabled(dev, pipe))
1652 return -EINVAL;
1653
1654 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1655 ironlake_enable_display_irq(dev_priv,
1656 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1657 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1658
1659 return 0;
1660}
1661
7e231dbe
JB		 1662static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1663{
1664 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1665 unsigned long irqflags;
31acc7f5 1666 u32 imr;
7e231dbe
JB		 1667
1668 if (!i915_pipe_enabled(dev, pipe))
1669 return -EINVAL;
1670
1671 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1672 imr = I915_READ(VLV_IMR);
31acc7f5 1673 if (pipe == 0)
7e231dbe 1674 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1675 else
7e231dbe 1676 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1677 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1678 i915_enable_pipestat(dev_priv, pipe,
1679 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1680 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1681
1682 return 0;
1683}
1684
42f52ef8
KP		 1685/* Called from drm generic code, passed 'crtc' which
1686 * we use as a pipe index
1687 */
f71d4af4 1688static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1689{
1690 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1691 unsigned long irqflags;
0a3e67a4 1692
1ec14ad3 1693 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1694 if (dev_priv->info->gen == 3)
6b26c86d 1695 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1696
f796cf8f
JB		 1697 i915_disable_pipestat(dev_priv, pipe,
1698 PIPE_VBLANK_INTERRUPT_ENABLE |
1699 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1700 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1701}
1702
f71d4af4 1703static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1704{
1705 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1706 unsigned long irqflags;
1707
1708 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1709 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1710 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1711 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1712}
1713
f71d4af4 1714static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1715{
1716 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1717 unsigned long irqflags;
1718
1719 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1720 ironlake_disable_display_irq(dev_priv,
1721 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1722 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1723}
1724
7e231dbe
JB		 1725static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1726{
1727 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1728 unsigned long irqflags;
31acc7f5 1729 u32 imr;
7e231dbe
JB		 1730
1731 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1732 i915_disable_pipestat(dev_priv, pipe,
1733 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1734 imr = I915_READ(VLV_IMR);
31acc7f5 1735 if (pipe == 0)
7e231dbe 1736 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1737 else
7e231dbe 1738 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1739 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1740 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1741}
1742
893eead0
CW		 1743static u32
1744ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1745{
893eead0
CW		 1746 return list_entry(ring->request_list.prev,
1747 struct drm_i915_gem_request, list)->seqno;
1748}
1749
1750static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1751{
1752 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1753 i915_seqno_passed(ring->get_seqno(ring, false),
1754 ring_last_seqno(ring))) {
893eead0 1755 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1756 if (waitqueue_active(&ring->irq_queue)) {
1757 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1758 ring->name);
893eead0
CW		 1759 wake_up_all(&ring->irq_queue);
1760 *err = true;
1761 }
1762 return true;
1763 }
1764 return false;
f65d9421
BG		 1765}
1766
1ec14ad3
CW		 1767static bool kick_ring(struct intel_ring_buffer *ring)
1768{
1769 struct drm_device *dev = ring->dev;
1770 struct drm_i915_private *dev_priv = dev->dev_private;
1771 u32 tmp = I915_READ_CTL(ring);
1772 if (tmp & RING_WAIT) {
1773 DRM_ERROR("Kicking stuck wait on %s\n",
1774 ring->name);
1775 I915_WRITE_CTL(ring, tmp);
1776 return true;
1777 }
1ec14ad3
CW		 1778 return false;
1779}
1780
d1e61e7f
CW		 1781static bool i915_hangcheck_hung(struct drm_device *dev)
1782{
1783 drm_i915_private_t *dev_priv = dev->dev_private;
1784
99584db3 1785 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
b4519513
CW		 1786 bool hung = true;
1787
d1e61e7f
CW		 1788 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1789 i915_handle_error(dev, true);
1790
1791 if (!IS_GEN2(dev)) {
b4519513
CW		 1792 struct intel_ring_buffer *ring;
1793 int i;
1794
d1e61e7f
CW		 1795 /* Is the chip hanging on a WAIT_FOR_EVENT?
1796 * If so we can simply poke the RB_WAIT bit
1797 * and break the hang. This should work on
1798 * all but the second generation chipsets.
1799 */
b4519513
CW		 1800 for_each_ring(ring, dev_priv, i)
1801 hung &= !kick_ring(ring);
d1e61e7f
CW		 1802 }
1803
b4519513 1804 return hung;
d1e61e7f
CW		 1805 }
1806
1807 return false;
1808}
1809
f65d9421
BG		 1810/**
1811 * This is called when the chip hasn't reported back with completed
1812 * batchbuffers in a long time. The first time this is called we simply record
1813 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1814 * again, we assume the chip is wedged and try to fix it.
1815 */
1816void i915_hangcheck_elapsed(unsigned long data)
1817{
1818 struct drm_device *dev = (struct drm_device *)data;
1819 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1820 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1821 struct intel_ring_buffer *ring;
1822 bool err = false, idle;
1823 int i;
893eead0 1824
3e0dc6b0
BW		 1825 if (!i915_enable_hangcheck)
1826 return;
1827
b4519513
CW		 1828 memset(acthd, 0, sizeof(acthd));
1829 idle = true;
1830 for_each_ring(ring, dev_priv, i) {
1831 idle &= i915_hangcheck_ring_idle(ring, &err);
1832 acthd[i] = intel_ring_get_active_head(ring);
1833 }
1834
893eead0 1835 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1836 if (idle) {
d1e61e7f
CW		 1837 if (err) {
1838 if (i915_hangcheck_hung(dev))
1839 return;
1840
893eead0 1841 goto repeat;
d1e61e7f
CW		 1842 }
1843
99584db3 1844 dev_priv->gpu_error.hangcheck_count = 0;
893eead0
CW		 1845 return;
1846 }
b9201c14 1847
bd9854f9 1848 i915_get_extra_instdone(dev, instdone);
99584db3
DV		 1849 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1850 sizeof(acthd)) == 0 &&
1851 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1852 sizeof(instdone)) == 0) {
d1e61e7f 1853 if (i915_hangcheck_hung(dev))
cbb465e7 1854 return;
cbb465e7 1855 } else {
99584db3 1856 dev_priv->gpu_error.hangcheck_count = 0;
cbb465e7 1857
99584db3
DV		 1858 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1859 sizeof(acthd));
1860 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1861 sizeof(instdone));
cbb465e7 1862 }
f65d9421 1863
893eead0 1864repeat:
f65d9421 1865 /* Reset timer case chip hangs without another request being added */
99584db3 1866 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 1867 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1868}
1869
1da177e4
LT		 1870/* drm_dma.h hooks
1871*/
f71d4af4 1872static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1873{
1874 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1875
4697995b
JB		 1876 atomic_set(&dev_priv->irq_received, 0);
1877
036a4a7d 1878 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1879
036a4a7d
ZW		 1880 /* XXX hotplug from PCH */
1881
1882 I915_WRITE(DEIMR, 0xffffffff);
1883 I915_WRITE(DEIER, 0x0);
3143a2bf 1884 POSTING_READ(DEIER);
036a4a7d
ZW		 1885
1886 /* and GT */
1887 I915_WRITE(GTIMR, 0xffffffff);
1888 I915_WRITE(GTIER, 0x0);
3143a2bf 1889 POSTING_READ(GTIER);
c650156a
ZW		 1890
1891 /* south display irq */
1892 I915_WRITE(SDEIMR, 0xffffffff);
1893 I915_WRITE(SDEIER, 0x0);
3143a2bf 1894 POSTING_READ(SDEIER);
036a4a7d
ZW		 1895}
1896
7e231dbe
JB		 1897static void valleyview_irq_preinstall(struct drm_device *dev)
1898{
1899 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1900 int pipe;
1901
1902 atomic_set(&dev_priv->irq_received, 0);
1903
7e231dbe
JB		 1904 /* VLV magic */
1905 I915_WRITE(VLV_IMR, 0);
1906 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1907 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1908 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1909
7e231dbe
JB		 1910 /* and GT */
1911 I915_WRITE(GTIIR, I915_READ(GTIIR));
1912 I915_WRITE(GTIIR, I915_READ(GTIIR));
1913 I915_WRITE(GTIMR, 0xffffffff);
1914 I915_WRITE(GTIER, 0x0);
1915 POSTING_READ(GTIER);
1916
1917 I915_WRITE(DPINVGTT, 0xff);
1918
1919 I915_WRITE(PORT_HOTPLUG_EN, 0);
1920 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1921 for_each_pipe(pipe)
1922 I915_WRITE(PIPESTAT(pipe), 0xffff);
1923 I915_WRITE(VLV_IIR, 0xffffffff);
1924 I915_WRITE(VLV_IMR, 0xffffffff);
1925 I915_WRITE(VLV_IER, 0x0);
1926 POSTING_READ(VLV_IER);
1927}
1928
7fe0b973
KP		 1929/*
1930 * Enable digital hotplug on the PCH, and configure the DP short pulse
1931 * duration to 2ms (which is the minimum in the Display Port spec)
1932 *
1933 * This register is the same on all known PCH chips.
1934 */
1935
d46da437 1936static void ibx_enable_hotplug(struct drm_device *dev)
7fe0b973
KP		 1937{
1938 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1939 u32 hotplug;
1940
1941 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1942 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1943 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1944 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1945 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1946 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1947}
1948
d46da437
PZ		 1949static void ibx_irq_postinstall(struct drm_device *dev)
1950{
1951 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1952 u32 mask;
1953
1954 if (HAS_PCH_IBX(dev))
1955 mask = SDE_HOTPLUG_MASK |
1956 SDE_GMBUS |
1957 SDE_AUX_MASK;
1958 else
1959 mask = SDE_HOTPLUG_MASK_CPT |
1960 SDE_GMBUS_CPT |
1961 SDE_AUX_MASK_CPT;
1962
1963 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1964 I915_WRITE(SDEIMR, ~mask);
1965 I915_WRITE(SDEIER, mask);
1966 POSTING_READ(SDEIER);
1967
1968 ibx_enable_hotplug(dev);
1969}
1970
f71d4af4 1971static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1972{
1973 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1974 /* enable kind of interrupts always enabled */
013d5aa2 1975 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256
DV		 1976 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
1977 DE_AUX_CHANNEL_A;
1ec14ad3 1978 u32 render_irqs;
036a4a7d 1979
1ec14ad3 1980 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1981
1982 /* should always can generate irq */
1983 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1984 I915_WRITE(DEIMR, dev_priv->irq_mask);
1985 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1986 POSTING_READ(DEIER);
036a4a7d 1987
1ec14ad3 1988 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1989
1990 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1991 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1992
1ec14ad3
CW		 1993 if (IS_GEN6(dev))
1994 render_irqs =
1995 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1996 GEN6_BSD_USER_INTERRUPT |
1997 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1998 else
1999 render_irqs =
88f23b8f 2000 GT_USER_INTERRUPT |
c6df541c 2001 GT_PIPE_NOTIFY |
1ec14ad3
CW		 2002 GT_BSD_USER_INTERRUPT;
2003 I915_WRITE(GTIER, render_irqs);
3143a2bf 2004 POSTING_READ(GTIER);
036a4a7d 2005
d46da437 2006 ibx_irq_postinstall(dev);
7fe0b973 2007
f97108d1
JB		 2008 if (IS_IRONLAKE_M(dev)) {
2009 /* Clear & enable PCU event interrupts */
2010 I915_WRITE(DEIIR, DE_PCU_EVENT);
2011 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2012 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2013 }
2014
036a4a7d
ZW		 2015 return 0;
2016}
2017
f71d4af4 2018static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2019{
2020 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2021 /* enable kind of interrupts always enabled */
b615b57a
CW		 2022 u32 display_mask =
2023 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2024 DE_PLANEC_FLIP_DONE_IVB |
2025 DE_PLANEB_FLIP_DONE_IVB |
ce99c256
DV		 2026 DE_PLANEA_FLIP_DONE_IVB |
2027 DE_AUX_CHANNEL_A_IVB;
b1f14ad0 2028 u32 render_irqs;
b1f14ad0 2029
b1f14ad0
JB		 2030 dev_priv->irq_mask = ~display_mask;
2031
2032 /* should always can generate irq */
2033 I915_WRITE(DEIIR, I915_READ(DEIIR));
2034 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2035 I915_WRITE(DEIER,
2036 display_mask |
2037 DE_PIPEC_VBLANK_IVB |
2038 DE_PIPEB_VBLANK_IVB |
2039 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2040 POSTING_READ(DEIER);
2041
15b9f80e 2042 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2043
2044 I915_WRITE(GTIIR, I915_READ(GTIIR));
2045 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2046
e2a1e2f0 2047 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 2048 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2049 I915_WRITE(GTIER, render_irqs);
2050 POSTING_READ(GTIER);
2051
d46da437 2052 ibx_irq_postinstall(dev);
7fe0b973 2053
b1f14ad0
JB		 2054 return 0;
2055}
2056
7e231dbe
JB		 2057static int valleyview_irq_postinstall(struct drm_device *dev)
2058{
2059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2060 u32 enable_mask;
31acc7f5 2061 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 2062 u32 render_irqs;
7e231dbe
JB		 2063 u16 msid;
2064
2065 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2066 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2067 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2068 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2069 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2070
31acc7f5
JB		 2071 /*
2072 *Leave vblank interrupts masked initially. enable/disable will
2073 * toggle them based on usage.
2074 */
2075 dev_priv->irq_mask = (~enable_mask) |
2076 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2077 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2078
7e231dbe
JB		 2079 /* Hack for broken MSIs on VLV */
2080 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2081 pci_read_config_word(dev->pdev, 0x98, &msid);
2082 msid &= 0xff; /* mask out delivery bits */
2083 msid |= (1<<14);
2084 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2085
20afbda2
DV		 2086 I915_WRITE(PORT_HOTPLUG_EN, 0);
2087 POSTING_READ(PORT_HOTPLUG_EN);
2088
7e231dbe
JB		 2089 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2090 I915_WRITE(VLV_IER, enable_mask);
2091 I915_WRITE(VLV_IIR, 0xffffffff);
2092 I915_WRITE(PIPESTAT(0), 0xffff);
2093 I915_WRITE(PIPESTAT(1), 0xffff);
2094 POSTING_READ(VLV_IER);
2095
31acc7f5 2096 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2097 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2098 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2099
7e231dbe
JB		 2100 I915_WRITE(VLV_IIR, 0xffffffff);
2101 I915_WRITE(VLV_IIR, 0xffffffff);
2102
7e231dbe 2103 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2104 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2105
2106 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2107 GEN6_BLITTER_USER_INTERRUPT;
2108 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2109 POSTING_READ(GTIER);
2110
2111 /* ack & enable invalid PTE error interrupts */
2112#if 0 /* FIXME: add support to irq handler for checking these bits */
2113 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2114 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2115#endif
2116
2117 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2118
2119 return 0;
2120}
2121
2122static void valleyview_hpd_irq_setup(struct drm_device *dev)
2123{
2124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2125 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2126
7e231dbe 2127 /* Note HDMI and DP share bits */
26739f12
DV		 2128 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2129 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2130 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2131 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2132 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2133 hotplug_en |= PORTD_HOTPLUG_INT_EN;
ae33cdcf 2134 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2135 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2136 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2137 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2138 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2139 hotplug_en |= CRT_HOTPLUG_INT_EN;
2140 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2141 }
7e231dbe
JB		 2142
2143 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
7e231dbe
JB		 2144}
2145
7e231dbe
JB		 2146static void valleyview_irq_uninstall(struct drm_device *dev)
2147{
2148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2149 int pipe;
2150
2151 if (!dev_priv)
2152 return;
2153
7e231dbe
JB		 2154 for_each_pipe(pipe)
2155 I915_WRITE(PIPESTAT(pipe), 0xffff);
2156
2157 I915_WRITE(HWSTAM, 0xffffffff);
2158 I915_WRITE(PORT_HOTPLUG_EN, 0);
2159 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2160 for_each_pipe(pipe)
2161 I915_WRITE(PIPESTAT(pipe), 0xffff);
2162 I915_WRITE(VLV_IIR, 0xffffffff);
2163 I915_WRITE(VLV_IMR, 0xffffffff);
2164 I915_WRITE(VLV_IER, 0x0);
2165 POSTING_READ(VLV_IER);
2166}
2167
f71d4af4 2168static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2169{
2170 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2171
2172 if (!dev_priv)
2173 return;
2174
036a4a7d
ZW		 2175 I915_WRITE(HWSTAM, 0xffffffff);
2176
2177 I915_WRITE(DEIMR, 0xffffffff);
2178 I915_WRITE(DEIER, 0x0);
2179 I915_WRITE(DEIIR, I915_READ(DEIIR));
2180
2181 I915_WRITE(GTIMR, 0xffffffff);
2182 I915_WRITE(GTIER, 0x0);
2183 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2184
2185 I915_WRITE(SDEIMR, 0xffffffff);
2186 I915_WRITE(SDEIER, 0x0);
2187 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2188}
2189
a266c7d5 2190static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2191{
2192 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2193 int pipe;
91e3738e 2194
a266c7d5 2195 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2196
9db4a9c7
JB		 2197 for_each_pipe(pipe)
2198 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2199 I915_WRITE16(IMR, 0xffff);
2200 I915_WRITE16(IER, 0x0);
2201 POSTING_READ16(IER);
c2798b19
CW		 2202}
2203
2204static int i8xx_irq_postinstall(struct drm_device *dev)
2205{
2206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2207
c2798b19
CW		 2208 I915_WRITE16(EMR,
2209 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2210
2211 /* Unmask the interrupts that we always want on. */
2212 dev_priv->irq_mask =
2213 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2214 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2215 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2216 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2217 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2218 I915_WRITE16(IMR, dev_priv->irq_mask);
2219
2220 I915_WRITE16(IER,
2221 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2222 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2223 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2224 I915_USER_INTERRUPT);
2225 POSTING_READ16(IER);
2226
2227 return 0;
2228}
2229
90a72f87
VS		 2230/*
2231 * Returns true when a page flip has completed.
2232 */
2233static bool i8xx_handle_vblank(struct drm_device *dev,
2234 int pipe, u16 iir)
2235{
2236 drm_i915_private_t *dev_priv = dev->dev_private;
2237 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2238
2239 if (!drm_handle_vblank(dev, pipe))
2240 return false;
2241
2242 if ((iir & flip_pending) == 0)
2243 return false;
2244
2245 intel_prepare_page_flip(dev, pipe);
2246
2247 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2248 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2249 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2250 * the flip is completed (no longer pending). Since this doesn't raise
2251 * an interrupt per se, we watch for the change at vblank.
2252 */
2253 if (I915_READ16(ISR) & flip_pending)
2254 return false;
2255
2256 intel_finish_page_flip(dev, pipe);
2257
2258 return true;
2259}
2260
ff1f525e 2261static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2262{
2263 struct drm_device *dev = (struct drm_device *) arg;
2264 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2265 u16 iir, new_iir;
2266 u32 pipe_stats[2];
2267 unsigned long irqflags;
2268 int irq_received;
2269 int pipe;
2270 u16 flip_mask =
2271 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2272 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2273
2274 atomic_inc(&dev_priv->irq_received);
2275
2276 iir = I915_READ16(IIR);
2277 if (iir == 0)
2278 return IRQ_NONE;
2279
2280 while (iir & ~flip_mask) {
2281 /* Can't rely on pipestat interrupt bit in iir as it might
2282 * have been cleared after the pipestat interrupt was received.
2283 * It doesn't set the bit in iir again, but it still produces
2284 * interrupts (for non-MSI).
2285 */
2286 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2287 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2288 i915_handle_error(dev, false);
2289
2290 for_each_pipe(pipe) {
2291 int reg = PIPESTAT(pipe);
2292 pipe_stats[pipe] = I915_READ(reg);
2293
2294 /*
2295 * Clear the PIPE*STAT regs before the IIR
2296 */
2297 if (pipe_stats[pipe] & 0x8000ffff) {
2298 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2299 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2300 pipe_name(pipe));
2301 I915_WRITE(reg, pipe_stats[pipe]);
2302 irq_received = 1;
2303 }
2304 }
2305 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2306
2307 I915_WRITE16(IIR, iir & ~flip_mask);
2308 new_iir = I915_READ16(IIR); /* Flush posted writes */
2309
d05c617e 2310 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2311
2312 if (iir & I915_USER_INTERRUPT)
2313 notify_ring(dev, &dev_priv->ring[RCS]);
2314
2315 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2316 i8xx_handle_vblank(dev, 0, iir))
2317 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2318
2319 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2320 i8xx_handle_vblank(dev, 1, iir))
2321 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2322
2323 iir = new_iir;
2324 }
2325
2326 return IRQ_HANDLED;
2327}
2328
2329static void i8xx_irq_uninstall(struct drm_device * dev)
2330{
2331 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2332 int pipe;
2333
c2798b19
CW		 2334 for_each_pipe(pipe) {
2335 /* Clear enable bits; then clear status bits */
2336 I915_WRITE(PIPESTAT(pipe), 0);
2337 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2338 }
2339 I915_WRITE16(IMR, 0xffff);
2340 I915_WRITE16(IER, 0x0);
2341 I915_WRITE16(IIR, I915_READ16(IIR));
2342}
2343
a266c7d5
CW		 2344static void i915_irq_preinstall(struct drm_device * dev)
2345{
2346 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2347 int pipe;
2348
2349 atomic_set(&dev_priv->irq_received, 0);
2350
2351 if (I915_HAS_HOTPLUG(dev)) {
2352 I915_WRITE(PORT_HOTPLUG_EN, 0);
2353 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2354 }
2355
00d98ebd 2356 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2357 for_each_pipe(pipe)
2358 I915_WRITE(PIPESTAT(pipe), 0);
2359 I915_WRITE(IMR, 0xffffffff);
2360 I915_WRITE(IER, 0x0);
2361 POSTING_READ(IER);
2362}
2363
2364static int i915_irq_postinstall(struct drm_device *dev)
2365{
2366 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2367 u32 enable_mask;
a266c7d5 2368
38bde180
CW		 2369 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2370
2371 /* Unmask the interrupts that we always want on. */
2372 dev_priv->irq_mask =
2373 ~(I915_ASLE_INTERRUPT |
2374 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2375 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2376 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2377 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2378 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2379
2380 enable_mask =
2381 I915_ASLE_INTERRUPT |
2382 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2383 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2384 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2385 I915_USER_INTERRUPT;
2386
a266c7d5 2387 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2388 I915_WRITE(PORT_HOTPLUG_EN, 0);
2389 POSTING_READ(PORT_HOTPLUG_EN);
2390
a266c7d5
CW		 2391 /* Enable in IER... */
2392 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2393 /* and unmask in IMR */
2394 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2395 }
2396
a266c7d5
CW		 2397 I915_WRITE(IMR, dev_priv->irq_mask);
2398 I915_WRITE(IER, enable_mask);
2399 POSTING_READ(IER);
2400
20afbda2
DV		 2401 intel_opregion_enable_asle(dev);
2402
2403 return 0;
2404}
2405
2406static void i915_hpd_irq_setup(struct drm_device *dev)
2407{
2408 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2409 u32 hotplug_en;
2410
a266c7d5 2411 if (I915_HAS_HOTPLUG(dev)) {
20afbda2 2412 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
a266c7d5 2413
26739f12
DV		 2414 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2415 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2416 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2417 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2418 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2419 hotplug_en |= PORTD_HOTPLUG_INT_EN;
084b612e 2420 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2421 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2422 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2423 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2424 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2425 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2426 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2427 }
2428
2429 /* Ignore TV since it's buggy */
2430
2431 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2432 }
a266c7d5
CW		 2433}
2434
90a72f87
VS		 2435/*
2436 * Returns true when a page flip has completed.
2437 */
2438static bool i915_handle_vblank(struct drm_device *dev,
2439 int plane, int pipe, u32 iir)
2440{
2441 drm_i915_private_t *dev_priv = dev->dev_private;
2442 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2443
2444 if (!drm_handle_vblank(dev, pipe))
2445 return false;
2446
2447 if ((iir & flip_pending) == 0)
2448 return false;
2449
2450 intel_prepare_page_flip(dev, plane);
2451
2452 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2453 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2454 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2455 * the flip is completed (no longer pending). Since this doesn't raise
2456 * an interrupt per se, we watch for the change at vblank.
2457 */
2458 if (I915_READ(ISR) & flip_pending)
2459 return false;
2460
2461 intel_finish_page_flip(dev, pipe);
2462
2463 return true;
2464}
2465
ff1f525e 2466static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2467{
2468 struct drm_device *dev = (struct drm_device *) arg;
2469 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2470 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2471 unsigned long irqflags;
38bde180
CW		 2472 u32 flip_mask =
2473 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2474 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2475 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2476
2477 atomic_inc(&dev_priv->irq_received);
2478
2479 iir = I915_READ(IIR);
38bde180
CW		 2480 do {
2481 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2482 bool blc_event = false;
a266c7d5
CW		 2483
2484 /* Can't rely on pipestat interrupt bit in iir as it might
2485 * have been cleared after the pipestat interrupt was received.
2486 * It doesn't set the bit in iir again, but it still produces
2487 * interrupts (for non-MSI).
2488 */
2489 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2490 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2491 i915_handle_error(dev, false);
2492
2493 for_each_pipe(pipe) {
2494 int reg = PIPESTAT(pipe);
2495 pipe_stats[pipe] = I915_READ(reg);
2496
38bde180 2497 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2498 if (pipe_stats[pipe] & 0x8000ffff) {
2499 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2500 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2501 pipe_name(pipe));
2502 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2503 irq_received = true;
a266c7d5
CW		 2504 }
2505 }
2506 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2507
2508 if (!irq_received)
2509 break;
2510
a266c7d5
CW		 2511 /* Consume port. Then clear IIR or we'll miss events */
2512 if ((I915_HAS_HOTPLUG(dev)) &&
2513 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2514 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2515
2516 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2517 hotplug_status);
2518 if (hotplug_status & dev_priv->hotplug_supported_mask)
2519 queue_work(dev_priv->wq,
2520 &dev_priv->hotplug_work);
2521
2522 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2523 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2524 }
2525
38bde180 2526 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2527 new_iir = I915_READ(IIR); /* Flush posted writes */
2528
a266c7d5
CW		 2529 if (iir & I915_USER_INTERRUPT)
2530 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2531
a266c7d5 2532 for_each_pipe(pipe) {
38bde180
CW		 2533 int plane = pipe;
2534 if (IS_MOBILE(dev))
2535 plane = !plane;
90a72f87 2536
8291ee90 2537 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2538 i915_handle_vblank(dev, plane, pipe, iir))
2539 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2540
2541 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2542 blc_event = true;
2543 }
2544
a266c7d5
CW		 2545 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2546 intel_opregion_asle_intr(dev);
2547
2548 /* With MSI, interrupts are only generated when iir
2549 * transitions from zero to nonzero. If another bit got
2550 * set while we were handling the existing iir bits, then
2551 * we would never get another interrupt.
2552 *
2553 * This is fine on non-MSI as well, as if we hit this path
2554 * we avoid exiting the interrupt handler only to generate
2555 * another one.
2556 *
2557 * Note that for MSI this could cause a stray interrupt report
2558 * if an interrupt landed in the time between writing IIR and
2559 * the posting read. This should be rare enough to never
2560 * trigger the 99% of 100,000 interrupts test for disabling
2561 * stray interrupts.
2562 */
38bde180 2563 ret = IRQ_HANDLED;
a266c7d5 2564 iir = new_iir;
38bde180 2565 } while (iir & ~flip_mask);
a266c7d5 2566
d05c617e 2567 i915_update_dri1_breadcrumb(dev);
8291ee90 2568
a266c7d5
CW		 2569 return ret;
2570}
2571
2572static void i915_irq_uninstall(struct drm_device * dev)
2573{
2574 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2575 int pipe;
2576
a266c7d5
CW		 2577 if (I915_HAS_HOTPLUG(dev)) {
2578 I915_WRITE(PORT_HOTPLUG_EN, 0);
2579 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2580 }
2581
00d98ebd 2582 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2583 for_each_pipe(pipe) {
2584 /* Clear enable bits; then clear status bits */
a266c7d5 2585 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2586 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2587 }
a266c7d5
CW		 2588 I915_WRITE(IMR, 0xffffffff);
2589 I915_WRITE(IER, 0x0);
2590
a266c7d5
CW		 2591 I915_WRITE(IIR, I915_READ(IIR));
2592}
2593
2594static void i965_irq_preinstall(struct drm_device * dev)
2595{
2596 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2597 int pipe;
2598
2599 atomic_set(&dev_priv->irq_received, 0);
2600
adca4730
CW		 2601 I915_WRITE(PORT_HOTPLUG_EN, 0);
2602 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2603
2604 I915_WRITE(HWSTAM, 0xeffe);
2605 for_each_pipe(pipe)
2606 I915_WRITE(PIPESTAT(pipe), 0);
2607 I915_WRITE(IMR, 0xffffffff);
2608 I915_WRITE(IER, 0x0);
2609 POSTING_READ(IER);
2610}
2611
2612static int i965_irq_postinstall(struct drm_device *dev)
2613{
2614 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2615 u32 enable_mask;
a266c7d5
CW		 2616 u32 error_mask;
2617
a266c7d5 2618 /* Unmask the interrupts that we always want on. */
bbba0a97 2619 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2620 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2621 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2622 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2623 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2624 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2625 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2626
2627 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2628 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2629 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2630 enable_mask |= I915_USER_INTERRUPT;
2631
2632 if (IS_G4X(dev))
2633 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 2634
515ac2bb 2635 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 2636
a266c7d5
CW		 2637 /*
2638 * Enable some error detection, note the instruction error mask
2639 * bit is reserved, so we leave it masked.
2640 */
2641 if (IS_G4X(dev)) {
2642 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2643 GM45_ERROR_MEM_PRIV |
2644 GM45_ERROR_CP_PRIV |
2645 I915_ERROR_MEMORY_REFRESH);
2646 } else {
2647 error_mask = ~(I915_ERROR_PAGE_TABLE |
2648 I915_ERROR_MEMORY_REFRESH);
2649 }
2650 I915_WRITE(EMR, error_mask);
2651
2652 I915_WRITE(IMR, dev_priv->irq_mask);
2653 I915_WRITE(IER, enable_mask);
2654 POSTING_READ(IER);
2655
20afbda2
DV		 2656 I915_WRITE(PORT_HOTPLUG_EN, 0);
2657 POSTING_READ(PORT_HOTPLUG_EN);
2658
2659 intel_opregion_enable_asle(dev);
2660
2661 return 0;
2662}
2663
2664static void i965_hpd_irq_setup(struct drm_device *dev)
2665{
2666 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2667 u32 hotplug_en;
2668
adca4730
CW		 2669 /* Note HDMI and DP share hotplug bits */
2670 hotplug_en = 0;
26739f12
DV		 2671 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2672 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2673 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2674 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2675 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2676 hotplug_en |= PORTD_HOTPLUG_INT_EN;
084b612e
CW		 2677 if (IS_G4X(dev)) {
2678 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2679 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2680 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2681 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2682 } else {
2683 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2684 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2685 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2686 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2687 }
adca4730
CW		 2688 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2689 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2690
adca4730
CW		 2691 /* Programming the CRT detection parameters tends
2692 to generate a spurious hotplug event about three
2693 seconds later. So just do it once.
2694 */
2695 if (IS_G4X(dev))
2696 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2697 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2698 }
a266c7d5 2699
adca4730 2700 /* Ignore TV since it's buggy */
a266c7d5 2701
adca4730 2702 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2703}
2704
ff1f525e 2705static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2706{
2707 struct drm_device *dev = (struct drm_device *) arg;
2708 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2709 u32 iir, new_iir;
2710 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2711 unsigned long irqflags;
2712 int irq_received;
2713 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2714 u32 flip_mask =
2715 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2716 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2717
2718 atomic_inc(&dev_priv->irq_received);
2719
2720 iir = I915_READ(IIR);
2721
a266c7d5 2722 for (;;) {
2c8ba29f
CW		 2723 bool blc_event = false;
2724
21ad8330 2725 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 2726
2727 /* Can't rely on pipestat interrupt bit in iir as it might
2728 * have been cleared after the pipestat interrupt was received.
2729 * It doesn't set the bit in iir again, but it still produces
2730 * interrupts (for non-MSI).
2731 */
2732 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2733 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2734 i915_handle_error(dev, false);
2735
2736 for_each_pipe(pipe) {
2737 int reg = PIPESTAT(pipe);
2738 pipe_stats[pipe] = I915_READ(reg);
2739
2740 /*
2741 * Clear the PIPE*STAT regs before the IIR
2742 */
2743 if (pipe_stats[pipe] & 0x8000ffff) {
2744 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2745 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2746 pipe_name(pipe));
2747 I915_WRITE(reg, pipe_stats[pipe]);
2748 irq_received = 1;
2749 }
2750 }
2751 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2752
2753 if (!irq_received)
2754 break;
2755
2756 ret = IRQ_HANDLED;
2757
2758 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2759 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2760 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2761
2762 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2763 hotplug_status);
2764 if (hotplug_status & dev_priv->hotplug_supported_mask)
2765 queue_work(dev_priv->wq,
2766 &dev_priv->hotplug_work);
2767
2768 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2769 I915_READ(PORT_HOTPLUG_STAT);
2770 }
2771
21ad8330 2772 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2773 new_iir = I915_READ(IIR); /* Flush posted writes */
2774
a266c7d5
CW		 2775 if (iir & I915_USER_INTERRUPT)
2776 notify_ring(dev, &dev_priv->ring[RCS]);
2777 if (iir & I915_BSD_USER_INTERRUPT)
2778 notify_ring(dev, &dev_priv->ring[VCS]);
2779
a266c7d5 2780 for_each_pipe(pipe) {
2c8ba29f 2781 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2782 i915_handle_vblank(dev, pipe, pipe, iir))
2783 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 2784
2785 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2786 blc_event = true;
2787 }
2788
2789
2790 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2791 intel_opregion_asle_intr(dev);
2792
515ac2bb
DV		 2793 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2794 gmbus_irq_handler(dev);
2795
a266c7d5
CW		 2796 /* With MSI, interrupts are only generated when iir
2797 * transitions from zero to nonzero. If another bit got
2798 * set while we were handling the existing iir bits, then
2799 * we would never get another interrupt.
2800 *
2801 * This is fine on non-MSI as well, as if we hit this path
2802 * we avoid exiting the interrupt handler only to generate
2803 * another one.
2804 *
2805 * Note that for MSI this could cause a stray interrupt report
2806 * if an interrupt landed in the time between writing IIR and
2807 * the posting read. This should be rare enough to never
2808 * trigger the 99% of 100,000 interrupts test for disabling
2809 * stray interrupts.
2810 */
2811 iir = new_iir;
2812 }
2813
d05c617e 2814 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2815
a266c7d5
CW		 2816 return ret;
2817}
2818
2819static void i965_irq_uninstall(struct drm_device * dev)
2820{
2821 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2822 int pipe;
2823
2824 if (!dev_priv)
2825 return;
2826
adca4730
CW		 2827 I915_WRITE(PORT_HOTPLUG_EN, 0);
2828 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2829
2830 I915_WRITE(HWSTAM, 0xffffffff);
2831 for_each_pipe(pipe)
2832 I915_WRITE(PIPESTAT(pipe), 0);
2833 I915_WRITE(IMR, 0xffffffff);
2834 I915_WRITE(IER, 0x0);
2835
2836 for_each_pipe(pipe)
2837 I915_WRITE(PIPESTAT(pipe),
2838 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2839 I915_WRITE(IIR, I915_READ(IIR));
2840}
2841
f71d4af4
JB		 2842void intel_irq_init(struct drm_device *dev)
2843{
8b2e326d
CW		 2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845
2846 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 2847 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 2848 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2849 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2850
99584db3
DV		 2851 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2852 i915_hangcheck_elapsed,
61bac78e
DV		 2853 (unsigned long) dev);
2854
97a19a24 2855 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 2856
f71d4af4
JB		 2857 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2858 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2859 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2860 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2861 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2862 }
2863
c3613de9
KP		 2864 if (drm_core_check_feature(dev, DRIVER_MODESET))
2865 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2866 else
2867 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2868 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2869
7e231dbe
JB		 2870 if (IS_VALLEYVIEW(dev)) {
2871 dev->driver->irq_handler = valleyview_irq_handler;
2872 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2873 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2874 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2875 dev->driver->enable_vblank = valleyview_enable_vblank;
2876 dev->driver->disable_vblank = valleyview_disable_vblank;
20afbda2 2877 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
4a06e201 2878 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2879 /* Share pre & uninstall handlers with ILK/SNB */
2880 dev->driver->irq_handler = ivybridge_irq_handler;
2881 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2882 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2883 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2884 dev->driver->enable_vblank = ivybridge_enable_vblank;
2885 dev->driver->disable_vblank = ivybridge_disable_vblank;
2886 } else if (HAS_PCH_SPLIT(dev)) {
2887 dev->driver->irq_handler = ironlake_irq_handler;
2888 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2889 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2890 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2891 dev->driver->enable_vblank = ironlake_enable_vblank;
2892 dev->driver->disable_vblank = ironlake_disable_vblank;
2893 } else {
c2798b19
CW		 2894 if (INTEL_INFO(dev)->gen == 2) {
2895 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2896 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2897 dev->driver->irq_handler = i8xx_irq_handler;
2898 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2899 } else if (INTEL_INFO(dev)->gen == 3) {
2900 dev->driver->irq_preinstall = i915_irq_preinstall;
2901 dev->driver->irq_postinstall = i915_irq_postinstall;
2902 dev->driver->irq_uninstall = i915_irq_uninstall;
2903 dev->driver->irq_handler = i915_irq_handler;
20afbda2 2904 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 2905 } else {
a266c7d5
CW		 2906 dev->driver->irq_preinstall = i965_irq_preinstall;
2907 dev->driver->irq_postinstall = i965_irq_postinstall;
2908 dev->driver->irq_uninstall = i965_irq_uninstall;
2909 dev->driver->irq_handler = i965_irq_handler;
20afbda2 2910 dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
c2798b19 2911 }
f71d4af4
JB		 2912 dev->driver->enable_vblank = i915_enable_vblank;
2913 dev->driver->disable_vblank = i915_disable_vblank;
2914 }
2915}
20afbda2
DV		 2916
2917void intel_hpd_init(struct drm_device *dev)
2918{
2919 struct drm_i915_private *dev_priv = dev->dev_private;
2920
2921 if (dev_priv->display.hpd_irq_setup)
2922 dev_priv->display.hpd_irq_setup(dev);
2923}
Linux kernel - Deliverables
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