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drm/i915: enable SDEIER later
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
b2c88f5b 33#include <linux/circ_buf.h>
760285e7
DH		 34#include <drm/drmP.h>
35#include <drm/i915_drm.h>
1da177e4 36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
e5868a31
EE		 40static const u32 hpd_ibx[] = {
41 [HPD_CRT] = SDE_CRT_HOTPLUG,
42 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
43 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
44 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
45 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
46};
47
48static const u32 hpd_cpt[] = {
49 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
73c352a2 50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
e5868a31
EE		 51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
54};
55
56static const u32 hpd_mask_i915[] = {
57 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
58 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
59 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
60 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
61 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
62 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
63};
64
704cfb87 65static const u32 hpd_status_g4x[] = {
e5868a31
EE		 66 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
67 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
68 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
69 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
70 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
71 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
72};
73
e5868a31
EE		 74static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
75 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
76 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
77 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
78 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
79 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
80 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
81};
82
5c502442 83/* IIR can theoretically queue up two events. Be paranoid. */
f86f3fb0 84#define GEN8_IRQ_RESET_NDX(type, which) do { \
5c502442
PZ		 85 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
86 POSTING_READ(GEN8_##type##_IMR(which)); \
87 I915_WRITE(GEN8_##type##_IER(which), 0); \
88 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
89 POSTING_READ(GEN8_##type##_IIR(which)); \
90 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
91 POSTING_READ(GEN8_##type##_IIR(which)); \
92} while (0)
93
f86f3fb0 94#define GEN5_IRQ_RESET(type) do { \
a9d356a6 95 I915_WRITE(type##IMR, 0xffffffff); \
5c502442 96 POSTING_READ(type##IMR); \
a9d356a6 97 I915_WRITE(type##IER, 0); \
5c502442
PZ		 98 I915_WRITE(type##IIR, 0xffffffff); \
99 POSTING_READ(type##IIR); \
100 I915_WRITE(type##IIR, 0xffffffff); \
101 POSTING_READ(type##IIR); \
a9d356a6
PZ		 102} while (0)
103
337ba017
PZ		 104/*
105 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
106 */
107#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
108 u32 val = I915_READ(reg); \
109 if (val) { \
110 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
111 (reg), val); \
112 I915_WRITE((reg), 0xffffffff); \
113 POSTING_READ(reg); \
114 I915_WRITE((reg), 0xffffffff); \
115 POSTING_READ(reg); \
116 } \
117} while (0)
118
35079899 119#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
337ba017 120 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
35079899
PZ		 121 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
122 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
123 POSTING_READ(GEN8_##type##_IER(which)); \
124} while (0)
125
126#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
337ba017 127 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
35079899
PZ		 128 I915_WRITE(type##IMR, (imr_val)); \
129 I915_WRITE(type##IER, (ier_val)); \
130 POSTING_READ(type##IER); \
131} while (0)
132
036a4a7d 133/* For display hotplug interrupt */
995b6762 134static void
2d1013dd 135ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 136{
4bc9d430
DV		 137 assert_spin_locked(&dev_priv->irq_lock);
138
5d584b2e 139 if (dev_priv->pm.irqs_disabled) {
c67a470b 140 WARN(1, "IRQs disabled\n");
5d584b2e 141 dev_priv->pm.regsave.deimr &= ~mask;
c67a470b
PZ		 142 return;
143 }
144
1ec14ad3
CW		 145 if ((dev_priv->irq_mask & mask) != 0) {
146 dev_priv->irq_mask &= ~mask;
147 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 148 POSTING_READ(DEIMR);
036a4a7d
ZW		 149 }
150}
151
0ff9800a 152static void
2d1013dd 153ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
036a4a7d 154{
4bc9d430
DV		 155 assert_spin_locked(&dev_priv->irq_lock);
156
5d584b2e 157 if (dev_priv->pm.irqs_disabled) {
c67a470b 158 WARN(1, "IRQs disabled\n");
5d584b2e 159 dev_priv->pm.regsave.deimr |= mask;
c67a470b
PZ		 160 return;
161 }
162
1ec14ad3
CW		 163 if ((dev_priv->irq_mask & mask) != mask) {
164 dev_priv->irq_mask |= mask;
165 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 166 POSTING_READ(DEIMR);
036a4a7d
ZW		 167 }
168}
169
43eaea13
PZ		 170/**
171 * ilk_update_gt_irq - update GTIMR
172 * @dev_priv: driver private
173 * @interrupt_mask: mask of interrupt bits to update
174 * @enabled_irq_mask: mask of interrupt bits to enable
175 */
176static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
177 uint32_t interrupt_mask,
178 uint32_t enabled_irq_mask)
179{
180 assert_spin_locked(&dev_priv->irq_lock);
181
5d584b2e 182 if (dev_priv->pm.irqs_disabled) {
c67a470b 183 WARN(1, "IRQs disabled\n");
5d584b2e
PZ		 184 dev_priv->pm.regsave.gtimr &= ~interrupt_mask;
185 dev_priv->pm.regsave.gtimr |= (~enabled_irq_mask &
c67a470b
PZ		 186 interrupt_mask);
187 return;
188 }
189
43eaea13
PZ		 190 dev_priv->gt_irq_mask &= ~interrupt_mask;
191 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
192 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
193 POSTING_READ(GTIMR);
194}
195
196void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
197{
198 ilk_update_gt_irq(dev_priv, mask, mask);
199}
200
201void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
202{
203 ilk_update_gt_irq(dev_priv, mask, 0);
204}
205
edbfdb45
PZ		 206/**
207 * snb_update_pm_irq - update GEN6_PMIMR
208 * @dev_priv: driver private
209 * @interrupt_mask: mask of interrupt bits to update
210 * @enabled_irq_mask: mask of interrupt bits to enable
211 */
212static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
213 uint32_t interrupt_mask,
214 uint32_t enabled_irq_mask)
215{
605cd25b 216 uint32_t new_val;
edbfdb45
PZ		 217
218 assert_spin_locked(&dev_priv->irq_lock);
219
5d584b2e 220 if (dev_priv->pm.irqs_disabled) {
c67a470b 221 WARN(1, "IRQs disabled\n");
5d584b2e
PZ		 222 dev_priv->pm.regsave.gen6_pmimr &= ~interrupt_mask;
223 dev_priv->pm.regsave.gen6_pmimr |= (~enabled_irq_mask &
c67a470b
PZ		 224 interrupt_mask);
225 return;
226 }
227
605cd25b 228 new_val = dev_priv->pm_irq_mask;
f52ecbcf
PZ		 229 new_val &= ~interrupt_mask;
230 new_val |= (~enabled_irq_mask & interrupt_mask);
231
605cd25b
PZ		 232 if (new_val != dev_priv->pm_irq_mask) {
233 dev_priv->pm_irq_mask = new_val;
234 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
f52ecbcf
PZ		 235 POSTING_READ(GEN6_PMIMR);
236 }
edbfdb45
PZ		 237}
238
239void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
240{
241 snb_update_pm_irq(dev_priv, mask, mask);
242}
243
244void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
245{
246 snb_update_pm_irq(dev_priv, mask, 0);
247}
248
8664281b
PZ		 249static bool ivb_can_enable_err_int(struct drm_device *dev)
250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
252 struct intel_crtc *crtc;
253 enum pipe pipe;
254
4bc9d430
DV		 255 assert_spin_locked(&dev_priv->irq_lock);
256
8664281b
PZ		 257 for_each_pipe(pipe) {
258 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
259
260 if (crtc->cpu_fifo_underrun_disabled)
261 return false;
262 }
263
264 return true;
265}
266
267static bool cpt_can_enable_serr_int(struct drm_device *dev)
268{
269 struct drm_i915_private *dev_priv = dev->dev_private;
270 enum pipe pipe;
271 struct intel_crtc *crtc;
272
fee884ed
DV		 273 assert_spin_locked(&dev_priv->irq_lock);
274
8664281b
PZ		 275 for_each_pipe(pipe) {
276 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
277
278 if (crtc->pch_fifo_underrun_disabled)
279 return false;
280 }
281
282 return true;
283}
284
2d9d2b0b
VS		 285static void i9xx_clear_fifo_underrun(struct drm_device *dev, enum pipe pipe)
286{
287 struct drm_i915_private *dev_priv = dev->dev_private;
288 u32 reg = PIPESTAT(pipe);
289 u32 pipestat = I915_READ(reg) & 0x7fff0000;
290
291 assert_spin_locked(&dev_priv->irq_lock);
292
293 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
294 POSTING_READ(reg);
295}
296
8664281b
PZ		 297static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
298 enum pipe pipe, bool enable)
299{
300 struct drm_i915_private *dev_priv = dev->dev_private;
301 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
302 DE_PIPEB_FIFO_UNDERRUN;
303
304 if (enable)
305 ironlake_enable_display_irq(dev_priv, bit);
306 else
307 ironlake_disable_display_irq(dev_priv, bit);
308}
309
310static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
7336df65 311 enum pipe pipe, bool enable)
8664281b
PZ		 312{
313 struct drm_i915_private *dev_priv = dev->dev_private;
8664281b 314 if (enable) {
7336df65
DV		 315 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
316
8664281b
PZ		 317 if (!ivb_can_enable_err_int(dev))
318 return;
319
8664281b
PZ		 320 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
321 } else {
7336df65
DV		 322 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
323
324 /* Change the state _after_ we've read out the current one. */
8664281b 325 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
7336df65
DV		 326
327 if (!was_enabled &&
328 (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
329 DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
330 pipe_name(pipe));
331 }
8664281b
PZ		 332 }
333}
334
38d83c96
DV		 335static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
336 enum pipe pipe, bool enable)
337{
338 struct drm_i915_private *dev_priv = dev->dev_private;
339
340 assert_spin_locked(&dev_priv->irq_lock);
341
342 if (enable)
343 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
344 else
345 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
346 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
347 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
348}
349
fee884ed
DV		 350/**
351 * ibx_display_interrupt_update - update SDEIMR
352 * @dev_priv: driver private
353 * @interrupt_mask: mask of interrupt bits to update
354 * @enabled_irq_mask: mask of interrupt bits to enable
355 */
356static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
357 uint32_t interrupt_mask,
358 uint32_t enabled_irq_mask)
359{
360 uint32_t sdeimr = I915_READ(SDEIMR);
361 sdeimr &= ~interrupt_mask;
362 sdeimr |= (~enabled_irq_mask & interrupt_mask);
363
364 assert_spin_locked(&dev_priv->irq_lock);
365
5d584b2e 366 if (dev_priv->pm.irqs_disabled &&
c67a470b
PZ		 367 (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
368 WARN(1, "IRQs disabled\n");
5d584b2e
PZ		 369 dev_priv->pm.regsave.sdeimr &= ~interrupt_mask;
370 dev_priv->pm.regsave.sdeimr |= (~enabled_irq_mask &
c67a470b
PZ		 371 interrupt_mask);
372 return;
373 }
374
fee884ed
DV		 375 I915_WRITE(SDEIMR, sdeimr);
376 POSTING_READ(SDEIMR);
377}
378#define ibx_enable_display_interrupt(dev_priv, bits) \
379 ibx_display_interrupt_update((dev_priv), (bits), (bits))
380#define ibx_disable_display_interrupt(dev_priv, bits) \
381 ibx_display_interrupt_update((dev_priv), (bits), 0)
382
de28075d
DV		 383static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
384 enum transcoder pch_transcoder,
8664281b
PZ		 385 bool enable)
386{
8664281b 387 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 388 uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
389 SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
8664281b
PZ		 390
391 if (enable)
fee884ed 392 ibx_enable_display_interrupt(dev_priv, bit);
8664281b 393 else
fee884ed 394 ibx_disable_display_interrupt(dev_priv, bit);
8664281b
PZ		 395}
396
397static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
398 enum transcoder pch_transcoder,
399 bool enable)
400{
401 struct drm_i915_private *dev_priv = dev->dev_private;
402
403 if (enable) {
1dd246fb
DV		 404 I915_WRITE(SERR_INT,
405 SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
406
8664281b
PZ		 407 if (!cpt_can_enable_serr_int(dev))
408 return;
409
fee884ed 410 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
8664281b 411 } else {
1dd246fb
DV		 412 uint32_t tmp = I915_READ(SERR_INT);
413 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
414
415 /* Change the state _after_ we've read out the current one. */
fee884ed 416 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
1dd246fb
DV		 417
418 if (!was_enabled &&
419 (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
420 DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
421 transcoder_name(pch_transcoder));
422 }
8664281b 423 }
8664281b
PZ		 424}
425
426/**
427 * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
428 * @dev: drm device
429 * @pipe: pipe
430 * @enable: true if we want to report FIFO underrun errors, false otherwise
431 *
432 * This function makes us disable or enable CPU fifo underruns for a specific
433 * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
434 * reporting for one pipe may also disable all the other CPU error interruts for
435 * the other pipes, due to the fact that there's just one interrupt mask/enable
436 * bit for all the pipes.
437 *
438 * Returns the previous state of underrun reporting.
439 */
f88d42f1
ID		 440bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
441 enum pipe pipe, bool enable)
8664281b
PZ		 442{
443 struct drm_i915_private *dev_priv = dev->dev_private;
444 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 446 bool ret;
447
77961eb9
ID		 448 assert_spin_locked(&dev_priv->irq_lock);
449
8664281b
PZ		 450 ret = !intel_crtc->cpu_fifo_underrun_disabled;
451
452 if (enable == ret)
453 goto done;
454
455 intel_crtc->cpu_fifo_underrun_disabled = !enable;
456
2d9d2b0b
VS		 457 if (enable && (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)))
458 i9xx_clear_fifo_underrun(dev, pipe);
459 else if (IS_GEN5(dev) || IS_GEN6(dev))
8664281b
PZ		 460 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
461 else if (IS_GEN7(dev))
7336df65 462 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
38d83c96
DV		 463 else if (IS_GEN8(dev))
464 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
8664281b
PZ		 465
466done:
f88d42f1
ID		 467 return ret;
468}
469
470bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
471 enum pipe pipe, bool enable)
472{
473 struct drm_i915_private *dev_priv = dev->dev_private;
474 unsigned long flags;
475 bool ret;
476
477 spin_lock_irqsave(&dev_priv->irq_lock, flags);
478 ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
8664281b 479 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
f88d42f1 480
8664281b
PZ		 481 return ret;
482}
483
91d181dd
ID		 484static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
485 enum pipe pipe)
486{
487 struct drm_i915_private *dev_priv = dev->dev_private;
488 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
490
491 return !intel_crtc->cpu_fifo_underrun_disabled;
492}
493
8664281b
PZ		 494/**
495 * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
496 * @dev: drm device
497 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
498 * @enable: true if we want to report FIFO underrun errors, false otherwise
499 *
500 * This function makes us disable or enable PCH fifo underruns for a specific
501 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
502 * underrun reporting for one transcoder may also disable all the other PCH
503 * error interruts for the other transcoders, due to the fact that there's just
504 * one interrupt mask/enable bit for all the transcoders.
505 *
506 * Returns the previous state of underrun reporting.
507 */
508bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
509 enum transcoder pch_transcoder,
510 bool enable)
511{
512 struct drm_i915_private *dev_priv = dev->dev_private;
de28075d
DV		 513 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8664281b
PZ		 515 unsigned long flags;
516 bool ret;
517
de28075d
DV		 518 /*
519 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
520 * has only one pch transcoder A that all pipes can use. To avoid racy
521 * pch transcoder -> pipe lookups from interrupt code simply store the
522 * underrun statistics in crtc A. Since we never expose this anywhere
523 * nor use it outside of the fifo underrun code here using the "wrong"
524 * crtc on LPT won't cause issues.
525 */
8664281b
PZ		 526
527 spin_lock_irqsave(&dev_priv->irq_lock, flags);
528
529 ret = !intel_crtc->pch_fifo_underrun_disabled;
530
531 if (enable == ret)
532 goto done;
533
534 intel_crtc->pch_fifo_underrun_disabled = !enable;
535
536 if (HAS_PCH_IBX(dev))
de28075d 537 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
8664281b
PZ		 538 else
539 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
540
541done:
542 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
543 return ret;
544}
545
546
b5ea642a 547static void
755e9019
ID		 548__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
549 u32 enable_mask, u32 status_mask)
7c463586 550{
46c06a30 551 u32 reg = PIPESTAT(pipe);
755e9019 552 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 553
b79480ba
DV		 554 assert_spin_locked(&dev_priv->irq_lock);
555
755e9019
ID		 556 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
557 status_mask & ~PIPESTAT_INT_STATUS_MASK))
558 return;
559
560 if ((pipestat & enable_mask) == enable_mask)
46c06a30
VS		 561 return;
562
91d181dd
ID		 563 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
564
46c06a30 565 /* Enable the interrupt, clear any pending status */
755e9019 566 pipestat |= enable_mask | status_mask;
46c06a30
VS		 567 I915_WRITE(reg, pipestat);
568 POSTING_READ(reg);
7c463586
KP		 569}
570
b5ea642a 571static void
755e9019
ID		 572__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
573 u32 enable_mask, u32 status_mask)
7c463586 574{
46c06a30 575 u32 reg = PIPESTAT(pipe);
755e9019 576 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
7c463586 577
b79480ba
DV		 578 assert_spin_locked(&dev_priv->irq_lock);
579
755e9019
ID		 580 if (WARN_ON_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
581 status_mask & ~PIPESTAT_INT_STATUS_MASK))
46c06a30
VS		 582 return;
583
755e9019
ID		 584 if ((pipestat & enable_mask) == 0)
585 return;
586
91d181dd
ID		 587 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
588
755e9019 589 pipestat &= ~enable_mask;
46c06a30
VS		 590 I915_WRITE(reg, pipestat);
591 POSTING_READ(reg);
7c463586
KP		 592}
593
10c59c51
ID		 594static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
595{
596 u32 enable_mask = status_mask << 16;
597
598 /*
599 * On pipe A we don't support the PSR interrupt yet, on pipe B the
600 * same bit MBZ.
601 */
602 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
603 return 0;
604
605 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
606 SPRITE0_FLIP_DONE_INT_EN_VLV |
607 SPRITE1_FLIP_DONE_INT_EN_VLV);
608 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
609 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
610 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
611 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
612
613 return enable_mask;
614}
615
755e9019
ID		 616void
617i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
618 u32 status_mask)
619{
620 u32 enable_mask;
621
10c59c51
ID		 622 if (IS_VALLEYVIEW(dev_priv->dev))
623 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
624 status_mask);
625 else
626 enable_mask = status_mask << 16;
755e9019
ID		 627 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
628}
629
630void
631i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
632 u32 status_mask)
633{
634 u32 enable_mask;
635
10c59c51
ID		 636 if (IS_VALLEYVIEW(dev_priv->dev))
637 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
638 status_mask);
639 else
640 enable_mask = status_mask << 16;
755e9019
ID		 641 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
642}
643
01c66889 644/**
f49e38dd 645 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
01c66889 646 */
f49e38dd 647static void i915_enable_asle_pipestat(struct drm_device *dev)
01c66889 648{
2d1013dd 649 struct drm_i915_private *dev_priv = dev->dev_private;
1ec14ad3
CW		 650 unsigned long irqflags;
651
f49e38dd
JN		 652 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
653 return;
654
1ec14ad3 655 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 656
755e9019 657 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
f898780b 658 if (INTEL_INFO(dev)->gen >= 4)
3b6c42e8 659 i915_enable_pipestat(dev_priv, PIPE_A,
755e9019 660 PIPE_LEGACY_BLC_EVENT_STATUS);
1ec14ad3
CW		 661
662 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 663}
664
0a3e67a4
JB		 665/**
666 * i915_pipe_enabled - check if a pipe is enabled
667 * @dev: DRM device
668 * @pipe: pipe to check
669 *
670 * Reading certain registers when the pipe is disabled can hang the chip.
671 * Use this routine to make sure the PLL is running and the pipe is active
672 * before reading such registers if unsure.
673 */
674static int
675i915_pipe_enabled(struct drm_device *dev, int pipe)
676{
2d1013dd 677 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56 678
a01025af
DV		 679 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
680 /* Locking is horribly broken here, but whatever. */
681 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
71f8ba6b 683
a01025af
DV		 684 return intel_crtc->active;
685 } else {
686 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
687 }
0a3e67a4
JB		 688}
689
4cdb83ec
VS		 690static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
691{
692 /* Gen2 doesn't have a hardware frame counter */
693 return 0;
694}
695
42f52ef8
KP		 696/* Called from drm generic code, passed a 'crtc', which
697 * we use as a pipe index
698 */
f71d4af4 699static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4 700{
2d1013dd 701 struct drm_i915_private *dev_priv = dev->dev_private;
0a3e67a4
JB		 702 unsigned long high_frame;
703 unsigned long low_frame;
391f75e2 704 u32 high1, high2, low, pixel, vbl_start;
0a3e67a4
JB		 705
706 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 707 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 708 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 709 return 0;
710 }
711
391f75e2
VS		 712 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
713 struct intel_crtc *intel_crtc =
714 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
715 const struct drm_display_mode *mode =
716 &intel_crtc->config.adjusted_mode;
717
718 vbl_start = mode->crtc_vblank_start * mode->crtc_htotal;
719 } else {
a2d213dd 720 enum transcoder cpu_transcoder = (enum transcoder) pipe;
391f75e2
VS		 721 u32 htotal;
722
723 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
724 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
725
726 vbl_start *= htotal;
727 }
728
9db4a9c7
JB		 729 high_frame = PIPEFRAME(pipe);
730 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 731
0a3e67a4
JB		 732 /*
733 * High & low register fields aren't synchronized, so make sure
734 * we get a low value that's stable across two reads of the high
735 * register.
736 */
737 do {
5eddb70b 738 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
391f75e2 739 low = I915_READ(low_frame);
5eddb70b 740 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 741 } while (high1 != high2);
742
5eddb70b 743 high1 >>= PIPE_FRAME_HIGH_SHIFT;
391f75e2 744 pixel = low & PIPE_PIXEL_MASK;
5eddb70b 745 low >>= PIPE_FRAME_LOW_SHIFT;
391f75e2
VS		 746
747 /*
748 * The frame counter increments at beginning of active.
749 * Cook up a vblank counter by also checking the pixel
750 * counter against vblank start.
751 */
edc08d0a 752 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
0a3e67a4
JB		 753}
754
f71d4af4 755static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5 756{
2d1013dd 757 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 758 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 759
760 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 761 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 762 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 763 return 0;
764 }
765
766 return I915_READ(reg);
767}
768
ad3543ed
MK		 769/* raw reads, only for fast reads of display block, no need for forcewake etc. */
770#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
ad3543ed 771
095163ba 772static bool ilk_pipe_in_vblank_locked(struct drm_device *dev, enum pipe pipe)
54ddcbd2
VS		 773{
774 struct drm_i915_private *dev_priv = dev->dev_private;
775 uint32_t status;
24302624
VS		 776 int reg;
777
778 if (INTEL_INFO(dev)->gen >= 8) {
779 status = GEN8_PIPE_VBLANK;
780 reg = GEN8_DE_PIPE_ISR(pipe);
781 } else if (INTEL_INFO(dev)->gen >= 7) {
782 status = DE_PIPE_VBLANK_IVB(pipe);
783 reg = DEISR;
54ddcbd2 784 } else {
24302624
VS		 785 status = DE_PIPE_VBLANK(pipe);
786 reg = DEISR;
54ddcbd2 787 }
ad3543ed 788
24302624 789 return __raw_i915_read32(dev_priv, reg) & status;
54ddcbd2
VS		 790}
791
f71d4af4 792static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
abca9e45
VS		 793 unsigned int flags, int *vpos, int *hpos,
794 ktime_t *stime, ktime_t *etime)
0af7e4df 795{
c2baf4b7
VS		 796 struct drm_i915_private *dev_priv = dev->dev_private;
797 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
799 const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
3aa18df8 800 int position;
0af7e4df
MK		 801 int vbl_start, vbl_end, htotal, vtotal;
802 bool in_vbl = true;
803 int ret = 0;
ad3543ed 804 unsigned long irqflags;
0af7e4df 805
c2baf4b7 806 if (!intel_crtc->active) {
0af7e4df 807 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 808 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 809 return 0;
810 }
811
c2baf4b7
VS		 812 htotal = mode->crtc_htotal;
813 vtotal = mode->crtc_vtotal;
814 vbl_start = mode->crtc_vblank_start;
815 vbl_end = mode->crtc_vblank_end;
0af7e4df 816
d31faf65
VS		 817 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
818 vbl_start = DIV_ROUND_UP(vbl_start, 2);
819 vbl_end /= 2;
820 vtotal /= 2;
821 }
822
c2baf4b7
VS		 823 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
824
ad3543ed
MK		 825 /*
826 * Lock uncore.lock, as we will do multiple timing critical raw
827 * register reads, potentially with preemption disabled, so the
828 * following code must not block on uncore.lock.
829 */
830 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
831
832 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
833
834 /* Get optional system timestamp before query. */
835 if (stime)
836 *stime = ktime_get();
837
7c06b08a 838 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
0af7e4df
MK		 839 /* No obvious pixelcount register. Only query vertical
840 * scanout position from Display scan line register.
841 */
7c06b08a 842 if (IS_GEN2(dev))
ad3543ed 843 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
7c06b08a 844 else
ad3543ed 845 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
54ddcbd2 846
fcb81823
VS		 847 if (HAS_DDI(dev)) {
848 /*
849 * On HSW HDMI outputs there seems to be a 2 line
850 * difference, whereas eDP has the normal 1 line
851 * difference that earlier platforms have. External
852 * DP is unknown. For now just check for the 2 line
853 * difference case on all output types on HSW+.
854 *
855 * This might misinterpret the scanline counter being
856 * one line too far along on eDP, but that's less
857 * dangerous than the alternative since that would lead
858 * the vblank timestamp code astray when it sees a
859 * scanline count before vblank_start during a vblank
860 * interrupt.
861 */
862 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
863 if ((in_vbl && (position == vbl_start - 2 ||
864 position == vbl_start - 1)) ||
865 (!in_vbl && (position == vbl_end - 2 ||
866 position == vbl_end - 1)))
867 position = (position + 2) % vtotal;
868 } else if (HAS_PCH_SPLIT(dev)) {
095163ba
VS		 869 /*
870 * The scanline counter increments at the leading edge
871 * of hsync, ie. it completely misses the active portion
872 * of the line. Fix up the counter at both edges of vblank
873 * to get a more accurate picture whether we're in vblank
874 * or not.
875 */
876 in_vbl = ilk_pipe_in_vblank_locked(dev, pipe);
877 if ((in_vbl && position == vbl_start - 1) ||
878 (!in_vbl && position == vbl_end - 1))
879 position = (position + 1) % vtotal;
880 } else {
881 /*
882 * ISR vblank status bits don't work the way we'd want
883 * them to work on non-PCH platforms (for
884 * ilk_pipe_in_vblank_locked()), and there doesn't
885 * appear any other way to determine if we're currently
886 * in vblank.
887 *
888 * Instead let's assume that we're already in vblank if
889 * we got called from the vblank interrupt and the
890 * scanline counter value indicates that we're on the
891 * line just prior to vblank start. This should result
892 * in the correct answer, unless the vblank interrupt
893 * delivery really got delayed for almost exactly one
894 * full frame/field.
895 */
896 if (flags & DRM_CALLED_FROM_VBLIRQ &&
897 position == vbl_start - 1) {
898 position = (position + 1) % vtotal;
899
900 /* Signal this correction as "applied". */
901 ret |= 0x8;
902 }
903 }
0af7e4df
MK		 904 } else {
905 /* Have access to pixelcount since start of frame.
906 * We can split this into vertical and horizontal
907 * scanout position.
908 */
ad3543ed 909 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
0af7e4df 910
3aa18df8
VS		 911 /* convert to pixel counts */
912 vbl_start *= htotal;
913 vbl_end *= htotal;
914 vtotal *= htotal;
0af7e4df
MK		 915 }
916
ad3543ed
MK		 917 /* Get optional system timestamp after query. */
918 if (etime)
919 *etime = ktime_get();
920
921 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
922
923 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
924
3aa18df8
VS		 925 in_vbl = position >= vbl_start && position < vbl_end;
926
927 /*
928 * While in vblank, position will be negative
929 * counting up towards 0 at vbl_end. And outside
930 * vblank, position will be positive counting
931 * up since vbl_end.
932 */
933 if (position >= vbl_start)
934 position -= vbl_end;
935 else
936 position += vtotal - vbl_end;
0af7e4df 937
7c06b08a 938 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3aa18df8
VS		 939 *vpos = position;
940 *hpos = 0;
941 } else {
942 *vpos = position / htotal;
943 *hpos = position - (*vpos * htotal);
944 }
0af7e4df 945
0af7e4df
MK		 946 /* In vblank? */
947 if (in_vbl)
948 ret |= DRM_SCANOUTPOS_INVBL;
949
950 return ret;
951}
952
f71d4af4 953static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 954 int *max_error,
955 struct timeval *vblank_time,
956 unsigned flags)
957{
4041b853 958 struct drm_crtc *crtc;
0af7e4df 959
7eb552ae 960 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 961 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 962 return -EINVAL;
963 }
964
965 /* Get drm_crtc to timestamp: */
4041b853
CW		 966 crtc = intel_get_crtc_for_pipe(dev, pipe);
967 if (crtc == NULL) {
968 DRM_ERROR("Invalid crtc %d\n", pipe);
969 return -EINVAL;
970 }
971
972 if (!crtc->enabled) {
973 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
974 return -EBUSY;
975 }
0af7e4df
MK		 976
977 /* Helper routine in DRM core does all the work: */
4041b853
CW		 978 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
979 vblank_time, flags,
7da903ef
VS		 980 crtc,
981 &to_intel_crtc(crtc)->config.adjusted_mode);
0af7e4df
MK		 982}
983
67c347ff
JN		 984static bool intel_hpd_irq_event(struct drm_device *dev,
985 struct drm_connector *connector)
321a1b30
EE		 986{
987 enum drm_connector_status old_status;
988
989 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
990 old_status = connector->status;
991
992 connector->status = connector->funcs->detect(connector, false);
67c347ff
JN		 993 if (old_status == connector->status)
994 return false;
995
996 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
321a1b30
EE		 997 connector->base.id,
998 drm_get_connector_name(connector),
67c347ff
JN		 999 drm_get_connector_status_name(old_status),
1000 drm_get_connector_status_name(connector->status));
1001
1002 return true;
321a1b30
EE		 1003}
1004
5ca58282
JB		 1005/*
1006 * Handle hotplug events outside the interrupt handler proper.
1007 */
ac4c16c5
EE		 1008#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1009
5ca58282
JB		 1010static void i915_hotplug_work_func(struct work_struct *work)
1011{
2d1013dd
JN		 1012 struct drm_i915_private *dev_priv =
1013 container_of(work, struct drm_i915_private, hotplug_work);
5ca58282 1014 struct drm_device *dev = dev_priv->dev;
c31c4ba3 1015 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed
EE		 1016 struct intel_connector *intel_connector;
1017 struct intel_encoder *intel_encoder;
1018 struct drm_connector *connector;
1019 unsigned long irqflags;
1020 bool hpd_disabled = false;
321a1b30 1021 bool changed = false;
142e2398 1022 u32 hpd_event_bits;
4ef69c7a 1023
52d7eced
DV		 1024 /* HPD irq before everything is fully set up. */
1025 if (!dev_priv->enable_hotplug_processing)
1026 return;
1027
a65e34c7 1028 mutex_lock(&mode_config->mutex);
e67189ab
JB		 1029 DRM_DEBUG_KMS("running encoder hotplug functions\n");
1030
cd569aed 1031 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
142e2398
EE		 1032
1033 hpd_event_bits = dev_priv->hpd_event_bits;
1034 dev_priv->hpd_event_bits = 0;
cd569aed
EE		 1035 list_for_each_entry(connector, &mode_config->connector_list, head) {
1036 intel_connector = to_intel_connector(connector);
1037 intel_encoder = intel_connector->encoder;
1038 if (intel_encoder->hpd_pin > HPD_NONE &&
1039 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1040 connector->polled == DRM_CONNECTOR_POLL_HPD) {
1041 DRM_INFO("HPD interrupt storm detected on connector %s: "
1042 "switching from hotplug detection to polling\n",
1043 drm_get_connector_name(connector));
1044 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1045 connector->polled = DRM_CONNECTOR_POLL_CONNECT
1046 | DRM_CONNECTOR_POLL_DISCONNECT;
1047 hpd_disabled = true;
1048 }
142e2398
EE		 1049 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1050 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1051 drm_get_connector_name(connector), intel_encoder->hpd_pin);
1052 }
cd569aed
EE		 1053 }
1054 /* if there were no outputs to poll, poll was disabled,
1055 * therefore make sure it's enabled when disabling HPD on
1056 * some connectors */
ac4c16c5 1057 if (hpd_disabled) {
cd569aed 1058 drm_kms_helper_poll_enable(dev);
ac4c16c5
EE		 1059 mod_timer(&dev_priv->hotplug_reenable_timer,
1060 jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1061 }
cd569aed
EE		 1062
1063 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1064
321a1b30
EE		 1065 list_for_each_entry(connector, &mode_config->connector_list, head) {
1066 intel_connector = to_intel_connector(connector);
1067 intel_encoder = intel_connector->encoder;
1068 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1069 if (intel_encoder->hot_plug)
1070 intel_encoder->hot_plug(intel_encoder);
1071 if (intel_hpd_irq_event(dev, connector))
1072 changed = true;
1073 }
1074 }
40ee3381
KP		 1075 mutex_unlock(&mode_config->mutex);
1076
321a1b30
EE		 1077 if (changed)
1078 drm_kms_helper_hotplug_event(dev);
5ca58282
JB		 1079}
1080
3ca1cced
VS		 1081static void intel_hpd_irq_uninstall(struct drm_i915_private *dev_priv)
1082{
1083 del_timer_sync(&dev_priv->hotplug_reenable_timer);
1084}
1085
d0ecd7e2 1086static void ironlake_rps_change_irq_handler(struct drm_device *dev)
f97108d1 1087{
2d1013dd 1088 struct drm_i915_private *dev_priv = dev->dev_private;
b5b72e89 1089 u32 busy_up, busy_down, max_avg, min_avg;
9270388e 1090 u8 new_delay;
9270388e 1091
d0ecd7e2 1092 spin_lock(&mchdev_lock);
f97108d1 1093
73edd18f
DV		 1094 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1095
20e4d407 1096 new_delay = dev_priv->ips.cur_delay;
9270388e 1097
7648fa99 1098 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 1099 busy_up = I915_READ(RCPREVBSYTUPAVG);
1100 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 1101 max_avg = I915_READ(RCBMAXAVG);
1102 min_avg = I915_READ(RCBMINAVG);
1103
1104 /* Handle RCS change request from hw */
b5b72e89 1105 if (busy_up > max_avg) {
20e4d407
DV		 1106 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1107 new_delay = dev_priv->ips.cur_delay - 1;
1108 if (new_delay < dev_priv->ips.max_delay)
1109 new_delay = dev_priv->ips.max_delay;
b5b72e89 1110 } else if (busy_down < min_avg) {
20e4d407
DV		 1111 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1112 new_delay = dev_priv->ips.cur_delay + 1;
1113 if (new_delay > dev_priv->ips.min_delay)
1114 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 1115 }
1116
7648fa99 1117 if (ironlake_set_drps(dev, new_delay))
20e4d407 1118 dev_priv->ips.cur_delay = new_delay;
f97108d1 1119
d0ecd7e2 1120 spin_unlock(&mchdev_lock);
9270388e 1121
f97108d1
JB		 1122 return;
1123}
1124
549f7365
CW		 1125static void notify_ring(struct drm_device *dev,
1126 struct intel_ring_buffer *ring)
1127{
475553de
CW		 1128 if (ring->obj == NULL)
1129 return;
1130
814e9b57 1131 trace_i915_gem_request_complete(ring);
9862e600 1132
549f7365 1133 wake_up_all(&ring->irq_queue);
10cd45b6 1134 i915_queue_hangcheck(dev);
549f7365
CW		 1135}
1136
4912d041 1137static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 1138{
2d1013dd
JN		 1139 struct drm_i915_private *dev_priv =
1140 container_of(work, struct drm_i915_private, rps.work);
edbfdb45 1141 u32 pm_iir;
dd75fdc8 1142 int new_delay, adj;
4912d041 1143
59cdb63d 1144 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3
DV		 1145 pm_iir = dev_priv->rps.pm_iir;
1146 dev_priv->rps.pm_iir = 0;
4848405c 1147 /* Make sure not to corrupt PMIMR state used by ringbuffer code */
a6706b45 1148 snb_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
59cdb63d 1149 spin_unlock_irq(&dev_priv->irq_lock);
3b8d8d91 1150
60611c13 1151 /* Make sure we didn't queue anything we're not going to process. */
a6706b45 1152 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
60611c13 1153
a6706b45 1154 if ((pm_iir & dev_priv->pm_rps_events) == 0)
3b8d8d91
JB		 1155 return;
1156
4fc688ce 1157 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6 1158
dd75fdc8 1159 adj = dev_priv->rps.last_adj;
7425034a 1160 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
dd75fdc8
CW		 1161 if (adj > 0)
1162 adj *= 2;
1163 else
1164 adj = 1;
b39fb297 1165 new_delay = dev_priv->rps.cur_freq + adj;
7425034a
VS		 1166
1167 /*
1168 * For better performance, jump directly
1169 * to RPe if we're below it.
1170 */
b39fb297
BW		 1171 if (new_delay < dev_priv->rps.efficient_freq)
1172 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1173 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
b39fb297
BW		 1174 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1175 new_delay = dev_priv->rps.efficient_freq;
dd75fdc8 1176 else
b39fb297 1177 new_delay = dev_priv->rps.min_freq_softlimit;
dd75fdc8
CW		 1178 adj = 0;
1179 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1180 if (adj < 0)
1181 adj *= 2;
1182 else
1183 adj = -1;
b39fb297 1184 new_delay = dev_priv->rps.cur_freq + adj;
dd75fdc8 1185 } else { /* unknown event */
b39fb297 1186 new_delay = dev_priv->rps.cur_freq;
dd75fdc8 1187 }
3b8d8d91 1188
79249636
BW		 1189 /* sysfs frequency interfaces may have snuck in while servicing the
1190 * interrupt
1191 */
1272e7b8 1192 new_delay = clamp_t(int, new_delay,
b39fb297
BW		 1193 dev_priv->rps.min_freq_softlimit,
1194 dev_priv->rps.max_freq_softlimit);
27544369 1195
b39fb297 1196 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
dd75fdc8
CW		 1197
1198 if (IS_VALLEYVIEW(dev_priv->dev))
1199 valleyview_set_rps(dev_priv->dev, new_delay);
1200 else
1201 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 1202
4fc688ce 1203 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 1204}
1205
e3689190
BW		 1206
1207/**
1208 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1209 * occurred.
1210 * @work: workqueue struct
1211 *
1212 * Doesn't actually do anything except notify userspace. As a consequence of
1213 * this event, userspace should try to remap the bad rows since statistically
1214 * it is likely the same row is more likely to go bad again.
1215 */
1216static void ivybridge_parity_work(struct work_struct *work)
1217{
2d1013dd
JN		 1218 struct drm_i915_private *dev_priv =
1219 container_of(work, struct drm_i915_private, l3_parity.error_work);
e3689190 1220 u32 error_status, row, bank, subbank;
35a85ac6 1221 char *parity_event[6];
e3689190
BW		 1222 uint32_t misccpctl;
1223 unsigned long flags;
35a85ac6 1224 uint8_t slice = 0;
e3689190
BW		 1225
1226 /* We must turn off DOP level clock gating to access the L3 registers.
1227 * In order to prevent a get/put style interface, acquire struct mutex
1228 * any time we access those registers.
1229 */
1230 mutex_lock(&dev_priv->dev->struct_mutex);
1231
35a85ac6
BW		 1232 /* If we've screwed up tracking, just let the interrupt fire again */
1233 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1234 goto out;
1235
e3689190
BW		 1236 misccpctl = I915_READ(GEN7_MISCCPCTL);
1237 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1238 POSTING_READ(GEN7_MISCCPCTL);
1239
35a85ac6
BW		 1240 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1241 u32 reg;
e3689190 1242
35a85ac6
BW		 1243 slice--;
1244 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1245 break;
e3689190 1246
35a85ac6 1247 dev_priv->l3_parity.which_slice &= ~(1<<slice);
e3689190 1248
35a85ac6 1249 reg = GEN7_L3CDERRST1 + (slice * 0x200);
e3689190 1250
35a85ac6
BW		 1251 error_status = I915_READ(reg);
1252 row = GEN7_PARITY_ERROR_ROW(error_status);
1253 bank = GEN7_PARITY_ERROR_BANK(error_status);
1254 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1255
1256 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1257 POSTING_READ(reg);
1258
1259 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1260 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1261 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1262 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1263 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1264 parity_event[5] = NULL;
1265
5bdebb18 1266 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
35a85ac6 1267 KOBJ_CHANGE, parity_event);
e3689190 1268
35a85ac6
BW		 1269 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1270 slice, row, bank, subbank);
e3689190 1271
35a85ac6
BW		 1272 kfree(parity_event[4]);
1273 kfree(parity_event[3]);
1274 kfree(parity_event[2]);
1275 kfree(parity_event[1]);
1276 }
e3689190 1277
35a85ac6 1278 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
e3689190 1279
35a85ac6
BW		 1280out:
1281 WARN_ON(dev_priv->l3_parity.which_slice);
1282 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1283 ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1284 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1285
1286 mutex_unlock(&dev_priv->dev->struct_mutex);
e3689190
BW		 1287}
1288
35a85ac6 1289static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
e3689190 1290{
2d1013dd 1291 struct drm_i915_private *dev_priv = dev->dev_private;
e3689190 1292
040d2baa 1293 if (!HAS_L3_DPF(dev))
e3689190
BW		 1294 return;
1295
d0ecd7e2 1296 spin_lock(&dev_priv->irq_lock);
35a85ac6 1297 ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
d0ecd7e2 1298 spin_unlock(&dev_priv->irq_lock);
e3689190 1299
35a85ac6
BW		 1300 iir &= GT_PARITY_ERROR(dev);
1301 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1302 dev_priv->l3_parity.which_slice |= 1 << 1;
1303
1304 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1305 dev_priv->l3_parity.which_slice |= 1 << 0;
1306
a4da4fa4 1307 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 1308}
1309
f1af8fc1
PZ		 1310static void ilk_gt_irq_handler(struct drm_device *dev,
1311 struct drm_i915_private *dev_priv,
1312 u32 gt_iir)
1313{
1314 if (gt_iir &
1315 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1316 notify_ring(dev, &dev_priv->ring[RCS]);
1317 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1318 notify_ring(dev, &dev_priv->ring[VCS]);
1319}
1320
e7b4c6b1
DV		 1321static void snb_gt_irq_handler(struct drm_device *dev,
1322 struct drm_i915_private *dev_priv,
1323 u32 gt_iir)
1324{
1325
cc609d5d
BW		 1326 if (gt_iir &
1327 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
e7b4c6b1 1328 notify_ring(dev, &dev_priv->ring[RCS]);
cc609d5d 1329 if (gt_iir & GT_BSD_USER_INTERRUPT)
e7b4c6b1 1330 notify_ring(dev, &dev_priv->ring[VCS]);
cc609d5d 1331 if (gt_iir & GT_BLT_USER_INTERRUPT)
e7b4c6b1
DV		 1332 notify_ring(dev, &dev_priv->ring[BCS]);
1333
cc609d5d
BW		 1334 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1335 GT_BSD_CS_ERROR_INTERRUPT |
1336 GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
58174462
MK		 1337 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1338 gt_iir);
e7b4c6b1 1339 }
e3689190 1340
35a85ac6
BW		 1341 if (gt_iir & GT_PARITY_ERROR(dev))
1342 ivybridge_parity_error_irq_handler(dev, gt_iir);
e7b4c6b1
DV		 1343}
1344
abd58f01
BW		 1345static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1346 struct drm_i915_private *dev_priv,
1347 u32 master_ctl)
1348{
1349 u32 rcs, bcs, vcs;
1350 uint32_t tmp = 0;
1351 irqreturn_t ret = IRQ_NONE;
1352
1353 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1354 tmp = I915_READ(GEN8_GT_IIR(0));
1355 if (tmp) {
1356 ret = IRQ_HANDLED;
1357 rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1358 bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1359 if (rcs & GT_RENDER_USER_INTERRUPT)
1360 notify_ring(dev, &dev_priv->ring[RCS]);
1361 if (bcs & GT_RENDER_USER_INTERRUPT)
1362 notify_ring(dev, &dev_priv->ring[BCS]);
1363 I915_WRITE(GEN8_GT_IIR(0), tmp);
1364 } else
1365 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1366 }
1367
1368 if (master_ctl & GEN8_GT_VCS1_IRQ) {
1369 tmp = I915_READ(GEN8_GT_IIR(1));
1370 if (tmp) {
1371 ret = IRQ_HANDLED;
1372 vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1373 if (vcs & GT_RENDER_USER_INTERRUPT)
1374 notify_ring(dev, &dev_priv->ring[VCS]);
1375 I915_WRITE(GEN8_GT_IIR(1), tmp);
1376 } else
1377 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1378 }
1379
1380 if (master_ctl & GEN8_GT_VECS_IRQ) {
1381 tmp = I915_READ(GEN8_GT_IIR(3));
1382 if (tmp) {
1383 ret = IRQ_HANDLED;
1384 vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1385 if (vcs & GT_RENDER_USER_INTERRUPT)
1386 notify_ring(dev, &dev_priv->ring[VECS]);
1387 I915_WRITE(GEN8_GT_IIR(3), tmp);
1388 } else
1389 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1390 }
1391
1392 return ret;
1393}
1394
b543fb04
EE		 1395#define HPD_STORM_DETECT_PERIOD 1000
1396#define HPD_STORM_THRESHOLD 5
1397
10a504de 1398static inline void intel_hpd_irq_handler(struct drm_device *dev,
22062dba
DV		 1399 u32 hotplug_trigger,
1400 const u32 *hpd)
b543fb04 1401{
2d1013dd 1402 struct drm_i915_private *dev_priv = dev->dev_private;
b543fb04 1403 int i;
10a504de 1404 bool storm_detected = false;
b543fb04 1405
91d131d2
DV		 1406 if (!hotplug_trigger)
1407 return;
1408
cc9bd499
ID		 1409 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1410 hotplug_trigger);
1411
b5ea2d56 1412 spin_lock(&dev_priv->irq_lock);
b543fb04 1413 for (i = 1; i < HPD_NUM_PINS; i++) {
821450c6 1414
3432087e 1415 WARN_ONCE(hpd[i] & hotplug_trigger &&
8b5565b8 1416 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED,
cba1c073
CW		 1417 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1418 hotplug_trigger, i, hpd[i]);
b8f102e8 1419
b543fb04
EE		 1420 if (!(hpd[i] & hotplug_trigger) ||
1421 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1422 continue;
1423
bc5ead8c 1424 dev_priv->hpd_event_bits |= (1 << i);
b543fb04
EE		 1425 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1426 dev_priv->hpd_stats[i].hpd_last_jiffies
1427 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1428 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1429 dev_priv->hpd_stats[i].hpd_cnt = 0;
b8f102e8 1430 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
b543fb04
EE		 1431 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1432 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
142e2398 1433 dev_priv->hpd_event_bits &= ~(1 << i);
b543fb04 1434 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
10a504de 1435 storm_detected = true;
b543fb04
EE		 1436 } else {
1437 dev_priv->hpd_stats[i].hpd_cnt++;
b8f102e8
EE		 1438 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1439 dev_priv->hpd_stats[i].hpd_cnt);
b543fb04
EE		 1440 }
1441 }
1442
10a504de
DV		 1443 if (storm_detected)
1444 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 1445 spin_unlock(&dev_priv->irq_lock);
5876fa0d 1446
645416f5
DV		 1447 /*
1448 * Our hotplug handler can grab modeset locks (by calling down into the
1449 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1450 * queue for otherwise the flush_work in the pageflip code will
1451 * deadlock.
1452 */
1453 schedule_work(&dev_priv->hotplug_work);
b543fb04
EE		 1454}
1455
515ac2bb
DV		 1456static void gmbus_irq_handler(struct drm_device *dev)
1457{
2d1013dd 1458 struct drm_i915_private *dev_priv = dev->dev_private;
28c70f16 1459
28c70f16 1460 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 1461}
1462
ce99c256
DV		 1463static void dp_aux_irq_handler(struct drm_device *dev)
1464{
2d1013dd 1465 struct drm_i915_private *dev_priv = dev->dev_private;
9ee32fea 1466
9ee32fea 1467 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 1468}
1469
8bf1e9f1 1470#if defined(CONFIG_DEBUG_FS)
277de95e
DV		 1471static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1472 uint32_t crc0, uint32_t crc1,
1473 uint32_t crc2, uint32_t crc3,
1474 uint32_t crc4)
8bf1e9f1
SH		 1475{
1476 struct drm_i915_private *dev_priv = dev->dev_private;
1477 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1478 struct intel_pipe_crc_entry *entry;
ac2300d4 1479 int head, tail;
b2c88f5b 1480
d538bbdf
DL		 1481 spin_lock(&pipe_crc->lock);
1482
0c912c79 1483 if (!pipe_crc->entries) {
d538bbdf 1484 spin_unlock(&pipe_crc->lock);
0c912c79
DL		 1485 DRM_ERROR("spurious interrupt\n");
1486 return;
1487 }
1488
d538bbdf
DL		 1489 head = pipe_crc->head;
1490 tail = pipe_crc->tail;
b2c88f5b
DL		 1491
1492 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
d538bbdf 1493 spin_unlock(&pipe_crc->lock);
b2c88f5b
DL		 1494 DRM_ERROR("CRC buffer overflowing\n");
1495 return;
1496 }
1497
1498 entry = &pipe_crc->entries[head];
8bf1e9f1 1499
8bc5e955 1500 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
eba94eb9
DV		 1501 entry->crc[0] = crc0;
1502 entry->crc[1] = crc1;
1503 entry->crc[2] = crc2;
1504 entry->crc[3] = crc3;
1505 entry->crc[4] = crc4;
b2c88f5b
DL		 1506
1507 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
d538bbdf
DL		 1508 pipe_crc->head = head;
1509
1510 spin_unlock(&pipe_crc->lock);
07144428
DL		 1511
1512 wake_up_interruptible(&pipe_crc->wq);
8bf1e9f1 1513}
277de95e
DV		 1514#else
1515static inline void
1516display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1517 uint32_t crc0, uint32_t crc1,
1518 uint32_t crc2, uint32_t crc3,
1519 uint32_t crc4) {}
1520#endif
1521
eba94eb9 1522
277de95e 1523static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5a69b89f
DV		 1524{
1525 struct drm_i915_private *dev_priv = dev->dev_private;
1526
277de95e
DV		 1527 display_pipe_crc_irq_handler(dev, pipe,
1528 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1529 0, 0, 0, 0);
5a69b89f
DV		 1530}
1531
277de95e 1532static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
eba94eb9
DV		 1533{
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535
277de95e
DV		 1536 display_pipe_crc_irq_handler(dev, pipe,
1537 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1538 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1539 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1540 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1541 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
eba94eb9 1542}
5b3a856b 1543
277de95e 1544static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
5b3a856b
DV		 1545{
1546 struct drm_i915_private *dev_priv = dev->dev_private;
0b5c5ed0
DV		 1547 uint32_t res1, res2;
1548
1549 if (INTEL_INFO(dev)->gen >= 3)
1550 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1551 else
1552 res1 = 0;
1553
1554 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1555 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1556 else
1557 res2 = 0;
5b3a856b 1558
277de95e
DV		 1559 display_pipe_crc_irq_handler(dev, pipe,
1560 I915_READ(PIPE_CRC_RES_RED(pipe)),
1561 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1562 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1563 res1, res2);
5b3a856b 1564}
8bf1e9f1 1565
1403c0d4
PZ		 1566/* The RPS events need forcewake, so we add them to a work queue and mask their
1567 * IMR bits until the work is done. Other interrupts can be processed without
1568 * the work queue. */
1569static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
baf02a1f 1570{
a6706b45 1571 if (pm_iir & dev_priv->pm_rps_events) {
59cdb63d 1572 spin_lock(&dev_priv->irq_lock);
a6706b45
D		 1573 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1574 snb_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
59cdb63d 1575 spin_unlock(&dev_priv->irq_lock);
2adbee62
DV		 1576
1577 queue_work(dev_priv->wq, &dev_priv->rps.work);
baf02a1f 1578 }
baf02a1f 1579
1403c0d4
PZ		 1580 if (HAS_VEBOX(dev_priv->dev)) {
1581 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1582 notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
12638c57 1583
1403c0d4 1584 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
58174462
MK		 1585 i915_handle_error(dev_priv->dev, false,
1586 "VEBOX CS error interrupt 0x%08x",
1587 pm_iir);
1403c0d4 1588 }
12638c57 1589 }
baf02a1f
BW		 1590}
1591
c1874ed7
ID		 1592static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
91d181dd 1595 u32 pipe_stats[I915_MAX_PIPES] = { };
c1874ed7
ID		 1596 int pipe;
1597
58ead0d7 1598 spin_lock(&dev_priv->irq_lock);
c1874ed7 1599 for_each_pipe(pipe) {
91d181dd 1600 int reg;
bbb5eebf 1601 u32 mask, iir_bit = 0;
91d181dd 1602
bbb5eebf
DV		 1603 /*
1604 * PIPESTAT bits get signalled even when the interrupt is
1605 * disabled with the mask bits, and some of the status bits do
1606 * not generate interrupts at all (like the underrun bit). Hence
1607 * we need to be careful that we only handle what we want to
1608 * handle.
1609 */
1610 mask = 0;
1611 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
1612 mask |= PIPE_FIFO_UNDERRUN_STATUS;
1613
1614 switch (pipe) {
1615 case PIPE_A:
1616 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1617 break;
1618 case PIPE_B:
1619 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1620 break;
1621 }
1622 if (iir & iir_bit)
1623 mask |= dev_priv->pipestat_irq_mask[pipe];
1624
1625 if (!mask)
91d181dd
ID		 1626 continue;
1627
1628 reg = PIPESTAT(pipe);
bbb5eebf
DV		 1629 mask |= PIPESTAT_INT_ENABLE_MASK;
1630 pipe_stats[pipe] = I915_READ(reg) & mask;
c1874ed7
ID		 1631
1632 /*
1633 * Clear the PIPE*STAT regs before the IIR
1634 */
91d181dd
ID		 1635 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1636 PIPESTAT_INT_STATUS_MASK))
c1874ed7
ID		 1637 I915_WRITE(reg, pipe_stats[pipe]);
1638 }
58ead0d7 1639 spin_unlock(&dev_priv->irq_lock);
c1874ed7
ID		 1640
1641 for_each_pipe(pipe) {
1642 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1643 drm_handle_vblank(dev, pipe);
1644
579a9b0e 1645 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
c1874ed7
ID		 1646 intel_prepare_page_flip(dev, pipe);
1647 intel_finish_page_flip(dev, pipe);
1648 }
1649
1650 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1651 i9xx_pipe_crc_irq_handler(dev, pipe);
1652
1653 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
1654 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
1655 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
1656 }
1657
1658 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1659 gmbus_irq_handler(dev);
1660}
1661
16c6c56b
VS		 1662static void i9xx_hpd_irq_handler(struct drm_device *dev)
1663{
1664 struct drm_i915_private *dev_priv = dev->dev_private;
1665 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1666
1667 if (IS_G4X(dev)) {
1668 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1669
1670 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_g4x);
1671 } else {
1672 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1673
1674 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1675 }
1676
1677 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1678 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1679 dp_aux_irq_handler(dev);
1680
1681 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1682 /*
1683 * Make sure hotplug status is cleared before we clear IIR, or else we
1684 * may miss hotplug events.
1685 */
1686 POSTING_READ(PORT_HOTPLUG_STAT);
1687}
1688
ff1f525e 1689static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 1690{
1691 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 1692 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 1693 u32 iir, gt_iir, pm_iir;
1694 irqreturn_t ret = IRQ_NONE;
7e231dbe 1695
7e231dbe
JB		 1696 while (true) {
1697 iir = I915_READ(VLV_IIR);
1698 gt_iir = I915_READ(GTIIR);
1699 pm_iir = I915_READ(GEN6_PMIIR);
1700
1701 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1702 goto out;
1703
1704 ret = IRQ_HANDLED;
1705
e7b4c6b1 1706 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe 1707
c1874ed7 1708 valleyview_pipestat_irq_handler(dev, iir);
31acc7f5 1709
7e231dbe 1710 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 1711 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1712 i9xx_hpd_irq_handler(dev);
7e231dbe 1713
60611c13 1714 if (pm_iir)
d0ecd7e2 1715 gen6_rps_irq_handler(dev_priv, pm_iir);
7e231dbe
JB		 1716
1717 I915_WRITE(GTIIR, gt_iir);
1718 I915_WRITE(GEN6_PMIIR, pm_iir);
1719 I915_WRITE(VLV_IIR, iir);
1720 }
1721
1722out:
1723 return ret;
1724}
1725
23e81d69 1726static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806 1727{
2d1013dd 1728 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 1729 int pipe;
b543fb04 1730 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
776ad806 1731
91d131d2
DV		 1732 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1733
cfc33bf7
VS		 1734 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1735 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1736 SDE_AUDIO_POWER_SHIFT);
776ad806 1737 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
cfc33bf7
VS		 1738 port_name(port));
1739 }
776ad806 1740
ce99c256
DV		 1741 if (pch_iir & SDE_AUX_MASK)
1742 dp_aux_irq_handler(dev);
1743
776ad806 1744 if (pch_iir & SDE_GMBUS)
515ac2bb 1745 gmbus_irq_handler(dev);
776ad806
JB		 1746
1747 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1748 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1749
1750 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1751 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1752
1753 if (pch_iir & SDE_POISON)
1754 DRM_ERROR("PCH poison interrupt\n");
1755
9db4a9c7
JB		 1756 if (pch_iir & SDE_FDI_MASK)
1757 for_each_pipe(pipe)
1758 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1759 pipe_name(pipe),
1760 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 1761
1762 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1763 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1764
1765 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1766 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1767
776ad806 1768 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
8664281b
PZ		 1769 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1770 false))
fc2c807b 1771 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 1772
1773 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1774 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1775 false))
fc2c807b 1776 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 1777}
1778
1779static void ivb_err_int_handler(struct drm_device *dev)
1780{
1781 struct drm_i915_private *dev_priv = dev->dev_private;
1782 u32 err_int = I915_READ(GEN7_ERR_INT);
5a69b89f 1783 enum pipe pipe;
8664281b 1784
de032bf4
PZ		 1785 if (err_int & ERR_INT_POISON)
1786 DRM_ERROR("Poison interrupt\n");
1787
5a69b89f
DV		 1788 for_each_pipe(pipe) {
1789 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
1790 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
1791 false))
fc2c807b
VS		 1792 DRM_ERROR("Pipe %c FIFO underrun\n",
1793 pipe_name(pipe));
5a69b89f 1794 }
8bf1e9f1 1795
5a69b89f
DV		 1796 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1797 if (IS_IVYBRIDGE(dev))
277de95e 1798 ivb_pipe_crc_irq_handler(dev, pipe);
5a69b89f 1799 else
277de95e 1800 hsw_pipe_crc_irq_handler(dev, pipe);
5a69b89f
DV		 1801 }
1802 }
8bf1e9f1 1803
8664281b
PZ		 1804 I915_WRITE(GEN7_ERR_INT, err_int);
1805}
1806
1807static void cpt_serr_int_handler(struct drm_device *dev)
1808{
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 u32 serr_int = I915_READ(SERR_INT);
1811
de032bf4
PZ		 1812 if (serr_int & SERR_INT_POISON)
1813 DRM_ERROR("PCH poison interrupt\n");
1814
8664281b
PZ		 1815 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1816 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1817 false))
fc2c807b 1818 DRM_ERROR("PCH transcoder A FIFO underrun\n");
8664281b
PZ		 1819
1820 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1821 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1822 false))
fc2c807b 1823 DRM_ERROR("PCH transcoder B FIFO underrun\n");
8664281b
PZ		 1824
1825 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1826 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1827 false))
fc2c807b 1828 DRM_ERROR("PCH transcoder C FIFO underrun\n");
8664281b
PZ		 1829
1830 I915_WRITE(SERR_INT, serr_int);
776ad806
JB		 1831}
1832
23e81d69
AJ		 1833static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1834{
2d1013dd 1835 struct drm_i915_private *dev_priv = dev->dev_private;
23e81d69 1836 int pipe;
b543fb04 1837 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
23e81d69 1838
91d131d2
DV		 1839 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1840
cfc33bf7
VS		 1841 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1842 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1843 SDE_AUDIO_POWER_SHIFT_CPT);
1844 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1845 port_name(port));
1846 }
23e81d69
AJ		 1847
1848 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 1849 dp_aux_irq_handler(dev);
23e81d69
AJ		 1850
1851 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 1852 gmbus_irq_handler(dev);
23e81d69
AJ		 1853
1854 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1855 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1856
1857 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1858 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1859
1860 if (pch_iir & SDE_FDI_MASK_CPT)
1861 for_each_pipe(pipe)
1862 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1863 pipe_name(pipe),
1864 I915_READ(FDI_RX_IIR(pipe)));
8664281b
PZ		 1865
1866 if (pch_iir & SDE_ERROR_CPT)
1867 cpt_serr_int_handler(dev);
23e81d69
AJ		 1868}
1869
c008bc6e
PZ		 1870static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1871{
1872 struct drm_i915_private *dev_priv = dev->dev_private;
40da17c2 1873 enum pipe pipe;
c008bc6e
PZ		 1874
1875 if (de_iir & DE_AUX_CHANNEL_A)
1876 dp_aux_irq_handler(dev);
1877
1878 if (de_iir & DE_GSE)
1879 intel_opregion_asle_intr(dev);
1880
c008bc6e
PZ		 1881 if (de_iir & DE_POISON)
1882 DRM_ERROR("Poison interrupt\n");
1883
40da17c2
DV		 1884 for_each_pipe(pipe) {
1885 if (de_iir & DE_PIPE_VBLANK(pipe))
1886 drm_handle_vblank(dev, pipe);
5b3a856b 1887
40da17c2
DV		 1888 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1889 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b
VS		 1890 DRM_ERROR("Pipe %c FIFO underrun\n",
1891 pipe_name(pipe));
5b3a856b 1892
40da17c2
DV		 1893 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1894 i9xx_pipe_crc_irq_handler(dev, pipe);
c008bc6e 1895
40da17c2
DV		 1896 /* plane/pipes map 1:1 on ilk+ */
1897 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
1898 intel_prepare_page_flip(dev, pipe);
1899 intel_finish_page_flip_plane(dev, pipe);
1900 }
c008bc6e
PZ		 1901 }
1902
1903 /* check event from PCH */
1904 if (de_iir & DE_PCH_EVENT) {
1905 u32 pch_iir = I915_READ(SDEIIR);
1906
1907 if (HAS_PCH_CPT(dev))
1908 cpt_irq_handler(dev, pch_iir);
1909 else
1910 ibx_irq_handler(dev, pch_iir);
1911
1912 /* should clear PCH hotplug event before clear CPU irq */
1913 I915_WRITE(SDEIIR, pch_iir);
1914 }
1915
1916 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1917 ironlake_rps_change_irq_handler(dev);
1918}
1919
9719fb98
PZ		 1920static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1921{
1922 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 1923 enum pipe pipe;
9719fb98
PZ		 1924
1925 if (de_iir & DE_ERR_INT_IVB)
1926 ivb_err_int_handler(dev);
1927
1928 if (de_iir & DE_AUX_CHANNEL_A_IVB)
1929 dp_aux_irq_handler(dev);
1930
1931 if (de_iir & DE_GSE_IVB)
1932 intel_opregion_asle_intr(dev);
1933
07d27e20
DL		 1934 for_each_pipe(pipe) {
1935 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
1936 drm_handle_vblank(dev, pipe);
40da17c2
DV		 1937
1938 /* plane/pipes map 1:1 on ilk+ */
07d27e20
DL		 1939 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
1940 intel_prepare_page_flip(dev, pipe);
1941 intel_finish_page_flip_plane(dev, pipe);
9719fb98
PZ		 1942 }
1943 }
1944
1945 /* check event from PCH */
1946 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1947 u32 pch_iir = I915_READ(SDEIIR);
1948
1949 cpt_irq_handler(dev, pch_iir);
1950
1951 /* clear PCH hotplug event before clear CPU irq */
1952 I915_WRITE(SDEIIR, pch_iir);
1953 }
1954}
1955
f1af8fc1 1956static irqreturn_t ironlake_irq_handler(int irq, void *arg)
b1f14ad0
JB		 1957{
1958 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 1959 struct drm_i915_private *dev_priv = dev->dev_private;
f1af8fc1 1960 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
0e43406b 1961 irqreturn_t ret = IRQ_NONE;
b1f14ad0 1962
8664281b
PZ		 1963 /* We get interrupts on unclaimed registers, so check for this before we
1964 * do any I915_{READ,WRITE}. */
907b28c5 1965 intel_uncore_check_errors(dev);
8664281b 1966
b1f14ad0
JB		 1967 /* disable master interrupt before clearing iir */
1968 de_ier = I915_READ(DEIER);
1969 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
23a78516 1970 POSTING_READ(DEIER);
b1f14ad0 1971
44498aea
PZ		 1972 /* Disable south interrupts. We'll only write to SDEIIR once, so further
1973 * interrupts will will be stored on its back queue, and then we'll be
1974 * able to process them after we restore SDEIER (as soon as we restore
1975 * it, we'll get an interrupt if SDEIIR still has something to process
1976 * due to its back queue). */
ab5c608b
BW		 1977 if (!HAS_PCH_NOP(dev)) {
1978 sde_ier = I915_READ(SDEIER);
1979 I915_WRITE(SDEIER, 0);
1980 POSTING_READ(SDEIER);
1981 }
44498aea 1982
b1f14ad0 1983 gt_iir = I915_READ(GTIIR);
0e43406b 1984 if (gt_iir) {
d8fc8a47 1985 if (INTEL_INFO(dev)->gen >= 6)
f1af8fc1 1986 snb_gt_irq_handler(dev, dev_priv, gt_iir);
d8fc8a47
PZ		 1987 else
1988 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
0e43406b
CW		 1989 I915_WRITE(GTIIR, gt_iir);
1990 ret = IRQ_HANDLED;
b1f14ad0
JB		 1991 }
1992
0e43406b
CW		 1993 de_iir = I915_READ(DEIIR);
1994 if (de_iir) {
f1af8fc1
PZ		 1995 if (INTEL_INFO(dev)->gen >= 7)
1996 ivb_display_irq_handler(dev, de_iir);
1997 else
1998 ilk_display_irq_handler(dev, de_iir);
0e43406b
CW		 1999 I915_WRITE(DEIIR, de_iir);
2000 ret = IRQ_HANDLED;
b1f14ad0
JB		 2001 }
2002
f1af8fc1
PZ		 2003 if (INTEL_INFO(dev)->gen >= 6) {
2004 u32 pm_iir = I915_READ(GEN6_PMIIR);
2005 if (pm_iir) {
1403c0d4 2006 gen6_rps_irq_handler(dev_priv, pm_iir);
f1af8fc1
PZ		 2007 I915_WRITE(GEN6_PMIIR, pm_iir);
2008 ret = IRQ_HANDLED;
2009 }
0e43406b 2010 }
b1f14ad0 2011
b1f14ad0
JB		 2012 I915_WRITE(DEIER, de_ier);
2013 POSTING_READ(DEIER);
ab5c608b
BW		 2014 if (!HAS_PCH_NOP(dev)) {
2015 I915_WRITE(SDEIER, sde_ier);
2016 POSTING_READ(SDEIER);
2017 }
b1f14ad0
JB		 2018
2019 return ret;
2020}
2021
abd58f01
BW		 2022static irqreturn_t gen8_irq_handler(int irq, void *arg)
2023{
2024 struct drm_device *dev = arg;
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026 u32 master_ctl;
2027 irqreturn_t ret = IRQ_NONE;
2028 uint32_t tmp = 0;
c42664cc 2029 enum pipe pipe;
abd58f01 2030
abd58f01
BW		 2031 master_ctl = I915_READ(GEN8_MASTER_IRQ);
2032 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2033 if (!master_ctl)
2034 return IRQ_NONE;
2035
2036 I915_WRITE(GEN8_MASTER_IRQ, 0);
2037 POSTING_READ(GEN8_MASTER_IRQ);
2038
2039 ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2040
2041 if (master_ctl & GEN8_DE_MISC_IRQ) {
2042 tmp = I915_READ(GEN8_DE_MISC_IIR);
2043 if (tmp & GEN8_DE_MISC_GSE)
2044 intel_opregion_asle_intr(dev);
2045 else if (tmp)
2046 DRM_ERROR("Unexpected DE Misc interrupt\n");
2047 else
2048 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2049
2050 if (tmp) {
2051 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2052 ret = IRQ_HANDLED;
2053 }
2054 }
2055
6d766f02
DV		 2056 if (master_ctl & GEN8_DE_PORT_IRQ) {
2057 tmp = I915_READ(GEN8_DE_PORT_IIR);
2058 if (tmp & GEN8_AUX_CHANNEL_A)
2059 dp_aux_irq_handler(dev);
2060 else if (tmp)
2061 DRM_ERROR("Unexpected DE Port interrupt\n");
2062 else
2063 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2064
2065 if (tmp) {
2066 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2067 ret = IRQ_HANDLED;
2068 }
2069 }
2070
c42664cc
DV		 2071 for_each_pipe(pipe) {
2072 uint32_t pipe_iir;
abd58f01 2073
c42664cc
DV		 2074 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2075 continue;
abd58f01 2076
c42664cc
DV		 2077 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2078 if (pipe_iir & GEN8_PIPE_VBLANK)
2079 drm_handle_vblank(dev, pipe);
abd58f01 2080
c42664cc
DV		 2081 if (pipe_iir & GEN8_PIPE_FLIP_DONE) {
2082 intel_prepare_page_flip(dev, pipe);
2083 intel_finish_page_flip_plane(dev, pipe);
abd58f01 2084 }
c42664cc 2085
0fbe7870
DV		 2086 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2087 hsw_pipe_crc_irq_handler(dev, pipe);
2088
38d83c96
DV		 2089 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2090 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2091 false))
fc2c807b
VS		 2092 DRM_ERROR("Pipe %c FIFO underrun\n",
2093 pipe_name(pipe));
38d83c96
DV		 2094 }
2095
30100f2b
DV		 2096 if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2097 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2098 pipe_name(pipe),
2099 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2100 }
c42664cc
DV		 2101
2102 if (pipe_iir) {
2103 ret = IRQ_HANDLED;
2104 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2105 } else
abd58f01
BW		 2106 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2107 }
2108
92d03a80
DV		 2109 if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2110 /*
2111 * FIXME(BDW): Assume for now that the new interrupt handling
2112 * scheme also closed the SDE interrupt handling race we've seen
2113 * on older pch-split platforms. But this needs testing.
2114 */
2115 u32 pch_iir = I915_READ(SDEIIR);
2116
2117 cpt_irq_handler(dev, pch_iir);
2118
2119 if (pch_iir) {
2120 I915_WRITE(SDEIIR, pch_iir);
2121 ret = IRQ_HANDLED;
2122 }
2123 }
2124
abd58f01
BW		 2125 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2126 POSTING_READ(GEN8_MASTER_IRQ);
2127
2128 return ret;
2129}
2130
17e1df07
DV		 2131static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2132 bool reset_completed)
2133{
2134 struct intel_ring_buffer *ring;
2135 int i;
2136
2137 /*
2138 * Notify all waiters for GPU completion events that reset state has
2139 * been changed, and that they need to restart their wait after
2140 * checking for potential errors (and bail out to drop locks if there is
2141 * a gpu reset pending so that i915_error_work_func can acquire them).
2142 */
2143
2144 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2145 for_each_ring(ring, dev_priv, i)
2146 wake_up_all(&ring->irq_queue);
2147
2148 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2149 wake_up_all(&dev_priv->pending_flip_queue);
2150
2151 /*
2152 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2153 * reset state is cleared.
2154 */
2155 if (reset_completed)
2156 wake_up_all(&dev_priv->gpu_error.reset_queue);
2157}
2158
8a905236
JB		 2159/**
2160 * i915_error_work_func - do process context error handling work
2161 * @work: work struct
2162 *
2163 * Fire an error uevent so userspace can see that a hang or error
2164 * was detected.
2165 */
2166static void i915_error_work_func(struct work_struct *work)
2167{
1f83fee0
DV		 2168 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2169 work);
2d1013dd
JN		 2170 struct drm_i915_private *dev_priv =
2171 container_of(error, struct drm_i915_private, gpu_error);
8a905236 2172 struct drm_device *dev = dev_priv->dev;
cce723ed
BW		 2173 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2174 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2175 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
17e1df07 2176 int ret;
8a905236 2177
5bdebb18 2178 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
f316a42c 2179
7db0ba24
DV		 2180 /*
2181 * Note that there's only one work item which does gpu resets, so we
2182 * need not worry about concurrent gpu resets potentially incrementing
2183 * error->reset_counter twice. We only need to take care of another
2184 * racing irq/hangcheck declaring the gpu dead for a second time. A
2185 * quick check for that is good enough: schedule_work ensures the
2186 * correct ordering between hang detection and this work item, and since
2187 * the reset in-progress bit is only ever set by code outside of this
2188 * work we don't need to worry about any other races.
2189 */
2190 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 2191 DRM_DEBUG_DRIVER("resetting chip\n");
5bdebb18 2192 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
7db0ba24 2193 reset_event);
1f83fee0 2194
17e1df07
DV		 2195 /*
2196 * All state reset _must_ be completed before we update the
2197 * reset counter, for otherwise waiters might miss the reset
2198 * pending state and not properly drop locks, resulting in
2199 * deadlocks with the reset work.
2200 */
f69061be
DV		 2201 ret = i915_reset(dev);
2202
17e1df07
DV		 2203 intel_display_handle_reset(dev);
2204
f69061be
DV		 2205 if (ret == 0) {
2206 /*
2207 * After all the gem state is reset, increment the reset
2208 * counter and wake up everyone waiting for the reset to
2209 * complete.
2210 *
2211 * Since unlock operations are a one-sided barrier only,
2212 * we need to insert a barrier here to order any seqno
2213 * updates before
2214 * the counter increment.
2215 */
2216 smp_mb__before_atomic_inc();
2217 atomic_inc(&dev_priv->gpu_error.reset_counter);
2218
5bdebb18 2219 kobject_uevent_env(&dev->primary->kdev->kobj,
f69061be 2220 KOBJ_CHANGE, reset_done_event);
1f83fee0 2221 } else {
2ac0f450 2222 atomic_set_mask(I915_WEDGED, &error->reset_counter);
f316a42c 2223 }
1f83fee0 2224
17e1df07
DV		 2225 /*
2226 * Note: The wake_up also serves as a memory barrier so that
2227 * waiters see the update value of the reset counter atomic_t.
2228 */
2229 i915_error_wake_up(dev_priv, true);
f316a42c 2230 }
8a905236
JB		 2231}
2232
35aed2e6 2233static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 2234{
2235 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 2236 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 2237 u32 eir = I915_READ(EIR);
050ee91f 2238 int pipe, i;
8a905236 2239
35aed2e6
CW		 2240 if (!eir)
2241 return;
8a905236 2242
a70491cc 2243 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 2244
bd9854f9
BW		 2245 i915_get_extra_instdone(dev, instdone);
2246
8a905236
JB		 2247 if (IS_G4X(dev)) {
2248 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2249 u32 ipeir = I915_READ(IPEIR_I965);
2250
a70491cc
JP		 2251 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2252 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 2253 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2254 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 2255 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2256 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2257 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2258 POSTING_READ(IPEIR_I965);
8a905236
JB		 2259 }
2260 if (eir & GM45_ERROR_PAGE_TABLE) {
2261 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2262 pr_err("page table error\n");
2263 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2264 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2265 POSTING_READ(PGTBL_ER);
8a905236
JB		 2266 }
2267 }
2268
a6c45cf0 2269 if (!IS_GEN2(dev)) {
8a905236
JB		 2270 if (eir & I915_ERROR_PAGE_TABLE) {
2271 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 2272 pr_err("page table error\n");
2273 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 2274 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 2275 POSTING_READ(PGTBL_ER);
8a905236
JB		 2276 }
2277 }
2278
2279 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 2280 pr_err("memory refresh error:\n");
9db4a9c7 2281 for_each_pipe(pipe)
a70491cc 2282 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 2283 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 2284 /* pipestat has already been acked */
2285 }
2286 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 2287 pr_err("instruction error\n");
2288 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 2289 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2290 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 2291 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 2292 u32 ipeir = I915_READ(IPEIR);
2293
a70491cc
JP		 2294 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2295 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 2296 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 2297 I915_WRITE(IPEIR, ipeir);
3143a2bf 2298 POSTING_READ(IPEIR);
8a905236
JB		 2299 } else {
2300 u32 ipeir = I915_READ(IPEIR_I965);
2301
a70491cc
JP		 2302 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2303 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 2304 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 2305 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 2306 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 2307 POSTING_READ(IPEIR_I965);
8a905236
JB		 2308 }
2309 }
2310
2311 I915_WRITE(EIR, eir);
3143a2bf 2312 POSTING_READ(EIR);
8a905236
JB		 2313 eir = I915_READ(EIR);
2314 if (eir) {
2315 /*
2316 * some errors might have become stuck,
2317 * mask them.
2318 */
2319 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2320 I915_WRITE(EMR, I915_READ(EMR) | eir);
2321 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2322 }
35aed2e6
CW		 2323}
2324
2325/**
2326 * i915_handle_error - handle an error interrupt
2327 * @dev: drm device
2328 *
2329 * Do some basic checking of regsiter state at error interrupt time and
2330 * dump it to the syslog. Also call i915_capture_error_state() to make
2331 * sure we get a record and make it available in debugfs. Fire a uevent
2332 * so userspace knows something bad happened (should trigger collection
2333 * of a ring dump etc.).
2334 */
58174462
MK		 2335void i915_handle_error(struct drm_device *dev, bool wedged,
2336 const char *fmt, ...)
35aed2e6
CW		 2337{
2338 struct drm_i915_private *dev_priv = dev->dev_private;
58174462
MK		 2339 va_list args;
2340 char error_msg[80];
35aed2e6 2341
58174462
MK		 2342 va_start(args, fmt);
2343 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2344 va_end(args);
2345
2346 i915_capture_error_state(dev, wedged, error_msg);
35aed2e6 2347 i915_report_and_clear_eir(dev);
8a905236 2348
ba1234d1 2349 if (wedged) {
f69061be
DV		 2350 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2351 &dev_priv->gpu_error.reset_counter);
ba1234d1 2352
11ed50ec 2353 /*
17e1df07
DV		 2354 * Wakeup waiting processes so that the reset work function
2355 * i915_error_work_func doesn't deadlock trying to grab various
2356 * locks. By bumping the reset counter first, the woken
2357 * processes will see a reset in progress and back off,
2358 * releasing their locks and then wait for the reset completion.
2359 * We must do this for _all_ gpu waiters that might hold locks
2360 * that the reset work needs to acquire.
2361 *
2362 * Note: The wake_up serves as the required memory barrier to
2363 * ensure that the waiters see the updated value of the reset
2364 * counter atomic_t.
11ed50ec 2365 */
17e1df07 2366 i915_error_wake_up(dev_priv, false);
11ed50ec
BG		 2367 }
2368
122f46ba
DV		 2369 /*
2370 * Our reset work can grab modeset locks (since it needs to reset the
2371 * state of outstanding pagelips). Hence it must not be run on our own
2372 * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2373 * code will deadlock.
2374 */
2375 schedule_work(&dev_priv->gpu_error.work);
8a905236
JB		 2376}
2377
21ad8330 2378static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd 2379{
2d1013dd 2380 struct drm_i915_private *dev_priv = dev->dev_private;
4e5359cd
SF		 2381 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 2383 struct drm_i915_gem_object *obj;
4e5359cd
SF		 2384 struct intel_unpin_work *work;
2385 unsigned long flags;
2386 bool stall_detected;
2387
2388 /* Ignore early vblank irqs */
2389 if (intel_crtc == NULL)
2390 return;
2391
2392 spin_lock_irqsave(&dev->event_lock, flags);
2393 work = intel_crtc->unpin_work;
2394
e7d841ca
CW		 2395 if (work == NULL ||
2396 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2397 !work->enable_stall_check) {
4e5359cd
SF		 2398 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2399 spin_unlock_irqrestore(&dev->event_lock, flags);
2400 return;
2401 }
2402
2403 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 2404 obj = work->pending_flip_obj;
a6c45cf0 2405 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 2406 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545 2407 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
f343c5f6 2408 i915_gem_obj_ggtt_offset(obj);
4e5359cd 2409 } else {
9db4a9c7 2410 int dspaddr = DSPADDR(intel_crtc->plane);
f343c5f6 2411 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
01f2c773 2412 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 2413 crtc->x * crtc->fb->bits_per_pixel/8);
2414 }
2415
2416 spin_unlock_irqrestore(&dev->event_lock, flags);
2417
2418 if (stall_detected) {
2419 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2420 intel_prepare_page_flip(dev, intel_crtc->plane);
2421 }
2422}
2423
42f52ef8
KP		 2424/* Called from drm generic code, passed 'crtc' which
2425 * we use as a pipe index
2426 */
f71d4af4 2427static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2428{
2d1013dd 2429 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2430 unsigned long irqflags;
71e0ffa5 2431
5eddb70b 2432 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 2433 return -EINVAL;
0a3e67a4 2434
1ec14ad3 2435 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 2436 if (INTEL_INFO(dev)->gen >= 4)
7c463586 2437 i915_enable_pipestat(dev_priv, pipe,
755e9019 2438 PIPE_START_VBLANK_INTERRUPT_STATUS);
e9d21d7f 2439 else
7c463586 2440 i915_enable_pipestat(dev_priv, pipe,
755e9019 2441 PIPE_VBLANK_INTERRUPT_STATUS);
8692d00e
CW		 2442
2443 /* maintain vblank delivery even in deep C-states */
3d13ef2e 2444 if (INTEL_INFO(dev)->gen == 3)
6b26c86d 2445 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 2446 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 2447
0a3e67a4
JB		 2448 return 0;
2449}
2450
f71d4af4 2451static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2452{
2d1013dd 2453 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2454 unsigned long irqflags;
b518421f 2455 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2456 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2457
2458 if (!i915_pipe_enabled(dev, pipe))
2459 return -EINVAL;
2460
2461 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2462 ironlake_enable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2463 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2464
2465 return 0;
2466}
2467
7e231dbe
JB		 2468static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2469{
2d1013dd 2470 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2471 unsigned long irqflags;
7e231dbe
JB		 2472
2473 if (!i915_pipe_enabled(dev, pipe))
2474 return -EINVAL;
2475
2476 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2477 i915_enable_pipestat(dev_priv, pipe,
755e9019 2478 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2479 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2480
2481 return 0;
2482}
2483
abd58f01
BW		 2484static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2485{
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487 unsigned long irqflags;
abd58f01
BW		 2488
2489 if (!i915_pipe_enabled(dev, pipe))
2490 return -EINVAL;
2491
2492 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2493 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2494 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2495 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2496 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2497 return 0;
2498}
2499
42f52ef8
KP		 2500/* Called from drm generic code, passed 'crtc' which
2501 * we use as a pipe index
2502 */
f71d4af4 2503static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4 2504{
2d1013dd 2505 struct drm_i915_private *dev_priv = dev->dev_private;
e9d21d7f 2506 unsigned long irqflags;
0a3e67a4 2507
1ec14ad3 2508 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3d13ef2e 2509 if (INTEL_INFO(dev)->gen == 3)
6b26c86d 2510 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 2511
f796cf8f 2512 i915_disable_pipestat(dev_priv, pipe,
755e9019
ID		 2513 PIPE_VBLANK_INTERRUPT_STATUS |
2514 PIPE_START_VBLANK_INTERRUPT_STATUS);
f796cf8f
JB		 2515 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2516}
2517
f71d4af4 2518static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f 2519{
2d1013dd 2520 struct drm_i915_private *dev_priv = dev->dev_private;
f796cf8f 2521 unsigned long irqflags;
b518421f 2522 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
40da17c2 2523 DE_PIPE_VBLANK(pipe);
f796cf8f
JB		 2524
2525 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b518421f 2526 ironlake_disable_display_irq(dev_priv, bit);
b1f14ad0
JB		 2527 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2528}
2529
7e231dbe
JB		 2530static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2531{
2d1013dd 2532 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe 2533 unsigned long irqflags;
7e231dbe
JB		 2534
2535 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5 2536 i915_disable_pipestat(dev_priv, pipe,
755e9019 2537 PIPE_START_VBLANK_INTERRUPT_STATUS);
7e231dbe
JB		 2538 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2539}
2540
abd58f01
BW		 2541static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2542{
2543 struct drm_i915_private *dev_priv = dev->dev_private;
2544 unsigned long irqflags;
abd58f01
BW		 2545
2546 if (!i915_pipe_enabled(dev, pipe))
2547 return;
2548
2549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7167d7c6
DV		 2550 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2551 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2552 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
abd58f01
BW		 2553 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2554}
2555
893eead0
CW		 2556static u32
2557ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 2558{
893eead0
CW		 2559 return list_entry(ring->request_list.prev,
2560 struct drm_i915_gem_request, list)->seqno;
2561}
2562
9107e9d2
CW		 2563static bool
2564ring_idle(struct intel_ring_buffer *ring, u32 seqno)
2565{
2566 return (list_empty(&ring->request_list) ||
2567 i915_seqno_passed(seqno, ring_last_seqno(ring)));
f65d9421
BG		 2568}
2569
a028c4b0
DV		 2570static bool
2571ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2572{
2573 if (INTEL_INFO(dev)->gen >= 8) {
2574 /*
2575 * FIXME: gen8 semaphore support - currently we don't emit
2576 * semaphores on bdw anyway, but this needs to be addressed when
2577 * we merge that code.
2578 */
2579 return false;
2580 } else {
2581 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2582 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2583 MI_SEMAPHORE_REGISTER);
2584 }
2585}
2586
921d42ea
DV		 2587static struct intel_ring_buffer *
2588semaphore_wait_to_signaller_ring(struct intel_ring_buffer *ring, u32 ipehr)
2589{
2590 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2591 struct intel_ring_buffer *signaller;
2592 int i;
2593
2594 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
2595 /*
2596 * FIXME: gen8 semaphore support - currently we don't emit
2597 * semaphores on bdw anyway, but this needs to be addressed when
2598 * we merge that code.
2599 */
2600 return NULL;
2601 } else {
2602 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2603
2604 for_each_ring(signaller, dev_priv, i) {
2605 if(ring == signaller)
2606 continue;
2607
2608 if (sync_bits ==
2609 signaller->semaphore_register[ring->id])
2610 return signaller;
2611 }
2612 }
2613
2614 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x\n",
2615 ring->id, ipehr);
2616
2617 return NULL;
2618}
2619
6274f212
CW		 2620static struct intel_ring_buffer *
2621semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
a24a11e6
CW		 2622{
2623 struct drm_i915_private *dev_priv = ring->dev->dev_private;
88fe429d
DV		 2624 u32 cmd, ipehr, head;
2625 int i;
a24a11e6
CW		 2626
2627 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
a028c4b0 2628 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
6274f212 2629 return NULL;
a24a11e6 2630
88fe429d
DV		 2631 /*
2632 * HEAD is likely pointing to the dword after the actual command,
2633 * so scan backwards until we find the MBOX. But limit it to just 3
2634 * dwords. Note that we don't care about ACTHD here since that might
2635 * point at at batch, and semaphores are always emitted into the
2636 * ringbuffer itself.
a24a11e6 2637 */
88fe429d
DV		 2638 head = I915_READ_HEAD(ring) & HEAD_ADDR;
2639
2640 for (i = 4; i; --i) {
2641 /*
2642 * Be paranoid and presume the hw has gone off into the wild -
2643 * our ring is smaller than what the hardware (and hence
2644 * HEAD_ADDR) allows. Also handles wrap-around.
2645 */
2646 head &= ring->size - 1;
2647
2648 /* This here seems to blow up */
2649 cmd = ioread32(ring->virtual_start + head);
a24a11e6
CW		 2650 if (cmd == ipehr)
2651 break;
2652
88fe429d
DV		 2653 head -= 4;
2654 }
2655
2656 if (!i)
2657 return NULL;
a24a11e6 2658
88fe429d 2659 *seqno = ioread32(ring->virtual_start + head + 4) + 1;
921d42ea 2660 return semaphore_wait_to_signaller_ring(ring, ipehr);
a24a11e6
CW		 2661}
2662
6274f212
CW		 2663static int semaphore_passed(struct intel_ring_buffer *ring)
2664{
2665 struct drm_i915_private *dev_priv = ring->dev->dev_private;
2666 struct intel_ring_buffer *signaller;
2667 u32 seqno, ctl;
2668
2669 ring->hangcheck.deadlock = true;
2670
2671 signaller = semaphore_waits_for(ring, &seqno);
2672 if (signaller == NULL || signaller->hangcheck.deadlock)
2673 return -1;
2674
2675 /* cursory check for an unkickable deadlock */
2676 ctl = I915_READ_CTL(signaller);
2677 if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
2678 return -1;
2679
2680 return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
2681}
2682
2683static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2684{
2685 struct intel_ring_buffer *ring;
2686 int i;
2687
2688 for_each_ring(ring, dev_priv, i)
2689 ring->hangcheck.deadlock = false;
2690}
2691
ad8beaea 2692static enum intel_ring_hangcheck_action
50877445 2693ring_stuck(struct intel_ring_buffer *ring, u64 acthd)
1ec14ad3
CW		 2694{
2695 struct drm_device *dev = ring->dev;
2696 struct drm_i915_private *dev_priv = dev->dev_private;
9107e9d2
CW		 2697 u32 tmp;
2698
6274f212 2699 if (ring->hangcheck.acthd != acthd)
f2f4d82f 2700 return HANGCHECK_ACTIVE;
6274f212 2701
9107e9d2 2702 if (IS_GEN2(dev))
f2f4d82f 2703 return HANGCHECK_HUNG;
9107e9d2
CW		 2704
2705 /* Is the chip hanging on a WAIT_FOR_EVENT?
2706 * If so we can simply poke the RB_WAIT bit
2707 * and break the hang. This should work on
2708 * all but the second generation chipsets.
2709 */
2710 tmp = I915_READ_CTL(ring);
1ec14ad3 2711 if (tmp & RING_WAIT) {
58174462
MK		 2712 i915_handle_error(dev, false,
2713 "Kicking stuck wait on %s",
2714 ring->name);
1ec14ad3 2715 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2716 return HANGCHECK_KICK;
6274f212
CW		 2717 }
2718
2719 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2720 switch (semaphore_passed(ring)) {
2721 default:
f2f4d82f 2722 return HANGCHECK_HUNG;
6274f212 2723 case 1:
58174462
MK		 2724 i915_handle_error(dev, false,
2725 "Kicking stuck semaphore on %s",
2726 ring->name);
6274f212 2727 I915_WRITE_CTL(ring, tmp);
f2f4d82f 2728 return HANGCHECK_KICK;
6274f212 2729 case 0:
f2f4d82f 2730 return HANGCHECK_WAIT;
6274f212 2731 }
9107e9d2 2732 }
ed5cbb03 2733
f2f4d82f 2734 return HANGCHECK_HUNG;
ed5cbb03
MK		 2735}
2736
f65d9421
BG		 2737/**
2738 * This is called when the chip hasn't reported back with completed
05407ff8
MK		 2739 * batchbuffers in a long time. We keep track per ring seqno progress and
2740 * if there are no progress, hangcheck score for that ring is increased.
2741 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2742 * we kick the ring. If we see no progress on three subsequent calls
2743 * we assume chip is wedged and try to fix it by resetting the chip.
f65d9421 2744 */
a658b5d2 2745static void i915_hangcheck_elapsed(unsigned long data)
f65d9421
BG		 2746{
2747 struct drm_device *dev = (struct drm_device *)data;
2d1013dd 2748 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2749 struct intel_ring_buffer *ring;
b4519513 2750 int i;
05407ff8 2751 int busy_count = 0, rings_hung = 0;
9107e9d2
CW		 2752 bool stuck[I915_NUM_RINGS] = { 0 };
2753#define BUSY 1
2754#define KICK 5
2755#define HUNG 20
893eead0 2756
d330a953 2757 if (!i915.enable_hangcheck)
3e0dc6b0
BW		 2758 return;
2759
b4519513 2760 for_each_ring(ring, dev_priv, i) {
50877445
CW		 2761 u64 acthd;
2762 u32 seqno;
9107e9d2 2763 bool busy = true;
05407ff8 2764
6274f212
CW		 2765 semaphore_clear_deadlocks(dev_priv);
2766
05407ff8
MK		 2767 seqno = ring->get_seqno(ring, false);
2768 acthd = intel_ring_get_active_head(ring);
b4519513 2769
9107e9d2
CW		 2770 if (ring->hangcheck.seqno == seqno) {
2771 if (ring_idle(ring, seqno)) {
da661464
MK		 2772 ring->hangcheck.action = HANGCHECK_IDLE;
2773
9107e9d2
CW		 2774 if (waitqueue_active(&ring->irq_queue)) {
2775 /* Issue a wake-up to catch stuck h/w. */
094f9a54 2776 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
f4adcd24
DV		 2777 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2778 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2779 ring->name);
2780 else
2781 DRM_INFO("Fake missed irq on %s\n",
2782 ring->name);
094f9a54
CW		 2783 wake_up_all(&ring->irq_queue);
2784 }
2785 /* Safeguard against driver failure */
2786 ring->hangcheck.score += BUSY;
9107e9d2
CW		 2787 } else
2788 busy = false;
05407ff8 2789 } else {
6274f212
CW		 2790 /* We always increment the hangcheck score
2791 * if the ring is busy and still processing
2792 * the same request, so that no single request
2793 * can run indefinitely (such as a chain of
2794 * batches). The only time we do not increment
2795 * the hangcheck score on this ring, if this
2796 * ring is in a legitimate wait for another
2797 * ring. In that case the waiting ring is a
2798 * victim and we want to be sure we catch the
2799 * right culprit. Then every time we do kick
2800 * the ring, add a small increment to the
2801 * score so that we can catch a batch that is
2802 * being repeatedly kicked and so responsible
2803 * for stalling the machine.
2804 */
ad8beaea
MK		 2805 ring->hangcheck.action = ring_stuck(ring,
2806 acthd);
2807
2808 switch (ring->hangcheck.action) {
da661464 2809 case HANGCHECK_IDLE:
f2f4d82f 2810 case HANGCHECK_WAIT:
6274f212 2811 break;
f2f4d82f 2812 case HANGCHECK_ACTIVE:
ea04cb31 2813 ring->hangcheck.score += BUSY;
6274f212 2814 break;
f2f4d82f 2815 case HANGCHECK_KICK:
ea04cb31 2816 ring->hangcheck.score += KICK;
6274f212 2817 break;
f2f4d82f 2818 case HANGCHECK_HUNG:
ea04cb31 2819 ring->hangcheck.score += HUNG;
6274f212
CW		 2820 stuck[i] = true;
2821 break;
2822 }
05407ff8 2823 }
9107e9d2 2824 } else {
da661464
MK		 2825 ring->hangcheck.action = HANGCHECK_ACTIVE;
2826
9107e9d2
CW		 2827 /* Gradually reduce the count so that we catch DoS
2828 * attempts across multiple batches.
2829 */
2830 if (ring->hangcheck.score > 0)
2831 ring->hangcheck.score--;
d1e61e7f
CW		 2832 }
2833
05407ff8
MK		 2834 ring->hangcheck.seqno = seqno;
2835 ring->hangcheck.acthd = acthd;
9107e9d2 2836 busy_count += busy;
893eead0 2837 }
b9201c14 2838
92cab734 2839 for_each_ring(ring, dev_priv, i) {
b6b0fac0 2840 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
b8d88d1d
DV		 2841 DRM_INFO("%s on %s\n",
2842 stuck[i] ? "stuck" : "no progress",
2843 ring->name);
a43adf07 2844 rings_hung++;
92cab734
MK		 2845 }
2846 }
2847
05407ff8 2848 if (rings_hung)
58174462 2849 return i915_handle_error(dev, true, "Ring hung");
f65d9421 2850
05407ff8
MK		 2851 if (busy_count)
2852 /* Reset timer case chip hangs without another request
2853 * being added */
10cd45b6
MK		 2854 i915_queue_hangcheck(dev);
2855}
2856
2857void i915_queue_hangcheck(struct drm_device *dev)
2858{
2859 struct drm_i915_private *dev_priv = dev->dev_private;
d330a953 2860 if (!i915.enable_hangcheck)
10cd45b6
MK		 2861 return;
2862
2863 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2864 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2865}
2866
91738a95
PZ		 2867static void ibx_irq_preinstall(struct drm_device *dev)
2868{
2869 struct drm_i915_private *dev_priv = dev->dev_private;
2870
2871 if (HAS_PCH_NOP(dev))
2872 return;
2873
f86f3fb0 2874 GEN5_IRQ_RESET(SDE);
105b122e
PZ		 2875
2876 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2877 I915_WRITE(SERR_INT, 0xffffffff);
622364b6 2878}
105b122e 2879
622364b6
PZ		 2880/*
2881 * SDEIER is also touched by the interrupt handler to work around missed PCH
2882 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2883 * instead we unconditionally enable all PCH interrupt sources here, but then
2884 * only unmask them as needed with SDEIMR.
2885 *
2886 * This function needs to be called before interrupts are enabled.
2887 */
2888static void ibx_irq_pre_postinstall(struct drm_device *dev)
2889{
2890 struct drm_i915_private *dev_priv = dev->dev_private;
2891
2892 if (HAS_PCH_NOP(dev))
2893 return;
2894
2895 WARN_ON(I915_READ(SDEIER) != 0);
91738a95
PZ		 2896 I915_WRITE(SDEIER, 0xffffffff);
2897 POSTING_READ(SDEIER);
2898}
2899
7c4d664e 2900static void gen5_gt_irq_reset(struct drm_device *dev)
d18ea1b5
DV		 2901{
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903
f86f3fb0 2904 GEN5_IRQ_RESET(GT);
a9d356a6 2905 if (INTEL_INFO(dev)->gen >= 6)
f86f3fb0 2906 GEN5_IRQ_RESET(GEN6_PM);
d18ea1b5
DV		 2907}
2908
1da177e4
LT		 2909/* drm_dma.h hooks
2910*/
f71d4af4 2911static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d 2912{
2d1013dd 2913 struct drm_i915_private *dev_priv = dev->dev_private;
036a4a7d
ZW		 2914
2915 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2916
f86f3fb0 2917 GEN5_IRQ_RESET(DE);
c6d954c1
PZ		 2918 if (IS_GEN7(dev))
2919 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
2920
7c4d664e 2921 gen5_gt_irq_reset(dev);
c650156a 2922
91738a95 2923 ibx_irq_preinstall(dev);
7d99163d
BW		 2924}
2925
7e231dbe
JB		 2926static void valleyview_irq_preinstall(struct drm_device *dev)
2927{
2d1013dd 2928 struct drm_i915_private *dev_priv = dev->dev_private;
7e231dbe
JB		 2929 int pipe;
2930
7e231dbe
JB		 2931 /* VLV magic */
2932 I915_WRITE(VLV_IMR, 0);
2933 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2934 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2935 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2936
7e231dbe
JB		 2937 /* and GT */
2938 I915_WRITE(GTIIR, I915_READ(GTIIR));
2939 I915_WRITE(GTIIR, I915_READ(GTIIR));
d18ea1b5 2940
7c4d664e 2941 gen5_gt_irq_reset(dev);
7e231dbe
JB		 2942
2943 I915_WRITE(DPINVGTT, 0xff);
2944
2945 I915_WRITE(PORT_HOTPLUG_EN, 0);
2946 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2947 for_each_pipe(pipe)
2948 I915_WRITE(PIPESTAT(pipe), 0xffff);
2949 I915_WRITE(VLV_IIR, 0xffffffff);
2950 I915_WRITE(VLV_IMR, 0xffffffff);
2951 I915_WRITE(VLV_IER, 0x0);
2952 POSTING_READ(VLV_IER);
2953}
2954
abd58f01
BW		 2955static void gen8_irq_preinstall(struct drm_device *dev)
2956{
2957 struct drm_i915_private *dev_priv = dev->dev_private;
2958 int pipe;
2959
abd58f01
BW		 2960 I915_WRITE(GEN8_MASTER_IRQ, 0);
2961 POSTING_READ(GEN8_MASTER_IRQ);
2962
f86f3fb0
PZ		 2963 GEN8_IRQ_RESET_NDX(GT, 0);
2964 GEN8_IRQ_RESET_NDX(GT, 1);
2965 GEN8_IRQ_RESET_NDX(GT, 2);
2966 GEN8_IRQ_RESET_NDX(GT, 3);
abd58f01
BW		 2967
2968 for_each_pipe(pipe) {
f86f3fb0 2969 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01
BW		 2970 }
2971
f86f3fb0
PZ		 2972 GEN5_IRQ_RESET(GEN8_DE_PORT_);
2973 GEN5_IRQ_RESET(GEN8_DE_MISC_);
2974 GEN5_IRQ_RESET(GEN8_PCU_);
09f2344d
JB		 2975
2976 ibx_irq_preinstall(dev);
abd58f01
BW		 2977}
2978
82a28bcf 2979static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973 2980{
2d1013dd 2981 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf
DV		 2982 struct drm_mode_config *mode_config = &dev->mode_config;
2983 struct intel_encoder *intel_encoder;
fee884ed 2984 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
82a28bcf
DV		 2985
2986 if (HAS_PCH_IBX(dev)) {
fee884ed 2987 hotplug_irqs = SDE_HOTPLUG_MASK;
82a28bcf 2988 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2989 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2990 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
82a28bcf 2991 } else {
fee884ed 2992 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
82a28bcf 2993 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
cd569aed 2994 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
fee884ed 2995 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
82a28bcf 2996 }
7fe0b973 2997
fee884ed 2998 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
82a28bcf
DV		 2999
3000 /*
3001 * Enable digital hotplug on the PCH, and configure the DP short pulse
3002 * duration to 2ms (which is the minimum in the Display Port spec)
3003 *
3004 * This register is the same on all known PCH chips.
3005 */
7fe0b973
KP		 3006 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3007 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3008 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3009 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3010 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3011 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3012}
3013
d46da437
PZ		 3014static void ibx_irq_postinstall(struct drm_device *dev)
3015{
2d1013dd 3016 struct drm_i915_private *dev_priv = dev->dev_private;
82a28bcf 3017 u32 mask;
e5868a31 3018
692a04cf
DV		 3019 if (HAS_PCH_NOP(dev))
3020 return;
3021
105b122e 3022 if (HAS_PCH_IBX(dev))
5c673b60 3023 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
105b122e 3024 else
5c673b60 3025 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
8664281b 3026
337ba017 3027 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
d46da437 3028 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 3029}
3030
0a9a8c91
DV		 3031static void gen5_gt_irq_postinstall(struct drm_device *dev)
3032{
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 u32 pm_irqs, gt_irqs;
3035
3036 pm_irqs = gt_irqs = 0;
3037
3038 dev_priv->gt_irq_mask = ~0;
040d2baa 3039 if (HAS_L3_DPF(dev)) {
0a9a8c91 3040 /* L3 parity interrupt is always unmasked. */
35a85ac6
BW		 3041 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3042 gt_irqs |= GT_PARITY_ERROR(dev);
0a9a8c91
DV		 3043 }
3044
3045 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3046 if (IS_GEN5(dev)) {
3047 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3048 ILK_BSD_USER_INTERRUPT;
3049 } else {
3050 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3051 }
3052
35079899 3053 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
0a9a8c91
DV		 3054
3055 if (INTEL_INFO(dev)->gen >= 6) {
a6706b45 3056 pm_irqs |= dev_priv->pm_rps_events;
0a9a8c91
DV		 3057
3058 if (HAS_VEBOX(dev))
3059 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3060
605cd25b 3061 dev_priv->pm_irq_mask = 0xffffffff;
35079899 3062 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
0a9a8c91
DV		 3063 }
3064}
3065
f71d4af4 3066static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d 3067{
4bc9d430 3068 unsigned long irqflags;
2d1013dd 3069 struct drm_i915_private *dev_priv = dev->dev_private;
8e76f8dc
PZ		 3070 u32 display_mask, extra_mask;
3071
3072 if (INTEL_INFO(dev)->gen >= 7) {
3073 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3074 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3075 DE_PLANEB_FLIP_DONE_IVB |
5c673b60 3076 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
8e76f8dc 3077 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
5c673b60 3078 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
8e76f8dc
PZ		 3079 } else {
3080 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3081 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
5b3a856b 3082 DE_AUX_CHANNEL_A |
5b3a856b
DV		 3083 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3084 DE_POISON);
5c673b60
DV		 3085 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3086 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
8e76f8dc 3087 }
036a4a7d 3088
1ec14ad3 3089 dev_priv->irq_mask = ~display_mask;
036a4a7d 3090
622364b6
PZ		 3091 ibx_irq_pre_postinstall(dev);
3092
35079899 3093 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
036a4a7d 3094
0a9a8c91 3095 gen5_gt_irq_postinstall(dev);
036a4a7d 3096
d46da437 3097 ibx_irq_postinstall(dev);
7fe0b973 3098
f97108d1 3099 if (IS_IRONLAKE_M(dev)) {
6005ce42
DV		 3100 /* Enable PCU event interrupts
3101 *
3102 * spinlocking not required here for correctness since interrupt
4bc9d430
DV		 3103 * setup is guaranteed to run in single-threaded context. But we
3104 * need it to make the assert_spin_locked happy. */
3105 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f97108d1 3106 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
4bc9d430 3107 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
f97108d1
JB		 3108 }
3109
036a4a7d
ZW		 3110 return 0;
3111}
3112
f8b79e58
ID		 3113static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3114{
3115 u32 pipestat_mask;
3116 u32 iir_mask;
3117
3118 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3119 PIPE_FIFO_UNDERRUN_STATUS;
3120
3121 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3122 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3123 POSTING_READ(PIPESTAT(PIPE_A));
3124
3125 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3126 PIPE_CRC_DONE_INTERRUPT_STATUS;
3127
3128 i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3129 PIPE_GMBUS_INTERRUPT_STATUS);
3130 i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3131
3132 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3133 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3134 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3135 dev_priv->irq_mask &= ~iir_mask;
3136
3137 I915_WRITE(VLV_IIR, iir_mask);
3138 I915_WRITE(VLV_IIR, iir_mask);
3139 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3140 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3141 POSTING_READ(VLV_IER);
3142}
3143
3144static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3145{
3146 u32 pipestat_mask;
3147 u32 iir_mask;
3148
3149 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3150 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
6c7fba04 3151 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
f8b79e58
ID		 3152
3153 dev_priv->irq_mask |= iir_mask;
3154 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3155 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3156 I915_WRITE(VLV_IIR, iir_mask);
3157 I915_WRITE(VLV_IIR, iir_mask);
3158 POSTING_READ(VLV_IIR);
3159
3160 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3161 PIPE_CRC_DONE_INTERRUPT_STATUS;
3162
3163 i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3164 PIPE_GMBUS_INTERRUPT_STATUS);
3165 i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3166
3167 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3168 PIPE_FIFO_UNDERRUN_STATUS;
3169 I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3170 I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3171 POSTING_READ(PIPESTAT(PIPE_A));
3172}
3173
3174void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3175{
3176 assert_spin_locked(&dev_priv->irq_lock);
3177
3178 if (dev_priv->display_irqs_enabled)
3179 return;
3180
3181 dev_priv->display_irqs_enabled = true;
3182
3183 if (dev_priv->dev->irq_enabled)
3184 valleyview_display_irqs_install(dev_priv);
3185}
3186
3187void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3188{
3189 assert_spin_locked(&dev_priv->irq_lock);
3190
3191 if (!dev_priv->display_irqs_enabled)
3192 return;
3193
3194 dev_priv->display_irqs_enabled = false;
3195
3196 if (dev_priv->dev->irq_enabled)
3197 valleyview_display_irqs_uninstall(dev_priv);
3198}
3199
7e231dbe
JB		 3200static int valleyview_irq_postinstall(struct drm_device *dev)
3201{
2d1013dd 3202 struct drm_i915_private *dev_priv = dev->dev_private;
b79480ba 3203 unsigned long irqflags;
7e231dbe 3204
f8b79e58 3205 dev_priv->irq_mask = ~0;
7e231dbe 3206
20afbda2
DV		 3207 I915_WRITE(PORT_HOTPLUG_EN, 0);
3208 POSTING_READ(PORT_HOTPLUG_EN);
3209
7e231dbe 3210 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
f8b79e58 3211 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
7e231dbe 3212 I915_WRITE(VLV_IIR, 0xffffffff);
7e231dbe
JB		 3213 POSTING_READ(VLV_IER);
3214
b79480ba
DV		 3215 /* Interrupt setup is already guaranteed to be single-threaded, this is
3216 * just to make the assert_spin_locked check happy. */
3217 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f8b79e58
ID		 3218 if (dev_priv->display_irqs_enabled)
3219 valleyview_display_irqs_install(dev_priv);
b79480ba 3220 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
31acc7f5 3221
7e231dbe
JB		 3222 I915_WRITE(VLV_IIR, 0xffffffff);
3223 I915_WRITE(VLV_IIR, 0xffffffff);
3224
0a9a8c91 3225 gen5_gt_irq_postinstall(dev);
7e231dbe
JB		 3226
3227 /* ack & enable invalid PTE error interrupts */
3228#if 0 /* FIXME: add support to irq handler for checking these bits */
3229 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3230 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3231#endif
3232
3233 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 3234
3235 return 0;
3236}
3237
abd58f01
BW		 3238static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3239{
3240 int i;
3241
3242 /* These are interrupts we'll toggle with the ring mask register */
3243 uint32_t gt_interrupts[] = {
3244 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3245 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3246 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3247 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3248 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3249 0,
3250 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3251 };
3252
337ba017 3253 for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
35079899 3254 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
abd58f01
BW		 3255}
3256
3257static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3258{
3259 struct drm_device *dev = dev_priv->dev;
13b3a0a7
DV		 3260 uint32_t de_pipe_masked = GEN8_PIPE_FLIP_DONE |
3261 GEN8_PIPE_CDCLK_CRC_DONE |
13b3a0a7 3262 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
5c673b60
DV		 3263 uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3264 GEN8_PIPE_FIFO_UNDERRUN;
abd58f01 3265 int pipe;
13b3a0a7
DV		 3266 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3267 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3268 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
abd58f01 3269
337ba017 3270 for_each_pipe(pipe)
35079899
PZ		 3271 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe],
3272 de_pipe_enables);
abd58f01 3273
35079899 3274 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
abd58f01
BW		 3275}
3276
3277static int gen8_irq_postinstall(struct drm_device *dev)
3278{
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280
622364b6
PZ		 3281 ibx_irq_pre_postinstall(dev);
3282
abd58f01
BW		 3283 gen8_gt_irq_postinstall(dev_priv);
3284 gen8_de_irq_postinstall(dev_priv);
3285
3286 ibx_irq_postinstall(dev);
3287
3288 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3289 POSTING_READ(GEN8_MASTER_IRQ);
3290
3291 return 0;
3292}
3293
efbd3fc3
PZ		 3294static void ibx_irq_uninstall(struct drm_device *dev)
3295{
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297
3298 if (HAS_PCH_NOP(dev))
3299 return;
3300
3301 GEN5_IRQ_RESET(SDE);
3302
3303 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3304 I915_WRITE(SERR_INT, 0xffffffff);
3305}
3306
abd58f01
BW		 3307static void gen8_irq_uninstall(struct drm_device *dev)
3308{
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 int pipe;
3311
3312 if (!dev_priv)
3313 return;
3314
abd58f01
BW		 3315 I915_WRITE(GEN8_MASTER_IRQ, 0);
3316
f86f3fb0
PZ		 3317 GEN8_IRQ_RESET_NDX(GT, 0);
3318 GEN8_IRQ_RESET_NDX(GT, 1);
3319 GEN8_IRQ_RESET_NDX(GT, 2);
3320 GEN8_IRQ_RESET_NDX(GT, 3);
abd58f01 3321
f86f3fb0
PZ		 3322 for_each_pipe(pipe)
3323 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
abd58f01 3324
f86f3fb0
PZ		 3325 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3326 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3327 GEN5_IRQ_RESET(GEN8_PCU_);
8f6ff03d
PZ		 3328
3329 ibx_irq_uninstall(dev);
abd58f01
BW		 3330}
3331
7e231dbe
JB		 3332static void valleyview_irq_uninstall(struct drm_device *dev)
3333{
2d1013dd 3334 struct drm_i915_private *dev_priv = dev->dev_private;
f8b79e58 3335 unsigned long irqflags;
7e231dbe
JB		 3336 int pipe;
3337
3338 if (!dev_priv)
3339 return;
3340
3ca1cced 3341 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3342
7e231dbe
JB		 3343 for_each_pipe(pipe)
3344 I915_WRITE(PIPESTAT(pipe), 0xffff);
3345
3346 I915_WRITE(HWSTAM, 0xffffffff);
3347 I915_WRITE(PORT_HOTPLUG_EN, 0);
3348 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
f8b79e58
ID		 3349
3350 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3351 if (dev_priv->display_irqs_enabled)
3352 valleyview_display_irqs_uninstall(dev_priv);
3353 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3354
3355 dev_priv->irq_mask = 0;
3356
7e231dbe
JB		 3357 I915_WRITE(VLV_IIR, 0xffffffff);
3358 I915_WRITE(VLV_IMR, 0xffffffff);
3359 I915_WRITE(VLV_IER, 0x0);
3360 POSTING_READ(VLV_IER);
3361}
3362
f71d4af4 3363static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d 3364{
2d1013dd 3365 struct drm_i915_private *dev_priv = dev->dev_private;
4697995b
JB		 3366
3367 if (!dev_priv)
3368 return;
3369
3ca1cced 3370 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3371
036a4a7d
ZW		 3372 I915_WRITE(HWSTAM, 0xffffffff);
3373
f86f3fb0 3374 GEN5_IRQ_RESET(DE);
8664281b 3375 if (IS_GEN7(dev))
c6d954c1 3376 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
036a4a7d 3377
7c4d664e 3378 gen5_gt_irq_reset(dev);
192aac1f 3379
efbd3fc3 3380 ibx_irq_uninstall(dev);
036a4a7d
ZW		 3381}
3382
a266c7d5 3383static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4 3384{
2d1013dd 3385 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 3386 int pipe;
91e3738e 3387
9db4a9c7
JB		 3388 for_each_pipe(pipe)
3389 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 3390 I915_WRITE16(IMR, 0xffff);
3391 I915_WRITE16(IER, 0x0);
3392 POSTING_READ16(IER);
c2798b19
CW		 3393}
3394
3395static int i8xx_irq_postinstall(struct drm_device *dev)
3396{
2d1013dd 3397 struct drm_i915_private *dev_priv = dev->dev_private;
379ef82d 3398 unsigned long irqflags;
c2798b19 3399
c2798b19
CW		 3400 I915_WRITE16(EMR,
3401 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3402
3403 /* Unmask the interrupts that we always want on. */
3404 dev_priv->irq_mask =
3405 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3406 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3407 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3408 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3409 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3410 I915_WRITE16(IMR, dev_priv->irq_mask);
3411
3412 I915_WRITE16(IER,
3413 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3414 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3415 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3416 I915_USER_INTERRUPT);
3417 POSTING_READ16(IER);
3418
379ef82d
DV		 3419 /* Interrupt setup is already guaranteed to be single-threaded, this is
3420 * just to make the assert_spin_locked check happy. */
3421 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 3422 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3423 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
379ef82d
DV		 3424 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3425
c2798b19
CW		 3426 return 0;
3427}
3428
90a72f87
VS		 3429/*
3430 * Returns true when a page flip has completed.
3431 */
3432static bool i8xx_handle_vblank(struct drm_device *dev,
1f1c2e24 3433 int plane, int pipe, u32 iir)
90a72f87 3434{
2d1013dd 3435 struct drm_i915_private *dev_priv = dev->dev_private;
1f1c2e24 3436 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
90a72f87
VS		 3437
3438 if (!drm_handle_vblank(dev, pipe))
3439 return false;
3440
3441 if ((iir & flip_pending) == 0)
3442 return false;
3443
1f1c2e24 3444 intel_prepare_page_flip(dev, plane);
90a72f87
VS		 3445
3446 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3447 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3448 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3449 * the flip is completed (no longer pending). Since this doesn't raise
3450 * an interrupt per se, we watch for the change at vblank.
3451 */
3452 if (I915_READ16(ISR) & flip_pending)
3453 return false;
3454
3455 intel_finish_page_flip(dev, pipe);
3456
3457 return true;
3458}
3459
ff1f525e 3460static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 3461{
3462 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 3463 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3464 u16 iir, new_iir;
3465 u32 pipe_stats[2];
3466 unsigned long irqflags;
c2798b19
CW		 3467 int pipe;
3468 u16 flip_mask =
3469 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3470 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3471
c2798b19
CW		 3472 iir = I915_READ16(IIR);
3473 if (iir == 0)
3474 return IRQ_NONE;
3475
3476 while (iir & ~flip_mask) {
3477 /* Can't rely on pipestat interrupt bit in iir as it might
3478 * have been cleared after the pipestat interrupt was received.
3479 * It doesn't set the bit in iir again, but it still produces
3480 * interrupts (for non-MSI).
3481 */
3482 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3483 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 3484 i915_handle_error(dev, false,
3485 "Command parser error, iir 0x%08x",
3486 iir);
c2798b19
CW		 3487
3488 for_each_pipe(pipe) {
3489 int reg = PIPESTAT(pipe);
3490 pipe_stats[pipe] = I915_READ(reg);
3491
3492 /*
3493 * Clear the PIPE*STAT regs before the IIR
3494 */
2d9d2b0b 3495 if (pipe_stats[pipe] & 0x8000ffff)
c2798b19 3496 I915_WRITE(reg, pipe_stats[pipe]);
c2798b19
CW		 3497 }
3498 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3499
3500 I915_WRITE16(IIR, iir & ~flip_mask);
3501 new_iir = I915_READ16(IIR); /* Flush posted writes */
3502
d05c617e 3503 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 3504
3505 if (iir & I915_USER_INTERRUPT)
3506 notify_ring(dev, &dev_priv->ring[RCS]);
3507
4356d586 3508 for_each_pipe(pipe) {
1f1c2e24 3509 int plane = pipe;
3a77c4c4 3510 if (HAS_FBC(dev))
1f1c2e24
VS		 3511 plane = !plane;
3512
4356d586 3513 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
1f1c2e24
VS		 3514 i8xx_handle_vblank(dev, plane, pipe, iir))
3515 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
c2798b19 3516
4356d586 3517 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3518 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3519
3520 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3521 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3522 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4356d586 3523 }
c2798b19
CW		 3524
3525 iir = new_iir;
3526 }
3527
3528 return IRQ_HANDLED;
3529}
3530
3531static void i8xx_irq_uninstall(struct drm_device * dev)
3532{
2d1013dd 3533 struct drm_i915_private *dev_priv = dev->dev_private;
c2798b19
CW		 3534 int pipe;
3535
c2798b19
CW		 3536 for_each_pipe(pipe) {
3537 /* Clear enable bits; then clear status bits */
3538 I915_WRITE(PIPESTAT(pipe), 0);
3539 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3540 }
3541 I915_WRITE16(IMR, 0xffff);
3542 I915_WRITE16(IER, 0x0);
3543 I915_WRITE16(IIR, I915_READ16(IIR));
3544}
3545
a266c7d5
CW		 3546static void i915_irq_preinstall(struct drm_device * dev)
3547{
2d1013dd 3548 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3549 int pipe;
3550
a266c7d5
CW		 3551 if (I915_HAS_HOTPLUG(dev)) {
3552 I915_WRITE(PORT_HOTPLUG_EN, 0);
3553 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3554 }
3555
00d98ebd 3556 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 3557 for_each_pipe(pipe)
3558 I915_WRITE(PIPESTAT(pipe), 0);
3559 I915_WRITE(IMR, 0xffffffff);
3560 I915_WRITE(IER, 0x0);
3561 POSTING_READ(IER);
3562}
3563
3564static int i915_irq_postinstall(struct drm_device *dev)
3565{
2d1013dd 3566 struct drm_i915_private *dev_priv = dev->dev_private;
38bde180 3567 u32 enable_mask;
379ef82d 3568 unsigned long irqflags;
a266c7d5 3569
38bde180
CW		 3570 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3571
3572 /* Unmask the interrupts that we always want on. */
3573 dev_priv->irq_mask =
3574 ~(I915_ASLE_INTERRUPT |
3575 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3576 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3577 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3578 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3579 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3580
3581 enable_mask =
3582 I915_ASLE_INTERRUPT |
3583 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3584 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3585 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
3586 I915_USER_INTERRUPT;
3587
a266c7d5 3588 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 3589 I915_WRITE(PORT_HOTPLUG_EN, 0);
3590 POSTING_READ(PORT_HOTPLUG_EN);
3591
a266c7d5
CW		 3592 /* Enable in IER... */
3593 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3594 /* and unmask in IMR */
3595 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3596 }
3597
a266c7d5
CW		 3598 I915_WRITE(IMR, dev_priv->irq_mask);
3599 I915_WRITE(IER, enable_mask);
3600 POSTING_READ(IER);
3601
f49e38dd 3602 i915_enable_asle_pipestat(dev);
20afbda2 3603
379ef82d
DV		 3604 /* Interrupt setup is already guaranteed to be single-threaded, this is
3605 * just to make the assert_spin_locked check happy. */
3606 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 3607 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3608 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
379ef82d
DV		 3609 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3610
20afbda2
DV		 3611 return 0;
3612}
3613
90a72f87
VS		 3614/*
3615 * Returns true when a page flip has completed.
3616 */
3617static bool i915_handle_vblank(struct drm_device *dev,
3618 int plane, int pipe, u32 iir)
3619{
2d1013dd 3620 struct drm_i915_private *dev_priv = dev->dev_private;
90a72f87
VS		 3621 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3622
3623 if (!drm_handle_vblank(dev, pipe))
3624 return false;
3625
3626 if ((iir & flip_pending) == 0)
3627 return false;
3628
3629 intel_prepare_page_flip(dev, plane);
3630
3631 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3632 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3633 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3634 * the flip is completed (no longer pending). Since this doesn't raise
3635 * an interrupt per se, we watch for the change at vblank.
3636 */
3637 if (I915_READ(ISR) & flip_pending)
3638 return false;
3639
3640 intel_finish_page_flip(dev, pipe);
3641
3642 return true;
3643}
3644
ff1f525e 3645static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 3646{
3647 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 3648 struct drm_i915_private *dev_priv = dev->dev_private;
8291ee90 3649 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 3650 unsigned long irqflags;
38bde180
CW		 3651 u32 flip_mask =
3652 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3653 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 3654 int pipe, ret = IRQ_NONE;
a266c7d5 3655
a266c7d5 3656 iir = I915_READ(IIR);
38bde180
CW		 3657 do {
3658 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 3659 bool blc_event = false;
a266c7d5
CW		 3660
3661 /* Can't rely on pipestat interrupt bit in iir as it might
3662 * have been cleared after the pipestat interrupt was received.
3663 * It doesn't set the bit in iir again, but it still produces
3664 * interrupts (for non-MSI).
3665 */
3666 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3667 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 3668 i915_handle_error(dev, false,
3669 "Command parser error, iir 0x%08x",
3670 iir);
a266c7d5
CW		 3671
3672 for_each_pipe(pipe) {
3673 int reg = PIPESTAT(pipe);
3674 pipe_stats[pipe] = I915_READ(reg);
3675
38bde180 3676 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5 3677 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3678 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 3679 irq_received = true;
a266c7d5
CW		 3680 }
3681 }
3682 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3683
3684 if (!irq_received)
3685 break;
3686
a266c7d5 3687 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3688 if (I915_HAS_HOTPLUG(dev) &&
3689 iir & I915_DISPLAY_PORT_INTERRUPT)
3690 i9xx_hpd_irq_handler(dev);
a266c7d5 3691
38bde180 3692 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3693 new_iir = I915_READ(IIR); /* Flush posted writes */
3694
a266c7d5
CW		 3695 if (iir & I915_USER_INTERRUPT)
3696 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 3697
a266c7d5 3698 for_each_pipe(pipe) {
38bde180 3699 int plane = pipe;
3a77c4c4 3700 if (HAS_FBC(dev))
38bde180 3701 plane = !plane;
90a72f87 3702
8291ee90 3703 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3704 i915_handle_vblank(dev, plane, pipe, iir))
3705 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 3706
3707 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3708 blc_event = true;
4356d586
DV		 3709
3710 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3711 i9xx_pipe_crc_irq_handler(dev, pipe);
2d9d2b0b
VS		 3712
3713 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3714 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3715 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
a266c7d5
CW		 3716 }
3717
a266c7d5
CW		 3718 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3719 intel_opregion_asle_intr(dev);
3720
3721 /* With MSI, interrupts are only generated when iir
3722 * transitions from zero to nonzero. If another bit got
3723 * set while we were handling the existing iir bits, then
3724 * we would never get another interrupt.
3725 *
3726 * This is fine on non-MSI as well, as if we hit this path
3727 * we avoid exiting the interrupt handler only to generate
3728 * another one.
3729 *
3730 * Note that for MSI this could cause a stray interrupt report
3731 * if an interrupt landed in the time between writing IIR and
3732 * the posting read. This should be rare enough to never
3733 * trigger the 99% of 100,000 interrupts test for disabling
3734 * stray interrupts.
3735 */
38bde180 3736 ret = IRQ_HANDLED;
a266c7d5 3737 iir = new_iir;
38bde180 3738 } while (iir & ~flip_mask);
a266c7d5 3739
d05c617e 3740 i915_update_dri1_breadcrumb(dev);
8291ee90 3741
a266c7d5
CW		 3742 return ret;
3743}
3744
3745static void i915_irq_uninstall(struct drm_device * dev)
3746{
2d1013dd 3747 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3748 int pipe;
3749
3ca1cced 3750 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3751
a266c7d5
CW		 3752 if (I915_HAS_HOTPLUG(dev)) {
3753 I915_WRITE(PORT_HOTPLUG_EN, 0);
3754 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3755 }
3756
00d98ebd 3757 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 3758 for_each_pipe(pipe) {
3759 /* Clear enable bits; then clear status bits */
a266c7d5 3760 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 3761 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3762 }
a266c7d5
CW		 3763 I915_WRITE(IMR, 0xffffffff);
3764 I915_WRITE(IER, 0x0);
3765
a266c7d5
CW		 3766 I915_WRITE(IIR, I915_READ(IIR));
3767}
3768
3769static void i965_irq_preinstall(struct drm_device * dev)
3770{
2d1013dd 3771 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3772 int pipe;
3773
adca4730
CW		 3774 I915_WRITE(PORT_HOTPLUG_EN, 0);
3775 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3776
3777 I915_WRITE(HWSTAM, 0xeffe);
3778 for_each_pipe(pipe)
3779 I915_WRITE(PIPESTAT(pipe), 0);
3780 I915_WRITE(IMR, 0xffffffff);
3781 I915_WRITE(IER, 0x0);
3782 POSTING_READ(IER);
3783}
3784
3785static int i965_irq_postinstall(struct drm_device *dev)
3786{
2d1013dd 3787 struct drm_i915_private *dev_priv = dev->dev_private;
bbba0a97 3788 u32 enable_mask;
a266c7d5 3789 u32 error_mask;
b79480ba 3790 unsigned long irqflags;
a266c7d5 3791
a266c7d5 3792 /* Unmask the interrupts that we always want on. */
bbba0a97 3793 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 3794 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 3795 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3796 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3797 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3798 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
3799 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
3800
3801 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 3802 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3803 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 3804 enable_mask |= I915_USER_INTERRUPT;
3805
3806 if (IS_G4X(dev))
3807 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 3808
b79480ba
DV		 3809 /* Interrupt setup is already guaranteed to be single-threaded, this is
3810 * just to make the assert_spin_locked check happy. */
3811 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
755e9019
ID		 3812 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3813 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3814 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
b79480ba 3815 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
a266c7d5 3816
a266c7d5
CW		 3817 /*
3818 * Enable some error detection, note the instruction error mask
3819 * bit is reserved, so we leave it masked.
3820 */
3821 if (IS_G4X(dev)) {
3822 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3823 GM45_ERROR_MEM_PRIV |
3824 GM45_ERROR_CP_PRIV |
3825 I915_ERROR_MEMORY_REFRESH);
3826 } else {
3827 error_mask = ~(I915_ERROR_PAGE_TABLE |
3828 I915_ERROR_MEMORY_REFRESH);
3829 }
3830 I915_WRITE(EMR, error_mask);
3831
3832 I915_WRITE(IMR, dev_priv->irq_mask);
3833 I915_WRITE(IER, enable_mask);
3834 POSTING_READ(IER);
3835
20afbda2
DV		 3836 I915_WRITE(PORT_HOTPLUG_EN, 0);
3837 POSTING_READ(PORT_HOTPLUG_EN);
3838
f49e38dd 3839 i915_enable_asle_pipestat(dev);
20afbda2
DV		 3840
3841 return 0;
3842}
3843
bac56d5b 3844static void i915_hpd_irq_setup(struct drm_device *dev)
20afbda2 3845{
2d1013dd 3846 struct drm_i915_private *dev_priv = dev->dev_private;
e5868a31 3847 struct drm_mode_config *mode_config = &dev->mode_config;
cd569aed 3848 struct intel_encoder *intel_encoder;
20afbda2
DV		 3849 u32 hotplug_en;
3850
b5ea2d56
DV		 3851 assert_spin_locked(&dev_priv->irq_lock);
3852
bac56d5b
EE		 3853 if (I915_HAS_HOTPLUG(dev)) {
3854 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
3855 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
3856 /* Note HDMI and DP share hotplug bits */
e5868a31 3857 /* enable bits are the same for all generations */
cd569aed
EE		 3858 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
3859 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3860 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
bac56d5b
EE		 3861 /* Programming the CRT detection parameters tends
3862 to generate a spurious hotplug event about three
3863 seconds later. So just do it once.
3864 */
3865 if (IS_G4X(dev))
3866 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
85fc95ba 3867 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
bac56d5b 3868 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 3869
bac56d5b
EE		 3870 /* Ignore TV since it's buggy */
3871 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
3872 }
a266c7d5
CW		 3873}
3874
ff1f525e 3875static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 3876{
3877 struct drm_device *dev = (struct drm_device *) arg;
2d1013dd 3878 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3879 u32 iir, new_iir;
3880 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5 3881 unsigned long irqflags;
a266c7d5 3882 int ret = IRQ_NONE, pipe;
21ad8330
VS		 3883 u32 flip_mask =
3884 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3885 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5 3886
a266c7d5
CW		 3887 iir = I915_READ(IIR);
3888
a266c7d5 3889 for (;;) {
501e01d7 3890 bool irq_received = (iir & ~flip_mask) != 0;
2c8ba29f
CW		 3891 bool blc_event = false;
3892
a266c7d5
CW		 3893 /* Can't rely on pipestat interrupt bit in iir as it might
3894 * have been cleared after the pipestat interrupt was received.
3895 * It doesn't set the bit in iir again, but it still produces
3896 * interrupts (for non-MSI).
3897 */
3898 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3899 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
58174462
MK		 3900 i915_handle_error(dev, false,
3901 "Command parser error, iir 0x%08x",
3902 iir);
a266c7d5
CW		 3903
3904 for_each_pipe(pipe) {
3905 int reg = PIPESTAT(pipe);
3906 pipe_stats[pipe] = I915_READ(reg);
3907
3908 /*
3909 * Clear the PIPE*STAT regs before the IIR
3910 */
3911 if (pipe_stats[pipe] & 0x8000ffff) {
a266c7d5 3912 I915_WRITE(reg, pipe_stats[pipe]);
501e01d7 3913 irq_received = true;
a266c7d5
CW		 3914 }
3915 }
3916 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3917
3918 if (!irq_received)
3919 break;
3920
3921 ret = IRQ_HANDLED;
3922
3923 /* Consume port. Then clear IIR or we'll miss events */
16c6c56b
VS		 3924 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3925 i9xx_hpd_irq_handler(dev);
a266c7d5 3926
21ad8330 3927 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 3928 new_iir = I915_READ(IIR); /* Flush posted writes */
3929
a266c7d5
CW		 3930 if (iir & I915_USER_INTERRUPT)
3931 notify_ring(dev, &dev_priv->ring[RCS]);
3932 if (iir & I915_BSD_USER_INTERRUPT)
3933 notify_ring(dev, &dev_priv->ring[VCS]);
3934
a266c7d5 3935 for_each_pipe(pipe) {
2c8ba29f 3936 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 3937 i915_handle_vblank(dev, pipe, pipe, iir))
3938 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 3939
3940 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3941 blc_event = true;
4356d586
DV		 3942
3943 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
277de95e 3944 i9xx_pipe_crc_irq_handler(dev, pipe);
a266c7d5 3945
2d9d2b0b
VS		 3946 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
3947 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
fc2c807b 3948 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2d9d2b0b 3949 }
a266c7d5
CW		 3950
3951 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3952 intel_opregion_asle_intr(dev);
3953
515ac2bb
DV		 3954 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3955 gmbus_irq_handler(dev);
3956
a266c7d5
CW		 3957 /* With MSI, interrupts are only generated when iir
3958 * transitions from zero to nonzero. If another bit got
3959 * set while we were handling the existing iir bits, then
3960 * we would never get another interrupt.
3961 *
3962 * This is fine on non-MSI as well, as if we hit this path
3963 * we avoid exiting the interrupt handler only to generate
3964 * another one.
3965 *
3966 * Note that for MSI this could cause a stray interrupt report
3967 * if an interrupt landed in the time between writing IIR and
3968 * the posting read. This should be rare enough to never
3969 * trigger the 99% of 100,000 interrupts test for disabling
3970 * stray interrupts.
3971 */
3972 iir = new_iir;
3973 }
3974
d05c617e 3975 i915_update_dri1_breadcrumb(dev);
2c8ba29f 3976
a266c7d5
CW		 3977 return ret;
3978}
3979
3980static void i965_irq_uninstall(struct drm_device * dev)
3981{
2d1013dd 3982 struct drm_i915_private *dev_priv = dev->dev_private;
a266c7d5
CW		 3983 int pipe;
3984
3985 if (!dev_priv)
3986 return;
3987
3ca1cced 3988 intel_hpd_irq_uninstall(dev_priv);
ac4c16c5 3989
adca4730
CW		 3990 I915_WRITE(PORT_HOTPLUG_EN, 0);
3991 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 3992
3993 I915_WRITE(HWSTAM, 0xffffffff);
3994 for_each_pipe(pipe)
3995 I915_WRITE(PIPESTAT(pipe), 0);
3996 I915_WRITE(IMR, 0xffffffff);
3997 I915_WRITE(IER, 0x0);
3998
3999 for_each_pipe(pipe)
4000 I915_WRITE(PIPESTAT(pipe),
4001 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4002 I915_WRITE(IIR, I915_READ(IIR));
4003}
4004
3ca1cced 4005static void intel_hpd_irq_reenable(unsigned long data)
ac4c16c5 4006{
2d1013dd 4007 struct drm_i915_private *dev_priv = (struct drm_i915_private *)data;
ac4c16c5
EE		 4008 struct drm_device *dev = dev_priv->dev;
4009 struct drm_mode_config *mode_config = &dev->mode_config;
4010 unsigned long irqflags;
4011 int i;
4012
4013 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4014 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4015 struct drm_connector *connector;
4016
4017 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4018 continue;
4019
4020 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4021
4022 list_for_each_entry(connector, &mode_config->connector_list, head) {
4023 struct intel_connector *intel_connector = to_intel_connector(connector);
4024
4025 if (intel_connector->encoder->hpd_pin == i) {
4026 if (connector->polled != intel_connector->polled)
4027 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4028 drm_get_connector_name(connector));
4029 connector->polled = intel_connector->polled;
4030 if (!connector->polled)
4031 connector->polled = DRM_CONNECTOR_POLL_HPD;
4032 }
4033 }
4034 }
4035 if (dev_priv->display.hpd_irq_setup)
4036 dev_priv->display.hpd_irq_setup(dev);
4037 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4038}
4039
f71d4af4
JB		 4040void intel_irq_init(struct drm_device *dev)
4041{
8b2e326d
CW		 4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043
4044 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 4045 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 4046 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 4047 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 4048
a6706b45
D		 4049 /* Let's track the enabled rps events */
4050 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4051
99584db3
DV		 4052 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4053 i915_hangcheck_elapsed,
61bac78e 4054 (unsigned long) dev);
3ca1cced 4055 setup_timer(&dev_priv->hotplug_reenable_timer, intel_hpd_irq_reenable,
ac4c16c5 4056 (unsigned long) dev_priv);
61bac78e 4057
97a19a24 4058 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 4059
4cdb83ec
VS		 4060 if (IS_GEN2(dev)) {
4061 dev->max_vblank_count = 0;
4062 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4063 } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 4064 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4065 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
391f75e2
VS		 4066 } else {
4067 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4068 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
f71d4af4
JB		 4069 }
4070
c2baf4b7 4071 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c3613de9 4072 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
c2baf4b7
VS		 4073 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4074 }
f71d4af4 4075
7e231dbe
JB		 4076 if (IS_VALLEYVIEW(dev)) {
4077 dev->driver->irq_handler = valleyview_irq_handler;
4078 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4079 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4080 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4081 dev->driver->enable_vblank = valleyview_enable_vblank;
4082 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 4083 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
abd58f01
BW		 4084 } else if (IS_GEN8(dev)) {
4085 dev->driver->irq_handler = gen8_irq_handler;
4086 dev->driver->irq_preinstall = gen8_irq_preinstall;
4087 dev->driver->irq_postinstall = gen8_irq_postinstall;
4088 dev->driver->irq_uninstall = gen8_irq_uninstall;
4089 dev->driver->enable_vblank = gen8_enable_vblank;
4090 dev->driver->disable_vblank = gen8_disable_vblank;
4091 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 4092 } else if (HAS_PCH_SPLIT(dev)) {
4093 dev->driver->irq_handler = ironlake_irq_handler;
4094 dev->driver->irq_preinstall = ironlake_irq_preinstall;
4095 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4096 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4097 dev->driver->enable_vblank = ironlake_enable_vblank;
4098 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 4099 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 4100 } else {
c2798b19
CW		 4101 if (INTEL_INFO(dev)->gen == 2) {
4102 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4103 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4104 dev->driver->irq_handler = i8xx_irq_handler;
4105 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 4106 } else if (INTEL_INFO(dev)->gen == 3) {
4107 dev->driver->irq_preinstall = i915_irq_preinstall;
4108 dev->driver->irq_postinstall = i915_irq_postinstall;
4109 dev->driver->irq_uninstall = i915_irq_uninstall;
4110 dev->driver->irq_handler = i915_irq_handler;
20afbda2 4111 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 4112 } else {
a266c7d5
CW		 4113 dev->driver->irq_preinstall = i965_irq_preinstall;
4114 dev->driver->irq_postinstall = i965_irq_postinstall;
4115 dev->driver->irq_uninstall = i965_irq_uninstall;
4116 dev->driver->irq_handler = i965_irq_handler;
bac56d5b 4117 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 4118 }
f71d4af4
JB		 4119 dev->driver->enable_vblank = i915_enable_vblank;
4120 dev->driver->disable_vblank = i915_disable_vblank;
4121 }
4122}
20afbda2
DV		 4123
4124void intel_hpd_init(struct drm_device *dev)
4125{
4126 struct drm_i915_private *dev_priv = dev->dev_private;
821450c6
EE		 4127 struct drm_mode_config *mode_config = &dev->mode_config;
4128 struct drm_connector *connector;
b5ea2d56 4129 unsigned long irqflags;
821450c6 4130 int i;
20afbda2 4131
821450c6
EE		 4132 for (i = 1; i < HPD_NUM_PINS; i++) {
4133 dev_priv->hpd_stats[i].hpd_cnt = 0;
4134 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4135 }
4136 list_for_each_entry(connector, &mode_config->connector_list, head) {
4137 struct intel_connector *intel_connector = to_intel_connector(connector);
4138 connector->polled = intel_connector->polled;
4139 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4140 connector->polled = DRM_CONNECTOR_POLL_HPD;
4141 }
b5ea2d56
DV		 4142
4143 /* Interrupt setup is already guaranteed to be single-threaded, this is
4144 * just to make the assert_spin_locked checks happy. */
4145 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
20afbda2
DV		 4146 if (dev_priv->display.hpd_irq_setup)
4147 dev_priv->display.hpd_irq_setup(dev);
b5ea2d56 4148 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
20afbda2 4149}
c67a470b 4150
5d584b2e
PZ		 4151/* Disable interrupts so we can allow runtime PM. */
4152void hsw_runtime_pm_disable_interrupts(struct drm_device *dev)
c67a470b
PZ		 4153{
4154 struct drm_i915_private *dev_priv = dev->dev_private;
4155 unsigned long irqflags;
4156
4157 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4158
5d584b2e
PZ		 4159 dev_priv->pm.regsave.deimr = I915_READ(DEIMR);
4160 dev_priv->pm.regsave.sdeimr = I915_READ(SDEIMR);
4161 dev_priv->pm.regsave.gtimr = I915_READ(GTIMR);
4162 dev_priv->pm.regsave.gtier = I915_READ(GTIER);
4163 dev_priv->pm.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
c67a470b 4164
1f2d4531
PZ		 4165 ironlake_disable_display_irq(dev_priv, 0xffffffff);
4166 ibx_disable_display_interrupt(dev_priv, 0xffffffff);
c67a470b
PZ		 4167 ilk_disable_gt_irq(dev_priv, 0xffffffff);
4168 snb_disable_pm_irq(dev_priv, 0xffffffff);
4169
5d584b2e 4170 dev_priv->pm.irqs_disabled = true;
c67a470b
PZ		 4171
4172 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4173}
4174
5d584b2e
PZ		 4175/* Restore interrupts so we can recover from runtime PM. */
4176void hsw_runtime_pm_restore_interrupts(struct drm_device *dev)
c67a470b
PZ		 4177{
4178 struct drm_i915_private *dev_priv = dev->dev_private;
4179 unsigned long irqflags;
1f2d4531 4180 uint32_t val;
c67a470b
PZ		 4181
4182 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4183
4184 val = I915_READ(DEIMR);
1f2d4531 4185 WARN(val != 0xffffffff, "DEIMR is 0x%08x\n", val);
c67a470b 4186
1f2d4531
PZ		 4187 val = I915_READ(SDEIMR);
4188 WARN(val != 0xffffffff, "SDEIMR is 0x%08x\n", val);
c67a470b
PZ		 4189
4190 val = I915_READ(GTIMR);
1f2d4531 4191 WARN(val != 0xffffffff, "GTIMR is 0x%08x\n", val);
c67a470b
PZ		 4192
4193 val = I915_READ(GEN6_PMIMR);
1f2d4531 4194 WARN(val != 0xffffffff, "GEN6_PMIMR is 0x%08x\n", val);
c67a470b 4195
5d584b2e 4196 dev_priv->pm.irqs_disabled = false;
c67a470b 4197
5d584b2e
PZ		 4198 ironlake_enable_display_irq(dev_priv, ~dev_priv->pm.regsave.deimr);
4199 ibx_enable_display_interrupt(dev_priv, ~dev_priv->pm.regsave.sdeimr);
4200 ilk_enable_gt_irq(dev_priv, ~dev_priv->pm.regsave.gtimr);
4201 snb_enable_pm_irq(dev_priv, ~dev_priv->pm.regsave.gen6_pmimr);
4202 I915_WRITE(GTIER, dev_priv->pm.regsave.gtier);
c67a470b
PZ		 4203
4204 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4205}
Linux kernel - Deliverables
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