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char/agp: add another Ironlake host bridge
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
4912d041 353 u32 pm_iir, pm_imr;
7b9e0ae6 354 u8 new_delay;
4912d041
BW		 355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
7b9e0ae6 363 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 367
368 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
369 new_delay = dev_priv->cur_delay + 1;
370 else
371 new_delay = dev_priv->cur_delay - 1;
3b8d8d91 372
4912d041 373 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 374
4912d041 375 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 376}
377
e7b4c6b1
DV		 378static void snb_gt_irq_handler(struct drm_device *dev,
379 struct drm_i915_private *dev_priv,
380 u32 gt_iir)
381{
382
383 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
384 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
385 notify_ring(dev, &dev_priv->ring[RCS]);
386 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
387 notify_ring(dev, &dev_priv->ring[VCS]);
388 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
389 notify_ring(dev, &dev_priv->ring[BCS]);
390
391 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
392 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
393 GT_RENDER_CS_ERROR_INTERRUPT)) {
394 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
395 i915_handle_error(dev, false);
396 }
397}
398
fc6826d1
CW		 399static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
400 u32 pm_iir)
401{
402 unsigned long flags;
403
404 /*
405 * IIR bits should never already be set because IMR should
406 * prevent an interrupt from being shown in IIR. The warning
407 * displays a case where we've unsafely cleared
408 * dev_priv->pm_iir. Although missing an interrupt of the same
409 * type is not a problem, it displays a problem in the logic.
410 *
411 * The mask bit in IMR is cleared by rps_work.
412 */
413
414 spin_lock_irqsave(&dev_priv->rps_lock, flags);
415 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
416 dev_priv->pm_iir |= pm_iir;
417 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
418 POSTING_READ(GEN6_PMIMR);
419 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
420
421 queue_work(dev_priv->wq, &dev_priv->rps_work);
422}
423
7e231dbe
JB		 424static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
425{
426 struct drm_device *dev = (struct drm_device *) arg;
427 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
428 u32 iir, gt_iir, pm_iir;
429 irqreturn_t ret = IRQ_NONE;
430 unsigned long irqflags;
431 int pipe;
432 u32 pipe_stats[I915_MAX_PIPES];
433 u32 vblank_status;
434 int vblank = 0;
435 bool blc_event;
436
437 atomic_inc(&dev_priv->irq_received);
438
439 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
440 PIPE_VBLANK_INTERRUPT_STATUS;
441
442 while (true) {
443 iir = I915_READ(VLV_IIR);
444 gt_iir = I915_READ(GTIIR);
445 pm_iir = I915_READ(GEN6_PMIIR);
446
447 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
448 goto out;
449
450 ret = IRQ_HANDLED;
451
e7b4c6b1 452 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 453
454 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
455 for_each_pipe(pipe) {
456 int reg = PIPESTAT(pipe);
457 pipe_stats[pipe] = I915_READ(reg);
458
459 /*
460 * Clear the PIPE*STAT regs before the IIR
461 */
462 if (pipe_stats[pipe] & 0x8000ffff) {
463 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
464 DRM_DEBUG_DRIVER("pipe %c underrun\n",
465 pipe_name(pipe));
466 I915_WRITE(reg, pipe_stats[pipe]);
467 }
468 }
469 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
470
471 /* Consume port. Then clear IIR or we'll miss events */
472 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
473 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
474
475 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
476 hotplug_status);
477 if (hotplug_status & dev_priv->hotplug_supported_mask)
478 queue_work(dev_priv->wq,
479 &dev_priv->hotplug_work);
480
481 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
482 I915_READ(PORT_HOTPLUG_STAT);
483 }
484
485
486 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
487 drm_handle_vblank(dev, 0);
488 vblank++;
e0f608d7 489 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 490 }
491
492 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
493 drm_handle_vblank(dev, 1);
494 vblank++;
e0f608d7 495 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 496 }
497
498 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
499 blc_event = true;
500
fc6826d1
CW		 501 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
502 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 503
504 I915_WRITE(GTIIR, gt_iir);
505 I915_WRITE(GEN6_PMIIR, pm_iir);
506 I915_WRITE(VLV_IIR, iir);
507 }
508
509out:
510 return ret;
511}
512
9adab8b5 513static void pch_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 514{
515 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 516 int pipe;
776ad806 517
776ad806
JB		 518 if (pch_iir & SDE_AUDIO_POWER_MASK)
519 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
520 (pch_iir & SDE_AUDIO_POWER_MASK) >>
521 SDE_AUDIO_POWER_SHIFT);
522
523 if (pch_iir & SDE_GMBUS)
524 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
525
526 if (pch_iir & SDE_AUDIO_HDCP_MASK)
527 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
528
529 if (pch_iir & SDE_AUDIO_TRANS_MASK)
530 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
531
532 if (pch_iir & SDE_POISON)
533 DRM_ERROR("PCH poison interrupt\n");
534
9db4a9c7
JB		 535 if (pch_iir & SDE_FDI_MASK)
536 for_each_pipe(pipe)
537 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
538 pipe_name(pipe),
539 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 540
541 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
542 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
543
544 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
545 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
546
547 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
548 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
549 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
550 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
551}
552
f71d4af4 553static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 554{
555 struct drm_device *dev = (struct drm_device *) arg;
556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 557 u32 de_iir, gt_iir, de_ier, pm_iir;
558 irqreturn_t ret = IRQ_NONE;
559 int i;
b1f14ad0
JB		 560
561 atomic_inc(&dev_priv->irq_received);
562
563 /* disable master interrupt before clearing iir */
564 de_ier = I915_READ(DEIER);
565 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 566
b1f14ad0 567 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 568 if (gt_iir) {
569 snb_gt_irq_handler(dev, dev_priv, gt_iir);
570 I915_WRITE(GTIIR, gt_iir);
571 ret = IRQ_HANDLED;
b1f14ad0
JB		 572 }
573
0e43406b
CW		 574 de_iir = I915_READ(DEIIR);
575 if (de_iir) {
576 if (de_iir & DE_GSE_IVB)
577 intel_opregion_gse_intr(dev);
578
579 for (i = 0; i < 3; i++) {
580 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
581 intel_prepare_page_flip(dev, i);
582 intel_finish_page_flip_plane(dev, i);
583 }
584 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
585 drm_handle_vblank(dev, i);
586 }
b615b57a 587
0e43406b
CW		 588 /* check event from PCH */
589 if (de_iir & DE_PCH_EVENT_IVB) {
590 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 591
0e43406b
CW		 592 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
593 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
594 pch_irq_handler(dev, pch_iir);
b1f14ad0 595
0e43406b
CW		 596 /* clear PCH hotplug event before clear CPU irq */
597 I915_WRITE(SDEIIR, pch_iir);
598 }
b615b57a 599
0e43406b
CW		 600 I915_WRITE(DEIIR, de_iir);
601 ret = IRQ_HANDLED;
b1f14ad0
JB		 602 }
603
0e43406b
CW		 604 pm_iir = I915_READ(GEN6_PMIIR);
605 if (pm_iir) {
606 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
607 gen6_queue_rps_work(dev_priv, pm_iir);
608 I915_WRITE(GEN6_PMIIR, pm_iir);
609 ret = IRQ_HANDLED;
610 }
b1f14ad0 611
b1f14ad0
JB		 612 I915_WRITE(DEIER, de_ier);
613 POSTING_READ(DEIER);
614
615 return ret;
616}
617
e7b4c6b1
DV		 618static void ilk_gt_irq_handler(struct drm_device *dev,
619 struct drm_i915_private *dev_priv,
620 u32 gt_iir)
621{
622 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
623 notify_ring(dev, &dev_priv->ring[RCS]);
624 if (gt_iir & GT_BSD_USER_INTERRUPT)
625 notify_ring(dev, &dev_priv->ring[VCS]);
626}
627
f71d4af4 628static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 629{
4697995b 630 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 631 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
632 int ret = IRQ_NONE;
3b8d8d91 633 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 634 u32 hotplug_mask;
881f47b6 635
4697995b
JB		 636 atomic_inc(&dev_priv->irq_received);
637
2d109a84
ZN		 638 /* disable master interrupt before clearing iir */
639 de_ier = I915_READ(DEIER);
640 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 641 POSTING_READ(DEIER);
2d109a84 642
036a4a7d
ZW		 643 de_iir = I915_READ(DEIIR);
644 gt_iir = I915_READ(GTIIR);
c650156a 645 pch_iir = I915_READ(SDEIIR);
3b8d8d91 646 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 647
3b8d8d91
JB		 648 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
649 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 650 goto done;
036a4a7d 651
2d7b8366
YL		 652 if (HAS_PCH_CPT(dev))
653 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
654 else
655 hotplug_mask = SDE_HOTPLUG_MASK;
656
c7c85101 657 ret = IRQ_HANDLED;
036a4a7d 658
e7b4c6b1
DV		 659 if (IS_GEN5(dev))
660 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
661 else
662 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 663
c7c85101 664 if (de_iir & DE_GSE)
3b617967 665 intel_opregion_gse_intr(dev);
c650156a 666
f072d2e7 667 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 668 intel_prepare_page_flip(dev, 0);
2bbda389 669 intel_finish_page_flip_plane(dev, 0);
f072d2e7 670 }
013d5aa2 671
f072d2e7 672 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 673 intel_prepare_page_flip(dev, 1);
2bbda389 674 intel_finish_page_flip_plane(dev, 1);
f072d2e7 675 }
013d5aa2 676
f072d2e7 677 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 678 drm_handle_vblank(dev, 0);
679
f072d2e7 680 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 681 drm_handle_vblank(dev, 1);
682
c7c85101 683 /* check event from PCH */
776ad806
JB		 684 if (de_iir & DE_PCH_EVENT) {
685 if (pch_iir & hotplug_mask)
686 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
9adab8b5 687 pch_irq_handler(dev, pch_iir);
776ad806 688 }
036a4a7d 689
f97108d1 690 if (de_iir & DE_PCU_EVENT) {
7648fa99 691 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 692 i915_handle_rps_change(dev);
693 }
694
fc6826d1
CW		 695 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
696 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 697
c7c85101
ZN		 698 /* should clear PCH hotplug event before clear CPU irq */
699 I915_WRITE(SDEIIR, pch_iir);
700 I915_WRITE(GTIIR, gt_iir);
701 I915_WRITE(DEIIR, de_iir);
4912d041 702 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 703
704done:
2d109a84 705 I915_WRITE(DEIER, de_ier);
3143a2bf 706 POSTING_READ(DEIER);
2d109a84 707
036a4a7d
ZW		 708 return ret;
709}
710
8a905236
JB		 711/**
712 * i915_error_work_func - do process context error handling work
713 * @work: work struct
714 *
715 * Fire an error uevent so userspace can see that a hang or error
716 * was detected.
717 */
718static void i915_error_work_func(struct work_struct *work)
719{
720 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
721 error_work);
722 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 723 char *error_event[] = { "ERROR=1", NULL };
724 char *reset_event[] = { "RESET=1", NULL };
725 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 726
f316a42c
BG		 727 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
728
ba1234d1 729 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 730 DRM_DEBUG_DRIVER("resetting chip\n");
731 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 732 if (!i915_reset(dev)) {
f803aa55
CW		 733 atomic_set(&dev_priv->mm.wedged, 0);
734 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 735 }
30dbf0c0 736 complete_all(&dev_priv->error_completion);
f316a42c 737 }
8a905236
JB		 738}
739
3bd3c932 740#ifdef CONFIG_DEBUG_FS
9df30794 741static struct drm_i915_error_object *
bcfb2e28 742i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 743 struct drm_i915_gem_object *src)
9df30794
CW		 744{
745 struct drm_i915_error_object *dst;
9df30794 746 int page, page_count;
e56660dd 747 u32 reloc_offset;
9df30794 748
05394f39 749 if (src == NULL || src->pages == NULL)
9df30794
CW		 750 return NULL;
751
05394f39 752 page_count = src->base.size / PAGE_SIZE;
9df30794 753
0206e353 754 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 755 if (dst == NULL)
756 return NULL;
757
05394f39 758 reloc_offset = src->gtt_offset;
9df30794 759 for (page = 0; page < page_count; page++) {
788885ae 760 unsigned long flags;
e56660dd 761 void *d;
788885ae 762
e56660dd 763 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 764 if (d == NULL)
765 goto unwind;
e56660dd 766
788885ae 767 local_irq_save(flags);
74898d7e
DV		 768 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
769 src->has_global_gtt_mapping) {
172975aa
CW		 770 void __iomem *s;
771
772 /* Simply ignore tiling or any overlapping fence.
773 * It's part of the error state, and this hopefully
774 * captures what the GPU read.
775 */
776
777 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
778 reloc_offset);
779 memcpy_fromio(d, s, PAGE_SIZE);
780 io_mapping_unmap_atomic(s);
781 } else {
782 void *s;
783
784 drm_clflush_pages(&src->pages[page], 1);
785
786 s = kmap_atomic(src->pages[page]);
787 memcpy(d, s, PAGE_SIZE);
788 kunmap_atomic(s);
789
790 drm_clflush_pages(&src->pages[page], 1);
791 }
788885ae 792 local_irq_restore(flags);
e56660dd 793
9df30794 794 dst->pages[page] = d;
e56660dd
CW		 795
796 reloc_offset += PAGE_SIZE;
9df30794
CW		 797 }
798 dst->page_count = page_count;
05394f39 799 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 800
801 return dst;
802
803unwind:
804 while (page--)
805 kfree(dst->pages[page]);
806 kfree(dst);
807 return NULL;
808}
809
810static void
811i915_error_object_free(struct drm_i915_error_object *obj)
812{
813 int page;
814
815 if (obj == NULL)
816 return;
817
818 for (page = 0; page < obj->page_count; page++)
819 kfree(obj->pages[page]);
820
821 kfree(obj);
822}
823
742cbee8
DV		 824void
825i915_error_state_free(struct kref *error_ref)
9df30794 826{
742cbee8
DV		 827 struct drm_i915_error_state *error = container_of(error_ref,
828 typeof(*error), ref);
e2f973d5
CW		 829 int i;
830
52d39a21
CW		 831 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
832 i915_error_object_free(error->ring[i].batchbuffer);
833 i915_error_object_free(error->ring[i].ringbuffer);
834 kfree(error->ring[i].requests);
835 }
e2f973d5 836
9df30794 837 kfree(error->active_bo);
6ef3d427 838 kfree(error->overlay);
9df30794
CW		 839 kfree(error);
840}
1b50247a
CW		 841static void capture_bo(struct drm_i915_error_buffer *err,
842 struct drm_i915_gem_object *obj)
843{
844 err->size = obj->base.size;
845 err->name = obj->base.name;
846 err->seqno = obj->last_rendering_seqno;
847 err->gtt_offset = obj->gtt_offset;
848 err->read_domains = obj->base.read_domains;
849 err->write_domain = obj->base.write_domain;
850 err->fence_reg = obj->fence_reg;
851 err->pinned = 0;
852 if (obj->pin_count > 0)
853 err->pinned = 1;
854 if (obj->user_pin_count > 0)
855 err->pinned = -1;
856 err->tiling = obj->tiling_mode;
857 err->dirty = obj->dirty;
858 err->purgeable = obj->madv != I915_MADV_WILLNEED;
859 err->ring = obj->ring ? obj->ring->id : -1;
860 err->cache_level = obj->cache_level;
861}
9df30794 862
1b50247a
CW		 863static u32 capture_active_bo(struct drm_i915_error_buffer *err,
864 int count, struct list_head *head)
c724e8a9
CW		 865{
866 struct drm_i915_gem_object *obj;
867 int i = 0;
868
869 list_for_each_entry(obj, head, mm_list) {
1b50247a 870 capture_bo(err++, obj);
c724e8a9
CW		 871 if (++i == count)
872 break;
1b50247a
CW		 873 }
874
875 return i;
876}
877
878static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
879 int count, struct list_head *head)
880{
881 struct drm_i915_gem_object *obj;
882 int i = 0;
883
884 list_for_each_entry(obj, head, gtt_list) {
885 if (obj->pin_count == 0)
886 continue;
c724e8a9 887
1b50247a
CW		 888 capture_bo(err++, obj);
889 if (++i == count)
890 break;
c724e8a9
CW		 891 }
892
893 return i;
894}
895
748ebc60
CW		 896static void i915_gem_record_fences(struct drm_device *dev,
897 struct drm_i915_error_state *error)
898{
899 struct drm_i915_private *dev_priv = dev->dev_private;
900 int i;
901
902 /* Fences */
903 switch (INTEL_INFO(dev)->gen) {
775d17b6 904 case 7:
748ebc60
CW		 905 case 6:
906 for (i = 0; i < 16; i++)
907 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
908 break;
909 case 5:
910 case 4:
911 for (i = 0; i < 16; i++)
912 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
913 break;
914 case 3:
915 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
916 for (i = 0; i < 8; i++)
917 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
918 case 2:
919 for (i = 0; i < 8; i++)
920 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
921 break;
922
923 }
924}
925
bcfb2e28
CW		 926static struct drm_i915_error_object *
927i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
928 struct intel_ring_buffer *ring)
929{
930 struct drm_i915_gem_object *obj;
931 u32 seqno;
932
933 if (!ring->get_seqno)
934 return NULL;
935
936 seqno = ring->get_seqno(ring);
937 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
938 if (obj->ring != ring)
939 continue;
940
c37d9a5d 941 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 942 continue;
943
944 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
945 continue;
946
947 /* We need to copy these to an anonymous buffer as the simplest
948 * method to avoid being overwritten by userspace.
949 */
950 return i915_error_object_create(dev_priv, obj);
951 }
952
953 return NULL;
954}
955
d27b1e0e
DV		 956static void i915_record_ring_state(struct drm_device *dev,
957 struct drm_i915_error_state *error,
958 struct intel_ring_buffer *ring)
959{
960 struct drm_i915_private *dev_priv = dev->dev_private;
961
33f3f518 962 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 963 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 964 error->semaphore_mboxes[ring->id][0]
965 = I915_READ(RING_SYNC_0(ring->mmio_base));
966 error->semaphore_mboxes[ring->id][1]
967 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 968 }
c1cd90ed 969
d27b1e0e 970 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 971 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 972 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
973 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
974 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 975 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 976 if (ring->id == RCS) {
d27b1e0e
DV		 977 error->instdone1 = I915_READ(INSTDONE1);
978 error->bbaddr = I915_READ64(BB_ADDR);
979 }
980 } else {
9d2f41fa 981 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 982 error->ipeir[ring->id] = I915_READ(IPEIR);
983 error->ipehr[ring->id] = I915_READ(IPEHR);
984 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 985 }
986
9574b3fe 987 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 988 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 989 error->seqno[ring->id] = ring->get_seqno(ring);
990 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 991 error->head[ring->id] = I915_READ_HEAD(ring);
992 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 993
994 error->cpu_ring_head[ring->id] = ring->head;
995 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 996}
997
52d39a21
CW		 998static void i915_gem_record_rings(struct drm_device *dev,
999 struct drm_i915_error_state *error)
1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1002 struct intel_ring_buffer *ring;
52d39a21
CW		 1003 struct drm_i915_gem_request *request;
1004 int i, count;
1005
b4519513 1006 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1007 i915_record_ring_state(dev, error, ring);
1008
1009 error->ring[i].batchbuffer =
1010 i915_error_first_batchbuffer(dev_priv, ring);
1011
1012 error->ring[i].ringbuffer =
1013 i915_error_object_create(dev_priv, ring->obj);
1014
1015 count = 0;
1016 list_for_each_entry(request, &ring->request_list, list)
1017 count++;
1018
1019 error->ring[i].num_requests = count;
1020 error->ring[i].requests =
1021 kmalloc(count*sizeof(struct drm_i915_error_request),
1022 GFP_ATOMIC);
1023 if (error->ring[i].requests == NULL) {
1024 error->ring[i].num_requests = 0;
1025 continue;
1026 }
1027
1028 count = 0;
1029 list_for_each_entry(request, &ring->request_list, list) {
1030 struct drm_i915_error_request *erq;
1031
1032 erq = &error->ring[i].requests[count++];
1033 erq->seqno = request->seqno;
1034 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1035 erq->tail = request->tail;
52d39a21
CW		 1036 }
1037 }
1038}
1039
8a905236
JB		 1040/**
1041 * i915_capture_error_state - capture an error record for later analysis
1042 * @dev: drm device
1043 *
1044 * Should be called when an error is detected (either a hang or an error
1045 * interrupt) to capture error state from the time of the error. Fills
1046 * out a structure which becomes available in debugfs for user level tools
1047 * to pick up.
1048 */
63eeaf38
JB		 1049static void i915_capture_error_state(struct drm_device *dev)
1050{
1051 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1052 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1053 struct drm_i915_error_state *error;
1054 unsigned long flags;
9db4a9c7 1055 int i, pipe;
63eeaf38
JB		 1056
1057 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1058 error = dev_priv->first_error;
1059 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1060 if (error)
1061 return;
63eeaf38 1062
9db4a9c7 1063 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1064 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1065 if (!error) {
9df30794
CW		 1066 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1067 return;
63eeaf38
JB		 1068 }
1069
b6f7833b
CW		 1070 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1071 dev->primary->index);
2fa772f3 1072
742cbee8 1073 kref_init(&error->ref);
63eeaf38
JB		 1074 error->eir = I915_READ(EIR);
1075 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1076
1077 if (HAS_PCH_SPLIT(dev))
1078 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1079 else if (IS_VALLEYVIEW(dev))
1080 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1081 else if (IS_GEN2(dev))
1082 error->ier = I915_READ16(IER);
1083 else
1084 error->ier = I915_READ(IER);
1085
9db4a9c7
JB		 1086 for_each_pipe(pipe)
1087 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1088
33f3f518 1089 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1090 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1091 error->done_reg = I915_READ(DONE_REG);
1092 }
d27b1e0e 1093
748ebc60 1094 i915_gem_record_fences(dev, error);
52d39a21 1095 i915_gem_record_rings(dev, error);
9df30794 1096
c724e8a9 1097 /* Record buffers on the active and pinned lists. */
9df30794 1098 error->active_bo = NULL;
c724e8a9 1099 error->pinned_bo = NULL;
9df30794 1100
bcfb2e28
CW		 1101 i = 0;
1102 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1103 i++;
1104 error->active_bo_count = i;
1b50247a
CW		 1105 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1106 if (obj->pin_count)
1107 i++;
bcfb2e28 1108 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1109
8e934dbf
CW		 1110 error->active_bo = NULL;
1111 error->pinned_bo = NULL;
bcfb2e28
CW		 1112 if (i) {
1113 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1114 GFP_ATOMIC);
c724e8a9
CW		 1115 if (error->active_bo)
1116 error->pinned_bo =
1117 error->active_bo + error->active_bo_count;
9df30794
CW		 1118 }
1119
c724e8a9
CW		 1120 if (error->active_bo)
1121 error->active_bo_count =
1b50247a
CW		 1122 capture_active_bo(error->active_bo,
1123 error->active_bo_count,
1124 &dev_priv->mm.active_list);
c724e8a9
CW		 1125
1126 if (error->pinned_bo)
1127 error->pinned_bo_count =
1b50247a
CW		 1128 capture_pinned_bo(error->pinned_bo,
1129 error->pinned_bo_count,
1130 &dev_priv->mm.gtt_list);
c724e8a9 1131
9df30794
CW		 1132 do_gettimeofday(&error->time);
1133
6ef3d427 1134 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1135 error->display = intel_display_capture_error_state(dev);
6ef3d427 1136
9df30794
CW		 1137 spin_lock_irqsave(&dev_priv->error_lock, flags);
1138 if (dev_priv->first_error == NULL) {
1139 dev_priv->first_error = error;
1140 error = NULL;
1141 }
63eeaf38 1142 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1143
1144 if (error)
742cbee8 1145 i915_error_state_free(&error->ref);
9df30794
CW		 1146}
1147
1148void i915_destroy_error_state(struct drm_device *dev)
1149{
1150 struct drm_i915_private *dev_priv = dev->dev_private;
1151 struct drm_i915_error_state *error;
6dc0e816 1152 unsigned long flags;
9df30794 1153
6dc0e816 1154 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1155 error = dev_priv->first_error;
1156 dev_priv->first_error = NULL;
6dc0e816 1157 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1158
1159 if (error)
742cbee8 1160 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1161}
3bd3c932
CW		 1162#else
1163#define i915_capture_error_state(x)
1164#endif
63eeaf38 1165
35aed2e6 1166static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1167{
1168 struct drm_i915_private *dev_priv = dev->dev_private;
1169 u32 eir = I915_READ(EIR);
9db4a9c7 1170 int pipe;
8a905236 1171
35aed2e6
CW		 1172 if (!eir)
1173 return;
8a905236 1174
a70491cc 1175 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1176
1177 if (IS_G4X(dev)) {
1178 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1179 u32 ipeir = I915_READ(IPEIR_I965);
1180
a70491cc
JP		 1181 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1182 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1183 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1184 I915_READ(INSTDONE_I965));
a70491cc
JP		 1185 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1186 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1187 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1188 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1189 POSTING_READ(IPEIR_I965);
8a905236
JB		 1190 }
1191 if (eir & GM45_ERROR_PAGE_TABLE) {
1192 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1193 pr_err("page table error\n");
1194 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1195 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1196 POSTING_READ(PGTBL_ER);
8a905236
JB		 1197 }
1198 }
1199
a6c45cf0 1200 if (!IS_GEN2(dev)) {
8a905236
JB		 1201 if (eir & I915_ERROR_PAGE_TABLE) {
1202 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1203 pr_err("page table error\n");
1204 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1205 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1206 POSTING_READ(PGTBL_ER);
8a905236
JB		 1207 }
1208 }
1209
1210 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1211 pr_err("memory refresh error:\n");
9db4a9c7 1212 for_each_pipe(pipe)
a70491cc 1213 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1214 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1215 /* pipestat has already been acked */
1216 }
1217 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1218 pr_err("instruction error\n");
1219 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1220 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1221 u32 ipeir = I915_READ(IPEIR);
1222
a70491cc
JP		 1223 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1224 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1225 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1226 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1227 I915_WRITE(IPEIR, ipeir);
3143a2bf 1228 POSTING_READ(IPEIR);
8a905236
JB		 1229 } else {
1230 u32 ipeir = I915_READ(IPEIR_I965);
1231
a70491cc
JP		 1232 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1233 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1234 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1235 I915_READ(INSTDONE_I965));
a70491cc
JP		 1236 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1237 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1238 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1239 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1240 POSTING_READ(IPEIR_I965);
8a905236
JB		 1241 }
1242 }
1243
1244 I915_WRITE(EIR, eir);
3143a2bf 1245 POSTING_READ(EIR);
8a905236
JB		 1246 eir = I915_READ(EIR);
1247 if (eir) {
1248 /*
1249 * some errors might have become stuck,
1250 * mask them.
1251 */
1252 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1253 I915_WRITE(EMR, I915_READ(EMR) | eir);
1254 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1255 }
35aed2e6
CW		 1256}
1257
1258/**
1259 * i915_handle_error - handle an error interrupt
1260 * @dev: drm device
1261 *
1262 * Do some basic checking of regsiter state at error interrupt time and
1263 * dump it to the syslog. Also call i915_capture_error_state() to make
1264 * sure we get a record and make it available in debugfs. Fire a uevent
1265 * so userspace knows something bad happened (should trigger collection
1266 * of a ring dump etc.).
1267 */
527f9e90 1268void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1269{
1270 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1271 struct intel_ring_buffer *ring;
1272 int i;
35aed2e6
CW		 1273
1274 i915_capture_error_state(dev);
1275 i915_report_and_clear_eir(dev);
8a905236 1276
ba1234d1 1277 if (wedged) {
30dbf0c0 1278 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1279 atomic_set(&dev_priv->mm.wedged, 1);
1280
11ed50ec
BG		 1281 /*
1282 * Wakeup waiting processes so they don't hang
1283 */
b4519513
CW		 1284 for_each_ring(ring, dev_priv, i)
1285 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1286 }
1287
9c9fe1f8 1288 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1289}
1290
4e5359cd
SF		 1291static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1292{
1293 drm_i915_private_t *dev_priv = dev->dev_private;
1294 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1296 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1297 struct intel_unpin_work *work;
1298 unsigned long flags;
1299 bool stall_detected;
1300
1301 /* Ignore early vblank irqs */
1302 if (intel_crtc == NULL)
1303 return;
1304
1305 spin_lock_irqsave(&dev->event_lock, flags);
1306 work = intel_crtc->unpin_work;
1307
1308 if (work == NULL || work->pending || !work->enable_stall_check) {
1309 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1310 spin_unlock_irqrestore(&dev->event_lock, flags);
1311 return;
1312 }
1313
1314 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1315 obj = work->pending_flip_obj;
a6c45cf0 1316 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1317 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1318 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1319 obj->gtt_offset;
4e5359cd 1320 } else {
9db4a9c7 1321 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1322 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1323 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1324 crtc->x * crtc->fb->bits_per_pixel/8);
1325 }
1326
1327 spin_unlock_irqrestore(&dev->event_lock, flags);
1328
1329 if (stall_detected) {
1330 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1331 intel_prepare_page_flip(dev, intel_crtc->plane);
1332 }
1333}
1334
42f52ef8
KP		 1335/* Called from drm generic code, passed 'crtc' which
1336 * we use as a pipe index
1337 */
f71d4af4 1338static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1339{
1340 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1341 unsigned long irqflags;
71e0ffa5 1342
5eddb70b 1343 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1344 return -EINVAL;
0a3e67a4 1345
1ec14ad3 1346 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1347 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1348 i915_enable_pipestat(dev_priv, pipe,
1349 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1350 else
7c463586
KP		 1351 i915_enable_pipestat(dev_priv, pipe,
1352 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1353
1354 /* maintain vblank delivery even in deep C-states */
1355 if (dev_priv->info->gen == 3)
6b26c86d 1356 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1357 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1358
0a3e67a4
JB		 1359 return 0;
1360}
1361
f71d4af4 1362static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1363{
1364 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1365 unsigned long irqflags;
1366
1367 if (!i915_pipe_enabled(dev, pipe))
1368 return -EINVAL;
1369
1370 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1371 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1372 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1373 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1374
1375 return 0;
1376}
1377
f71d4af4 1378static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1379{
1380 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1381 unsigned long irqflags;
1382
1383 if (!i915_pipe_enabled(dev, pipe))
1384 return -EINVAL;
1385
1386 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1387 ironlake_enable_display_irq(dev_priv,
1388 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1389 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1390
1391 return 0;
1392}
1393
7e231dbe
JB		 1394static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1395{
1396 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1397 unsigned long irqflags;
1398 u32 dpfl, imr;
1399
1400 if (!i915_pipe_enabled(dev, pipe))
1401 return -EINVAL;
1402
1403 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1404 dpfl = I915_READ(VLV_DPFLIPSTAT);
1405 imr = I915_READ(VLV_IMR);
1406 if (pipe == 0) {
1407 dpfl |= PIPEA_VBLANK_INT_EN;
1408 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1409 } else {
1410 dpfl |= PIPEA_VBLANK_INT_EN;
1411 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1412 }
1413 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1414 I915_WRITE(VLV_IMR, imr);
1415 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1416
1417 return 0;
1418}
1419
42f52ef8
KP		 1420/* Called from drm generic code, passed 'crtc' which
1421 * we use as a pipe index
1422 */
f71d4af4 1423static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1424{
1425 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1426 unsigned long irqflags;
0a3e67a4 1427
1ec14ad3 1428 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1429 if (dev_priv->info->gen == 3)
6b26c86d 1430 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1431
f796cf8f
JB		 1432 i915_disable_pipestat(dev_priv, pipe,
1433 PIPE_VBLANK_INTERRUPT_ENABLE |
1434 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1435 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1436}
1437
f71d4af4 1438static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1439{
1440 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1441 unsigned long irqflags;
1442
1443 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1444 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1445 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1446 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1447}
1448
f71d4af4 1449static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1450{
1451 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1452 unsigned long irqflags;
1453
1454 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1455 ironlake_disable_display_irq(dev_priv,
1456 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1457 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1458}
1459
7e231dbe
JB		 1460static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1461{
1462 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1463 unsigned long irqflags;
1464 u32 dpfl, imr;
1465
1466 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1467 dpfl = I915_READ(VLV_DPFLIPSTAT);
1468 imr = I915_READ(VLV_IMR);
1469 if (pipe == 0) {
1470 dpfl &= ~PIPEA_VBLANK_INT_EN;
1471 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1472 } else {
1473 dpfl &= ~PIPEB_VBLANK_INT_EN;
1474 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1475 }
1476 I915_WRITE(VLV_IMR, imr);
1477 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1478 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1479}
1480
893eead0
CW		 1481static u32
1482ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1483{
893eead0
CW		 1484 return list_entry(ring->request_list.prev,
1485 struct drm_i915_gem_request, list)->seqno;
1486}
1487
1488static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1489{
1490 if (list_empty(&ring->request_list) ||
1491 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1492 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1493 if (waitqueue_active(&ring->irq_queue)) {
1494 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1495 ring->name);
893eead0
CW		 1496 wake_up_all(&ring->irq_queue);
1497 *err = true;
1498 }
1499 return true;
1500 }
1501 return false;
f65d9421
BG		 1502}
1503
1ec14ad3
CW		 1504static bool kick_ring(struct intel_ring_buffer *ring)
1505{
1506 struct drm_device *dev = ring->dev;
1507 struct drm_i915_private *dev_priv = dev->dev_private;
1508 u32 tmp = I915_READ_CTL(ring);
1509 if (tmp & RING_WAIT) {
1510 DRM_ERROR("Kicking stuck wait on %s\n",
1511 ring->name);
1512 I915_WRITE_CTL(ring, tmp);
1513 return true;
1514 }
1ec14ad3
CW		 1515 return false;
1516}
1517
d1e61e7f
CW		 1518static bool i915_hangcheck_hung(struct drm_device *dev)
1519{
1520 drm_i915_private_t *dev_priv = dev->dev_private;
1521
1522 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1523 bool hung = true;
1524
d1e61e7f
CW		 1525 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1526 i915_handle_error(dev, true);
1527
1528 if (!IS_GEN2(dev)) {
b4519513
CW		 1529 struct intel_ring_buffer *ring;
1530 int i;
1531
d1e61e7f
CW		 1532 /* Is the chip hanging on a WAIT_FOR_EVENT?
1533 * If so we can simply poke the RB_WAIT bit
1534 * and break the hang. This should work on
1535 * all but the second generation chipsets.
1536 */
b4519513
CW		 1537 for_each_ring(ring, dev_priv, i)
1538 hung &= !kick_ring(ring);
d1e61e7f
CW		 1539 }
1540
b4519513 1541 return hung;
d1e61e7f
CW		 1542 }
1543
1544 return false;
1545}
1546
f65d9421
BG		 1547/**
1548 * This is called when the chip hasn't reported back with completed
1549 * batchbuffers in a long time. The first time this is called we simply record
1550 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1551 * again, we assume the chip is wedged and try to fix it.
1552 */
1553void i915_hangcheck_elapsed(unsigned long data)
1554{
1555 struct drm_device *dev = (struct drm_device *)data;
1556 drm_i915_private_t *dev_priv = dev->dev_private;
b4519513
CW		 1557 uint32_t acthd[I915_NUM_RINGS], instdone, instdone1;
1558 struct intel_ring_buffer *ring;
1559 bool err = false, idle;
1560 int i;
893eead0 1561
3e0dc6b0
BW		 1562 if (!i915_enable_hangcheck)
1563 return;
1564
b4519513
CW		 1565 memset(acthd, 0, sizeof(acthd));
1566 idle = true;
1567 for_each_ring(ring, dev_priv, i) {
1568 idle &= i915_hangcheck_ring_idle(ring, &err);
1569 acthd[i] = intel_ring_get_active_head(ring);
1570 }
1571
893eead0 1572 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1573 if (idle) {
d1e61e7f
CW		 1574 if (err) {
1575 if (i915_hangcheck_hung(dev))
1576 return;
1577
893eead0 1578 goto repeat;
d1e61e7f
CW		 1579 }
1580
1581 dev_priv->hangcheck_count = 0;
893eead0
CW		 1582 return;
1583 }
b9201c14 1584
a6c45cf0 1585 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1586 instdone = I915_READ(INSTDONE);
1587 instdone1 = 0;
1588 } else {
cbb465e7
CW		 1589 instdone = I915_READ(INSTDONE_I965);
1590 instdone1 = I915_READ(INSTDONE1);
1591 }
b4519513
CW		 1592
1593 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
cbb465e7
CW		 1594 dev_priv->last_instdone == instdone &&
1595 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1596 if (i915_hangcheck_hung(dev))
cbb465e7 1597 return;
cbb465e7
CW		 1598 } else {
1599 dev_priv->hangcheck_count = 0;
1600
b4519513 1601 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
cbb465e7
CW		 1602 dev_priv->last_instdone = instdone;
1603 dev_priv->last_instdone1 = instdone1;
1604 }
f65d9421 1605
893eead0 1606repeat:
f65d9421 1607 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1608 mod_timer(&dev_priv->hangcheck_timer,
1609 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1610}
1611
1da177e4
LT		 1612/* drm_dma.h hooks
1613*/
f71d4af4 1614static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1615{
1616 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1617
4697995b
JB		 1618 atomic_set(&dev_priv->irq_received, 0);
1619
4697995b 1620
036a4a7d 1621 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1622
036a4a7d
ZW		 1623 /* XXX hotplug from PCH */
1624
1625 I915_WRITE(DEIMR, 0xffffffff);
1626 I915_WRITE(DEIER, 0x0);
3143a2bf 1627 POSTING_READ(DEIER);
036a4a7d
ZW		 1628
1629 /* and GT */
1630 I915_WRITE(GTIMR, 0xffffffff);
1631 I915_WRITE(GTIER, 0x0);
3143a2bf 1632 POSTING_READ(GTIER);
c650156a
ZW		 1633
1634 /* south display irq */
1635 I915_WRITE(SDEIMR, 0xffffffff);
1636 I915_WRITE(SDEIER, 0x0);
3143a2bf 1637 POSTING_READ(SDEIER);
036a4a7d
ZW		 1638}
1639
7e231dbe
JB		 1640static void valleyview_irq_preinstall(struct drm_device *dev)
1641{
1642 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1643 int pipe;
1644
1645 atomic_set(&dev_priv->irq_received, 0);
1646
7e231dbe
JB		 1647 /* VLV magic */
1648 I915_WRITE(VLV_IMR, 0);
1649 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1650 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1651 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1652
7e231dbe
JB		 1653 /* and GT */
1654 I915_WRITE(GTIIR, I915_READ(GTIIR));
1655 I915_WRITE(GTIIR, I915_READ(GTIIR));
1656 I915_WRITE(GTIMR, 0xffffffff);
1657 I915_WRITE(GTIER, 0x0);
1658 POSTING_READ(GTIER);
1659
1660 I915_WRITE(DPINVGTT, 0xff);
1661
1662 I915_WRITE(PORT_HOTPLUG_EN, 0);
1663 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1664 for_each_pipe(pipe)
1665 I915_WRITE(PIPESTAT(pipe), 0xffff);
1666 I915_WRITE(VLV_IIR, 0xffffffff);
1667 I915_WRITE(VLV_IMR, 0xffffffff);
1668 I915_WRITE(VLV_IER, 0x0);
1669 POSTING_READ(VLV_IER);
1670}
1671
7fe0b973
KP		 1672/*
1673 * Enable digital hotplug on the PCH, and configure the DP short pulse
1674 * duration to 2ms (which is the minimum in the Display Port spec)
1675 *
1676 * This register is the same on all known PCH chips.
1677 */
1678
1679static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1680{
1681 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1682 u32 hotplug;
1683
1684 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1685 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1686 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1687 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1688 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1689 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1690}
1691
f71d4af4 1692static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1693{
1694 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1695 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1696 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1697 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1698 u32 render_irqs;
2d7b8366 1699 u32 hotplug_mask;
036a4a7d 1700
1ec14ad3 1701 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1702
1703 /* should always can generate irq */
1704 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1705 I915_WRITE(DEIMR, dev_priv->irq_mask);
1706 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1707 POSTING_READ(DEIER);
036a4a7d 1708
1ec14ad3 1709 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1710
1711 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1712 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1713
1ec14ad3
CW		 1714 if (IS_GEN6(dev))
1715 render_irqs =
1716 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1717 GEN6_BSD_USER_INTERRUPT |
1718 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1719 else
1720 render_irqs =
88f23b8f 1721 GT_USER_INTERRUPT |
c6df541c 1722 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1723 GT_BSD_USER_INTERRUPT;
1724 I915_WRITE(GTIER, render_irqs);
3143a2bf 1725 POSTING_READ(GTIER);
036a4a7d 1726
2d7b8366 1727 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1728 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1729 SDE_PORTB_HOTPLUG_CPT |
1730 SDE_PORTC_HOTPLUG_CPT |
1731 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1732 } else {
9035a97a
CW		 1733 hotplug_mask = (SDE_CRT_HOTPLUG |
1734 SDE_PORTB_HOTPLUG |
1735 SDE_PORTC_HOTPLUG |
1736 SDE_PORTD_HOTPLUG |
1737 SDE_AUX_MASK);
2d7b8366
YL		 1738 }
1739
1ec14ad3 1740 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1741
1742 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1743 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1744 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1745 POSTING_READ(SDEIER);
c650156a 1746
7fe0b973
KP		 1747 ironlake_enable_pch_hotplug(dev);
1748
f97108d1
JB		 1749 if (IS_IRONLAKE_M(dev)) {
1750 /* Clear & enable PCU event interrupts */
1751 I915_WRITE(DEIIR, DE_PCU_EVENT);
1752 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1753 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1754 }
1755
036a4a7d
ZW		 1756 return 0;
1757}
1758
f71d4af4 1759static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1760{
1761 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1762 /* enable kind of interrupts always enabled */
b615b57a
CW		 1763 u32 display_mask =
1764 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1765 DE_PLANEC_FLIP_DONE_IVB |
1766 DE_PLANEB_FLIP_DONE_IVB |
1767 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1768 u32 render_irqs;
1769 u32 hotplug_mask;
1770
b1f14ad0
JB		 1771 dev_priv->irq_mask = ~display_mask;
1772
1773 /* should always can generate irq */
1774 I915_WRITE(DEIIR, I915_READ(DEIIR));
1775 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1776 I915_WRITE(DEIER,
1777 display_mask |
1778 DE_PIPEC_VBLANK_IVB |
1779 DE_PIPEB_VBLANK_IVB |
1780 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1781 POSTING_READ(DEIER);
1782
1783 dev_priv->gt_irq_mask = ~0;
1784
1785 I915_WRITE(GTIIR, I915_READ(GTIIR));
1786 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1787
e2a1e2f0
BW		 1788 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1789 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1790 I915_WRITE(GTIER, render_irqs);
1791 POSTING_READ(GTIER);
1792
1793 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1794 SDE_PORTB_HOTPLUG_CPT |
1795 SDE_PORTC_HOTPLUG_CPT |
1796 SDE_PORTD_HOTPLUG_CPT);
1797 dev_priv->pch_irq_mask = ~hotplug_mask;
1798
1799 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1800 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1801 I915_WRITE(SDEIER, hotplug_mask);
1802 POSTING_READ(SDEIER);
1803
7fe0b973
KP		 1804 ironlake_enable_pch_hotplug(dev);
1805
b1f14ad0
JB		 1806 return 0;
1807}
1808
7e231dbe
JB		 1809static int valleyview_irq_postinstall(struct drm_device *dev)
1810{
1811 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1812 u32 render_irqs;
1813 u32 enable_mask;
1814 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1815 u16 msid;
1816
1817 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1818 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1819 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1820
1821 dev_priv->irq_mask = ~enable_mask;
1822
7e231dbe
JB		 1823 dev_priv->pipestat[0] = 0;
1824 dev_priv->pipestat[1] = 0;
1825
7e231dbe
JB		 1826 /* Hack for broken MSIs on VLV */
1827 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1828 pci_read_config_word(dev->pdev, 0x98, &msid);
1829 msid &= 0xff; /* mask out delivery bits */
1830 msid |= (1<<14);
1831 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1832
1833 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1834 I915_WRITE(VLV_IER, enable_mask);
1835 I915_WRITE(VLV_IIR, 0xffffffff);
1836 I915_WRITE(PIPESTAT(0), 0xffff);
1837 I915_WRITE(PIPESTAT(1), 0xffff);
1838 POSTING_READ(VLV_IER);
1839
1840 I915_WRITE(VLV_IIR, 0xffffffff);
1841 I915_WRITE(VLV_IIR, 0xffffffff);
1842
1843 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1844 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1845 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1846 GT_GEN6_BSD_USER_INTERRUPT |
1847 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1848 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1849 GT_PIPE_NOTIFY |
1850 GT_RENDER_CS_ERROR_INTERRUPT |
1851 GT_SYNC_STATUS |
1852 GT_USER_INTERRUPT;
1853
1854 dev_priv->gt_irq_mask = ~render_irqs;
1855
1856 I915_WRITE(GTIIR, I915_READ(GTIIR));
1857 I915_WRITE(GTIIR, I915_READ(GTIIR));
1858 I915_WRITE(GTIMR, 0);
1859 I915_WRITE(GTIER, render_irqs);
1860 POSTING_READ(GTIER);
1861
1862 /* ack & enable invalid PTE error interrupts */
1863#if 0 /* FIXME: add support to irq handler for checking these bits */
1864 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1865 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1866#endif
1867
1868 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1869#if 0 /* FIXME: check register definitions; some have moved */
1870 /* Note HDMI and DP share bits */
1871 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1872 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1873 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1874 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1875 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1876 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1877 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1878 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1879 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1880 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1881 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1882 hotplug_en |= CRT_HOTPLUG_INT_EN;
1883 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1884 }
1885#endif
1886
1887 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1888
1889 return 0;
1890}
1891
7e231dbe
JB		 1892static void valleyview_irq_uninstall(struct drm_device *dev)
1893{
1894 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1895 int pipe;
1896
1897 if (!dev_priv)
1898 return;
1899
7e231dbe
JB		 1900 for_each_pipe(pipe)
1901 I915_WRITE(PIPESTAT(pipe), 0xffff);
1902
1903 I915_WRITE(HWSTAM, 0xffffffff);
1904 I915_WRITE(PORT_HOTPLUG_EN, 0);
1905 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1906 for_each_pipe(pipe)
1907 I915_WRITE(PIPESTAT(pipe), 0xffff);
1908 I915_WRITE(VLV_IIR, 0xffffffff);
1909 I915_WRITE(VLV_IMR, 0xffffffff);
1910 I915_WRITE(VLV_IER, 0x0);
1911 POSTING_READ(VLV_IER);
1912}
1913
f71d4af4 1914static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1915{
1916 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1917
1918 if (!dev_priv)
1919 return;
1920
036a4a7d
ZW		 1921 I915_WRITE(HWSTAM, 0xffffffff);
1922
1923 I915_WRITE(DEIMR, 0xffffffff);
1924 I915_WRITE(DEIER, 0x0);
1925 I915_WRITE(DEIIR, I915_READ(DEIIR));
1926
1927 I915_WRITE(GTIMR, 0xffffffff);
1928 I915_WRITE(GTIER, 0x0);
1929 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1930
1931 I915_WRITE(SDEIMR, 0xffffffff);
1932 I915_WRITE(SDEIER, 0x0);
1933 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1934}
1935
a266c7d5 1936static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1937{
1938 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1939 int pipe;
91e3738e 1940
a266c7d5 1941 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1942
9db4a9c7
JB		 1943 for_each_pipe(pipe)
1944 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1945 I915_WRITE16(IMR, 0xffff);
1946 I915_WRITE16(IER, 0x0);
1947 POSTING_READ16(IER);
c2798b19
CW		 1948}
1949
1950static int i8xx_irq_postinstall(struct drm_device *dev)
1951{
1952 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1953
c2798b19
CW		 1954 dev_priv->pipestat[0] = 0;
1955 dev_priv->pipestat[1] = 0;
1956
1957 I915_WRITE16(EMR,
1958 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1959
1960 /* Unmask the interrupts that we always want on. */
1961 dev_priv->irq_mask =
1962 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1963 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1964 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1965 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
1966 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1967 I915_WRITE16(IMR, dev_priv->irq_mask);
1968
1969 I915_WRITE16(IER,
1970 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1971 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1972 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
1973 I915_USER_INTERRUPT);
1974 POSTING_READ16(IER);
1975
1976 return 0;
1977}
1978
1979static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
1980{
1981 struct drm_device *dev = (struct drm_device *) arg;
1982 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 1983 u16 iir, new_iir;
1984 u32 pipe_stats[2];
1985 unsigned long irqflags;
1986 int irq_received;
1987 int pipe;
1988 u16 flip_mask =
1989 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
1990 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
1991
1992 atomic_inc(&dev_priv->irq_received);
1993
1994 iir = I915_READ16(IIR);
1995 if (iir == 0)
1996 return IRQ_NONE;
1997
1998 while (iir & ~flip_mask) {
1999 /* Can't rely on pipestat interrupt bit in iir as it might
2000 * have been cleared after the pipestat interrupt was received.
2001 * It doesn't set the bit in iir again, but it still produces
2002 * interrupts (for non-MSI).
2003 */
2004 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2005 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2006 i915_handle_error(dev, false);
2007
2008 for_each_pipe(pipe) {
2009 int reg = PIPESTAT(pipe);
2010 pipe_stats[pipe] = I915_READ(reg);
2011
2012 /*
2013 * Clear the PIPE*STAT regs before the IIR
2014 */
2015 if (pipe_stats[pipe] & 0x8000ffff) {
2016 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2017 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2018 pipe_name(pipe));
2019 I915_WRITE(reg, pipe_stats[pipe]);
2020 irq_received = 1;
2021 }
2022 }
2023 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2024
2025 I915_WRITE16(IIR, iir & ~flip_mask);
2026 new_iir = I915_READ16(IIR); /* Flush posted writes */
2027
d05c617e 2028 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2029
2030 if (iir & I915_USER_INTERRUPT)
2031 notify_ring(dev, &dev_priv->ring[RCS]);
2032
2033 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2034 drm_handle_vblank(dev, 0)) {
2035 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2036 intel_prepare_page_flip(dev, 0);
2037 intel_finish_page_flip(dev, 0);
2038 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2039 }
2040 }
2041
2042 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2043 drm_handle_vblank(dev, 1)) {
2044 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2045 intel_prepare_page_flip(dev, 1);
2046 intel_finish_page_flip(dev, 1);
2047 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2048 }
2049 }
2050
2051 iir = new_iir;
2052 }
2053
2054 return IRQ_HANDLED;
2055}
2056
2057static void i8xx_irq_uninstall(struct drm_device * dev)
2058{
2059 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2060 int pipe;
2061
c2798b19
CW		 2062 for_each_pipe(pipe) {
2063 /* Clear enable bits; then clear status bits */
2064 I915_WRITE(PIPESTAT(pipe), 0);
2065 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2066 }
2067 I915_WRITE16(IMR, 0xffff);
2068 I915_WRITE16(IER, 0x0);
2069 I915_WRITE16(IIR, I915_READ16(IIR));
2070}
2071
a266c7d5
CW		 2072static void i915_irq_preinstall(struct drm_device * dev)
2073{
2074 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2075 int pipe;
2076
2077 atomic_set(&dev_priv->irq_received, 0);
2078
2079 if (I915_HAS_HOTPLUG(dev)) {
2080 I915_WRITE(PORT_HOTPLUG_EN, 0);
2081 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2082 }
2083
00d98ebd 2084 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2085 for_each_pipe(pipe)
2086 I915_WRITE(PIPESTAT(pipe), 0);
2087 I915_WRITE(IMR, 0xffffffff);
2088 I915_WRITE(IER, 0x0);
2089 POSTING_READ(IER);
2090}
2091
2092static int i915_irq_postinstall(struct drm_device *dev)
2093{
2094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2095 u32 enable_mask;
a266c7d5 2096
a266c7d5
CW		 2097 dev_priv->pipestat[0] = 0;
2098 dev_priv->pipestat[1] = 0;
2099
38bde180
CW		 2100 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2101
2102 /* Unmask the interrupts that we always want on. */
2103 dev_priv->irq_mask =
2104 ~(I915_ASLE_INTERRUPT |
2105 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2106 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2107 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2108 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2109 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2110
2111 enable_mask =
2112 I915_ASLE_INTERRUPT |
2113 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2114 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2115 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2116 I915_USER_INTERRUPT;
2117
a266c7d5
CW		 2118 if (I915_HAS_HOTPLUG(dev)) {
2119 /* Enable in IER... */
2120 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2121 /* and unmask in IMR */
2122 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2123 }
2124
a266c7d5
CW		 2125 I915_WRITE(IMR, dev_priv->irq_mask);
2126 I915_WRITE(IER, enable_mask);
2127 POSTING_READ(IER);
2128
2129 if (I915_HAS_HOTPLUG(dev)) {
2130 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2131
a266c7d5
CW		 2132 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2133 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2134 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2135 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2136 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2137 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2138 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2139 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2140 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2141 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2142 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2143 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2144 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2145 }
2146
2147 /* Ignore TV since it's buggy */
2148
2149 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2150 }
2151
2152 intel_opregion_enable_asle(dev);
2153
2154 return 0;
2155}
2156
2157static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2158{
2159 struct drm_device *dev = (struct drm_device *) arg;
2160 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2161 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2162 unsigned long irqflags;
38bde180
CW		 2163 u32 flip_mask =
2164 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2165 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2166 u32 flip[2] = {
2167 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2168 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2169 };
2170 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2171
2172 atomic_inc(&dev_priv->irq_received);
2173
2174 iir = I915_READ(IIR);
38bde180
CW		 2175 do {
2176 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2177 bool blc_event = false;
a266c7d5
CW		 2178
2179 /* Can't rely on pipestat interrupt bit in iir as it might
2180 * have been cleared after the pipestat interrupt was received.
2181 * It doesn't set the bit in iir again, but it still produces
2182 * interrupts (for non-MSI).
2183 */
2184 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2185 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2186 i915_handle_error(dev, false);
2187
2188 for_each_pipe(pipe) {
2189 int reg = PIPESTAT(pipe);
2190 pipe_stats[pipe] = I915_READ(reg);
2191
38bde180 2192 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2193 if (pipe_stats[pipe] & 0x8000ffff) {
2194 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2195 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2196 pipe_name(pipe));
2197 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2198 irq_received = true;
a266c7d5
CW		 2199 }
2200 }
2201 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2202
2203 if (!irq_received)
2204 break;
2205
a266c7d5
CW		 2206 /* Consume port. Then clear IIR or we'll miss events */
2207 if ((I915_HAS_HOTPLUG(dev)) &&
2208 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2209 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2210
2211 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2212 hotplug_status);
2213 if (hotplug_status & dev_priv->hotplug_supported_mask)
2214 queue_work(dev_priv->wq,
2215 &dev_priv->hotplug_work);
2216
2217 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2218 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2219 }
2220
38bde180 2221 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2222 new_iir = I915_READ(IIR); /* Flush posted writes */
2223
a266c7d5
CW		 2224 if (iir & I915_USER_INTERRUPT)
2225 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2226
a266c7d5 2227 for_each_pipe(pipe) {
38bde180
CW		 2228 int plane = pipe;
2229 if (IS_MOBILE(dev))
2230 plane = !plane;
8291ee90 2231 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2232 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2233 if (iir & flip[plane]) {
2234 intel_prepare_page_flip(dev, plane);
2235 intel_finish_page_flip(dev, pipe);
2236 flip_mask &= ~flip[plane];
2237 }
a266c7d5
CW		 2238 }
2239
2240 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2241 blc_event = true;
2242 }
2243
a266c7d5
CW		 2244 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2245 intel_opregion_asle_intr(dev);
2246
2247 /* With MSI, interrupts are only generated when iir
2248 * transitions from zero to nonzero. If another bit got
2249 * set while we were handling the existing iir bits, then
2250 * we would never get another interrupt.
2251 *
2252 * This is fine on non-MSI as well, as if we hit this path
2253 * we avoid exiting the interrupt handler only to generate
2254 * another one.
2255 *
2256 * Note that for MSI this could cause a stray interrupt report
2257 * if an interrupt landed in the time between writing IIR and
2258 * the posting read. This should be rare enough to never
2259 * trigger the 99% of 100,000 interrupts test for disabling
2260 * stray interrupts.
2261 */
38bde180 2262 ret = IRQ_HANDLED;
a266c7d5 2263 iir = new_iir;
38bde180 2264 } while (iir & ~flip_mask);
a266c7d5 2265
d05c617e 2266 i915_update_dri1_breadcrumb(dev);
8291ee90 2267
a266c7d5
CW		 2268 return ret;
2269}
2270
2271static void i915_irq_uninstall(struct drm_device * dev)
2272{
2273 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2274 int pipe;
2275
a266c7d5
CW		 2276 if (I915_HAS_HOTPLUG(dev)) {
2277 I915_WRITE(PORT_HOTPLUG_EN, 0);
2278 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2279 }
2280
00d98ebd 2281 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2282 for_each_pipe(pipe) {
2283 /* Clear enable bits; then clear status bits */
a266c7d5 2284 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2285 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2286 }
a266c7d5
CW		 2287 I915_WRITE(IMR, 0xffffffff);
2288 I915_WRITE(IER, 0x0);
2289
a266c7d5
CW		 2290 I915_WRITE(IIR, I915_READ(IIR));
2291}
2292
2293static void i965_irq_preinstall(struct drm_device * dev)
2294{
2295 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2296 int pipe;
2297
2298 atomic_set(&dev_priv->irq_received, 0);
2299
2300 if (I915_HAS_HOTPLUG(dev)) {
2301 I915_WRITE(PORT_HOTPLUG_EN, 0);
2302 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2303 }
2304
2305 I915_WRITE(HWSTAM, 0xeffe);
2306 for_each_pipe(pipe)
2307 I915_WRITE(PIPESTAT(pipe), 0);
2308 I915_WRITE(IMR, 0xffffffff);
2309 I915_WRITE(IER, 0x0);
2310 POSTING_READ(IER);
2311}
2312
2313static int i965_irq_postinstall(struct drm_device *dev)
2314{
2315 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2316 u32 enable_mask;
a266c7d5
CW		 2317 u32 error_mask;
2318
a266c7d5 2319 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2320 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2321 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2322 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2323 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2324 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2325 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2326
2327 enable_mask = ~dev_priv->irq_mask;
2328 enable_mask |= I915_USER_INTERRUPT;
2329
2330 if (IS_G4X(dev))
2331 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2332
2333 dev_priv->pipestat[0] = 0;
2334 dev_priv->pipestat[1] = 0;
2335
2336 if (I915_HAS_HOTPLUG(dev)) {
2337 /* Enable in IER... */
2338 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2339 /* and unmask in IMR */
2340 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2341 }
2342
2343 /*
2344 * Enable some error detection, note the instruction error mask
2345 * bit is reserved, so we leave it masked.
2346 */
2347 if (IS_G4X(dev)) {
2348 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2349 GM45_ERROR_MEM_PRIV |
2350 GM45_ERROR_CP_PRIV |
2351 I915_ERROR_MEMORY_REFRESH);
2352 } else {
2353 error_mask = ~(I915_ERROR_PAGE_TABLE |
2354 I915_ERROR_MEMORY_REFRESH);
2355 }
2356 I915_WRITE(EMR, error_mask);
2357
2358 I915_WRITE(IMR, dev_priv->irq_mask);
2359 I915_WRITE(IER, enable_mask);
2360 POSTING_READ(IER);
2361
2362 if (I915_HAS_HOTPLUG(dev)) {
2363 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2364
2365 /* Note HDMI and DP share bits */
2366 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2367 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2368 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2369 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2370 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2371 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2372 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2373 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2374 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2375 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2376 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2377 hotplug_en |= CRT_HOTPLUG_INT_EN;
2378
2379 /* Programming the CRT detection parameters tends
2380 to generate a spurious hotplug event about three
2381 seconds later. So just do it once.
2382 */
2383 if (IS_G4X(dev))
2384 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2385 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2386 }
2387
2388 /* Ignore TV since it's buggy */
2389
2390 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2391 }
2392
2393 intel_opregion_enable_asle(dev);
2394
2395 return 0;
2396}
2397
2398static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2399{
2400 struct drm_device *dev = (struct drm_device *) arg;
2401 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2402 u32 iir, new_iir;
2403 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2404 unsigned long irqflags;
2405 int irq_received;
2406 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2407
2408 atomic_inc(&dev_priv->irq_received);
2409
2410 iir = I915_READ(IIR);
2411
a266c7d5 2412 for (;;) {
2c8ba29f
CW		 2413 bool blc_event = false;
2414
a266c7d5
CW		 2415 irq_received = iir != 0;
2416
2417 /* Can't rely on pipestat interrupt bit in iir as it might
2418 * have been cleared after the pipestat interrupt was received.
2419 * It doesn't set the bit in iir again, but it still produces
2420 * interrupts (for non-MSI).
2421 */
2422 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2423 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2424 i915_handle_error(dev, false);
2425
2426 for_each_pipe(pipe) {
2427 int reg = PIPESTAT(pipe);
2428 pipe_stats[pipe] = I915_READ(reg);
2429
2430 /*
2431 * Clear the PIPE*STAT regs before the IIR
2432 */
2433 if (pipe_stats[pipe] & 0x8000ffff) {
2434 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2435 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2436 pipe_name(pipe));
2437 I915_WRITE(reg, pipe_stats[pipe]);
2438 irq_received = 1;
2439 }
2440 }
2441 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2442
2443 if (!irq_received)
2444 break;
2445
2446 ret = IRQ_HANDLED;
2447
2448 /* Consume port. Then clear IIR or we'll miss events */
2449 if ((I915_HAS_HOTPLUG(dev)) &&
2450 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2451 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2452
2453 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2454 hotplug_status);
2455 if (hotplug_status & dev_priv->hotplug_supported_mask)
2456 queue_work(dev_priv->wq,
2457 &dev_priv->hotplug_work);
2458
2459 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2460 I915_READ(PORT_HOTPLUG_STAT);
2461 }
2462
2463 I915_WRITE(IIR, iir);
2464 new_iir = I915_READ(IIR); /* Flush posted writes */
2465
a266c7d5
CW		 2466 if (iir & I915_USER_INTERRUPT)
2467 notify_ring(dev, &dev_priv->ring[RCS]);
2468 if (iir & I915_BSD_USER_INTERRUPT)
2469 notify_ring(dev, &dev_priv->ring[VCS]);
2470
4f7d1e79 2471 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2472 intel_prepare_page_flip(dev, 0);
a266c7d5 2473
4f7d1e79 2474 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2475 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2476
2477 for_each_pipe(pipe) {
2c8ba29f 2478 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2479 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2480 i915_pageflip_stall_check(dev, pipe);
2481 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2482 }
2483
2484 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2485 blc_event = true;
2486 }
2487
2488
2489 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2490 intel_opregion_asle_intr(dev);
2491
2492 /* With MSI, interrupts are only generated when iir
2493 * transitions from zero to nonzero. If another bit got
2494 * set while we were handling the existing iir bits, then
2495 * we would never get another interrupt.
2496 *
2497 * This is fine on non-MSI as well, as if we hit this path
2498 * we avoid exiting the interrupt handler only to generate
2499 * another one.
2500 *
2501 * Note that for MSI this could cause a stray interrupt report
2502 * if an interrupt landed in the time between writing IIR and
2503 * the posting read. This should be rare enough to never
2504 * trigger the 99% of 100,000 interrupts test for disabling
2505 * stray interrupts.
2506 */
2507 iir = new_iir;
2508 }
2509
d05c617e 2510 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2511
a266c7d5
CW		 2512 return ret;
2513}
2514
2515static void i965_irq_uninstall(struct drm_device * dev)
2516{
2517 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2518 int pipe;
2519
2520 if (!dev_priv)
2521 return;
2522
a266c7d5
CW		 2523 if (I915_HAS_HOTPLUG(dev)) {
2524 I915_WRITE(PORT_HOTPLUG_EN, 0);
2525 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2526 }
2527
2528 I915_WRITE(HWSTAM, 0xffffffff);
2529 for_each_pipe(pipe)
2530 I915_WRITE(PIPESTAT(pipe), 0);
2531 I915_WRITE(IMR, 0xffffffff);
2532 I915_WRITE(IER, 0x0);
2533
2534 for_each_pipe(pipe)
2535 I915_WRITE(PIPESTAT(pipe),
2536 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2537 I915_WRITE(IIR, I915_READ(IIR));
2538}
2539
f71d4af4
JB		 2540void intel_irq_init(struct drm_device *dev)
2541{
8b2e326d
CW		 2542 struct drm_i915_private *dev_priv = dev->dev_private;
2543
2544 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2545 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2546 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2547
f71d4af4
JB		 2548 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2549 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2550 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2551 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2552 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2553 }
2554
c3613de9
KP		 2555 if (drm_core_check_feature(dev, DRIVER_MODESET))
2556 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2557 else
2558 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2559 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2560
7e231dbe
JB		 2561 if (IS_VALLEYVIEW(dev)) {
2562 dev->driver->irq_handler = valleyview_irq_handler;
2563 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2564 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2565 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2566 dev->driver->enable_vblank = valleyview_enable_vblank;
2567 dev->driver->disable_vblank = valleyview_disable_vblank;
2568 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2569 /* Share pre & uninstall handlers with ILK/SNB */
2570 dev->driver->irq_handler = ivybridge_irq_handler;
2571 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2572 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2573 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2574 dev->driver->enable_vblank = ivybridge_enable_vblank;
2575 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2576 } else if (IS_HASWELL(dev)) {
2577 /* Share interrupts handling with IVB */
2578 dev->driver->irq_handler = ivybridge_irq_handler;
2579 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2580 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2581 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2582 dev->driver->enable_vblank = ivybridge_enable_vblank;
2583 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2584 } else if (HAS_PCH_SPLIT(dev)) {
2585 dev->driver->irq_handler = ironlake_irq_handler;
2586 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2587 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2588 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2589 dev->driver->enable_vblank = ironlake_enable_vblank;
2590 dev->driver->disable_vblank = ironlake_disable_vblank;
2591 } else {
c2798b19
CW		 2592 if (INTEL_INFO(dev)->gen == 2) {
2593 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2594 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2595 dev->driver->irq_handler = i8xx_irq_handler;
2596 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2597 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2598 /* IIR "flip pending" means done if this bit is set */
2599 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2600
a266c7d5
CW		 2601 dev->driver->irq_preinstall = i915_irq_preinstall;
2602 dev->driver->irq_postinstall = i915_irq_postinstall;
2603 dev->driver->irq_uninstall = i915_irq_uninstall;
2604 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2605 } else {
a266c7d5
CW		 2606 dev->driver->irq_preinstall = i965_irq_preinstall;
2607 dev->driver->irq_postinstall = i965_irq_postinstall;
2608 dev->driver->irq_uninstall = i965_irq_uninstall;
2609 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2610 }
f71d4af4
JB		 2611 dev->driver->enable_vblank = i915_enable_vblank;
2612 dev->driver->disable_vblank = i915_disable_vblank;
2613 }
2614}
Linux kernel - Deliverables
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