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drm/i915: implement ibx_hpd_irq_setup
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
e5868a31
EE		 39static const u32 hpd_ibx[] = {
40 [HPD_CRT] = SDE_CRT_HOTPLUG,
41 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
42 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
43 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
44 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
45};
46
47static const u32 hpd_cpt[] = {
48 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
49 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
50 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
51 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
52};
53
54static const u32 hpd_mask_i915[] = {
55 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
56 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
57 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
58 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
59 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
60 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
61};
62
63static const u32 hpd_status_gen4[] = {
64 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
65 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
66 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
67 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
68 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
69 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
70};
71
72static const u32 hpd_status_i965[] = {
73 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
74 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
75 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
76 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
77 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
78 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
79};
80
81static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
82 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
83 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
84 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
85 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
86 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
87 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
88};
89
90
91
036a4a7d 92/* For display hotplug interrupt */
995b6762 93static void
f2b115e6 94ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 95{
1ec14ad3
CW		 96 if ((dev_priv->irq_mask & mask) != 0) {
97 dev_priv->irq_mask &= ~mask;
98 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 99 POSTING_READ(DEIMR);
036a4a7d
ZW		 100 }
101}
102
103static inline void
f2b115e6 104ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 105{
1ec14ad3
CW		 106 if ((dev_priv->irq_mask & mask) != mask) {
107 dev_priv->irq_mask |= mask;
108 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 109 POSTING_READ(DEIMR);
036a4a7d
ZW		 110 }
111}
112
7c463586
KP		 113void
114i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
115{
46c06a30
VS		 116 u32 reg = PIPESTAT(pipe);
117 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 118
46c06a30
VS		 119 if ((pipestat & mask) == mask)
120 return;
121
122 /* Enable the interrupt, clear any pending status */
123 pipestat |= mask | (mask >> 16);
124 I915_WRITE(reg, pipestat);
125 POSTING_READ(reg);
7c463586
KP		 126}
127
128void
129i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
130{
46c06a30
VS		 131 u32 reg = PIPESTAT(pipe);
132 u32 pipestat = I915_READ(reg) & 0x7fff0000;
7c463586 133
46c06a30
VS		 134 if ((pipestat & mask) == 0)
135 return;
136
137 pipestat &= ~mask;
138 I915_WRITE(reg, pipestat);
139 POSTING_READ(reg);
7c463586
KP		 140}
141
01c66889
ZY		 142/**
143 * intel_enable_asle - enable ASLE interrupt for OpRegion
144 */
1ec14ad3 145void intel_enable_asle(struct drm_device *dev)
01c66889 146{
1ec14ad3
CW		 147 drm_i915_private_t *dev_priv = dev->dev_private;
148 unsigned long irqflags;
149
7e231dbe
JB		 150 /* FIXME: opregion/asle for VLV */
151 if (IS_VALLEYVIEW(dev))
152 return;
153
1ec14ad3 154 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 155
c619eed4 156 if (HAS_PCH_SPLIT(dev))
f2b115e6 157 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 158 else {
01c66889 159 i915_enable_pipestat(dev_priv, 1,
d874bcff 160 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 161 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 162 i915_enable_pipestat(dev_priv, 0,
d874bcff 163 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 164 }
1ec14ad3
CW		 165
166 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 167}
168
0a3e67a4
JB		 169/**
170 * i915_pipe_enabled - check if a pipe is enabled
171 * @dev: DRM device
172 * @pipe: pipe to check
173 *
174 * Reading certain registers when the pipe is disabled can hang the chip.
175 * Use this routine to make sure the PLL is running and the pipe is active
176 * before reading such registers if unsure.
177 */
178static int
179i915_pipe_enabled(struct drm_device *dev, int pipe)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 182 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
183 pipe);
184
185 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 186}
187
42f52ef8
KP		 188/* Called from drm generic code, passed a 'crtc', which
189 * we use as a pipe index
190 */
f71d4af4 191static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 192{
193 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
194 unsigned long high_frame;
195 unsigned long low_frame;
5eddb70b 196 u32 high1, high2, low;
0a3e67a4
JB		 197
198 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 199 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 200 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 201 return 0;
202 }
203
9db4a9c7
JB		 204 high_frame = PIPEFRAME(pipe);
205 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 206
0a3e67a4
JB		 207 /*
208 * High & low register fields aren't synchronized, so make sure
209 * we get a low value that's stable across two reads of the high
210 * register.
211 */
212 do {
5eddb70b
CW		 213 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
214 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
215 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 216 } while (high1 != high2);
217
5eddb70b
CW		 218 high1 >>= PIPE_FRAME_HIGH_SHIFT;
219 low >>= PIPE_FRAME_LOW_SHIFT;
220 return (high1 << 8) | low;
0a3e67a4
JB		 221}
222
f71d4af4 223static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 224{
225 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 226 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 227
228 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 229 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 230 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 231 return 0;
232 }
233
234 return I915_READ(reg);
235}
236
f71d4af4 237static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 238 int *vpos, int *hpos)
239{
240 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
241 u32 vbl = 0, position = 0;
242 int vbl_start, vbl_end, htotal, vtotal;
243 bool in_vbl = true;
244 int ret = 0;
fe2b8f9d
PZ		 245 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
246 pipe);
0af7e4df
MK		 247
248 if (!i915_pipe_enabled(dev, pipe)) {
249 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 250 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 251 return 0;
252 }
253
254 /* Get vtotal. */
fe2b8f9d 255 vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 256
257 if (INTEL_INFO(dev)->gen >= 4) {
258 /* No obvious pixelcount register. Only query vertical
259 * scanout position from Display scan line register.
260 */
261 position = I915_READ(PIPEDSL(pipe));
262
263 /* Decode into vertical scanout position. Don't have
264 * horizontal scanout position.
265 */
266 *vpos = position & 0x1fff;
267 *hpos = 0;
268 } else {
269 /* Have access to pixelcount since start of frame.
270 * We can split this into vertical and horizontal
271 * scanout position.
272 */
273 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
274
fe2b8f9d 275 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
0af7e4df
MK		 276 *vpos = position / htotal;
277 *hpos = position - (*vpos * htotal);
278 }
279
280 /* Query vblank area. */
fe2b8f9d 281 vbl = I915_READ(VBLANK(cpu_transcoder));
0af7e4df
MK		 282
283 /* Test position against vblank region. */
284 vbl_start = vbl & 0x1fff;
285 vbl_end = (vbl >> 16) & 0x1fff;
286
287 if ((*vpos < vbl_start) || (*vpos > vbl_end))
288 in_vbl = false;
289
290 /* Inside "upper part" of vblank area? Apply corrective offset: */
291 if (in_vbl && (*vpos >= vbl_start))
292 *vpos = *vpos - vtotal;
293
294 /* Readouts valid? */
295 if (vbl > 0)
296 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
297
298 /* In vblank? */
299 if (in_vbl)
300 ret |= DRM_SCANOUTPOS_INVBL;
301
302 return ret;
303}
304
f71d4af4 305static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 306 int *max_error,
307 struct timeval *vblank_time,
308 unsigned flags)
309{
4041b853 310 struct drm_crtc *crtc;
0af7e4df 311
7eb552ae 312 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
4041b853 313 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 314 return -EINVAL;
315 }
316
317 /* Get drm_crtc to timestamp: */
4041b853
CW		 318 crtc = intel_get_crtc_for_pipe(dev, pipe);
319 if (crtc == NULL) {
320 DRM_ERROR("Invalid crtc %d\n", pipe);
321 return -EINVAL;
322 }
323
324 if (!crtc->enabled) {
325 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
326 return -EBUSY;
327 }
0af7e4df
MK		 328
329 /* Helper routine in DRM core does all the work: */
4041b853
CW		 330 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
331 vblank_time, flags,
332 crtc);
0af7e4df
MK		 333}
334
5ca58282
JB		 335/*
336 * Handle hotplug events outside the interrupt handler proper.
337 */
338static void i915_hotplug_work_func(struct work_struct *work)
339{
340 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
341 hotplug_work);
342 struct drm_device *dev = dev_priv->dev;
c31c4ba3 343 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 344 struct intel_encoder *encoder;
345
52d7eced
DV		 346 /* HPD irq before everything is fully set up. */
347 if (!dev_priv->enable_hotplug_processing)
348 return;
349
a65e34c7 350 mutex_lock(&mode_config->mutex);
e67189ab
JB		 351 DRM_DEBUG_KMS("running encoder hotplug functions\n");
352
4ef69c7a
CW		 353 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
354 if (encoder->hot_plug)
355 encoder->hot_plug(encoder);
356
40ee3381
KP		 357 mutex_unlock(&mode_config->mutex);
358
5ca58282 359 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 360 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 361}
362
73edd18f 363static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 364{
365 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 366 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 367 u8 new_delay;
368 unsigned long flags;
369
370 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 371
73edd18f
DV		 372 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
373
20e4d407 374 new_delay = dev_priv->ips.cur_delay;
9270388e 375
7648fa99 376 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 377 busy_up = I915_READ(RCPREVBSYTUPAVG);
378 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 379 max_avg = I915_READ(RCBMAXAVG);
380 min_avg = I915_READ(RCBMINAVG);
381
382 /* Handle RCS change request from hw */
b5b72e89 383 if (busy_up > max_avg) {
20e4d407
DV		 384 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
385 new_delay = dev_priv->ips.cur_delay - 1;
386 if (new_delay < dev_priv->ips.max_delay)
387 new_delay = dev_priv->ips.max_delay;
b5b72e89 388 } else if (busy_down < min_avg) {
20e4d407
DV		 389 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
390 new_delay = dev_priv->ips.cur_delay + 1;
391 if (new_delay > dev_priv->ips.min_delay)
392 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 393 }
394
7648fa99 395 if (ironlake_set_drps(dev, new_delay))
20e4d407 396 dev_priv->ips.cur_delay = new_delay;
f97108d1 397
9270388e
DV		 398 spin_unlock_irqrestore(&mchdev_lock, flags);
399
f97108d1
JB		 400 return;
401}
402
549f7365
CW		 403static void notify_ring(struct drm_device *dev,
404 struct intel_ring_buffer *ring)
405{
406 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 407
475553de
CW		 408 if (ring->obj == NULL)
409 return;
410
b2eadbc8 411 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 412
549f7365 413 wake_up_all(&ring->irq_queue);
3e0dc6b0 414 if (i915_enable_hangcheck) {
99584db3
DV		 415 dev_priv->gpu_error.hangcheck_count = 0;
416 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 417 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 418 }
549f7365
CW		 419}
420
4912d041 421static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 422{
4912d041 423 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 424 rps.work);
4912d041 425 u32 pm_iir, pm_imr;
7b9e0ae6 426 u8 new_delay;
4912d041 427
c6a828d3
DV		 428 spin_lock_irq(&dev_priv->rps.lock);
429 pm_iir = dev_priv->rps.pm_iir;
430 dev_priv->rps.pm_iir = 0;
4912d041 431 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 432 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 433 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 434
7b9e0ae6 435 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 436 return;
437
4fc688ce 438 mutex_lock(&dev_priv->rps.hw_lock);
7b9e0ae6
CW		 439
440 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 441 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 442 else
c6a828d3 443 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 444
79249636
BW		 445 /* sysfs frequency interfaces may have snuck in while servicing the
446 * interrupt
447 */
448 if (!(new_delay > dev_priv->rps.max_delay ||
449 new_delay < dev_priv->rps.min_delay)) {
450 gen6_set_rps(dev_priv->dev, new_delay);
451 }
3b8d8d91 452
4fc688ce 453 mutex_unlock(&dev_priv->rps.hw_lock);
3b8d8d91
JB		 454}
455
e3689190
BW		 456
457/**
458 * ivybridge_parity_work - Workqueue called when a parity error interrupt
459 * occurred.
460 * @work: workqueue struct
461 *
462 * Doesn't actually do anything except notify userspace. As a consequence of
463 * this event, userspace should try to remap the bad rows since statistically
464 * it is likely the same row is more likely to go bad again.
465 */
466static void ivybridge_parity_work(struct work_struct *work)
467{
468 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
a4da4fa4 469 l3_parity.error_work);
e3689190
BW		 470 u32 error_status, row, bank, subbank;
471 char *parity_event[5];
472 uint32_t misccpctl;
473 unsigned long flags;
474
475 /* We must turn off DOP level clock gating to access the L3 registers.
476 * In order to prevent a get/put style interface, acquire struct mutex
477 * any time we access those registers.
478 */
479 mutex_lock(&dev_priv->dev->struct_mutex);
480
481 misccpctl = I915_READ(GEN7_MISCCPCTL);
482 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
483 POSTING_READ(GEN7_MISCCPCTL);
484
485 error_status = I915_READ(GEN7_L3CDERRST1);
486 row = GEN7_PARITY_ERROR_ROW(error_status);
487 bank = GEN7_PARITY_ERROR_BANK(error_status);
488 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
489
490 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
491 GEN7_L3CDERRST1_ENABLE);
492 POSTING_READ(GEN7_L3CDERRST1);
493
494 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
495
496 spin_lock_irqsave(&dev_priv->irq_lock, flags);
497 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
498 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
499 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
500
501 mutex_unlock(&dev_priv->dev->struct_mutex);
502
503 parity_event[0] = "L3_PARITY_ERROR=1";
504 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
505 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
506 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
507 parity_event[4] = NULL;
508
509 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
510 KOBJ_CHANGE, parity_event);
511
512 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
513 row, bank, subbank);
514
515 kfree(parity_event[3]);
516 kfree(parity_event[2]);
517 kfree(parity_event[1]);
518}
519
d2ba8470 520static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 521{
522 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
523 unsigned long flags;
524
e1ef7cc2 525 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 526 return;
527
528 spin_lock_irqsave(&dev_priv->irq_lock, flags);
529 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
530 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
531 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
532
a4da4fa4 533 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
e3689190
BW		 534}
535
e7b4c6b1
DV		 536static void snb_gt_irq_handler(struct drm_device *dev,
537 struct drm_i915_private *dev_priv,
538 u32 gt_iir)
539{
540
541 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
542 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
543 notify_ring(dev, &dev_priv->ring[RCS]);
544 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
545 notify_ring(dev, &dev_priv->ring[VCS]);
546 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
547 notify_ring(dev, &dev_priv->ring[BCS]);
548
549 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
550 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
551 GT_RENDER_CS_ERROR_INTERRUPT)) {
552 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
553 i915_handle_error(dev, false);
554 }
e3689190
BW		 555
556 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
557 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 558}
559
fc6826d1
CW		 560static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
561 u32 pm_iir)
562{
563 unsigned long flags;
564
565 /*
566 * IIR bits should never already be set because IMR should
567 * prevent an interrupt from being shown in IIR. The warning
568 * displays a case where we've unsafely cleared
c6a828d3 569 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 570 * type is not a problem, it displays a problem in the logic.
571 *
c6a828d3 572 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 573 */
574
c6a828d3 575 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 576 dev_priv->rps.pm_iir |= pm_iir;
577 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 578 POSTING_READ(GEN6_PMIMR);
c6a828d3 579 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 580
c6a828d3 581 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 582}
583
515ac2bb
DV		 584static void gmbus_irq_handler(struct drm_device *dev)
585{
28c70f16
DV		 586 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
587
28c70f16 588 wake_up_all(&dev_priv->gmbus_wait_queue);
515ac2bb
DV		 589}
590
ce99c256
DV		 591static void dp_aux_irq_handler(struct drm_device *dev)
592{
9ee32fea
DV		 593 struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
594
9ee32fea 595 wake_up_all(&dev_priv->gmbus_wait_queue);
ce99c256
DV		 596}
597
ff1f525e 598static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 599{
600 struct drm_device *dev = (struct drm_device *) arg;
601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
602 u32 iir, gt_iir, pm_iir;
603 irqreturn_t ret = IRQ_NONE;
604 unsigned long irqflags;
605 int pipe;
606 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 607
608 atomic_inc(&dev_priv->irq_received);
609
7e231dbe
JB		 610 while (true) {
611 iir = I915_READ(VLV_IIR);
612 gt_iir = I915_READ(GTIIR);
613 pm_iir = I915_READ(GEN6_PMIIR);
614
615 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
616 goto out;
617
618 ret = IRQ_HANDLED;
619
e7b4c6b1 620 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 621
622 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
623 for_each_pipe(pipe) {
624 int reg = PIPESTAT(pipe);
625 pipe_stats[pipe] = I915_READ(reg);
626
627 /*
628 * Clear the PIPE*STAT regs before the IIR
629 */
630 if (pipe_stats[pipe] & 0x8000ffff) {
631 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
632 DRM_DEBUG_DRIVER("pipe %c underrun\n",
633 pipe_name(pipe));
634 I915_WRITE(reg, pipe_stats[pipe]);
635 }
636 }
637 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
638
31acc7f5
JB		 639 for_each_pipe(pipe) {
640 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
641 drm_handle_vblank(dev, pipe);
642
643 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
644 intel_prepare_page_flip(dev, pipe);
645 intel_finish_page_flip(dev, pipe);
646 }
647 }
648
7e231dbe
JB		 649 /* Consume port. Then clear IIR or we'll miss events */
650 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
651 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
652
653 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
654 hotplug_status);
e5868a31 655 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 656 queue_work(dev_priv->wq,
657 &dev_priv->hotplug_work);
658
659 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
660 I915_READ(PORT_HOTPLUG_STAT);
661 }
662
515ac2bb
DV		 663 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
664 gmbus_irq_handler(dev);
7e231dbe 665
fc6826d1
CW		 666 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
667 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 668
669 I915_WRITE(GTIIR, gt_iir);
670 I915_WRITE(GEN6_PMIIR, pm_iir);
671 I915_WRITE(VLV_IIR, iir);
672 }
673
674out:
675 return ret;
676}
677
23e81d69 678static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 679{
680 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 681 int pipe;
776ad806 682
76e43830
DV		 683 if (pch_iir & SDE_HOTPLUG_MASK)
684 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
685
776ad806
JB		 686 if (pch_iir & SDE_AUDIO_POWER_MASK)
687 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
688 (pch_iir & SDE_AUDIO_POWER_MASK) >>
689 SDE_AUDIO_POWER_SHIFT);
690
ce99c256
DV		 691 if (pch_iir & SDE_AUX_MASK)
692 dp_aux_irq_handler(dev);
693
776ad806 694 if (pch_iir & SDE_GMBUS)
515ac2bb 695 gmbus_irq_handler(dev);
776ad806
JB		 696
697 if (pch_iir & SDE_AUDIO_HDCP_MASK)
698 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
699
700 if (pch_iir & SDE_AUDIO_TRANS_MASK)
701 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
702
703 if (pch_iir & SDE_POISON)
704 DRM_ERROR("PCH poison interrupt\n");
705
9db4a9c7
JB		 706 if (pch_iir & SDE_FDI_MASK)
707 for_each_pipe(pipe)
708 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
709 pipe_name(pipe),
710 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 711
712 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
713 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
714
715 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
716 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
717
718 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
719 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
720 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
721 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
722}
723
23e81d69
AJ		 724static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
725{
726 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
727 int pipe;
728
76e43830
DV		 729 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
730 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
731
23e81d69
AJ		 732 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
733 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
734 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
735 SDE_AUDIO_POWER_SHIFT_CPT);
736
737 if (pch_iir & SDE_AUX_MASK_CPT)
ce99c256 738 dp_aux_irq_handler(dev);
23e81d69
AJ		 739
740 if (pch_iir & SDE_GMBUS_CPT)
515ac2bb 741 gmbus_irq_handler(dev);
23e81d69
AJ		 742
743 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
744 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
745
746 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
747 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
748
749 if (pch_iir & SDE_FDI_MASK_CPT)
750 for_each_pipe(pipe)
751 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
752 pipe_name(pipe),
753 I915_READ(FDI_RX_IIR(pipe)));
754}
755
ff1f525e 756static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 757{
758 struct drm_device *dev = (struct drm_device *) arg;
759 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
44498aea 760 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
0e43406b
CW		 761 irqreturn_t ret = IRQ_NONE;
762 int i;
b1f14ad0
JB		 763
764 atomic_inc(&dev_priv->irq_received);
765
766 /* disable master interrupt before clearing iir */
767 de_ier = I915_READ(DEIER);
768 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 769
44498aea
PZ		 770 /* Disable south interrupts. We'll only write to SDEIIR once, so further
771 * interrupts will will be stored on its back queue, and then we'll be
772 * able to process them after we restore SDEIER (as soon as we restore
773 * it, we'll get an interrupt if SDEIIR still has something to process
774 * due to its back queue). */
775 sde_ier = I915_READ(SDEIER);
776 I915_WRITE(SDEIER, 0);
777 POSTING_READ(SDEIER);
778
b1f14ad0 779 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 780 if (gt_iir) {
781 snb_gt_irq_handler(dev, dev_priv, gt_iir);
782 I915_WRITE(GTIIR, gt_iir);
783 ret = IRQ_HANDLED;
b1f14ad0
JB		 784 }
785
0e43406b
CW		 786 de_iir = I915_READ(DEIIR);
787 if (de_iir) {
ce99c256
DV		 788 if (de_iir & DE_AUX_CHANNEL_A_IVB)
789 dp_aux_irq_handler(dev);
790
0e43406b
CW		 791 if (de_iir & DE_GSE_IVB)
792 intel_opregion_gse_intr(dev);
793
794 for (i = 0; i < 3; i++) {
74d44445
DV		 795 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
796 drm_handle_vblank(dev, i);
0e43406b
CW		 797 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
798 intel_prepare_page_flip(dev, i);
799 intel_finish_page_flip_plane(dev, i);
800 }
0e43406b 801 }
b615b57a 802
0e43406b
CW		 803 /* check event from PCH */
804 if (de_iir & DE_PCH_EVENT_IVB) {
805 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 806
23e81d69 807 cpt_irq_handler(dev, pch_iir);
b1f14ad0 808
0e43406b
CW		 809 /* clear PCH hotplug event before clear CPU irq */
810 I915_WRITE(SDEIIR, pch_iir);
811 }
b615b57a 812
0e43406b
CW		 813 I915_WRITE(DEIIR, de_iir);
814 ret = IRQ_HANDLED;
b1f14ad0
JB		 815 }
816
0e43406b
CW		 817 pm_iir = I915_READ(GEN6_PMIIR);
818 if (pm_iir) {
819 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
820 gen6_queue_rps_work(dev_priv, pm_iir);
821 I915_WRITE(GEN6_PMIIR, pm_iir);
822 ret = IRQ_HANDLED;
823 }
b1f14ad0 824
b1f14ad0
JB		 825 I915_WRITE(DEIER, de_ier);
826 POSTING_READ(DEIER);
44498aea
PZ		 827 I915_WRITE(SDEIER, sde_ier);
828 POSTING_READ(SDEIER);
b1f14ad0
JB		 829
830 return ret;
831}
832
e7b4c6b1
DV		 833static void ilk_gt_irq_handler(struct drm_device *dev,
834 struct drm_i915_private *dev_priv,
835 u32 gt_iir)
836{
837 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
838 notify_ring(dev, &dev_priv->ring[RCS]);
839 if (gt_iir & GT_BSD_USER_INTERRUPT)
840 notify_ring(dev, &dev_priv->ring[VCS]);
841}
842
ff1f525e 843static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 844{
4697995b 845 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
847 int ret = IRQ_NONE;
44498aea 848 u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
881f47b6 849
4697995b
JB		 850 atomic_inc(&dev_priv->irq_received);
851
2d109a84
ZN		 852 /* disable master interrupt before clearing iir */
853 de_ier = I915_READ(DEIER);
854 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 855 POSTING_READ(DEIER);
2d109a84 856
44498aea
PZ		 857 /* Disable south interrupts. We'll only write to SDEIIR once, so further
858 * interrupts will will be stored on its back queue, and then we'll be
859 * able to process them after we restore SDEIER (as soon as we restore
860 * it, we'll get an interrupt if SDEIIR still has something to process
861 * due to its back queue). */
862 sde_ier = I915_READ(SDEIER);
863 I915_WRITE(SDEIER, 0);
864 POSTING_READ(SDEIER);
865
036a4a7d
ZW		 866 de_iir = I915_READ(DEIIR);
867 gt_iir = I915_READ(GTIIR);
3b8d8d91 868 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 869
acd15b6c 870 if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 871 goto done;
036a4a7d 872
c7c85101 873 ret = IRQ_HANDLED;
036a4a7d 874
e7b4c6b1
DV		 875 if (IS_GEN5(dev))
876 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
877 else
878 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 879
ce99c256
DV		 880 if (de_iir & DE_AUX_CHANNEL_A)
881 dp_aux_irq_handler(dev);
882
c7c85101 883 if (de_iir & DE_GSE)
3b617967 884 intel_opregion_gse_intr(dev);
c650156a 885
74d44445
DV		 886 if (de_iir & DE_PIPEA_VBLANK)
887 drm_handle_vblank(dev, 0);
888
889 if (de_iir & DE_PIPEB_VBLANK)
890 drm_handle_vblank(dev, 1);
891
f072d2e7 892 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 893 intel_prepare_page_flip(dev, 0);
2bbda389 894 intel_finish_page_flip_plane(dev, 0);
f072d2e7 895 }
013d5aa2 896
f072d2e7 897 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 898 intel_prepare_page_flip(dev, 1);
2bbda389 899 intel_finish_page_flip_plane(dev, 1);
f072d2e7 900 }
013d5aa2 901
c7c85101 902 /* check event from PCH */
776ad806 903 if (de_iir & DE_PCH_EVENT) {
acd15b6c
DV		 904 u32 pch_iir = I915_READ(SDEIIR);
905
23e81d69
AJ		 906 if (HAS_PCH_CPT(dev))
907 cpt_irq_handler(dev, pch_iir);
908 else
909 ibx_irq_handler(dev, pch_iir);
acd15b6c
DV		 910
911 /* should clear PCH hotplug event before clear CPU irq */
912 I915_WRITE(SDEIIR, pch_iir);
776ad806 913 }
036a4a7d 914
73edd18f
DV		 915 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
916 ironlake_handle_rps_change(dev);
f97108d1 917
fc6826d1
CW		 918 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
919 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 920
c7c85101
ZN		 921 I915_WRITE(GTIIR, gt_iir);
922 I915_WRITE(DEIIR, de_iir);
4912d041 923 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 924
925done:
2d109a84 926 I915_WRITE(DEIER, de_ier);
3143a2bf 927 POSTING_READ(DEIER);
44498aea
PZ		 928 I915_WRITE(SDEIER, sde_ier);
929 POSTING_READ(SDEIER);
2d109a84 930
036a4a7d
ZW		 931 return ret;
932}
933
8a905236
JB		 934/**
935 * i915_error_work_func - do process context error handling work
936 * @work: work struct
937 *
938 * Fire an error uevent so userspace can see that a hang or error
939 * was detected.
940 */
941static void i915_error_work_func(struct work_struct *work)
942{
1f83fee0
DV		 943 struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
944 work);
945 drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
946 gpu_error);
8a905236 947 struct drm_device *dev = dev_priv->dev;
f69061be 948 struct intel_ring_buffer *ring;
f316a42c
BG		 949 char *error_event[] = { "ERROR=1", NULL };
950 char *reset_event[] = { "RESET=1", NULL };
951 char *reset_done_event[] = { "ERROR=0", NULL };
f69061be 952 int i, ret;
8a905236 953
f316a42c
BG		 954 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
955
7db0ba24
DV		 956 /*
957 * Note that there's only one work item which does gpu resets, so we
958 * need not worry about concurrent gpu resets potentially incrementing
959 * error->reset_counter twice. We only need to take care of another
960 * racing irq/hangcheck declaring the gpu dead for a second time. A
961 * quick check for that is good enough: schedule_work ensures the
962 * correct ordering between hang detection and this work item, and since
963 * the reset in-progress bit is only ever set by code outside of this
964 * work we don't need to worry about any other races.
965 */
966 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
f803aa55 967 DRM_DEBUG_DRIVER("resetting chip\n");
7db0ba24
DV		 968 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
969 reset_event);
1f83fee0 970
f69061be
DV		 971 ret = i915_reset(dev);
972
973 if (ret == 0) {
974 /*
975 * After all the gem state is reset, increment the reset
976 * counter and wake up everyone waiting for the reset to
977 * complete.
978 *
979 * Since unlock operations are a one-sided barrier only,
980 * we need to insert a barrier here to order any seqno
981 * updates before
982 * the counter increment.
983 */
984 smp_mb__before_atomic_inc();
985 atomic_inc(&dev_priv->gpu_error.reset_counter);
986
987 kobject_uevent_env(&dev->primary->kdev.kobj,
988 KOBJ_CHANGE, reset_done_event);
1f83fee0
DV		 989 } else {
990 atomic_set(&error->reset_counter, I915_WEDGED);
f316a42c 991 }
1f83fee0 992
f69061be
DV		 993 for_each_ring(ring, dev_priv, i)
994 wake_up_all(&ring->irq_queue);
995
96a02917
VS		 996 intel_display_handle_reset(dev);
997
1f83fee0 998 wake_up_all(&dev_priv->gpu_error.reset_queue);
f316a42c 999 }
8a905236
JB		 1000}
1001
85f9e50d
DV		 1002/* NB: please notice the memset */
1003static void i915_get_extra_instdone(struct drm_device *dev,
1004 uint32_t *instdone)
1005{
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1007 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1008
1009 switch(INTEL_INFO(dev)->gen) {
1010 case 2:
1011 case 3:
1012 instdone[0] = I915_READ(INSTDONE);
1013 break;
1014 case 4:
1015 case 5:
1016 case 6:
1017 instdone[0] = I915_READ(INSTDONE_I965);
1018 instdone[1] = I915_READ(INSTDONE1);
1019 break;
1020 default:
1021 WARN_ONCE(1, "Unsupported platform\n");
1022 case 7:
1023 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1024 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1025 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1026 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1027 break;
1028 }
1029}
1030
3bd3c932 1031#ifdef CONFIG_DEBUG_FS
9df30794 1032static struct drm_i915_error_object *
d0d045e8
BW		 1033i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1034 struct drm_i915_gem_object *src,
1035 const int num_pages)
9df30794
CW		 1036{
1037 struct drm_i915_error_object *dst;
d0d045e8 1038 int i;
e56660dd 1039 u32 reloc_offset;
9df30794 1040
05394f39 1041 if (src == NULL || src->pages == NULL)
9df30794
CW		 1042 return NULL;
1043
d0d045e8 1044 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 1045 if (dst == NULL)
1046 return NULL;
1047
05394f39 1048 reloc_offset = src->gtt_offset;
d0d045e8 1049 for (i = 0; i < num_pages; i++) {
788885ae 1050 unsigned long flags;
e56660dd 1051 void *d;
788885ae 1052
e56660dd 1053 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 1054 if (d == NULL)
1055 goto unwind;
e56660dd 1056
788885ae 1057 local_irq_save(flags);
5d4545ae 1058 if (reloc_offset < dev_priv->gtt.mappable_end &&
74898d7e 1059 src->has_global_gtt_mapping) {
172975aa
CW		 1060 void __iomem *s;
1061
1062 /* Simply ignore tiling or any overlapping fence.
1063 * It's part of the error state, and this hopefully
1064 * captures what the GPU read.
1065 */
1066
5d4545ae 1067 s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
172975aa
CW		 1068 reloc_offset);
1069 memcpy_fromio(d, s, PAGE_SIZE);
1070 io_mapping_unmap_atomic(s);
960e3564
CW		 1071 } else if (src->stolen) {
1072 unsigned long offset;
1073
1074 offset = dev_priv->mm.stolen_base;
1075 offset += src->stolen->start;
1076 offset += i << PAGE_SHIFT;
1077
1a240d4d 1078 memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
172975aa 1079 } else {
9da3da66 1080 struct page *page;
172975aa
CW		 1081 void *s;
1082
9da3da66 1083 page = i915_gem_object_get_page(src, i);
172975aa 1084
9da3da66
CW		 1085 drm_clflush_pages(&page, 1);
1086
1087 s = kmap_atomic(page);
172975aa
CW		 1088 memcpy(d, s, PAGE_SIZE);
1089 kunmap_atomic(s);
1090
9da3da66 1091 drm_clflush_pages(&page, 1);
172975aa 1092 }
788885ae 1093 local_irq_restore(flags);
e56660dd 1094
9da3da66 1095 dst->pages[i] = d;
e56660dd
CW		 1096
1097 reloc_offset += PAGE_SIZE;
9df30794 1098 }
d0d045e8 1099 dst->page_count = num_pages;
05394f39 1100 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 1101
1102 return dst;
1103
1104unwind:
9da3da66
CW		 1105 while (i--)
1106 kfree(dst->pages[i]);
9df30794
CW		 1107 kfree(dst);
1108 return NULL;
1109}
d0d045e8
BW		 1110#define i915_error_object_create(dev_priv, src) \
1111 i915_error_object_create_sized((dev_priv), (src), \
1112 (src)->base.size>>PAGE_SHIFT)
9df30794
CW		 1113
1114static void
1115i915_error_object_free(struct drm_i915_error_object *obj)
1116{
1117 int page;
1118
1119 if (obj == NULL)
1120 return;
1121
1122 for (page = 0; page < obj->page_count; page++)
1123 kfree(obj->pages[page]);
1124
1125 kfree(obj);
1126}
1127
742cbee8
DV		 1128void
1129i915_error_state_free(struct kref *error_ref)
9df30794 1130{
742cbee8
DV		 1131 struct drm_i915_error_state *error = container_of(error_ref,
1132 typeof(*error), ref);
e2f973d5
CW		 1133 int i;
1134
52d39a21
CW		 1135 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1136 i915_error_object_free(error->ring[i].batchbuffer);
1137 i915_error_object_free(error->ring[i].ringbuffer);
1138 kfree(error->ring[i].requests);
1139 }
e2f973d5 1140
9df30794 1141 kfree(error->active_bo);
6ef3d427 1142 kfree(error->overlay);
9df30794
CW		 1143 kfree(error);
1144}
1b50247a
CW		 1145static void capture_bo(struct drm_i915_error_buffer *err,
1146 struct drm_i915_gem_object *obj)
1147{
1148 err->size = obj->base.size;
1149 err->name = obj->base.name;
0201f1ec
CW		 1150 err->rseqno = obj->last_read_seqno;
1151 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 1152 err->gtt_offset = obj->gtt_offset;
1153 err->read_domains = obj->base.read_domains;
1154 err->write_domain = obj->base.write_domain;
1155 err->fence_reg = obj->fence_reg;
1156 err->pinned = 0;
1157 if (obj->pin_count > 0)
1158 err->pinned = 1;
1159 if (obj->user_pin_count > 0)
1160 err->pinned = -1;
1161 err->tiling = obj->tiling_mode;
1162 err->dirty = obj->dirty;
1163 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1164 err->ring = obj->ring ? obj->ring->id : -1;
1165 err->cache_level = obj->cache_level;
1166}
9df30794 1167
1b50247a
CW		 1168static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1169 int count, struct list_head *head)
c724e8a9
CW		 1170{
1171 struct drm_i915_gem_object *obj;
1172 int i = 0;
1173
1174 list_for_each_entry(obj, head, mm_list) {
1b50247a 1175 capture_bo(err++, obj);
c724e8a9
CW		 1176 if (++i == count)
1177 break;
1b50247a
CW		 1178 }
1179
1180 return i;
1181}
1182
1183static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1184 int count, struct list_head *head)
1185{
1186 struct drm_i915_gem_object *obj;
1187 int i = 0;
1188
1189 list_for_each_entry(obj, head, gtt_list) {
1190 if (obj->pin_count == 0)
1191 continue;
c724e8a9 1192
1b50247a
CW		 1193 capture_bo(err++, obj);
1194 if (++i == count)
1195 break;
c724e8a9
CW		 1196 }
1197
1198 return i;
1199}
1200
748ebc60
CW		 1201static void i915_gem_record_fences(struct drm_device *dev,
1202 struct drm_i915_error_state *error)
1203{
1204 struct drm_i915_private *dev_priv = dev->dev_private;
1205 int i;
1206
1207 /* Fences */
1208 switch (INTEL_INFO(dev)->gen) {
775d17b6 1209 case 7:
748ebc60
CW		 1210 case 6:
1211 for (i = 0; i < 16; i++)
1212 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1213 break;
1214 case 5:
1215 case 4:
1216 for (i = 0; i < 16; i++)
1217 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1218 break;
1219 case 3:
1220 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1221 for (i = 0; i < 8; i++)
1222 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1223 case 2:
1224 for (i = 0; i < 8; i++)
1225 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1226 break;
1227
7dbf9d6e
BW		 1228 default:
1229 BUG();
748ebc60
CW		 1230 }
1231}
1232
bcfb2e28
CW		 1233static struct drm_i915_error_object *
1234i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1235 struct intel_ring_buffer *ring)
1236{
1237 struct drm_i915_gem_object *obj;
1238 u32 seqno;
1239
1240 if (!ring->get_seqno)
1241 return NULL;
1242
b45305fc
DV		 1243 if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1244 u32 acthd = I915_READ(ACTHD);
1245
1246 if (WARN_ON(ring->id != RCS))
1247 return NULL;
1248
1249 obj = ring->private;
1250 if (acthd >= obj->gtt_offset &&
1251 acthd < obj->gtt_offset + obj->base.size)
1252 return i915_error_object_create(dev_priv, obj);
1253 }
1254
b2eadbc8 1255 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1256 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1257 if (obj->ring != ring)
1258 continue;
1259
0201f1ec 1260 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1261 continue;
1262
1263 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1264 continue;
1265
1266 /* We need to copy these to an anonymous buffer as the simplest
1267 * method to avoid being overwritten by userspace.
1268 */
1269 return i915_error_object_create(dev_priv, obj);
1270 }
1271
1272 return NULL;
1273}
1274
d27b1e0e
DV		 1275static void i915_record_ring_state(struct drm_device *dev,
1276 struct drm_i915_error_state *error,
1277 struct intel_ring_buffer *ring)
1278{
1279 struct drm_i915_private *dev_priv = dev->dev_private;
1280
33f3f518 1281 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1282 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1283 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1284 error->semaphore_mboxes[ring->id][0]
1285 = I915_READ(RING_SYNC_0(ring->mmio_base));
1286 error->semaphore_mboxes[ring->id][1]
1287 = I915_READ(RING_SYNC_1(ring->mmio_base));
df2b23d9
CW		 1288 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1289 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
33f3f518 1290 }
c1cd90ed 1291
d27b1e0e 1292 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1293 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1294 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1295 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1296 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1297 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1298 if (ring->id == RCS)
d27b1e0e 1299 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1300 } else {
9d2f41fa 1301 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1302 error->ipeir[ring->id] = I915_READ(IPEIR);
1303 error->ipehr[ring->id] = I915_READ(IPEHR);
1304 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1305 }
1306
9574b3fe 1307 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1308 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1309 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1310 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1311 error->head[ring->id] = I915_READ_HEAD(ring);
1312 error->tail[ring->id] = I915_READ_TAIL(ring);
0f3b6849 1313 error->ctl[ring->id] = I915_READ_CTL(ring);
7e3b8737
DV		 1314
1315 error->cpu_ring_head[ring->id] = ring->head;
1316 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1317}
1318
8c123e54
BW		 1319
1320static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1321 struct drm_i915_error_state *error,
1322 struct drm_i915_error_ring *ering)
1323{
1324 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1325 struct drm_i915_gem_object *obj;
1326
1327 /* Currently render ring is the only HW context user */
1328 if (ring->id != RCS || !error->ccid)
1329 return;
1330
1331 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1332 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1333 ering->ctx = i915_error_object_create_sized(dev_priv,
1334 obj, 1);
1335 }
1336 }
1337}
1338
52d39a21
CW		 1339static void i915_gem_record_rings(struct drm_device *dev,
1340 struct drm_i915_error_state *error)
1341{
1342 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1343 struct intel_ring_buffer *ring;
52d39a21
CW		 1344 struct drm_i915_gem_request *request;
1345 int i, count;
1346
b4519513 1347 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1348 i915_record_ring_state(dev, error, ring);
1349
1350 error->ring[i].batchbuffer =
1351 i915_error_first_batchbuffer(dev_priv, ring);
1352
1353 error->ring[i].ringbuffer =
1354 i915_error_object_create(dev_priv, ring->obj);
1355
8c123e54
BW		 1356
1357 i915_gem_record_active_context(ring, error, &error->ring[i]);
1358
52d39a21
CW		 1359 count = 0;
1360 list_for_each_entry(request, &ring->request_list, list)
1361 count++;
1362
1363 error->ring[i].num_requests = count;
1364 error->ring[i].requests =
1365 kmalloc(count*sizeof(struct drm_i915_error_request),
1366 GFP_ATOMIC);
1367 if (error->ring[i].requests == NULL) {
1368 error->ring[i].num_requests = 0;
1369 continue;
1370 }
1371
1372 count = 0;
1373 list_for_each_entry(request, &ring->request_list, list) {
1374 struct drm_i915_error_request *erq;
1375
1376 erq = &error->ring[i].requests[count++];
1377 erq->seqno = request->seqno;
1378 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1379 erq->tail = request->tail;
52d39a21
CW		 1380 }
1381 }
1382}
1383
8a905236
JB		 1384/**
1385 * i915_capture_error_state - capture an error record for later analysis
1386 * @dev: drm device
1387 *
1388 * Should be called when an error is detected (either a hang or an error
1389 * interrupt) to capture error state from the time of the error. Fills
1390 * out a structure which becomes available in debugfs for user level tools
1391 * to pick up.
1392 */
63eeaf38
JB		 1393static void i915_capture_error_state(struct drm_device *dev)
1394{
1395 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1396 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1397 struct drm_i915_error_state *error;
1398 unsigned long flags;
9db4a9c7 1399 int i, pipe;
63eeaf38 1400
99584db3
DV		 1401 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1402 error = dev_priv->gpu_error.first_error;
1403 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1404 if (error)
1405 return;
63eeaf38 1406
9db4a9c7 1407 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1408 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1409 if (!error) {
9df30794
CW		 1410 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1411 return;
63eeaf38
JB		 1412 }
1413
5d83d294 1414 DRM_INFO("capturing error event; look for more information in "
2f86f191 1415 "/sys/kernel/debug/dri/%d/i915_error_state\n",
b6f7833b 1416 dev->primary->index);
2fa772f3 1417
742cbee8 1418 kref_init(&error->ref);
63eeaf38
JB		 1419 error->eir = I915_READ(EIR);
1420 error->pgtbl_er = I915_READ(PGTBL_ER);
211816ec
BW		 1421 if (HAS_HW_CONTEXTS(dev))
1422 error->ccid = I915_READ(CCID);
be998e2e
BW		 1423
1424 if (HAS_PCH_SPLIT(dev))
1425 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1426 else if (IS_VALLEYVIEW(dev))
1427 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1428 else if (IS_GEN2(dev))
1429 error->ier = I915_READ16(IER);
1430 else
1431 error->ier = I915_READ(IER);
1432
0f3b6849
CW		 1433 if (INTEL_INFO(dev)->gen >= 6)
1434 error->derrmr = I915_READ(DERRMR);
1435
1436 if (IS_VALLEYVIEW(dev))
1437 error->forcewake = I915_READ(FORCEWAKE_VLV);
1438 else if (INTEL_INFO(dev)->gen >= 7)
1439 error->forcewake = I915_READ(FORCEWAKE_MT);
1440 else if (INTEL_INFO(dev)->gen == 6)
1441 error->forcewake = I915_READ(FORCEWAKE);
1442
4f3308b9
PZ		 1443 if (!HAS_PCH_SPLIT(dev))
1444 for_each_pipe(pipe)
1445 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1446
33f3f518 1447 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1448 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1449 error->done_reg = I915_READ(DONE_REG);
1450 }
d27b1e0e 1451
71e172e8
BW		 1452 if (INTEL_INFO(dev)->gen == 7)
1453 error->err_int = I915_READ(GEN7_ERR_INT);
1454
050ee91f
BW		 1455 i915_get_extra_instdone(dev, error->extra_instdone);
1456
748ebc60 1457 i915_gem_record_fences(dev, error);
52d39a21 1458 i915_gem_record_rings(dev, error);
9df30794 1459
c724e8a9 1460 /* Record buffers on the active and pinned lists. */
9df30794 1461 error->active_bo = NULL;
c724e8a9 1462 error->pinned_bo = NULL;
9df30794 1463
bcfb2e28
CW		 1464 i = 0;
1465 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1466 i++;
1467 error->active_bo_count = i;
6c085a72 1468 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1469 if (obj->pin_count)
1470 i++;
bcfb2e28 1471 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1472
8e934dbf
CW		 1473 error->active_bo = NULL;
1474 error->pinned_bo = NULL;
bcfb2e28
CW		 1475 if (i) {
1476 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1477 GFP_ATOMIC);
c724e8a9
CW		 1478 if (error->active_bo)
1479 error->pinned_bo =
1480 error->active_bo + error->active_bo_count;
9df30794
CW		 1481 }
1482
c724e8a9
CW		 1483 if (error->active_bo)
1484 error->active_bo_count =
1b50247a
CW		 1485 capture_active_bo(error->active_bo,
1486 error->active_bo_count,
1487 &dev_priv->mm.active_list);
c724e8a9
CW		 1488
1489 if (error->pinned_bo)
1490 error->pinned_bo_count =
1b50247a
CW		 1491 capture_pinned_bo(error->pinned_bo,
1492 error->pinned_bo_count,
6c085a72 1493 &dev_priv->mm.bound_list);
c724e8a9 1494
9df30794
CW		 1495 do_gettimeofday(&error->time);
1496
6ef3d427 1497 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1498 error->display = intel_display_capture_error_state(dev);
6ef3d427 1499
99584db3
DV		 1500 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1501 if (dev_priv->gpu_error.first_error == NULL) {
1502 dev_priv->gpu_error.first_error = error;
9df30794
CW		 1503 error = NULL;
1504 }
99584db3 1505 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1506
1507 if (error)
742cbee8 1508 i915_error_state_free(&error->ref);
9df30794
CW		 1509}
1510
1511void i915_destroy_error_state(struct drm_device *dev)
1512{
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1514 struct drm_i915_error_state *error;
6dc0e816 1515 unsigned long flags;
9df30794 1516
99584db3
DV		 1517 spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1518 error = dev_priv->gpu_error.first_error;
1519 dev_priv->gpu_error.first_error = NULL;
1520 spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
9df30794
CW		 1521
1522 if (error)
742cbee8 1523 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1524}
3bd3c932
CW		 1525#else
1526#define i915_capture_error_state(x)
1527#endif
63eeaf38 1528
35aed2e6 1529static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1530{
1531 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1532 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1533 u32 eir = I915_READ(EIR);
050ee91f 1534 int pipe, i;
8a905236 1535
35aed2e6
CW		 1536 if (!eir)
1537 return;
8a905236 1538
a70491cc 1539 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1540
bd9854f9
BW		 1541 i915_get_extra_instdone(dev, instdone);
1542
8a905236
JB		 1543 if (IS_G4X(dev)) {
1544 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1545 u32 ipeir = I915_READ(IPEIR_I965);
1546
a70491cc
JP		 1547 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1548 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1549 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1550 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1551 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1552 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1553 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1554 POSTING_READ(IPEIR_I965);
8a905236
JB		 1555 }
1556 if (eir & GM45_ERROR_PAGE_TABLE) {
1557 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1558 pr_err("page table error\n");
1559 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1560 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1561 POSTING_READ(PGTBL_ER);
8a905236
JB		 1562 }
1563 }
1564
a6c45cf0 1565 if (!IS_GEN2(dev)) {
8a905236
JB		 1566 if (eir & I915_ERROR_PAGE_TABLE) {
1567 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1568 pr_err("page table error\n");
1569 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1570 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1571 POSTING_READ(PGTBL_ER);
8a905236
JB		 1572 }
1573 }
1574
1575 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1576 pr_err("memory refresh error:\n");
9db4a9c7 1577 for_each_pipe(pipe)
a70491cc 1578 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1579 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1580 /* pipestat has already been acked */
1581 }
1582 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1583 pr_err("instruction error\n");
1584 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1585 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1586 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1587 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1588 u32 ipeir = I915_READ(IPEIR);
1589
a70491cc
JP		 1590 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1591 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1592 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1593 I915_WRITE(IPEIR, ipeir);
3143a2bf 1594 POSTING_READ(IPEIR);
8a905236
JB		 1595 } else {
1596 u32 ipeir = I915_READ(IPEIR_I965);
1597
a70491cc
JP		 1598 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1599 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1600 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1601 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1602 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1603 POSTING_READ(IPEIR_I965);
8a905236
JB		 1604 }
1605 }
1606
1607 I915_WRITE(EIR, eir);
3143a2bf 1608 POSTING_READ(EIR);
8a905236
JB		 1609 eir = I915_READ(EIR);
1610 if (eir) {
1611 /*
1612 * some errors might have become stuck,
1613 * mask them.
1614 */
1615 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1616 I915_WRITE(EMR, I915_READ(EMR) | eir);
1617 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1618 }
35aed2e6
CW		 1619}
1620
1621/**
1622 * i915_handle_error - handle an error interrupt
1623 * @dev: drm device
1624 *
1625 * Do some basic checking of regsiter state at error interrupt time and
1626 * dump it to the syslog. Also call i915_capture_error_state() to make
1627 * sure we get a record and make it available in debugfs. Fire a uevent
1628 * so userspace knows something bad happened (should trigger collection
1629 * of a ring dump etc.).
1630 */
527f9e90 1631void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1632{
1633 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1634 struct intel_ring_buffer *ring;
1635 int i;
35aed2e6
CW		 1636
1637 i915_capture_error_state(dev);
1638 i915_report_and_clear_eir(dev);
8a905236 1639
ba1234d1 1640 if (wedged) {
f69061be
DV		 1641 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1642 &dev_priv->gpu_error.reset_counter);
ba1234d1 1643
11ed50ec 1644 /*
1f83fee0
DV		 1645 * Wakeup waiting processes so that the reset work item
1646 * doesn't deadlock trying to grab various locks.
11ed50ec 1647 */
b4519513
CW		 1648 for_each_ring(ring, dev_priv, i)
1649 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1650 }
1651
99584db3 1652 queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
8a905236
JB		 1653}
1654
21ad8330 1655static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
4e5359cd
SF		 1656{
1657 drm_i915_private_t *dev_priv = dev->dev_private;
1658 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1660 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1661 struct intel_unpin_work *work;
1662 unsigned long flags;
1663 bool stall_detected;
1664
1665 /* Ignore early vblank irqs */
1666 if (intel_crtc == NULL)
1667 return;
1668
1669 spin_lock_irqsave(&dev->event_lock, flags);
1670 work = intel_crtc->unpin_work;
1671
e7d841ca
CW		 1672 if (work == NULL ||
1673 atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1674 !work->enable_stall_check) {
4e5359cd
SF		 1675 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1676 spin_unlock_irqrestore(&dev->event_lock, flags);
1677 return;
1678 }
1679
1680 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1681 obj = work->pending_flip_obj;
a6c45cf0 1682 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1683 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1684 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1685 obj->gtt_offset;
4e5359cd 1686 } else {
9db4a9c7 1687 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1688 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1689 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1690 crtc->x * crtc->fb->bits_per_pixel/8);
1691 }
1692
1693 spin_unlock_irqrestore(&dev->event_lock, flags);
1694
1695 if (stall_detected) {
1696 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1697 intel_prepare_page_flip(dev, intel_crtc->plane);
1698 }
1699}
1700
42f52ef8
KP		 1701/* Called from drm generic code, passed 'crtc' which
1702 * we use as a pipe index
1703 */
f71d4af4 1704static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1705{
1706 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1707 unsigned long irqflags;
71e0ffa5 1708
5eddb70b 1709 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1710 return -EINVAL;
0a3e67a4 1711
1ec14ad3 1712 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1713 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1714 i915_enable_pipestat(dev_priv, pipe,
1715 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1716 else
7c463586
KP		 1717 i915_enable_pipestat(dev_priv, pipe,
1718 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1719
1720 /* maintain vblank delivery even in deep C-states */
1721 if (dev_priv->info->gen == 3)
6b26c86d 1722 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1723 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1724
0a3e67a4
JB		 1725 return 0;
1726}
1727
f71d4af4 1728static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1729{
1730 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1731 unsigned long irqflags;
1732
1733 if (!i915_pipe_enabled(dev, pipe))
1734 return -EINVAL;
1735
1736 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1737 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1738 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1739 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1740
1741 return 0;
1742}
1743
f71d4af4 1744static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1745{
1746 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1747 unsigned long irqflags;
1748
1749 if (!i915_pipe_enabled(dev, pipe))
1750 return -EINVAL;
1751
1752 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1753 ironlake_enable_display_irq(dev_priv,
1754 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1755 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1756
1757 return 0;
1758}
1759
7e231dbe
JB		 1760static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1761{
1762 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1763 unsigned long irqflags;
31acc7f5 1764 u32 imr;
7e231dbe
JB		 1765
1766 if (!i915_pipe_enabled(dev, pipe))
1767 return -EINVAL;
1768
1769 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1770 imr = I915_READ(VLV_IMR);
31acc7f5 1771 if (pipe == 0)
7e231dbe 1772 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1773 else
7e231dbe 1774 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1775 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1776 i915_enable_pipestat(dev_priv, pipe,
1777 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1778 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1779
1780 return 0;
1781}
1782
42f52ef8
KP		 1783/* Called from drm generic code, passed 'crtc' which
1784 * we use as a pipe index
1785 */
f71d4af4 1786static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1787{
1788 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1789 unsigned long irqflags;
0a3e67a4 1790
1ec14ad3 1791 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1792 if (dev_priv->info->gen == 3)
6b26c86d 1793 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1794
f796cf8f
JB		 1795 i915_disable_pipestat(dev_priv, pipe,
1796 PIPE_VBLANK_INTERRUPT_ENABLE |
1797 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1798 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1799}
1800
f71d4af4 1801static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1802{
1803 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1804 unsigned long irqflags;
1805
1806 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1807 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1808 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1809 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1810}
1811
f71d4af4 1812static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1813{
1814 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1815 unsigned long irqflags;
1816
1817 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1818 ironlake_disable_display_irq(dev_priv,
1819 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1820 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1821}
1822
7e231dbe
JB		 1823static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1824{
1825 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1826 unsigned long irqflags;
31acc7f5 1827 u32 imr;
7e231dbe
JB		 1828
1829 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1830 i915_disable_pipestat(dev_priv, pipe,
1831 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1832 imr = I915_READ(VLV_IMR);
31acc7f5 1833 if (pipe == 0)
7e231dbe 1834 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1835 else
7e231dbe 1836 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1837 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1838 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1839}
1840
893eead0
CW		 1841static u32
1842ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1843{
893eead0
CW		 1844 return list_entry(ring->request_list.prev,
1845 struct drm_i915_gem_request, list)->seqno;
1846}
1847
1848static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1849{
1850 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1851 i915_seqno_passed(ring->get_seqno(ring, false),
1852 ring_last_seqno(ring))) {
893eead0 1853 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1854 if (waitqueue_active(&ring->irq_queue)) {
1855 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1856 ring->name);
893eead0
CW		 1857 wake_up_all(&ring->irq_queue);
1858 *err = true;
1859 }
1860 return true;
1861 }
1862 return false;
f65d9421
BG		 1863}
1864
a24a11e6
CW		 1865static bool semaphore_passed(struct intel_ring_buffer *ring)
1866{
1867 struct drm_i915_private *dev_priv = ring->dev->dev_private;
1868 u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1869 struct intel_ring_buffer *signaller;
1870 u32 cmd, ipehr, acthd_min;
1871
1872 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1873 if ((ipehr & ~(0x3 << 16)) !=
1874 (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1875 return false;
1876
1877 /* ACTHD is likely pointing to the dword after the actual command,
1878 * so scan backwards until we find the MBOX.
1879 */
1880 acthd_min = max((int)acthd - 3 * 4, 0);
1881 do {
1882 cmd = ioread32(ring->virtual_start + acthd);
1883 if (cmd == ipehr)
1884 break;
1885
1886 acthd -= 4;
1887 if (acthd < acthd_min)
1888 return false;
1889 } while (1);
1890
1891 signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1892 return i915_seqno_passed(signaller->get_seqno(signaller, false),
1893 ioread32(ring->virtual_start+acthd+4)+1);
1894}
1895
1ec14ad3
CW		 1896static bool kick_ring(struct intel_ring_buffer *ring)
1897{
1898 struct drm_device *dev = ring->dev;
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 u32 tmp = I915_READ_CTL(ring);
1901 if (tmp & RING_WAIT) {
1902 DRM_ERROR("Kicking stuck wait on %s\n",
1903 ring->name);
1904 I915_WRITE_CTL(ring, tmp);
1905 return true;
1906 }
a24a11e6
CW		 1907
1908 if (INTEL_INFO(dev)->gen >= 6 &&
1909 tmp & RING_WAIT_SEMAPHORE &&
1910 semaphore_passed(ring)) {
1911 DRM_ERROR("Kicking stuck semaphore on %s\n",
1912 ring->name);
1913 I915_WRITE_CTL(ring, tmp);
1914 return true;
1915 }
1ec14ad3
CW		 1916 return false;
1917}
1918
d1e61e7f
CW		 1919static bool i915_hangcheck_hung(struct drm_device *dev)
1920{
1921 drm_i915_private_t *dev_priv = dev->dev_private;
1922
99584db3 1923 if (dev_priv->gpu_error.hangcheck_count++ > 1) {
b4519513
CW		 1924 bool hung = true;
1925
d1e61e7f
CW		 1926 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1927 i915_handle_error(dev, true);
1928
1929 if (!IS_GEN2(dev)) {
b4519513
CW		 1930 struct intel_ring_buffer *ring;
1931 int i;
1932
d1e61e7f
CW		 1933 /* Is the chip hanging on a WAIT_FOR_EVENT?
1934 * If so we can simply poke the RB_WAIT bit
1935 * and break the hang. This should work on
1936 * all but the second generation chipsets.
1937 */
b4519513
CW		 1938 for_each_ring(ring, dev_priv, i)
1939 hung &= !kick_ring(ring);
d1e61e7f
CW		 1940 }
1941
b4519513 1942 return hung;
d1e61e7f
CW		 1943 }
1944
1945 return false;
1946}
1947
f65d9421
BG		 1948/**
1949 * This is called when the chip hasn't reported back with completed
1950 * batchbuffers in a long time. The first time this is called we simply record
1951 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1952 * again, we assume the chip is wedged and try to fix it.
1953 */
1954void i915_hangcheck_elapsed(unsigned long data)
1955{
1956 struct drm_device *dev = (struct drm_device *)data;
1957 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1958 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1959 struct intel_ring_buffer *ring;
1960 bool err = false, idle;
1961 int i;
893eead0 1962
3e0dc6b0
BW		 1963 if (!i915_enable_hangcheck)
1964 return;
1965
b4519513
CW		 1966 memset(acthd, 0, sizeof(acthd));
1967 idle = true;
1968 for_each_ring(ring, dev_priv, i) {
1969 idle &= i915_hangcheck_ring_idle(ring, &err);
1970 acthd[i] = intel_ring_get_active_head(ring);
1971 }
1972
893eead0 1973 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1974 if (idle) {
d1e61e7f
CW		 1975 if (err) {
1976 if (i915_hangcheck_hung(dev))
1977 return;
1978
893eead0 1979 goto repeat;
d1e61e7f
CW		 1980 }
1981
99584db3 1982 dev_priv->gpu_error.hangcheck_count = 0;
893eead0
CW		 1983 return;
1984 }
b9201c14 1985
bd9854f9 1986 i915_get_extra_instdone(dev, instdone);
99584db3
DV		 1987 if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1988 sizeof(acthd)) == 0 &&
1989 memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1990 sizeof(instdone)) == 0) {
d1e61e7f 1991 if (i915_hangcheck_hung(dev))
cbb465e7 1992 return;
cbb465e7 1993 } else {
99584db3 1994 dev_priv->gpu_error.hangcheck_count = 0;
cbb465e7 1995
99584db3
DV		 1996 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1997 sizeof(acthd));
1998 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1999 sizeof(instdone));
cbb465e7 2000 }
f65d9421 2001
893eead0 2002repeat:
f65d9421 2003 /* Reset timer case chip hangs without another request being added */
99584db3 2004 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
cecc21fe 2005 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 2006}
2007
1da177e4
LT		 2008/* drm_dma.h hooks
2009*/
f71d4af4 2010static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 2011{
2012 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2013
4697995b
JB		 2014 atomic_set(&dev_priv->irq_received, 0);
2015
036a4a7d 2016 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 2017
036a4a7d
ZW		 2018 /* XXX hotplug from PCH */
2019
2020 I915_WRITE(DEIMR, 0xffffffff);
2021 I915_WRITE(DEIER, 0x0);
3143a2bf 2022 POSTING_READ(DEIER);
036a4a7d
ZW		 2023
2024 /* and GT */
2025 I915_WRITE(GTIMR, 0xffffffff);
2026 I915_WRITE(GTIER, 0x0);
3143a2bf 2027 POSTING_READ(GTIER);
c650156a
ZW		 2028
2029 /* south display irq */
2030 I915_WRITE(SDEIMR, 0xffffffff);
82a28bcf
DV		 2031 /*
2032 * SDEIER is also touched by the interrupt handler to work around missed
2033 * PCH interrupts. Hence we can't update it after the interrupt handler
2034 * is enabled - instead we unconditionally enable all PCH interrupt
2035 * sources here, but then only unmask them as needed with SDEIMR.
2036 */
2037 I915_WRITE(SDEIER, 0xffffffff);
3143a2bf 2038 POSTING_READ(SDEIER);
036a4a7d
ZW		 2039}
2040
7e231dbe
JB		 2041static void valleyview_irq_preinstall(struct drm_device *dev)
2042{
2043 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2044 int pipe;
2045
2046 atomic_set(&dev_priv->irq_received, 0);
2047
7e231dbe
JB		 2048 /* VLV magic */
2049 I915_WRITE(VLV_IMR, 0);
2050 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2051 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2052 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2053
7e231dbe
JB		 2054 /* and GT */
2055 I915_WRITE(GTIIR, I915_READ(GTIIR));
2056 I915_WRITE(GTIIR, I915_READ(GTIIR));
2057 I915_WRITE(GTIMR, 0xffffffff);
2058 I915_WRITE(GTIER, 0x0);
2059 POSTING_READ(GTIER);
2060
2061 I915_WRITE(DPINVGTT, 0xff);
2062
2063 I915_WRITE(PORT_HOTPLUG_EN, 0);
2064 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2065 for_each_pipe(pipe)
2066 I915_WRITE(PIPESTAT(pipe), 0xffff);
2067 I915_WRITE(VLV_IIR, 0xffffffff);
2068 I915_WRITE(VLV_IMR, 0xffffffff);
2069 I915_WRITE(VLV_IER, 0x0);
2070 POSTING_READ(VLV_IER);
2071}
2072
82a28bcf 2073static void ibx_hpd_irq_setup(struct drm_device *dev)
7fe0b973
KP		 2074{
2075 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf
DV		 2076 struct drm_mode_config *mode_config = &dev->mode_config;
2077 struct intel_encoder *intel_encoder;
2078 u32 mask = ~I915_READ(SDEIMR);
2079 u32 hotplug;
2080
2081 if (HAS_PCH_IBX(dev)) {
2082 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2083 mask |= hpd_ibx[intel_encoder->hpd_pin];
2084 } else {
2085 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2086 mask |= hpd_cpt[intel_encoder->hpd_pin];
2087 }
7fe0b973 2088
82a28bcf
DV		 2089 I915_WRITE(SDEIMR, ~mask);
2090
2091 /*
2092 * Enable digital hotplug on the PCH, and configure the DP short pulse
2093 * duration to 2ms (which is the minimum in the Display Port spec)
2094 *
2095 * This register is the same on all known PCH chips.
2096 */
7fe0b973
KP		 2097 hotplug = I915_READ(PCH_PORT_HOTPLUG);
2098 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2099 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2100 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2101 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2102 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2103}
2104
d46da437
PZ		 2105static void ibx_irq_postinstall(struct drm_device *dev)
2106{
2107 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
82a28bcf 2108 u32 mask;
e5868a31 2109
82a28bcf
DV		 2110 if (HAS_PCH_IBX(dev))
2111 mask = SDE_GMBUS | SDE_AUX_MASK;
2112 else
2113 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
d46da437
PZ		 2114 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2115 I915_WRITE(SDEIMR, ~mask);
d46da437
PZ		 2116}
2117
f71d4af4 2118static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 2119{
2120 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2121 /* enable kind of interrupts always enabled */
013d5aa2 2122 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
ce99c256
DV		 2123 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2124 DE_AUX_CHANNEL_A;
1ec14ad3 2125 u32 render_irqs;
036a4a7d 2126
1ec14ad3 2127 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 2128
2129 /* should always can generate irq */
2130 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 2131 I915_WRITE(DEIMR, dev_priv->irq_mask);
2132 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 2133 POSTING_READ(DEIER);
036a4a7d 2134
1ec14ad3 2135 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 2136
2137 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 2138 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 2139
1ec14ad3
CW		 2140 if (IS_GEN6(dev))
2141 render_irqs =
2142 GT_USER_INTERRUPT |
e2a1e2f0
BW		 2143 GEN6_BSD_USER_INTERRUPT |
2144 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 2145 else
2146 render_irqs =
88f23b8f 2147 GT_USER_INTERRUPT |
c6df541c 2148 GT_PIPE_NOTIFY |
1ec14ad3
CW		 2149 GT_BSD_USER_INTERRUPT;
2150 I915_WRITE(GTIER, render_irqs);
3143a2bf 2151 POSTING_READ(GTIER);
036a4a7d 2152
d46da437 2153 ibx_irq_postinstall(dev);
7fe0b973 2154
f97108d1
JB		 2155 if (IS_IRONLAKE_M(dev)) {
2156 /* Clear & enable PCU event interrupts */
2157 I915_WRITE(DEIIR, DE_PCU_EVENT);
2158 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2159 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2160 }
2161
036a4a7d
ZW		 2162 return 0;
2163}
2164
f71d4af4 2165static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2166{
2167 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2168 /* enable kind of interrupts always enabled */
b615b57a
CW		 2169 u32 display_mask =
2170 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2171 DE_PLANEC_FLIP_DONE_IVB |
2172 DE_PLANEB_FLIP_DONE_IVB |
ce99c256
DV		 2173 DE_PLANEA_FLIP_DONE_IVB |
2174 DE_AUX_CHANNEL_A_IVB;
b1f14ad0 2175 u32 render_irqs;
b1f14ad0 2176
b1f14ad0
JB		 2177 dev_priv->irq_mask = ~display_mask;
2178
2179 /* should always can generate irq */
2180 I915_WRITE(DEIIR, I915_READ(DEIIR));
2181 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 2182 I915_WRITE(DEIER,
2183 display_mask |
2184 DE_PIPEC_VBLANK_IVB |
2185 DE_PIPEB_VBLANK_IVB |
2186 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 2187 POSTING_READ(DEIER);
2188
15b9f80e 2189 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2190
2191 I915_WRITE(GTIIR, I915_READ(GTIIR));
2192 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2193
e2a1e2f0 2194 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 2195 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 2196 I915_WRITE(GTIER, render_irqs);
2197 POSTING_READ(GTIER);
2198
d46da437 2199 ibx_irq_postinstall(dev);
7fe0b973 2200
b1f14ad0
JB		 2201 return 0;
2202}
2203
7e231dbe
JB		 2204static int valleyview_irq_postinstall(struct drm_device *dev)
2205{
2206 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe 2207 u32 enable_mask;
31acc7f5 2208 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 2209 u32 render_irqs;
7e231dbe
JB		 2210 u16 msid;
2211
2212 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 2213 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2214 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2215 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 2216 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2217
31acc7f5
JB		 2218 /*
2219 *Leave vblank interrupts masked initially. enable/disable will
2220 * toggle them based on usage.
2221 */
2222 dev_priv->irq_mask = (~enable_mask) |
2223 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2224 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 2225
7e231dbe
JB		 2226 /* Hack for broken MSIs on VLV */
2227 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2228 pci_read_config_word(dev->pdev, 0x98, &msid);
2229 msid &= 0xff; /* mask out delivery bits */
2230 msid |= (1<<14);
2231 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2232
20afbda2
DV		 2233 I915_WRITE(PORT_HOTPLUG_EN, 0);
2234 POSTING_READ(PORT_HOTPLUG_EN);
2235
7e231dbe
JB		 2236 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2237 I915_WRITE(VLV_IER, enable_mask);
2238 I915_WRITE(VLV_IIR, 0xffffffff);
2239 I915_WRITE(PIPESTAT(0), 0xffff);
2240 I915_WRITE(PIPESTAT(1), 0xffff);
2241 POSTING_READ(VLV_IER);
2242
31acc7f5 2243 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
515ac2bb 2244 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
31acc7f5
JB		 2245 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2246
7e231dbe
JB		 2247 I915_WRITE(VLV_IIR, 0xffffffff);
2248 I915_WRITE(VLV_IIR, 0xffffffff);
2249
7e231dbe 2250 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 2251 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 2252
2253 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2254 GEN6_BLITTER_USER_INTERRUPT;
2255 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2256 POSTING_READ(GTIER);
2257
2258 /* ack & enable invalid PTE error interrupts */
2259#if 0 /* FIXME: add support to irq handler for checking these bits */
2260 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2261 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2262#endif
2263
2264 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
20afbda2
DV		 2265
2266 return 0;
2267}
2268
7e231dbe
JB		 2269static void valleyview_irq_uninstall(struct drm_device *dev)
2270{
2271 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2272 int pipe;
2273
2274 if (!dev_priv)
2275 return;
2276
7e231dbe
JB		 2277 for_each_pipe(pipe)
2278 I915_WRITE(PIPESTAT(pipe), 0xffff);
2279
2280 I915_WRITE(HWSTAM, 0xffffffff);
2281 I915_WRITE(PORT_HOTPLUG_EN, 0);
2282 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2283 for_each_pipe(pipe)
2284 I915_WRITE(PIPESTAT(pipe), 0xffff);
2285 I915_WRITE(VLV_IIR, 0xffffffff);
2286 I915_WRITE(VLV_IMR, 0xffffffff);
2287 I915_WRITE(VLV_IER, 0x0);
2288 POSTING_READ(VLV_IER);
2289}
2290
f71d4af4 2291static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2292{
2293 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2294
2295 if (!dev_priv)
2296 return;
2297
036a4a7d
ZW		 2298 I915_WRITE(HWSTAM, 0xffffffff);
2299
2300 I915_WRITE(DEIMR, 0xffffffff);
2301 I915_WRITE(DEIER, 0x0);
2302 I915_WRITE(DEIIR, I915_READ(DEIIR));
2303
2304 I915_WRITE(GTIMR, 0xffffffff);
2305 I915_WRITE(GTIER, 0x0);
2306 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2307
2308 I915_WRITE(SDEIMR, 0xffffffff);
2309 I915_WRITE(SDEIER, 0x0);
2310 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2311}
2312
a266c7d5 2313static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2314{
2315 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2316 int pipe;
91e3738e 2317
a266c7d5 2318 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2319
9db4a9c7
JB		 2320 for_each_pipe(pipe)
2321 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2322 I915_WRITE16(IMR, 0xffff);
2323 I915_WRITE16(IER, 0x0);
2324 POSTING_READ16(IER);
c2798b19
CW		 2325}
2326
2327static int i8xx_irq_postinstall(struct drm_device *dev)
2328{
2329 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2330
c2798b19
CW		 2331 I915_WRITE16(EMR,
2332 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2333
2334 /* Unmask the interrupts that we always want on. */
2335 dev_priv->irq_mask =
2336 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2337 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2338 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2339 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2340 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2341 I915_WRITE16(IMR, dev_priv->irq_mask);
2342
2343 I915_WRITE16(IER,
2344 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2345 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2346 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2347 I915_USER_INTERRUPT);
2348 POSTING_READ16(IER);
2349
2350 return 0;
2351}
2352
90a72f87
VS		 2353/*
2354 * Returns true when a page flip has completed.
2355 */
2356static bool i8xx_handle_vblank(struct drm_device *dev,
2357 int pipe, u16 iir)
2358{
2359 drm_i915_private_t *dev_priv = dev->dev_private;
2360 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2361
2362 if (!drm_handle_vblank(dev, pipe))
2363 return false;
2364
2365 if ((iir & flip_pending) == 0)
2366 return false;
2367
2368 intel_prepare_page_flip(dev, pipe);
2369
2370 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2371 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2372 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2373 * the flip is completed (no longer pending). Since this doesn't raise
2374 * an interrupt per se, we watch for the change at vblank.
2375 */
2376 if (I915_READ16(ISR) & flip_pending)
2377 return false;
2378
2379 intel_finish_page_flip(dev, pipe);
2380
2381 return true;
2382}
2383
ff1f525e 2384static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2385{
2386 struct drm_device *dev = (struct drm_device *) arg;
2387 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2388 u16 iir, new_iir;
2389 u32 pipe_stats[2];
2390 unsigned long irqflags;
2391 int irq_received;
2392 int pipe;
2393 u16 flip_mask =
2394 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2395 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2396
2397 atomic_inc(&dev_priv->irq_received);
2398
2399 iir = I915_READ16(IIR);
2400 if (iir == 0)
2401 return IRQ_NONE;
2402
2403 while (iir & ~flip_mask) {
2404 /* Can't rely on pipestat interrupt bit in iir as it might
2405 * have been cleared after the pipestat interrupt was received.
2406 * It doesn't set the bit in iir again, but it still produces
2407 * interrupts (for non-MSI).
2408 */
2409 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2410 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2411 i915_handle_error(dev, false);
2412
2413 for_each_pipe(pipe) {
2414 int reg = PIPESTAT(pipe);
2415 pipe_stats[pipe] = I915_READ(reg);
2416
2417 /*
2418 * Clear the PIPE*STAT regs before the IIR
2419 */
2420 if (pipe_stats[pipe] & 0x8000ffff) {
2421 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2422 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2423 pipe_name(pipe));
2424 I915_WRITE(reg, pipe_stats[pipe]);
2425 irq_received = 1;
2426 }
2427 }
2428 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2429
2430 I915_WRITE16(IIR, iir & ~flip_mask);
2431 new_iir = I915_READ16(IIR); /* Flush posted writes */
2432
d05c617e 2433 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2434
2435 if (iir & I915_USER_INTERRUPT)
2436 notify_ring(dev, &dev_priv->ring[RCS]);
2437
2438 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2439 i8xx_handle_vblank(dev, 0, iir))
2440 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
c2798b19
CW		 2441
2442 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2443 i8xx_handle_vblank(dev, 1, iir))
2444 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
c2798b19
CW		 2445
2446 iir = new_iir;
2447 }
2448
2449 return IRQ_HANDLED;
2450}
2451
2452static void i8xx_irq_uninstall(struct drm_device * dev)
2453{
2454 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2455 int pipe;
2456
c2798b19
CW		 2457 for_each_pipe(pipe) {
2458 /* Clear enable bits; then clear status bits */
2459 I915_WRITE(PIPESTAT(pipe), 0);
2460 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2461 }
2462 I915_WRITE16(IMR, 0xffff);
2463 I915_WRITE16(IER, 0x0);
2464 I915_WRITE16(IIR, I915_READ16(IIR));
2465}
2466
a266c7d5
CW		 2467static void i915_irq_preinstall(struct drm_device * dev)
2468{
2469 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2470 int pipe;
2471
2472 atomic_set(&dev_priv->irq_received, 0);
2473
2474 if (I915_HAS_HOTPLUG(dev)) {
2475 I915_WRITE(PORT_HOTPLUG_EN, 0);
2476 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2477 }
2478
00d98ebd 2479 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2480 for_each_pipe(pipe)
2481 I915_WRITE(PIPESTAT(pipe), 0);
2482 I915_WRITE(IMR, 0xffffffff);
2483 I915_WRITE(IER, 0x0);
2484 POSTING_READ(IER);
2485}
2486
2487static int i915_irq_postinstall(struct drm_device *dev)
2488{
2489 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2490 u32 enable_mask;
a266c7d5 2491
38bde180
CW		 2492 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2493
2494 /* Unmask the interrupts that we always want on. */
2495 dev_priv->irq_mask =
2496 ~(I915_ASLE_INTERRUPT |
2497 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2498 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2499 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2500 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2501 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2502
2503 enable_mask =
2504 I915_ASLE_INTERRUPT |
2505 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2506 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2507 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2508 I915_USER_INTERRUPT;
2509
a266c7d5 2510 if (I915_HAS_HOTPLUG(dev)) {
20afbda2
DV		 2511 I915_WRITE(PORT_HOTPLUG_EN, 0);
2512 POSTING_READ(PORT_HOTPLUG_EN);
2513
a266c7d5
CW		 2514 /* Enable in IER... */
2515 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2516 /* and unmask in IMR */
2517 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2518 }
2519
a266c7d5
CW		 2520 I915_WRITE(IMR, dev_priv->irq_mask);
2521 I915_WRITE(IER, enable_mask);
2522 POSTING_READ(IER);
2523
20afbda2
DV		 2524 intel_opregion_enable_asle(dev);
2525
2526 return 0;
2527}
2528
2529static void i915_hpd_irq_setup(struct drm_device *dev)
2530{
a266c7d5 2531 if (I915_HAS_HOTPLUG(dev)) {
e5868a31
EE		 2532 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2533 struct drm_mode_config *mode_config = &dev->mode_config;
2534 struct intel_encoder *encoder;
2535 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2536
2537 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2538 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
2539 hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
2540 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5
CW		 2541
2542 /* Ignore TV since it's buggy */
2543
2544 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2545 }
a266c7d5
CW		 2546}
2547
90a72f87
VS		 2548/*
2549 * Returns true when a page flip has completed.
2550 */
2551static bool i915_handle_vblank(struct drm_device *dev,
2552 int plane, int pipe, u32 iir)
2553{
2554 drm_i915_private_t *dev_priv = dev->dev_private;
2555 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2556
2557 if (!drm_handle_vblank(dev, pipe))
2558 return false;
2559
2560 if ((iir & flip_pending) == 0)
2561 return false;
2562
2563 intel_prepare_page_flip(dev, plane);
2564
2565 /* We detect FlipDone by looking for the change in PendingFlip from '1'
2566 * to '0' on the following vblank, i.e. IIR has the Pendingflip
2567 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2568 * the flip is completed (no longer pending). Since this doesn't raise
2569 * an interrupt per se, we watch for the change at vblank.
2570 */
2571 if (I915_READ(ISR) & flip_pending)
2572 return false;
2573
2574 intel_finish_page_flip(dev, pipe);
2575
2576 return true;
2577}
2578
ff1f525e 2579static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2580{
2581 struct drm_device *dev = (struct drm_device *) arg;
2582 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2583 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2584 unsigned long irqflags;
38bde180
CW		 2585 u32 flip_mask =
2586 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2587 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
38bde180 2588 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2589
2590 atomic_inc(&dev_priv->irq_received);
2591
2592 iir = I915_READ(IIR);
38bde180
CW		 2593 do {
2594 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2595 bool blc_event = false;
a266c7d5
CW		 2596
2597 /* Can't rely on pipestat interrupt bit in iir as it might
2598 * have been cleared after the pipestat interrupt was received.
2599 * It doesn't set the bit in iir again, but it still produces
2600 * interrupts (for non-MSI).
2601 */
2602 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2603 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2604 i915_handle_error(dev, false);
2605
2606 for_each_pipe(pipe) {
2607 int reg = PIPESTAT(pipe);
2608 pipe_stats[pipe] = I915_READ(reg);
2609
38bde180 2610 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2611 if (pipe_stats[pipe] & 0x8000ffff) {
2612 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2613 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2614 pipe_name(pipe));
2615 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2616 irq_received = true;
a266c7d5
CW		 2617 }
2618 }
2619 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2620
2621 if (!irq_received)
2622 break;
2623
a266c7d5
CW		 2624 /* Consume port. Then clear IIR or we'll miss events */
2625 if ((I915_HAS_HOTPLUG(dev)) &&
2626 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2627 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2628
2629 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2630 hotplug_status);
e5868a31 2631 if (hotplug_status & HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2632 queue_work(dev_priv->wq,
2633 &dev_priv->hotplug_work);
2634
2635 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2636 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2637 }
2638
38bde180 2639 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2640 new_iir = I915_READ(IIR); /* Flush posted writes */
2641
a266c7d5
CW		 2642 if (iir & I915_USER_INTERRUPT)
2643 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2644
a266c7d5 2645 for_each_pipe(pipe) {
38bde180
CW		 2646 int plane = pipe;
2647 if (IS_MOBILE(dev))
2648 plane = !plane;
90a72f87 2649
8291ee90 2650 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2651 i915_handle_vblank(dev, plane, pipe, iir))
2652 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
a266c7d5
CW		 2653
2654 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2655 blc_event = true;
2656 }
2657
a266c7d5
CW		 2658 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2659 intel_opregion_asle_intr(dev);
2660
2661 /* With MSI, interrupts are only generated when iir
2662 * transitions from zero to nonzero. If another bit got
2663 * set while we were handling the existing iir bits, then
2664 * we would never get another interrupt.
2665 *
2666 * This is fine on non-MSI as well, as if we hit this path
2667 * we avoid exiting the interrupt handler only to generate
2668 * another one.
2669 *
2670 * Note that for MSI this could cause a stray interrupt report
2671 * if an interrupt landed in the time between writing IIR and
2672 * the posting read. This should be rare enough to never
2673 * trigger the 99% of 100,000 interrupts test for disabling
2674 * stray interrupts.
2675 */
38bde180 2676 ret = IRQ_HANDLED;
a266c7d5 2677 iir = new_iir;
38bde180 2678 } while (iir & ~flip_mask);
a266c7d5 2679
d05c617e 2680 i915_update_dri1_breadcrumb(dev);
8291ee90 2681
a266c7d5
CW		 2682 return ret;
2683}
2684
2685static void i915_irq_uninstall(struct drm_device * dev)
2686{
2687 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2688 int pipe;
2689
a266c7d5
CW		 2690 if (I915_HAS_HOTPLUG(dev)) {
2691 I915_WRITE(PORT_HOTPLUG_EN, 0);
2692 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2693 }
2694
00d98ebd 2695 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2696 for_each_pipe(pipe) {
2697 /* Clear enable bits; then clear status bits */
a266c7d5 2698 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2699 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2700 }
a266c7d5
CW		 2701 I915_WRITE(IMR, 0xffffffff);
2702 I915_WRITE(IER, 0x0);
2703
a266c7d5
CW		 2704 I915_WRITE(IIR, I915_READ(IIR));
2705}
2706
2707static void i965_irq_preinstall(struct drm_device * dev)
2708{
2709 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2710 int pipe;
2711
2712 atomic_set(&dev_priv->irq_received, 0);
2713
adca4730
CW		 2714 I915_WRITE(PORT_HOTPLUG_EN, 0);
2715 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2716
2717 I915_WRITE(HWSTAM, 0xeffe);
2718 for_each_pipe(pipe)
2719 I915_WRITE(PIPESTAT(pipe), 0);
2720 I915_WRITE(IMR, 0xffffffff);
2721 I915_WRITE(IER, 0x0);
2722 POSTING_READ(IER);
2723}
2724
2725static int i965_irq_postinstall(struct drm_device *dev)
2726{
2727 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2728 u32 enable_mask;
a266c7d5
CW		 2729 u32 error_mask;
2730
a266c7d5 2731 /* Unmask the interrupts that we always want on. */
bbba0a97 2732 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2733 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2734 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2735 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2736 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2737 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2738 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2739
2740 enable_mask = ~dev_priv->irq_mask;
21ad8330
VS		 2741 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2742 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
bbba0a97
CW		 2743 enable_mask |= I915_USER_INTERRUPT;
2744
2745 if (IS_G4X(dev))
2746 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5 2747
515ac2bb 2748 i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
a266c7d5 2749
a266c7d5
CW		 2750 /*
2751 * Enable some error detection, note the instruction error mask
2752 * bit is reserved, so we leave it masked.
2753 */
2754 if (IS_G4X(dev)) {
2755 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2756 GM45_ERROR_MEM_PRIV |
2757 GM45_ERROR_CP_PRIV |
2758 I915_ERROR_MEMORY_REFRESH);
2759 } else {
2760 error_mask = ~(I915_ERROR_PAGE_TABLE |
2761 I915_ERROR_MEMORY_REFRESH);
2762 }
2763 I915_WRITE(EMR, error_mask);
2764
2765 I915_WRITE(IMR, dev_priv->irq_mask);
2766 I915_WRITE(IER, enable_mask);
2767 POSTING_READ(IER);
2768
20afbda2
DV		 2769 I915_WRITE(PORT_HOTPLUG_EN, 0);
2770 POSTING_READ(PORT_HOTPLUG_EN);
2771
2772 intel_opregion_enable_asle(dev);
2773
2774 return 0;
2775}
2776
2777static void i965_hpd_irq_setup(struct drm_device *dev)
2778{
2779 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e5868a31
EE		 2780 struct drm_mode_config *mode_config = &dev->mode_config;
2781 struct intel_encoder *encoder;
20afbda2
DV		 2782 u32 hotplug_en;
2783
adca4730
CW		 2784 /* Note HDMI and DP share hotplug bits */
2785 hotplug_en = 0;
e5868a31
EE		 2786 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
2787 /* enable bits are the same for all generations */
2788 hotplug_en |= hpd_mask_i915[encoder->hpd_pin];
2789 /* Programming the CRT detection parameters tends
2790 to generate a spurious hotplug event about three
2791 seconds later. So just do it once.
2792 */
2793 if (IS_G4X(dev))
2794 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2795 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
a266c7d5 2796
adca4730 2797 /* Ignore TV since it's buggy */
a266c7d5 2798
adca4730 2799 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2800}
2801
ff1f525e 2802static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2803{
2804 struct drm_device *dev = (struct drm_device *) arg;
2805 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2806 u32 iir, new_iir;
2807 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2808 unsigned long irqflags;
2809 int irq_received;
2810 int ret = IRQ_NONE, pipe;
21ad8330
VS		 2811 u32 flip_mask =
2812 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2813 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
a266c7d5
CW		 2814
2815 atomic_inc(&dev_priv->irq_received);
2816
2817 iir = I915_READ(IIR);
2818
a266c7d5 2819 for (;;) {
2c8ba29f
CW		 2820 bool blc_event = false;
2821
21ad8330 2822 irq_received = (iir & ~flip_mask) != 0;
a266c7d5
CW		 2823
2824 /* Can't rely on pipestat interrupt bit in iir as it might
2825 * have been cleared after the pipestat interrupt was received.
2826 * It doesn't set the bit in iir again, but it still produces
2827 * interrupts (for non-MSI).
2828 */
2829 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2830 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2831 i915_handle_error(dev, false);
2832
2833 for_each_pipe(pipe) {
2834 int reg = PIPESTAT(pipe);
2835 pipe_stats[pipe] = I915_READ(reg);
2836
2837 /*
2838 * Clear the PIPE*STAT regs before the IIR
2839 */
2840 if (pipe_stats[pipe] & 0x8000ffff) {
2841 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2842 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2843 pipe_name(pipe));
2844 I915_WRITE(reg, pipe_stats[pipe]);
2845 irq_received = 1;
2846 }
2847 }
2848 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2849
2850 if (!irq_received)
2851 break;
2852
2853 ret = IRQ_HANDLED;
2854
2855 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2856 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2857 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2858
2859 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2860 hotplug_status);
e5868a31
EE		 2861 if (hotplug_status & (IS_G4X(dev) ?
2862 HOTPLUG_INT_STATUS_G4X :
2863 HOTPLUG_INT_STATUS_I965))
a266c7d5
CW		 2864 queue_work(dev_priv->wq,
2865 &dev_priv->hotplug_work);
2866
2867 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2868 I915_READ(PORT_HOTPLUG_STAT);
2869 }
2870
21ad8330 2871 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2872 new_iir = I915_READ(IIR); /* Flush posted writes */
2873
a266c7d5
CW		 2874 if (iir & I915_USER_INTERRUPT)
2875 notify_ring(dev, &dev_priv->ring[RCS]);
2876 if (iir & I915_BSD_USER_INTERRUPT)
2877 notify_ring(dev, &dev_priv->ring[VCS]);
2878
a266c7d5 2879 for_each_pipe(pipe) {
2c8ba29f 2880 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
90a72f87
VS		 2881 i915_handle_vblank(dev, pipe, pipe, iir))
2882 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
a266c7d5
CW		 2883
2884 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2885 blc_event = true;
2886 }
2887
2888
2889 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2890 intel_opregion_asle_intr(dev);
2891
515ac2bb
DV		 2892 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2893 gmbus_irq_handler(dev);
2894
a266c7d5
CW		 2895 /* With MSI, interrupts are only generated when iir
2896 * transitions from zero to nonzero. If another bit got
2897 * set while we were handling the existing iir bits, then
2898 * we would never get another interrupt.
2899 *
2900 * This is fine on non-MSI as well, as if we hit this path
2901 * we avoid exiting the interrupt handler only to generate
2902 * another one.
2903 *
2904 * Note that for MSI this could cause a stray interrupt report
2905 * if an interrupt landed in the time between writing IIR and
2906 * the posting read. This should be rare enough to never
2907 * trigger the 99% of 100,000 interrupts test for disabling
2908 * stray interrupts.
2909 */
2910 iir = new_iir;
2911 }
2912
d05c617e 2913 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2914
a266c7d5
CW		 2915 return ret;
2916}
2917
2918static void i965_irq_uninstall(struct drm_device * dev)
2919{
2920 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2921 int pipe;
2922
2923 if (!dev_priv)
2924 return;
2925
adca4730
CW		 2926 I915_WRITE(PORT_HOTPLUG_EN, 0);
2927 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2928
2929 I915_WRITE(HWSTAM, 0xffffffff);
2930 for_each_pipe(pipe)
2931 I915_WRITE(PIPESTAT(pipe), 0);
2932 I915_WRITE(IMR, 0xffffffff);
2933 I915_WRITE(IER, 0x0);
2934
2935 for_each_pipe(pipe)
2936 I915_WRITE(PIPESTAT(pipe),
2937 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2938 I915_WRITE(IIR, I915_READ(IIR));
2939}
2940
f71d4af4
JB		 2941void intel_irq_init(struct drm_device *dev)
2942{
8b2e326d
CW		 2943 struct drm_i915_private *dev_priv = dev->dev_private;
2944
2945 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
99584db3 2946 INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
c6a828d3 2947 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
a4da4fa4 2948 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
8b2e326d 2949
99584db3
DV		 2950 setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2951 i915_hangcheck_elapsed,
61bac78e
DV		 2952 (unsigned long) dev);
2953
97a19a24 2954 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
9ee32fea 2955
f71d4af4
JB		 2956 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2957 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2958 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2959 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2960 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2961 }
2962
c3613de9
KP		 2963 if (drm_core_check_feature(dev, DRIVER_MODESET))
2964 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2965 else
2966 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2967 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2968
7e231dbe
JB		 2969 if (IS_VALLEYVIEW(dev)) {
2970 dev->driver->irq_handler = valleyview_irq_handler;
2971 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2972 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2973 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2974 dev->driver->enable_vblank = valleyview_enable_vblank;
2975 dev->driver->disable_vblank = valleyview_disable_vblank;
fa00abe0 2976 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4a06e201 2977 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
f71d4af4
JB		 2978 /* Share pre & uninstall handlers with ILK/SNB */
2979 dev->driver->irq_handler = ivybridge_irq_handler;
2980 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2981 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2982 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2983 dev->driver->enable_vblank = ivybridge_enable_vblank;
2984 dev->driver->disable_vblank = ivybridge_disable_vblank;
82a28bcf 2985 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4
JB		 2986 } else if (HAS_PCH_SPLIT(dev)) {
2987 dev->driver->irq_handler = ironlake_irq_handler;
2988 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2989 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2990 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2991 dev->driver->enable_vblank = ironlake_enable_vblank;
2992 dev->driver->disable_vblank = ironlake_disable_vblank;
82a28bcf 2993 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
f71d4af4 2994 } else {
c2798b19
CW		 2995 if (INTEL_INFO(dev)->gen == 2) {
2996 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2997 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2998 dev->driver->irq_handler = i8xx_irq_handler;
2999 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 3000 } else if (INTEL_INFO(dev)->gen == 3) {
3001 dev->driver->irq_preinstall = i915_irq_preinstall;
3002 dev->driver->irq_postinstall = i915_irq_postinstall;
3003 dev->driver->irq_uninstall = i915_irq_uninstall;
3004 dev->driver->irq_handler = i915_irq_handler;
20afbda2 3005 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
c2798b19 3006 } else {
a266c7d5
CW		 3007 dev->driver->irq_preinstall = i965_irq_preinstall;
3008 dev->driver->irq_postinstall = i965_irq_postinstall;
3009 dev->driver->irq_uninstall = i965_irq_uninstall;
3010 dev->driver->irq_handler = i965_irq_handler;
20afbda2 3011 dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
c2798b19 3012 }
f71d4af4
JB		 3013 dev->driver->enable_vblank = i915_enable_vblank;
3014 dev->driver->disable_vblank = i915_disable_vblank;
3015 }
3016}
20afbda2
DV		 3017
3018void intel_hpd_init(struct drm_device *dev)
3019{
3020 struct drm_i915_private *dev_priv = dev->dev_private;
3021
3022 if (dev_priv->display.hpd_irq_setup)
3023 dev_priv->display.hpd_irq_setup(dev);
3024}
Linux kernel - Deliverables
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