Commit | Line | Data |
---|---|---|
0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | /* For display hotplug interrupt */ |
995b6762 | 68 | static void |
f2b115e6 | 69 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 70 | { |
1ec14ad3 CW |
71 | if ((dev_priv->irq_mask & mask) != 0) { |
72 | dev_priv->irq_mask &= ~mask; | |
73 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 74 | POSTING_READ(DEIMR); |
036a4a7d ZW |
75 | } |
76 | } | |
77 | ||
78 | static inline void | |
f2b115e6 | 79 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 80 | { |
1ec14ad3 CW |
81 | if ((dev_priv->irq_mask & mask) != mask) { |
82 | dev_priv->irq_mask |= mask; | |
83 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 84 | POSTING_READ(DEIMR); |
036a4a7d ZW |
85 | } |
86 | } | |
87 | ||
7c463586 KP |
88 | static inline u32 |
89 | i915_pipestat(int pipe) | |
90 | { | |
91 | if (pipe == 0) | |
92 | return PIPEASTAT; | |
93 | if (pipe == 1) | |
94 | return PIPEBSTAT; | |
9c84ba4e | 95 | BUG(); |
7c463586 KP |
96 | } |
97 | ||
98 | void | |
99 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
100 | { | |
101 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
102 | u32 reg = i915_pipestat(pipe); | |
103 | ||
104 | dev_priv->pipestat[pipe] |= mask; | |
105 | /* Enable the interrupt, clear any pending status */ | |
106 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 107 | POSTING_READ(reg); |
7c463586 KP |
108 | } |
109 | } | |
110 | ||
111 | void | |
112 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
113 | { | |
114 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
115 | u32 reg = i915_pipestat(pipe); | |
116 | ||
117 | dev_priv->pipestat[pipe] &= ~mask; | |
118 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 119 | POSTING_READ(reg); |
7c463586 KP |
120 | } |
121 | } | |
122 | ||
01c66889 ZY |
123 | /** |
124 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
125 | */ | |
1ec14ad3 | 126 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 127 | { |
1ec14ad3 CW |
128 | drm_i915_private_t *dev_priv = dev->dev_private; |
129 | unsigned long irqflags; | |
130 | ||
131 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
01c66889 | 132 | |
c619eed4 | 133 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 134 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 135 | else { |
01c66889 | 136 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 137 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 138 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 139 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 140 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 141 | } |
1ec14ad3 CW |
142 | |
143 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
144 | } |
145 | ||
0a3e67a4 JB |
146 | /** |
147 | * i915_pipe_enabled - check if a pipe is enabled | |
148 | * @dev: DRM device | |
149 | * @pipe: pipe to check | |
150 | * | |
151 | * Reading certain registers when the pipe is disabled can hang the chip. | |
152 | * Use this routine to make sure the PLL is running and the pipe is active | |
153 | * before reading such registers if unsure. | |
154 | */ | |
155 | static int | |
156 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
157 | { | |
158 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 159 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
160 | } |
161 | ||
42f52ef8 KP |
162 | /* Called from drm generic code, passed a 'crtc', which |
163 | * we use as a pipe index | |
164 | */ | |
165 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
166 | { |
167 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
168 | unsigned long high_frame; | |
169 | unsigned long low_frame; | |
5eddb70b | 170 | u32 high1, high2, low; |
0a3e67a4 JB |
171 | |
172 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
173 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
174 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
175 | return 0; |
176 | } | |
177 | ||
5eddb70b CW |
178 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
179 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
180 | ||
0a3e67a4 JB |
181 | /* |
182 | * High & low register fields aren't synchronized, so make sure | |
183 | * we get a low value that's stable across two reads of the high | |
184 | * register. | |
185 | */ | |
186 | do { | |
5eddb70b CW |
187 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
188 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
189 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
190 | } while (high1 != high2); |
191 | ||
5eddb70b CW |
192 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
193 | low >>= PIPE_FRAME_LOW_SHIFT; | |
194 | return (high1 << 8) | low; | |
0a3e67a4 JB |
195 | } |
196 | ||
9880b7a5 JB |
197 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
198 | { | |
199 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
200 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
201 | ||
202 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
203 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
204 | "pipe %d\n", pipe); | |
9880b7a5 JB |
205 | return 0; |
206 | } | |
207 | ||
208 | return I915_READ(reg); | |
209 | } | |
210 | ||
0af7e4df MK |
211 | int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
212 | int *vpos, int *hpos) | |
213 | { | |
214 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
215 | u32 vbl = 0, position = 0; | |
216 | int vbl_start, vbl_end, htotal, vtotal; | |
217 | bool in_vbl = true; | |
218 | int ret = 0; | |
219 | ||
220 | if (!i915_pipe_enabled(dev, pipe)) { | |
221 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
222 | "pipe %d\n", pipe); | |
223 | return 0; | |
224 | } | |
225 | ||
226 | /* Get vtotal. */ | |
227 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); | |
228 | ||
229 | if (INTEL_INFO(dev)->gen >= 4) { | |
230 | /* No obvious pixelcount register. Only query vertical | |
231 | * scanout position from Display scan line register. | |
232 | */ | |
233 | position = I915_READ(PIPEDSL(pipe)); | |
234 | ||
235 | /* Decode into vertical scanout position. Don't have | |
236 | * horizontal scanout position. | |
237 | */ | |
238 | *vpos = position & 0x1fff; | |
239 | *hpos = 0; | |
240 | } else { | |
241 | /* Have access to pixelcount since start of frame. | |
242 | * We can split this into vertical and horizontal | |
243 | * scanout position. | |
244 | */ | |
245 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
246 | ||
247 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); | |
248 | *vpos = position / htotal; | |
249 | *hpos = position - (*vpos * htotal); | |
250 | } | |
251 | ||
252 | /* Query vblank area. */ | |
253 | vbl = I915_READ(VBLANK(pipe)); | |
254 | ||
255 | /* Test position against vblank region. */ | |
256 | vbl_start = vbl & 0x1fff; | |
257 | vbl_end = (vbl >> 16) & 0x1fff; | |
258 | ||
259 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
260 | in_vbl = false; | |
261 | ||
262 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
263 | if (in_vbl && (*vpos >= vbl_start)) | |
264 | *vpos = *vpos - vtotal; | |
265 | ||
266 | /* Readouts valid? */ | |
267 | if (vbl > 0) | |
268 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
269 | ||
270 | /* In vblank? */ | |
271 | if (in_vbl) | |
272 | ret |= DRM_SCANOUTPOS_INVBL; | |
273 | ||
274 | return ret; | |
275 | } | |
276 | ||
4041b853 | 277 | int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
278 | int *max_error, |
279 | struct timeval *vblank_time, | |
280 | unsigned flags) | |
281 | { | |
4041b853 CW |
282 | struct drm_i915_private *dev_priv = dev->dev_private; |
283 | struct drm_crtc *crtc; | |
0af7e4df | 284 | |
4041b853 CW |
285 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
286 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
0af7e4df MK |
287 | return -EINVAL; |
288 | } | |
289 | ||
290 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
291 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
292 | if (crtc == NULL) { | |
293 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
294 | return -EINVAL; | |
295 | } | |
296 | ||
297 | if (!crtc->enabled) { | |
298 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
299 | return -EBUSY; | |
300 | } | |
0af7e4df MK |
301 | |
302 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
303 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
304 | vblank_time, flags, | |
305 | crtc); | |
0af7e4df MK |
306 | } |
307 | ||
5ca58282 JB |
308 | /* |
309 | * Handle hotplug events outside the interrupt handler proper. | |
310 | */ | |
311 | static void i915_hotplug_work_func(struct work_struct *work) | |
312 | { | |
313 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
314 | hotplug_work); | |
315 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 316 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
317 | struct intel_encoder *encoder; |
318 | ||
319 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
320 | if (encoder->hot_plug) | |
321 | encoder->hot_plug(encoder); | |
322 | ||
5ca58282 | 323 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 324 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
325 | } |
326 | ||
f97108d1 JB |
327 | static void i915_handle_rps_change(struct drm_device *dev) |
328 | { | |
329 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 330 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
331 | u8 new_delay = dev_priv->cur_delay; |
332 | ||
7648fa99 | 333 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
334 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
335 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
336 | max_avg = I915_READ(RCBMAXAVG); |
337 | min_avg = I915_READ(RCBMINAVG); | |
338 | ||
339 | /* Handle RCS change request from hw */ | |
b5b72e89 | 340 | if (busy_up > max_avg) { |
f97108d1 JB |
341 | if (dev_priv->cur_delay != dev_priv->max_delay) |
342 | new_delay = dev_priv->cur_delay - 1; | |
343 | if (new_delay < dev_priv->max_delay) | |
344 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 345 | } else if (busy_down < min_avg) { |
f97108d1 JB |
346 | if (dev_priv->cur_delay != dev_priv->min_delay) |
347 | new_delay = dev_priv->cur_delay + 1; | |
348 | if (new_delay > dev_priv->min_delay) | |
349 | new_delay = dev_priv->min_delay; | |
350 | } | |
351 | ||
7648fa99 JB |
352 | if (ironlake_set_drps(dev, new_delay)) |
353 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
354 | |
355 | return; | |
356 | } | |
357 | ||
549f7365 CW |
358 | static void notify_ring(struct drm_device *dev, |
359 | struct intel_ring_buffer *ring) | |
360 | { | |
361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
475553de | 362 | u32 seqno; |
9862e600 | 363 | |
475553de CW |
364 | if (ring->obj == NULL) |
365 | return; | |
366 | ||
367 | seqno = ring->get_seqno(ring); | |
549f7365 | 368 | trace_i915_gem_request_complete(dev, seqno); |
9862e600 CW |
369 | |
370 | ring->irq_seqno = seqno; | |
549f7365 | 371 | wake_up_all(&ring->irq_queue); |
9862e600 | 372 | |
549f7365 CW |
373 | dev_priv->hangcheck_count = 0; |
374 | mod_timer(&dev_priv->hangcheck_timer, | |
375 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
376 | } | |
377 | ||
3b8d8d91 JB |
378 | static void gen6_pm_irq_handler(struct drm_device *dev) |
379 | { | |
380 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
381 | u8 new_delay = dev_priv->cur_delay; | |
382 | u32 pm_iir; | |
383 | ||
384 | pm_iir = I915_READ(GEN6_PMIIR); | |
385 | if (!pm_iir) | |
386 | return; | |
387 | ||
388 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
389 | if (dev_priv->cur_delay != dev_priv->max_delay) | |
390 | new_delay = dev_priv->cur_delay + 1; | |
391 | if (new_delay > dev_priv->max_delay) | |
392 | new_delay = dev_priv->max_delay; | |
393 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { | |
394 | if (dev_priv->cur_delay != dev_priv->min_delay) | |
395 | new_delay = dev_priv->cur_delay - 1; | |
396 | if (new_delay < dev_priv->min_delay) { | |
397 | new_delay = dev_priv->min_delay; | |
398 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
399 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | | |
400 | ((new_delay << 16) & 0x3f0000)); | |
401 | } else { | |
402 | /* Make sure we continue to get down interrupts | |
403 | * until we hit the minimum frequency */ | |
404 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
405 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); | |
406 | } | |
407 | ||
408 | } | |
409 | ||
410 | gen6_set_rps(dev, new_delay); | |
411 | dev_priv->cur_delay = new_delay; | |
412 | ||
413 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
414 | } | |
415 | ||
776ad806 JB |
416 | static void pch_irq_handler(struct drm_device *dev) |
417 | { | |
418 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
419 | u32 pch_iir; | |
420 | ||
421 | pch_iir = I915_READ(SDEIIR); | |
422 | ||
423 | if (pch_iir & SDE_AUDIO_POWER_MASK) | |
424 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
425 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
426 | SDE_AUDIO_POWER_SHIFT); | |
427 | ||
428 | if (pch_iir & SDE_GMBUS) | |
429 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
430 | ||
431 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
432 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
433 | ||
434 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
435 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
436 | ||
437 | if (pch_iir & SDE_POISON) | |
438 | DRM_ERROR("PCH poison interrupt\n"); | |
439 | ||
440 | if (pch_iir & SDE_FDI_MASK) { | |
441 | u32 fdia, fdib; | |
442 | ||
443 | fdia = I915_READ(FDI_RXA_IIR); | |
444 | fdib = I915_READ(FDI_RXB_IIR); | |
445 | DRM_DEBUG_DRIVER("PCH FDI RX interrupt; FDI RXA IIR: 0x%08x, FDI RXB IIR: 0x%08x\n", fdia, fdib); | |
446 | } | |
447 | ||
448 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
449 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
450 | ||
451 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
452 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
453 | ||
454 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
455 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
456 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
457 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
458 | } | |
459 | ||
995b6762 | 460 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
461 | { |
462 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
463 | int ret = IRQ_NONE; | |
3b8d8d91 | 464 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
2d7b8366 | 465 | u32 hotplug_mask; |
036a4a7d | 466 | struct drm_i915_master_private *master_priv; |
881f47b6 XH |
467 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
468 | ||
469 | if (IS_GEN6(dev)) | |
470 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 471 | |
2d109a84 ZN |
472 | /* disable master interrupt before clearing iir */ |
473 | de_ier = I915_READ(DEIER); | |
474 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 475 | POSTING_READ(DEIER); |
2d109a84 | 476 | |
036a4a7d ZW |
477 | de_iir = I915_READ(DEIIR); |
478 | gt_iir = I915_READ(GTIIR); | |
c650156a | 479 | pch_iir = I915_READ(SDEIIR); |
3b8d8d91 | 480 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 481 | |
3b8d8d91 JB |
482 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
483 | (!IS_GEN6(dev) || pm_iir == 0)) | |
c7c85101 | 484 | goto done; |
036a4a7d | 485 | |
2d7b8366 YL |
486 | if (HAS_PCH_CPT(dev)) |
487 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
488 | else | |
489 | hotplug_mask = SDE_HOTPLUG_MASK; | |
490 | ||
c7c85101 | 491 | ret = IRQ_HANDLED; |
036a4a7d | 492 | |
c7c85101 ZN |
493 | if (dev->primary->master) { |
494 | master_priv = dev->primary->master->driver_priv; | |
495 | if (master_priv->sarea_priv) | |
496 | master_priv->sarea_priv->last_dispatch = | |
497 | READ_BREADCRUMB(dev_priv); | |
498 | } | |
036a4a7d | 499 | |
c6df541c | 500 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
1ec14ad3 | 501 | notify_ring(dev, &dev_priv->ring[RCS]); |
881f47b6 | 502 | if (gt_iir & bsd_usr_interrupt) |
1ec14ad3 CW |
503 | notify_ring(dev, &dev_priv->ring[VCS]); |
504 | if (gt_iir & GT_BLT_USER_INTERRUPT) | |
505 | notify_ring(dev, &dev_priv->ring[BCS]); | |
01c66889 | 506 | |
c7c85101 | 507 | if (de_iir & DE_GSE) |
3b617967 | 508 | intel_opregion_gse_intr(dev); |
c650156a | 509 | |
f072d2e7 | 510 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 511 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 512 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 513 | } |
013d5aa2 | 514 | |
f072d2e7 | 515 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 516 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 517 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 518 | } |
013d5aa2 | 519 | |
f072d2e7 | 520 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
521 | drm_handle_vblank(dev, 0); |
522 | ||
f072d2e7 | 523 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
524 | drm_handle_vblank(dev, 1); |
525 | ||
c7c85101 | 526 | /* check event from PCH */ |
776ad806 JB |
527 | if (de_iir & DE_PCH_EVENT) { |
528 | if (pch_iir & hotplug_mask) | |
529 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
530 | pch_irq_handler(dev); | |
531 | } | |
036a4a7d | 532 | |
f97108d1 | 533 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 534 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
535 | i915_handle_rps_change(dev); |
536 | } | |
537 | ||
3b8d8d91 JB |
538 | if (IS_GEN6(dev)) |
539 | gen6_pm_irq_handler(dev); | |
540 | ||
c7c85101 ZN |
541 | /* should clear PCH hotplug event before clear CPU irq */ |
542 | I915_WRITE(SDEIIR, pch_iir); | |
543 | I915_WRITE(GTIIR, gt_iir); | |
544 | I915_WRITE(DEIIR, de_iir); | |
545 | ||
546 | done: | |
2d109a84 | 547 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 548 | POSTING_READ(DEIER); |
2d109a84 | 549 | |
036a4a7d ZW |
550 | return ret; |
551 | } | |
552 | ||
8a905236 JB |
553 | /** |
554 | * i915_error_work_func - do process context error handling work | |
555 | * @work: work struct | |
556 | * | |
557 | * Fire an error uevent so userspace can see that a hang or error | |
558 | * was detected. | |
559 | */ | |
560 | static void i915_error_work_func(struct work_struct *work) | |
561 | { | |
562 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
563 | error_work); | |
564 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
565 | char *error_event[] = { "ERROR=1", NULL }; |
566 | char *reset_event[] = { "RESET=1", NULL }; | |
567 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 568 | |
f316a42c BG |
569 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
570 | ||
ba1234d1 | 571 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
572 | DRM_DEBUG_DRIVER("resetting chip\n"); |
573 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
574 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
575 | atomic_set(&dev_priv->mm.wedged, 0); | |
576 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 577 | } |
30dbf0c0 | 578 | complete_all(&dev_priv->error_completion); |
f316a42c | 579 | } |
8a905236 JB |
580 | } |
581 | ||
3bd3c932 | 582 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 583 | static struct drm_i915_error_object * |
bcfb2e28 | 584 | i915_error_object_create(struct drm_i915_private *dev_priv, |
05394f39 | 585 | struct drm_i915_gem_object *src) |
9df30794 CW |
586 | { |
587 | struct drm_i915_error_object *dst; | |
9df30794 | 588 | int page, page_count; |
e56660dd | 589 | u32 reloc_offset; |
9df30794 | 590 | |
05394f39 | 591 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
592 | return NULL; |
593 | ||
05394f39 | 594 | page_count = src->base.size / PAGE_SIZE; |
9df30794 CW |
595 | |
596 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
597 | if (dst == NULL) | |
598 | return NULL; | |
599 | ||
05394f39 | 600 | reloc_offset = src->gtt_offset; |
9df30794 | 601 | for (page = 0; page < page_count; page++) { |
788885ae | 602 | unsigned long flags; |
e56660dd CW |
603 | void __iomem *s; |
604 | void *d; | |
788885ae | 605 | |
e56660dd | 606 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
607 | if (d == NULL) |
608 | goto unwind; | |
e56660dd | 609 | |
788885ae | 610 | local_irq_save(flags); |
e56660dd | 611 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3e4d3af5 | 612 | reloc_offset); |
e56660dd | 613 | memcpy_fromio(d, s, PAGE_SIZE); |
3e4d3af5 | 614 | io_mapping_unmap_atomic(s); |
788885ae | 615 | local_irq_restore(flags); |
e56660dd | 616 | |
9df30794 | 617 | dst->pages[page] = d; |
e56660dd CW |
618 | |
619 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
620 | } |
621 | dst->page_count = page_count; | |
05394f39 | 622 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
623 | |
624 | return dst; | |
625 | ||
626 | unwind: | |
627 | while (page--) | |
628 | kfree(dst->pages[page]); | |
629 | kfree(dst); | |
630 | return NULL; | |
631 | } | |
632 | ||
633 | static void | |
634 | i915_error_object_free(struct drm_i915_error_object *obj) | |
635 | { | |
636 | int page; | |
637 | ||
638 | if (obj == NULL) | |
639 | return; | |
640 | ||
641 | for (page = 0; page < obj->page_count; page++) | |
642 | kfree(obj->pages[page]); | |
643 | ||
644 | kfree(obj); | |
645 | } | |
646 | ||
647 | static void | |
648 | i915_error_state_free(struct drm_device *dev, | |
649 | struct drm_i915_error_state *error) | |
650 | { | |
e2f973d5 CW |
651 | int i; |
652 | ||
653 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) | |
654 | i915_error_object_free(error->batchbuffer[i]); | |
655 | ||
656 | for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) | |
657 | i915_error_object_free(error->ringbuffer[i]); | |
658 | ||
9df30794 | 659 | kfree(error->active_bo); |
6ef3d427 | 660 | kfree(error->overlay); |
9df30794 CW |
661 | kfree(error); |
662 | } | |
663 | ||
c724e8a9 CW |
664 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
665 | int count, | |
666 | struct list_head *head) | |
667 | { | |
668 | struct drm_i915_gem_object *obj; | |
669 | int i = 0; | |
670 | ||
671 | list_for_each_entry(obj, head, mm_list) { | |
672 | err->size = obj->base.size; | |
673 | err->name = obj->base.name; | |
674 | err->seqno = obj->last_rendering_seqno; | |
675 | err->gtt_offset = obj->gtt_offset; | |
676 | err->read_domains = obj->base.read_domains; | |
677 | err->write_domain = obj->base.write_domain; | |
678 | err->fence_reg = obj->fence_reg; | |
679 | err->pinned = 0; | |
680 | if (obj->pin_count > 0) | |
681 | err->pinned = 1; | |
682 | if (obj->user_pin_count > 0) | |
683 | err->pinned = -1; | |
684 | err->tiling = obj->tiling_mode; | |
685 | err->dirty = obj->dirty; | |
686 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
3685092b | 687 | err->ring = obj->ring ? obj->ring->id : 0; |
a779e5ab | 688 | err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY; |
c724e8a9 CW |
689 | |
690 | if (++i == count) | |
691 | break; | |
692 | ||
693 | err++; | |
694 | } | |
695 | ||
696 | return i; | |
697 | } | |
698 | ||
748ebc60 CW |
699 | static void i915_gem_record_fences(struct drm_device *dev, |
700 | struct drm_i915_error_state *error) | |
701 | { | |
702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
703 | int i; | |
704 | ||
705 | /* Fences */ | |
706 | switch (INTEL_INFO(dev)->gen) { | |
707 | case 6: | |
708 | for (i = 0; i < 16; i++) | |
709 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
710 | break; | |
711 | case 5: | |
712 | case 4: | |
713 | for (i = 0; i < 16; i++) | |
714 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
715 | break; | |
716 | case 3: | |
717 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
718 | for (i = 0; i < 8; i++) | |
719 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
720 | case 2: | |
721 | for (i = 0; i < 8; i++) | |
722 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
723 | break; | |
724 | ||
725 | } | |
726 | } | |
727 | ||
bcfb2e28 CW |
728 | static struct drm_i915_error_object * |
729 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
730 | struct intel_ring_buffer *ring) | |
731 | { | |
732 | struct drm_i915_gem_object *obj; | |
733 | u32 seqno; | |
734 | ||
735 | if (!ring->get_seqno) | |
736 | return NULL; | |
737 | ||
738 | seqno = ring->get_seqno(ring); | |
739 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { | |
740 | if (obj->ring != ring) | |
741 | continue; | |
742 | ||
c37d9a5d | 743 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
bcfb2e28 CW |
744 | continue; |
745 | ||
746 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
747 | continue; | |
748 | ||
749 | /* We need to copy these to an anonymous buffer as the simplest | |
750 | * method to avoid being overwritten by userspace. | |
751 | */ | |
752 | return i915_error_object_create(dev_priv, obj); | |
753 | } | |
754 | ||
755 | return NULL; | |
756 | } | |
757 | ||
8a905236 JB |
758 | /** |
759 | * i915_capture_error_state - capture an error record for later analysis | |
760 | * @dev: drm device | |
761 | * | |
762 | * Should be called when an error is detected (either a hang or an error | |
763 | * interrupt) to capture error state from the time of the error. Fills | |
764 | * out a structure which becomes available in debugfs for user level tools | |
765 | * to pick up. | |
766 | */ | |
63eeaf38 JB |
767 | static void i915_capture_error_state(struct drm_device *dev) |
768 | { | |
769 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 770 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
771 | struct drm_i915_error_state *error; |
772 | unsigned long flags; | |
bcfb2e28 | 773 | int i; |
63eeaf38 JB |
774 | |
775 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
776 | error = dev_priv->first_error; |
777 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
778 | if (error) | |
779 | return; | |
63eeaf38 JB |
780 | |
781 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
782 | if (!error) { | |
9df30794 CW |
783 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
784 | return; | |
63eeaf38 JB |
785 | } |
786 | ||
2fa772f3 CW |
787 | DRM_DEBUG_DRIVER("generating error event\n"); |
788 | ||
1ec14ad3 | 789 | error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); |
63eeaf38 JB |
790 | error->eir = I915_READ(EIR); |
791 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
792 | error->pipeastat = I915_READ(PIPEASTAT); | |
793 | error->pipebstat = I915_READ(PIPEBSTAT); | |
794 | error->instpm = I915_READ(INSTPM); | |
f406839f CW |
795 | error->error = 0; |
796 | if (INTEL_INFO(dev)->gen >= 6) { | |
797 | error->error = I915_READ(ERROR_GEN6); | |
add354dd | 798 | |
1d8f38f4 CW |
799 | error->bcs_acthd = I915_READ(BCS_ACTHD); |
800 | error->bcs_ipehr = I915_READ(BCS_IPEHR); | |
801 | error->bcs_ipeir = I915_READ(BCS_IPEIR); | |
802 | error->bcs_instdone = I915_READ(BCS_INSTDONE); | |
803 | error->bcs_seqno = 0; | |
1ec14ad3 CW |
804 | if (dev_priv->ring[BCS].get_seqno) |
805 | error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]); | |
add354dd CW |
806 | |
807 | error->vcs_acthd = I915_READ(VCS_ACTHD); | |
808 | error->vcs_ipehr = I915_READ(VCS_IPEHR); | |
809 | error->vcs_ipeir = I915_READ(VCS_IPEIR); | |
810 | error->vcs_instdone = I915_READ(VCS_INSTDONE); | |
811 | error->vcs_seqno = 0; | |
1ec14ad3 CW |
812 | if (dev_priv->ring[VCS].get_seqno) |
813 | error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]); | |
f406839f CW |
814 | } |
815 | if (INTEL_INFO(dev)->gen >= 4) { | |
63eeaf38 JB |
816 | error->ipeir = I915_READ(IPEIR_I965); |
817 | error->ipehr = I915_READ(IPEHR_I965); | |
818 | error->instdone = I915_READ(INSTDONE_I965); | |
819 | error->instps = I915_READ(INSTPS); | |
820 | error->instdone1 = I915_READ(INSTDONE1); | |
821 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 822 | error->bbaddr = I915_READ64(BB_ADDR); |
f406839f CW |
823 | } else { |
824 | error->ipeir = I915_READ(IPEIR); | |
825 | error->ipehr = I915_READ(IPEHR); | |
826 | error->instdone = I915_READ(INSTDONE); | |
827 | error->acthd = I915_READ(ACTHD); | |
828 | error->bbaddr = 0; | |
63eeaf38 | 829 | } |
748ebc60 | 830 | i915_gem_record_fences(dev, error); |
63eeaf38 | 831 | |
e2f973d5 CW |
832 | /* Record the active batch and ring buffers */ |
833 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
bcfb2e28 CW |
834 | error->batchbuffer[i] = |
835 | i915_error_first_batchbuffer(dev_priv, | |
836 | &dev_priv->ring[i]); | |
9df30794 | 837 | |
e2f973d5 CW |
838 | error->ringbuffer[i] = |
839 | i915_error_object_create(dev_priv, | |
840 | dev_priv->ring[i].obj); | |
841 | } | |
9df30794 | 842 | |
c724e8a9 | 843 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 844 | error->active_bo = NULL; |
c724e8a9 | 845 | error->pinned_bo = NULL; |
9df30794 | 846 | |
bcfb2e28 CW |
847 | i = 0; |
848 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
849 | i++; | |
850 | error->active_bo_count = i; | |
05394f39 | 851 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
bcfb2e28 CW |
852 | i++; |
853 | error->pinned_bo_count = i - error->active_bo_count; | |
c724e8a9 | 854 | |
8e934dbf CW |
855 | error->active_bo = NULL; |
856 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
857 | if (i) { |
858 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 859 | GFP_ATOMIC); |
c724e8a9 CW |
860 | if (error->active_bo) |
861 | error->pinned_bo = | |
862 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
863 | } |
864 | ||
c724e8a9 CW |
865 | if (error->active_bo) |
866 | error->active_bo_count = | |
867 | capture_bo_list(error->active_bo, | |
868 | error->active_bo_count, | |
869 | &dev_priv->mm.active_list); | |
870 | ||
871 | if (error->pinned_bo) | |
872 | error->pinned_bo_count = | |
873 | capture_bo_list(error->pinned_bo, | |
874 | error->pinned_bo_count, | |
875 | &dev_priv->mm.pinned_list); | |
876 | ||
9df30794 CW |
877 | do_gettimeofday(&error->time); |
878 | ||
6ef3d427 | 879 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 880 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 881 | |
9df30794 CW |
882 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
883 | if (dev_priv->first_error == NULL) { | |
884 | dev_priv->first_error = error; | |
885 | error = NULL; | |
886 | } | |
63eeaf38 | 887 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
888 | |
889 | if (error) | |
890 | i915_error_state_free(dev, error); | |
891 | } | |
892 | ||
893 | void i915_destroy_error_state(struct drm_device *dev) | |
894 | { | |
895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
896 | struct drm_i915_error_state *error; | |
897 | ||
898 | spin_lock(&dev_priv->error_lock); | |
899 | error = dev_priv->first_error; | |
900 | dev_priv->first_error = NULL; | |
901 | spin_unlock(&dev_priv->error_lock); | |
902 | ||
903 | if (error) | |
904 | i915_error_state_free(dev, error); | |
63eeaf38 | 905 | } |
3bd3c932 CW |
906 | #else |
907 | #define i915_capture_error_state(x) | |
908 | #endif | |
63eeaf38 | 909 | |
35aed2e6 | 910 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
911 | { |
912 | struct drm_i915_private *dev_priv = dev->dev_private; | |
913 | u32 eir = I915_READ(EIR); | |
8a905236 | 914 | |
35aed2e6 CW |
915 | if (!eir) |
916 | return; | |
8a905236 JB |
917 | |
918 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
919 | eir); | |
920 | ||
921 | if (IS_G4X(dev)) { | |
922 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
923 | u32 ipeir = I915_READ(IPEIR_I965); | |
924 | ||
925 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
926 | I915_READ(IPEIR_I965)); | |
927 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
928 | I915_READ(IPEHR_I965)); | |
929 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
930 | I915_READ(INSTDONE_I965)); | |
931 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
932 | I915_READ(INSTPS)); | |
933 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
934 | I915_READ(INSTDONE1)); | |
935 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
936 | I915_READ(ACTHD_I965)); | |
937 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 938 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
939 | } |
940 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
941 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
942 | printk(KERN_ERR "page table error\n"); | |
943 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
944 | pgtbl_err); | |
945 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 946 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
947 | } |
948 | } | |
949 | ||
a6c45cf0 | 950 | if (!IS_GEN2(dev)) { |
8a905236 JB |
951 | if (eir & I915_ERROR_PAGE_TABLE) { |
952 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
953 | printk(KERN_ERR "page table error\n"); | |
954 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
955 | pgtbl_err); | |
956 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 957 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
958 | } |
959 | } | |
960 | ||
961 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
35aed2e6 CW |
962 | u32 pipea_stats = I915_READ(PIPEASTAT); |
963 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
964 | ||
8a905236 JB |
965 | printk(KERN_ERR "memory refresh error\n"); |
966 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
967 | pipea_stats); | |
968 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
969 | pipeb_stats); | |
970 | /* pipestat has already been acked */ | |
971 | } | |
972 | if (eir & I915_ERROR_INSTRUCTION) { | |
973 | printk(KERN_ERR "instruction error\n"); | |
974 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
975 | I915_READ(INSTPM)); | |
a6c45cf0 | 976 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
977 | u32 ipeir = I915_READ(IPEIR); |
978 | ||
979 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
980 | I915_READ(IPEIR)); | |
981 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
982 | I915_READ(IPEHR)); | |
983 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
984 | I915_READ(INSTDONE)); | |
985 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
986 | I915_READ(ACTHD)); | |
987 | I915_WRITE(IPEIR, ipeir); | |
3143a2bf | 988 | POSTING_READ(IPEIR); |
8a905236 JB |
989 | } else { |
990 | u32 ipeir = I915_READ(IPEIR_I965); | |
991 | ||
992 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
993 | I915_READ(IPEIR_I965)); | |
994 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
995 | I915_READ(IPEHR_I965)); | |
996 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
997 | I915_READ(INSTDONE_I965)); | |
998 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
999 | I915_READ(INSTPS)); | |
1000 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
1001 | I915_READ(INSTDONE1)); | |
1002 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1003 | I915_READ(ACTHD_I965)); | |
1004 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 1005 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1006 | } |
1007 | } | |
1008 | ||
1009 | I915_WRITE(EIR, eir); | |
3143a2bf | 1010 | POSTING_READ(EIR); |
8a905236 JB |
1011 | eir = I915_READ(EIR); |
1012 | if (eir) { | |
1013 | /* | |
1014 | * some errors might have become stuck, | |
1015 | * mask them. | |
1016 | */ | |
1017 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1018 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1019 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1020 | } | |
35aed2e6 CW |
1021 | } |
1022 | ||
1023 | /** | |
1024 | * i915_handle_error - handle an error interrupt | |
1025 | * @dev: drm device | |
1026 | * | |
1027 | * Do some basic checking of regsiter state at error interrupt time and | |
1028 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1029 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1030 | * so userspace knows something bad happened (should trigger collection | |
1031 | * of a ring dump etc.). | |
1032 | */ | |
527f9e90 | 1033 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1034 | { |
1035 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1036 | ||
1037 | i915_capture_error_state(dev); | |
1038 | i915_report_and_clear_eir(dev); | |
8a905236 | 1039 | |
ba1234d1 | 1040 | if (wedged) { |
30dbf0c0 | 1041 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
1042 | atomic_set(&dev_priv->mm.wedged, 1); |
1043 | ||
11ed50ec BG |
1044 | /* |
1045 | * Wakeup waiting processes so they don't hang | |
1046 | */ | |
1ec14ad3 | 1047 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
f787a5f5 | 1048 | if (HAS_BSD(dev)) |
1ec14ad3 | 1049 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1050 | if (HAS_BLT(dev)) |
1ec14ad3 | 1051 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
11ed50ec BG |
1052 | } |
1053 | ||
9c9fe1f8 | 1054 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
1055 | } |
1056 | ||
4e5359cd SF |
1057 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
1058 | { | |
1059 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1060 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1061 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1062 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1063 | struct intel_unpin_work *work; |
1064 | unsigned long flags; | |
1065 | bool stall_detected; | |
1066 | ||
1067 | /* Ignore early vblank irqs */ | |
1068 | if (intel_crtc == NULL) | |
1069 | return; | |
1070 | ||
1071 | spin_lock_irqsave(&dev->event_lock, flags); | |
1072 | work = intel_crtc->unpin_work; | |
1073 | ||
1074 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
1075 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
1076 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1077 | return; | |
1078 | } | |
1079 | ||
1080 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1081 | obj = work->pending_flip_obj; |
a6c45cf0 | 1082 | if (INTEL_INFO(dev)->gen >= 4) { |
4e5359cd | 1083 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
05394f39 | 1084 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
4e5359cd SF |
1085 | } else { |
1086 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; | |
05394f39 | 1087 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
4e5359cd SF |
1088 | crtc->y * crtc->fb->pitch + |
1089 | crtc->x * crtc->fb->bits_per_pixel/8); | |
1090 | } | |
1091 | ||
1092 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1093 | ||
1094 | if (stall_detected) { | |
1095 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1096 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1097 | } | |
1098 | } | |
1099 | ||
1da177e4 LT |
1100 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
1101 | { | |
84b1fd10 | 1102 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 1103 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 1104 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
1105 | u32 iir, new_iir; |
1106 | u32 pipea_stats, pipeb_stats; | |
05eff845 | 1107 | u32 vblank_status; |
0a3e67a4 | 1108 | int vblank = 0; |
7c463586 | 1109 | unsigned long irqflags; |
05eff845 KP |
1110 | int irq_received; |
1111 | int ret = IRQ_NONE; | |
6e5fca53 | 1112 | |
630681d9 EA |
1113 | atomic_inc(&dev_priv->irq_received); |
1114 | ||
bad720ff | 1115 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1116 | return ironlake_irq_handler(dev); |
036a4a7d | 1117 | |
ed4cb414 | 1118 | iir = I915_READ(IIR); |
a6b54f3f | 1119 | |
a6c45cf0 | 1120 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1121 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1122 | else |
d874bcff | 1123 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1124 | |
05eff845 KP |
1125 | for (;;) { |
1126 | irq_received = iir != 0; | |
1127 | ||
1128 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1129 | * have been cleared after the pipestat interrupt was received. | |
1130 | * It doesn't set the bit in iir again, but it still produces | |
1131 | * interrupts (for non-MSI). | |
1132 | */ | |
1ec14ad3 | 1133 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
05eff845 KP |
1134 | pipea_stats = I915_READ(PIPEASTAT); |
1135 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 1136 | |
8a905236 | 1137 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1138 | i915_handle_error(dev, false); |
8a905236 | 1139 | |
cdfbc41f EA |
1140 | /* |
1141 | * Clear the PIPE(A|B)STAT regs before the IIR | |
1142 | */ | |
05eff845 | 1143 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 1144 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 1145 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 1146 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 1147 | irq_received = 1; |
cdfbc41f | 1148 | } |
1da177e4 | 1149 | |
05eff845 | 1150 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 1151 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 1152 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 1153 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 1154 | irq_received = 1; |
cdfbc41f | 1155 | } |
1ec14ad3 | 1156 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
05eff845 KP |
1157 | |
1158 | if (!irq_received) | |
1159 | break; | |
1160 | ||
1161 | ret = IRQ_HANDLED; | |
8ee1c3db | 1162 | |
5ca58282 JB |
1163 | /* Consume port. Then clear IIR or we'll miss events */ |
1164 | if ((I915_HAS_HOTPLUG(dev)) && | |
1165 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1166 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1167 | ||
44d98a61 | 1168 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1169 | hotplug_status); |
1170 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1171 | queue_work(dev_priv->wq, |
1172 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1173 | |
1174 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1175 | I915_READ(PORT_HOTPLUG_STAT); | |
1176 | } | |
1177 | ||
cdfbc41f EA |
1178 | I915_WRITE(IIR, iir); |
1179 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1180 | |
7c1c2871 DA |
1181 | if (dev->primary->master) { |
1182 | master_priv = dev->primary->master->driver_priv; | |
1183 | if (master_priv->sarea_priv) | |
1184 | master_priv->sarea_priv->last_dispatch = | |
1185 | READ_BREADCRUMB(dev_priv); | |
1186 | } | |
0a3e67a4 | 1187 | |
549f7365 | 1188 | if (iir & I915_USER_INTERRUPT) |
1ec14ad3 CW |
1189 | notify_ring(dev, &dev_priv->ring[RCS]); |
1190 | if (iir & I915_BSD_USER_INTERRUPT) | |
1191 | notify_ring(dev, &dev_priv->ring[VCS]); | |
d1b851fc | 1192 | |
1afe3e9d | 1193 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1194 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1195 | if (dev_priv->flip_pending_is_done) |
1196 | intel_finish_page_flip_plane(dev, 0); | |
1197 | } | |
6b95a207 | 1198 | |
1afe3e9d | 1199 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1200 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1201 | if (dev_priv->flip_pending_is_done) |
1202 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1203 | } |
6b95a207 | 1204 | |
78c6e170 CW |
1205 | if (pipea_stats & vblank_status && |
1206 | drm_handle_vblank(dev, 0)) { | |
cdfbc41f | 1207 | vblank++; |
4e5359cd SF |
1208 | if (!dev_priv->flip_pending_is_done) { |
1209 | i915_pageflip_stall_check(dev, 0); | |
1afe3e9d | 1210 | intel_finish_page_flip(dev, 0); |
4e5359cd | 1211 | } |
cdfbc41f | 1212 | } |
7c463586 | 1213 | |
78c6e170 CW |
1214 | if (pipeb_stats & vblank_status && |
1215 | drm_handle_vblank(dev, 1)) { | |
cdfbc41f | 1216 | vblank++; |
4e5359cd SF |
1217 | if (!dev_priv->flip_pending_is_done) { |
1218 | i915_pageflip_stall_check(dev, 1); | |
1afe3e9d | 1219 | intel_finish_page_flip(dev, 1); |
4e5359cd | 1220 | } |
cdfbc41f | 1221 | } |
7c463586 | 1222 | |
d874bcff JB |
1223 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
1224 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f | 1225 | (iir & I915_ASLE_INTERRUPT)) |
3b617967 | 1226 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1227 | |
1228 | /* With MSI, interrupts are only generated when iir | |
1229 | * transitions from zero to nonzero. If another bit got | |
1230 | * set while we were handling the existing iir bits, then | |
1231 | * we would never get another interrupt. | |
1232 | * | |
1233 | * This is fine on non-MSI as well, as if we hit this path | |
1234 | * we avoid exiting the interrupt handler only to generate | |
1235 | * another one. | |
1236 | * | |
1237 | * Note that for MSI this could cause a stray interrupt report | |
1238 | * if an interrupt landed in the time between writing IIR and | |
1239 | * the posting read. This should be rare enough to never | |
1240 | * trigger the 99% of 100,000 interrupts test for disabling | |
1241 | * stray interrupts. | |
1242 | */ | |
1243 | iir = new_iir; | |
05eff845 | 1244 | } |
0a3e67a4 | 1245 | |
05eff845 | 1246 | return ret; |
1da177e4 LT |
1247 | } |
1248 | ||
af6061af | 1249 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1250 | { |
1251 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1252 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1253 | |
1254 | i915_kernel_lost_context(dev); | |
1255 | ||
44d98a61 | 1256 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1257 | |
c99b058f | 1258 | dev_priv->counter++; |
c29b669c | 1259 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1260 | dev_priv->counter = 1; |
7c1c2871 DA |
1261 | if (master_priv->sarea_priv) |
1262 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1263 | |
e1f99ce6 CW |
1264 | if (BEGIN_LP_RING(4) == 0) { |
1265 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1266 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1267 | OUT_RING(dev_priv->counter); | |
1268 | OUT_RING(MI_USER_INTERRUPT); | |
1269 | ADVANCE_LP_RING(); | |
1270 | } | |
bc5f4523 | 1271 | |
c29b669c | 1272 | return dev_priv->counter; |
1da177e4 LT |
1273 | } |
1274 | ||
9d34e5db CW |
1275 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1276 | { | |
1277 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1ec14ad3 | 1278 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
9d34e5db | 1279 | |
b13c2b96 CW |
1280 | if (dev_priv->trace_irq_seqno == 0 && |
1281 | ring->irq_get(ring)) | |
1282 | dev_priv->trace_irq_seqno = seqno; | |
9d34e5db CW |
1283 | } |
1284 | ||
84b1fd10 | 1285 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1286 | { |
1287 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1288 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1289 | int ret = 0; |
1ec14ad3 | 1290 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 1291 | |
44d98a61 | 1292 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1293 | READ_BREADCRUMB(dev_priv)); |
1294 | ||
ed4cb414 | 1295 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1296 | if (master_priv->sarea_priv) |
1297 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1298 | return 0; |
ed4cb414 | 1299 | } |
1da177e4 | 1300 | |
7c1c2871 DA |
1301 | if (master_priv->sarea_priv) |
1302 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1303 | |
b13c2b96 CW |
1304 | if (ring->irq_get(ring)) { |
1305 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
1306 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
1307 | ring->irq_put(ring); | |
5a9a8d1a CW |
1308 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
1309 | ret = -EBUSY; | |
1da177e4 | 1310 | |
20caafa6 | 1311 | if (ret == -EBUSY) { |
3e684eae | 1312 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1313 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1314 | } | |
1315 | ||
af6061af DA |
1316 | return ret; |
1317 | } | |
1318 | ||
1da177e4 LT |
1319 | /* Needs the lock as it touches the ring. |
1320 | */ | |
c153f45f EA |
1321 | int i915_irq_emit(struct drm_device *dev, void *data, |
1322 | struct drm_file *file_priv) | |
1da177e4 | 1323 | { |
1da177e4 | 1324 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1325 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1326 | int result; |
1327 | ||
1ec14ad3 | 1328 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
3e684eae | 1329 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1330 | return -EINVAL; |
1da177e4 | 1331 | } |
299eb93c EA |
1332 | |
1333 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1334 | ||
546b0974 | 1335 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1336 | result = i915_emit_irq(dev); |
546b0974 | 1337 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1338 | |
c153f45f | 1339 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1340 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1341 | return -EFAULT; |
1da177e4 LT |
1342 | } |
1343 | ||
1344 | return 0; | |
1345 | } | |
1346 | ||
1347 | /* Doesn't need the hardware lock. | |
1348 | */ | |
c153f45f EA |
1349 | int i915_irq_wait(struct drm_device *dev, void *data, |
1350 | struct drm_file *file_priv) | |
1da177e4 | 1351 | { |
1da177e4 | 1352 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1353 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1354 | |
1355 | if (!dev_priv) { | |
3e684eae | 1356 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1357 | return -EINVAL; |
1da177e4 LT |
1358 | } |
1359 | ||
c153f45f | 1360 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1361 | } |
1362 | ||
b0b544cd CW |
1363 | static void i915_vblank_work_func(struct work_struct *work) |
1364 | { | |
1365 | drm_i915_private_t *dev_priv = | |
1366 | container_of(work, drm_i915_private_t, vblank_work); | |
1367 | ||
1368 | if (atomic_read(&dev_priv->vblank_enabled)) { | |
1369 | if (!dev_priv->vblank_pm_qos.pm_qos_class) | |
1370 | pm_qos_add_request(&dev_priv->vblank_pm_qos, | |
1371 | PM_QOS_CPU_DMA_LATENCY, | |
1372 | 15); //>=20 won't work | |
1373 | } else { | |
1374 | if (dev_priv->vblank_pm_qos.pm_qos_class) | |
1375 | pm_qos_remove_request(&dev_priv->vblank_pm_qos); | |
1376 | } | |
1377 | } | |
1378 | ||
42f52ef8 KP |
1379 | /* Called from drm generic code, passed 'crtc' which |
1380 | * we use as a pipe index | |
1381 | */ | |
1382 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1383 | { |
1384 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1385 | unsigned long irqflags; |
71e0ffa5 | 1386 | |
5eddb70b | 1387 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1388 | return -EINVAL; |
0a3e67a4 | 1389 | |
1ec14ad3 | 1390 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
bad720ff | 1391 | if (HAS_PCH_SPLIT(dev)) |
1ec14ad3 | 1392 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
c062df61 | 1393 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
a6c45cf0 | 1394 | else if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1395 | i915_enable_pipestat(dev_priv, pipe, |
1396 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1397 | else |
7c463586 KP |
1398 | i915_enable_pipestat(dev_priv, pipe, |
1399 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
1ec14ad3 | 1400 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
b0b544cd CW |
1401 | |
1402 | /* gen3 platforms have an issue with vsync interrupts not reaching | |
1403 | * cpu during deep c-state sleep (>C1), so we need to install a | |
1404 | * PM QoS handle to prevent C-state starvation of the GPU. | |
1405 | */ | |
1406 | if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) { | |
1407 | atomic_inc(&dev_priv->vblank_enabled); | |
1408 | queue_work(dev_priv->wq, &dev_priv->vblank_work); | |
1409 | } | |
1410 | ||
0a3e67a4 JB |
1411 | return 0; |
1412 | } | |
1413 | ||
42f52ef8 KP |
1414 | /* Called from drm generic code, passed 'crtc' which |
1415 | * we use as a pipe index | |
1416 | */ | |
1417 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1418 | { |
1419 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1420 | unsigned long irqflags; |
0a3e67a4 | 1421 | |
b0b544cd CW |
1422 | if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) { |
1423 | atomic_dec(&dev_priv->vblank_enabled); | |
1424 | queue_work(dev_priv->wq, &dev_priv->vblank_work); | |
1425 | } | |
1426 | ||
1ec14ad3 | 1427 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
bad720ff | 1428 | if (HAS_PCH_SPLIT(dev)) |
1ec14ad3 | 1429 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
c062df61 LP |
1430 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
1431 | else | |
1432 | i915_disable_pipestat(dev_priv, pipe, | |
1433 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1434 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1ec14ad3 | 1435 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1436 | } |
1437 | ||
702880f2 DA |
1438 | /* Set the vblank monitor pipe |
1439 | */ | |
c153f45f EA |
1440 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1441 | struct drm_file *file_priv) | |
702880f2 | 1442 | { |
702880f2 | 1443 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1444 | |
1445 | if (!dev_priv) { | |
3e684eae | 1446 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1447 | return -EINVAL; |
702880f2 DA |
1448 | } |
1449 | ||
5b51694a | 1450 | return 0; |
702880f2 DA |
1451 | } |
1452 | ||
c153f45f EA |
1453 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1454 | struct drm_file *file_priv) | |
702880f2 | 1455 | { |
702880f2 | 1456 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1457 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1458 | |
1459 | if (!dev_priv) { | |
3e684eae | 1460 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1461 | return -EINVAL; |
702880f2 DA |
1462 | } |
1463 | ||
0a3e67a4 | 1464 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1465 | |
702880f2 DA |
1466 | return 0; |
1467 | } | |
1468 | ||
a6b54f3f MCA |
1469 | /** |
1470 | * Schedule buffer swap at given vertical blank. | |
1471 | */ | |
c153f45f EA |
1472 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1473 | struct drm_file *file_priv) | |
a6b54f3f | 1474 | { |
bd95e0a4 EA |
1475 | /* The delayed swap mechanism was fundamentally racy, and has been |
1476 | * removed. The model was that the client requested a delayed flip/swap | |
1477 | * from the kernel, then waited for vblank before continuing to perform | |
1478 | * rendering. The problem was that the kernel might wake the client | |
1479 | * up before it dispatched the vblank swap (since the lock has to be | |
1480 | * held while touching the ringbuffer), in which case the client would | |
1481 | * clear and start the next frame before the swap occurred, and | |
1482 | * flicker would occur in addition to likely missing the vblank. | |
1483 | * | |
1484 | * In the absence of this ioctl, userland falls back to a correct path | |
1485 | * of waiting for a vblank, then dispatching the swap on its own. | |
1486 | * Context switching to userland and back is plenty fast enough for | |
1487 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1488 | */ |
bd95e0a4 | 1489 | return -EINVAL; |
a6b54f3f MCA |
1490 | } |
1491 | ||
893eead0 CW |
1492 | static u32 |
1493 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1494 | { |
893eead0 CW |
1495 | return list_entry(ring->request_list.prev, |
1496 | struct drm_i915_gem_request, list)->seqno; | |
1497 | } | |
1498 | ||
1499 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1500 | { | |
1501 | if (list_empty(&ring->request_list) || | |
1502 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1503 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1504 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1505 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1506 | ring->name, | |
b2223497 | 1507 | ring->waiting_seqno, |
893eead0 CW |
1508 | ring->get_seqno(ring)); |
1509 | wake_up_all(&ring->irq_queue); | |
1510 | *err = true; | |
1511 | } | |
1512 | return true; | |
1513 | } | |
1514 | return false; | |
f65d9421 BG |
1515 | } |
1516 | ||
1ec14ad3 CW |
1517 | static bool kick_ring(struct intel_ring_buffer *ring) |
1518 | { | |
1519 | struct drm_device *dev = ring->dev; | |
1520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1521 | u32 tmp = I915_READ_CTL(ring); | |
1522 | if (tmp & RING_WAIT) { | |
1523 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1524 | ring->name); | |
1525 | I915_WRITE_CTL(ring, tmp); | |
1526 | return true; | |
1527 | } | |
1528 | if (IS_GEN6(dev) && | |
1529 | (tmp & RING_WAIT_SEMAPHORE)) { | |
1530 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
1531 | ring->name); | |
1532 | I915_WRITE_CTL(ring, tmp); | |
1533 | return true; | |
1534 | } | |
1535 | return false; | |
1536 | } | |
1537 | ||
f65d9421 BG |
1538 | /** |
1539 | * This is called when the chip hasn't reported back with completed | |
1540 | * batchbuffers in a long time. The first time this is called we simply record | |
1541 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1542 | * again, we assume the chip is wedged and try to fix it. | |
1543 | */ | |
1544 | void i915_hangcheck_elapsed(unsigned long data) | |
1545 | { | |
1546 | struct drm_device *dev = (struct drm_device *)data; | |
1547 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1548 | uint32_t acthd, instdone, instdone1; |
893eead0 CW |
1549 | bool err = false; |
1550 | ||
1551 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
1ec14ad3 CW |
1552 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
1553 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && | |
1554 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { | |
893eead0 CW |
1555 | dev_priv->hangcheck_count = 0; |
1556 | if (err) | |
1557 | goto repeat; | |
1558 | return; | |
1559 | } | |
b9201c14 | 1560 | |
a6c45cf0 | 1561 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1562 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1563 | instdone = I915_READ(INSTDONE); |
1564 | instdone1 = 0; | |
1565 | } else { | |
f65d9421 | 1566 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1567 | instdone = I915_READ(INSTDONE_I965); |
1568 | instdone1 = I915_READ(INSTDONE1); | |
1569 | } | |
f65d9421 | 1570 | |
cbb465e7 CW |
1571 | if (dev_priv->last_acthd == acthd && |
1572 | dev_priv->last_instdone == instdone && | |
1573 | dev_priv->last_instdone1 == instdone1) { | |
1574 | if (dev_priv->hangcheck_count++ > 1) { | |
1575 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1576 | |
1577 | if (!IS_GEN2(dev)) { | |
1578 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1579 | * If so we can simply poke the RB_WAIT bit | |
1580 | * and break the hang. This should work on | |
1581 | * all but the second generation chipsets. | |
1582 | */ | |
1ec14ad3 CW |
1583 | |
1584 | if (kick_ring(&dev_priv->ring[RCS])) | |
1585 | goto repeat; | |
1586 | ||
1587 | if (HAS_BSD(dev) && | |
1588 | kick_ring(&dev_priv->ring[VCS])) | |
1589 | goto repeat; | |
1590 | ||
1591 | if (HAS_BLT(dev) && | |
1592 | kick_ring(&dev_priv->ring[BCS])) | |
893eead0 | 1593 | goto repeat; |
8c80b59b CW |
1594 | } |
1595 | ||
cbb465e7 CW |
1596 | i915_handle_error(dev, true); |
1597 | return; | |
1598 | } | |
1599 | } else { | |
1600 | dev_priv->hangcheck_count = 0; | |
1601 | ||
1602 | dev_priv->last_acthd = acthd; | |
1603 | dev_priv->last_instdone = instdone; | |
1604 | dev_priv->last_instdone1 = instdone1; | |
1605 | } | |
f65d9421 | 1606 | |
893eead0 | 1607 | repeat: |
f65d9421 | 1608 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1609 | mod_timer(&dev_priv->hangcheck_timer, |
1610 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1611 | } |
1612 | ||
1da177e4 LT |
1613 | /* drm_dma.h hooks |
1614 | */ | |
f2b115e6 | 1615 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1616 | { |
1617 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1618 | ||
1619 | I915_WRITE(HWSTAM, 0xeffe); | |
1620 | ||
1621 | /* XXX hotplug from PCH */ | |
1622 | ||
1623 | I915_WRITE(DEIMR, 0xffffffff); | |
1624 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1625 | POSTING_READ(DEIER); |
036a4a7d ZW |
1626 | |
1627 | /* and GT */ | |
1628 | I915_WRITE(GTIMR, 0xffffffff); | |
1629 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1630 | POSTING_READ(GTIER); |
c650156a ZW |
1631 | |
1632 | /* south display irq */ | |
1633 | I915_WRITE(SDEIMR, 0xffffffff); | |
1634 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1635 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1636 | } |
1637 | ||
f2b115e6 | 1638 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1639 | { |
1640 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1641 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1642 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1643 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
1ec14ad3 | 1644 | u32 render_irqs; |
2d7b8366 | 1645 | u32 hotplug_mask; |
036a4a7d | 1646 | |
1ec14ad3 | 1647 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
1648 | |
1649 | /* should always can generate irq */ | |
1650 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
1651 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
1652 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 1653 | POSTING_READ(DEIER); |
036a4a7d | 1654 | |
1ec14ad3 | 1655 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
1656 | |
1657 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 1658 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 1659 | |
1ec14ad3 CW |
1660 | if (IS_GEN6(dev)) |
1661 | render_irqs = | |
1662 | GT_USER_INTERRUPT | | |
1663 | GT_GEN6_BSD_USER_INTERRUPT | | |
1664 | GT_BLT_USER_INTERRUPT; | |
1665 | else | |
1666 | render_irqs = | |
88f23b8f | 1667 | GT_USER_INTERRUPT | |
c6df541c | 1668 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
1669 | GT_BSD_USER_INTERRUPT; |
1670 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 1671 | POSTING_READ(GTIER); |
036a4a7d | 1672 | |
2d7b8366 YL |
1673 | if (HAS_PCH_CPT(dev)) { |
1674 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | | |
1675 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; | |
1676 | } else { | |
1677 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | |
1678 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
776ad806 JB |
1679 | hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK; |
1680 | I915_WRITE(FDI_RXA_IMR, 0); | |
1681 | I915_WRITE(FDI_RXB_IMR, 0); | |
2d7b8366 YL |
1682 | } |
1683 | ||
1ec14ad3 | 1684 | dev_priv->pch_irq_mask = ~hotplug_mask; |
c650156a ZW |
1685 | |
1686 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1ec14ad3 CW |
1687 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
1688 | I915_WRITE(SDEIER, hotplug_mask); | |
3143a2bf | 1689 | POSTING_READ(SDEIER); |
c650156a | 1690 | |
f97108d1 JB |
1691 | if (IS_IRONLAKE_M(dev)) { |
1692 | /* Clear & enable PCU event interrupts */ | |
1693 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1694 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1695 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1696 | } | |
1697 | ||
036a4a7d ZW |
1698 | return 0; |
1699 | } | |
1700 | ||
84b1fd10 | 1701 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1702 | { |
1703 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1704 | ||
79e53945 | 1705 | atomic_set(&dev_priv->irq_received, 0); |
b0b544cd | 1706 | atomic_set(&dev_priv->vblank_enabled, 0); |
79e53945 | 1707 | |
036a4a7d | 1708 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1709 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
b0b544cd | 1710 | INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_func); |
036a4a7d | 1711 | |
bad720ff | 1712 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1713 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1714 | return; |
1715 | } | |
1716 | ||
5ca58282 JB |
1717 | if (I915_HAS_HOTPLUG(dev)) { |
1718 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1719 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1720 | } | |
1721 | ||
0a3e67a4 | 1722 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1723 | I915_WRITE(PIPEASTAT, 0); |
1724 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1725 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1726 | I915_WRITE(IER, 0x0); |
3143a2bf | 1727 | POSTING_READ(IER); |
1da177e4 LT |
1728 | } |
1729 | ||
b01f2c3a JB |
1730 | /* |
1731 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1732 | * enabled correctly. | |
1733 | */ | |
0a3e67a4 | 1734 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1735 | { |
1736 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1737 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1738 | u32 error_mask; |
0a3e67a4 | 1739 | |
1ec14ad3 | 1740 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
d1b851fc | 1741 | if (HAS_BSD(dev)) |
1ec14ad3 | 1742 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1743 | if (HAS_BLT(dev)) |
1ec14ad3 | 1744 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
d1b851fc | 1745 | |
0a3e67a4 | 1746 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1747 | |
bad720ff | 1748 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1749 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1750 | |
7c463586 | 1751 | /* Unmask the interrupts that we always want on. */ |
1ec14ad3 | 1752 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
7c463586 KP |
1753 | |
1754 | dev_priv->pipestat[0] = 0; | |
1755 | dev_priv->pipestat[1] = 0; | |
1756 | ||
5ca58282 | 1757 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1758 | /* Enable in IER... */ |
1759 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1760 | /* and unmask in IMR */ | |
1ec14ad3 | 1761 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1762 | } |
1763 | ||
63eeaf38 JB |
1764 | /* |
1765 | * Enable some error detection, note the instruction error mask | |
1766 | * bit is reserved, so we leave it masked. | |
1767 | */ | |
1768 | if (IS_G4X(dev)) { | |
1769 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1770 | GM45_ERROR_MEM_PRIV | | |
1771 | GM45_ERROR_CP_PRIV | | |
1772 | I915_ERROR_MEMORY_REFRESH); | |
1773 | } else { | |
1774 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1775 | I915_ERROR_MEMORY_REFRESH); | |
1776 | } | |
1777 | I915_WRITE(EMR, error_mask); | |
1778 | ||
1ec14ad3 | 1779 | I915_WRITE(IMR, dev_priv->irq_mask); |
c496fa1f | 1780 | I915_WRITE(IER, enable_mask); |
3143a2bf | 1781 | POSTING_READ(IER); |
ed4cb414 | 1782 | |
c496fa1f AJ |
1783 | if (I915_HAS_HOTPLUG(dev)) { |
1784 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1785 | ||
1786 | /* Note HDMI and DP share bits */ | |
1787 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1788 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1789 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1790 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1791 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1792 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1793 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1794 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1795 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1796 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1797 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1798 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1799 | |
1800 | /* Programming the CRT detection parameters tends | |
1801 | to generate a spurious hotplug event about three | |
1802 | seconds later. So just do it once. | |
1803 | */ | |
1804 | if (IS_G4X(dev)) | |
1805 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1806 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1807 | } | |
1808 | ||
c496fa1f AJ |
1809 | /* Ignore TV since it's buggy */ |
1810 | ||
1811 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1812 | } | |
1813 | ||
3b617967 | 1814 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1815 | |
1816 | return 0; | |
1da177e4 LT |
1817 | } |
1818 | ||
f2b115e6 | 1819 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1820 | { |
1821 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1822 | I915_WRITE(HWSTAM, 0xffffffff); | |
1823 | ||
1824 | I915_WRITE(DEIMR, 0xffffffff); | |
1825 | I915_WRITE(DEIER, 0x0); | |
1826 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1827 | ||
1828 | I915_WRITE(GTIMR, 0xffffffff); | |
1829 | I915_WRITE(GTIER, 0x0); | |
1830 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1831 | } | |
1832 | ||
84b1fd10 | 1833 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1834 | { |
1835 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1836 | |
1da177e4 LT |
1837 | if (!dev_priv) |
1838 | return; | |
1839 | ||
0a3e67a4 JB |
1840 | dev_priv->vblank_pipe = 0; |
1841 | ||
bad720ff | 1842 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1843 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1844 | return; |
1845 | } | |
1846 | ||
5ca58282 JB |
1847 | if (I915_HAS_HOTPLUG(dev)) { |
1848 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1849 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1850 | } | |
1851 | ||
0a3e67a4 | 1852 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1853 | I915_WRITE(PIPEASTAT, 0); |
1854 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1855 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1856 | I915_WRITE(IER, 0x0); |
af6061af | 1857 | |
7c463586 KP |
1858 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1859 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1860 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1861 | } |