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drm/i915/dp: Explicitly request 8/10 channel coding
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
63eeaf38 29#include <linux/sysrq.h>
5a0e3ad6 30#include <linux/slab.h>
1da177e4
LT		 31#include "drmP.h"
32#include "drm.h"
33#include "i915_drm.h"
34#include "i915_drv.h"
1c5d22f7 35#include "i915_trace.h"
79e53945 36#include "intel_drv.h"
1da177e4 37
1da177e4 38#define MAX_NOPID ((u32)~0)
1da177e4 39
7c463586
KP		 40/**
41 * Interrupts that are always left unmasked.
42 *
43 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
44 * we leave them always unmasked in IMR and then control enabling them through
45 * PIPESTAT alone.
46 */
6b95a207
KH		 47#define I915_INTERRUPT_ENABLE_FIX \
48 (I915_ASLE_INTERRUPT | \
49 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
50 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
51 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
52 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
53 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
7c463586
KP		 54
55/** Interrupts that we mask and unmask at runtime. */
d1b851fc 56#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
7c463586 57
79e53945
JB		 58#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
59 PIPE_VBLANK_INTERRUPT_STATUS)
60
61#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
62 PIPE_VBLANK_INTERRUPT_ENABLE)
63
64#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
65 DRM_I915_VBLANK_PIPE_B)
66
036a4a7d 67/* For display hotplug interrupt */
995b6762 68static void
f2b115e6 69ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 70{
1ec14ad3
CW		 71 if ((dev_priv->irq_mask & mask) != 0) {
72 dev_priv->irq_mask &= ~mask;
73 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 74 POSTING_READ(DEIMR);
036a4a7d
ZW		 75 }
76}
77
78static inline void
f2b115e6 79ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 80{
1ec14ad3
CW		 81 if ((dev_priv->irq_mask & mask) != mask) {
82 dev_priv->irq_mask |= mask;
83 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 84 POSTING_READ(DEIMR);
036a4a7d
ZW		 85 }
86}
87
7c463586
KP		 88void
89i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
90{
91 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 92 u32 reg = PIPESTAT(pipe);
7c463586
KP		 93
94 dev_priv->pipestat[pipe] |= mask;
95 /* Enable the interrupt, clear any pending status */
96 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 97 POSTING_READ(reg);
7c463586
KP		 98 }
99}
100
101void
102i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
103{
104 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 105 u32 reg = PIPESTAT(pipe);
7c463586
KP		 106
107 dev_priv->pipestat[pipe] &= ~mask;
108 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 109 POSTING_READ(reg);
7c463586
KP		 110 }
111}
112
01c66889
ZY		 113/**
114 * intel_enable_asle - enable ASLE interrupt for OpRegion
115 */
1ec14ad3 116void intel_enable_asle(struct drm_device *dev)
01c66889 117{
1ec14ad3
CW		 118 drm_i915_private_t *dev_priv = dev->dev_private;
119 unsigned long irqflags;
120
121 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 122
c619eed4 123 if (HAS_PCH_SPLIT(dev))
f2b115e6 124 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 125 else {
01c66889 126 i915_enable_pipestat(dev_priv, 1,
d874bcff 127 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 128 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 129 i915_enable_pipestat(dev_priv, 0,
d874bcff 130 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 131 }
1ec14ad3
CW		 132
133 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 134}
135
0a3e67a4
JB		 136/**
137 * i915_pipe_enabled - check if a pipe is enabled
138 * @dev: DRM device
139 * @pipe: pipe to check
140 *
141 * Reading certain registers when the pipe is disabled can hang the chip.
142 * Use this routine to make sure the PLL is running and the pipe is active
143 * before reading such registers if unsure.
144 */
145static int
146i915_pipe_enabled(struct drm_device *dev, int pipe)
147{
148 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 149 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 150}
151
42f52ef8
KP		 152/* Called from drm generic code, passed a 'crtc', which
153 * we use as a pipe index
154 */
f71d4af4 155static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 156{
157 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
158 unsigned long high_frame;
159 unsigned long low_frame;
5eddb70b 160 u32 high1, high2, low;
0a3e67a4
JB		 161
162 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 163 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 164 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 165 return 0;
166 }
167
9db4a9c7
JB		 168 high_frame = PIPEFRAME(pipe);
169 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 170
0a3e67a4
JB		 171 /*
172 * High & low register fields aren't synchronized, so make sure
173 * we get a low value that's stable across two reads of the high
174 * register.
175 */
176 do {
5eddb70b
CW		 177 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
178 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
179 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 180 } while (high1 != high2);
181
5eddb70b
CW		 182 high1 >>= PIPE_FRAME_HIGH_SHIFT;
183 low >>= PIPE_FRAME_LOW_SHIFT;
184 return (high1 << 8) | low;
0a3e67a4
JB		 185}
186
f71d4af4 187static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 188{
189 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 190 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 191
192 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 193 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 194 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 195 return 0;
196 }
197
198 return I915_READ(reg);
199}
200
f71d4af4 201static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 202 int *vpos, int *hpos)
203{
204 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
205 u32 vbl = 0, position = 0;
206 int vbl_start, vbl_end, htotal, vtotal;
207 bool in_vbl = true;
208 int ret = 0;
209
210 if (!i915_pipe_enabled(dev, pipe)) {
211 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 212 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 213 return 0;
214 }
215
216 /* Get vtotal. */
217 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
218
219 if (INTEL_INFO(dev)->gen >= 4) {
220 /* No obvious pixelcount register. Only query vertical
221 * scanout position from Display scan line register.
222 */
223 position = I915_READ(PIPEDSL(pipe));
224
225 /* Decode into vertical scanout position. Don't have
226 * horizontal scanout position.
227 */
228 *vpos = position & 0x1fff;
229 *hpos = 0;
230 } else {
231 /* Have access to pixelcount since start of frame.
232 * We can split this into vertical and horizontal
233 * scanout position.
234 */
235 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
236
237 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
238 *vpos = position / htotal;
239 *hpos = position - (*vpos * htotal);
240 }
241
242 /* Query vblank area. */
243 vbl = I915_READ(VBLANK(pipe));
244
245 /* Test position against vblank region. */
246 vbl_start = vbl & 0x1fff;
247 vbl_end = (vbl >> 16) & 0x1fff;
248
249 if ((*vpos < vbl_start) || (*vpos > vbl_end))
250 in_vbl = false;
251
252 /* Inside "upper part" of vblank area? Apply corrective offset: */
253 if (in_vbl && (*vpos >= vbl_start))
254 *vpos = *vpos - vtotal;
255
256 /* Readouts valid? */
257 if (vbl > 0)
258 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
259
260 /* In vblank? */
261 if (in_vbl)
262 ret |= DRM_SCANOUTPOS_INVBL;
263
264 return ret;
265}
266
f71d4af4 267static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 268 int *max_error,
269 struct timeval *vblank_time,
270 unsigned flags)
271{
4041b853
CW		 272 struct drm_i915_private *dev_priv = dev->dev_private;
273 struct drm_crtc *crtc;
0af7e4df 274
4041b853
CW		 275 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
276 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 277 return -EINVAL;
278 }
279
280 /* Get drm_crtc to timestamp: */
4041b853
CW		 281 crtc = intel_get_crtc_for_pipe(dev, pipe);
282 if (crtc == NULL) {
283 DRM_ERROR("Invalid crtc %d\n", pipe);
284 return -EINVAL;
285 }
286
287 if (!crtc->enabled) {
288 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
289 return -EBUSY;
290 }
0af7e4df
MK		 291
292 /* Helper routine in DRM core does all the work: */
4041b853
CW		 293 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
294 vblank_time, flags,
295 crtc);
0af7e4df
MK		 296}
297
5ca58282
JB		 298/*
299 * Handle hotplug events outside the interrupt handler proper.
300 */
301static void i915_hotplug_work_func(struct work_struct *work)
302{
303 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
304 hotplug_work);
305 struct drm_device *dev = dev_priv->dev;
c31c4ba3 306 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 307 struct intel_encoder *encoder;
308
e67189ab
JB		 309 DRM_DEBUG_KMS("running encoder hotplug functions\n");
310
4ef69c7a
CW		 311 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
312 if (encoder->hot_plug)
313 encoder->hot_plug(encoder);
314
5ca58282 315 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 316 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 317}
318
f97108d1
JB		 319static void i915_handle_rps_change(struct drm_device *dev)
320{
321 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 322 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 323 u8 new_delay = dev_priv->cur_delay;
324
7648fa99 325 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 326 busy_up = I915_READ(RCPREVBSYTUPAVG);
327 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 328 max_avg = I915_READ(RCBMAXAVG);
329 min_avg = I915_READ(RCBMINAVG);
330
331 /* Handle RCS change request from hw */
b5b72e89 332 if (busy_up > max_avg) {
f97108d1
JB		 333 if (dev_priv->cur_delay != dev_priv->max_delay)
334 new_delay = dev_priv->cur_delay - 1;
335 if (new_delay < dev_priv->max_delay)
336 new_delay = dev_priv->max_delay;
b5b72e89 337 } else if (busy_down < min_avg) {
f97108d1
JB		 338 if (dev_priv->cur_delay != dev_priv->min_delay)
339 new_delay = dev_priv->cur_delay + 1;
340 if (new_delay > dev_priv->min_delay)
341 new_delay = dev_priv->min_delay;
342 }
343
7648fa99
JB		 344 if (ironlake_set_drps(dev, new_delay))
345 dev_priv->cur_delay = new_delay;
f97108d1
JB		 346
347 return;
348}
349
549f7365
CW		 350static void notify_ring(struct drm_device *dev,
351 struct intel_ring_buffer *ring)
352{
353 struct drm_i915_private *dev_priv = dev->dev_private;
475553de 354 u32 seqno;
9862e600 355
475553de
CW		 356 if (ring->obj == NULL)
357 return;
358
359 seqno = ring->get_seqno(ring);
db53a302 360 trace_i915_gem_request_complete(ring, seqno);
9862e600
CW		 361
362 ring->irq_seqno = seqno;
549f7365 363 wake_up_all(&ring->irq_queue);
9862e600 364
549f7365
CW		 365 dev_priv->hangcheck_count = 0;
366 mod_timer(&dev_priv->hangcheck_timer,
367 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
368}
369
4912d041 370static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 371{
4912d041
BW		 372 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
373 rps_work);
3b8d8d91 374 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 375 u32 pm_iir, pm_imr;
376
377 spin_lock_irq(&dev_priv->rps_lock);
378 pm_iir = dev_priv->pm_iir;
379 dev_priv->pm_iir = 0;
380 pm_imr = I915_READ(GEN6_PMIMR);
381 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 382
3b8d8d91
JB		 383 if (!pm_iir)
384 return;
385
4912d041 386 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 387 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
388 if (dev_priv->cur_delay != dev_priv->max_delay)
389 new_delay = dev_priv->cur_delay + 1;
390 if (new_delay > dev_priv->max_delay)
391 new_delay = dev_priv->max_delay;
392 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 393 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 394 if (dev_priv->cur_delay != dev_priv->min_delay)
395 new_delay = dev_priv->cur_delay - 1;
396 if (new_delay < dev_priv->min_delay) {
397 new_delay = dev_priv->min_delay;
398 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
399 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
400 ((new_delay << 16) & 0x3f0000));
401 } else {
402 /* Make sure we continue to get down interrupts
403 * until we hit the minimum frequency */
404 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
405 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
406 }
4912d041 407 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 408 }
409
4912d041 410 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 411 dev_priv->cur_delay = new_delay;
412
4912d041
BW		 413 /*
414 * rps_lock not held here because clearing is non-destructive. There is
415 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
416 * by holding struct_mutex for the duration of the write.
417 */
418 I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir);
419 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 420}
421
776ad806
JB		 422static void pch_irq_handler(struct drm_device *dev)
423{
424 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
425 u32 pch_iir;
9db4a9c7 426 int pipe;
776ad806
JB		 427
428 pch_iir = I915_READ(SDEIIR);
429
430 if (pch_iir & SDE_AUDIO_POWER_MASK)
431 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
432 (pch_iir & SDE_AUDIO_POWER_MASK) >>
433 SDE_AUDIO_POWER_SHIFT);
434
435 if (pch_iir & SDE_GMBUS)
436 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
437
438 if (pch_iir & SDE_AUDIO_HDCP_MASK)
439 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
440
441 if (pch_iir & SDE_AUDIO_TRANS_MASK)
442 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
443
444 if (pch_iir & SDE_POISON)
445 DRM_ERROR("PCH poison interrupt\n");
446
9db4a9c7
JB		 447 if (pch_iir & SDE_FDI_MASK)
448 for_each_pipe(pipe)
449 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
450 pipe_name(pipe),
451 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 452
453 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
454 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
455
456 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
457 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
458
459 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
460 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
461 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
462 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
463}
464
f71d4af4 465static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 466{
467 struct drm_device *dev = (struct drm_device *) arg;
468 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
469 int ret = IRQ_NONE;
470 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
471 struct drm_i915_master_private *master_priv;
472
473 atomic_inc(&dev_priv->irq_received);
474
475 /* disable master interrupt before clearing iir */
476 de_ier = I915_READ(DEIER);
477 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
478 POSTING_READ(DEIER);
479
480 de_iir = I915_READ(DEIIR);
481 gt_iir = I915_READ(GTIIR);
482 pch_iir = I915_READ(SDEIIR);
483 pm_iir = I915_READ(GEN6_PMIIR);
484
485 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
486 goto done;
487
488 ret = IRQ_HANDLED;
489
490 if (dev->primary->master) {
491 master_priv = dev->primary->master->driver_priv;
492 if (master_priv->sarea_priv)
493 master_priv->sarea_priv->last_dispatch =
494 READ_BREADCRUMB(dev_priv);
495 }
496
497 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
498 notify_ring(dev, &dev_priv->ring[RCS]);
499 if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
500 notify_ring(dev, &dev_priv->ring[VCS]);
501 if (gt_iir & GT_BLT_USER_INTERRUPT)
502 notify_ring(dev, &dev_priv->ring[BCS]);
503
504 if (de_iir & DE_GSE_IVB)
505 intel_opregion_gse_intr(dev);
506
507 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
508 intel_prepare_page_flip(dev, 0);
509 intel_finish_page_flip_plane(dev, 0);
510 }
511
512 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
513 intel_prepare_page_flip(dev, 1);
514 intel_finish_page_flip_plane(dev, 1);
515 }
516
517 if (de_iir & DE_PIPEA_VBLANK_IVB)
518 drm_handle_vblank(dev, 0);
519
f6b07f45 520 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 521 drm_handle_vblank(dev, 1);
522
523 /* check event from PCH */
524 if (de_iir & DE_PCH_EVENT_IVB) {
525 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
526 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
527 pch_irq_handler(dev);
528 }
529
530 if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
531 unsigned long flags;
532 spin_lock_irqsave(&dev_priv->rps_lock, flags);
533 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
534 I915_WRITE(GEN6_PMIMR, pm_iir);
535 dev_priv->pm_iir |= pm_iir;
536 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
537 queue_work(dev_priv->wq, &dev_priv->rps_work);
538 }
539
540 /* should clear PCH hotplug event before clear CPU irq */
541 I915_WRITE(SDEIIR, pch_iir);
542 I915_WRITE(GTIIR, gt_iir);
543 I915_WRITE(DEIIR, de_iir);
544 I915_WRITE(GEN6_PMIIR, pm_iir);
545
546done:
547 I915_WRITE(DEIER, de_ier);
548 POSTING_READ(DEIER);
549
550 return ret;
551}
552
f71d4af4 553static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 554{
4697995b 555 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 556 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
557 int ret = IRQ_NONE;
3b8d8d91 558 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 559 u32 hotplug_mask;
036a4a7d 560 struct drm_i915_master_private *master_priv;
881f47b6
XH		 561 u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
562
4697995b
JB		 563 atomic_inc(&dev_priv->irq_received);
564
881f47b6
XH		 565 if (IS_GEN6(dev))
566 bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
036a4a7d 567
2d109a84
ZN		 568 /* disable master interrupt before clearing iir */
569 de_ier = I915_READ(DEIER);
570 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 571 POSTING_READ(DEIER);
2d109a84 572
036a4a7d
ZW		 573 de_iir = I915_READ(DEIIR);
574 gt_iir = I915_READ(GTIIR);
c650156a 575 pch_iir = I915_READ(SDEIIR);
3b8d8d91 576 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 577
3b8d8d91
JB		 578 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
579 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 580 goto done;
036a4a7d 581
2d7b8366
YL		 582 if (HAS_PCH_CPT(dev))
583 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
584 else
585 hotplug_mask = SDE_HOTPLUG_MASK;
586
c7c85101 587 ret = IRQ_HANDLED;
036a4a7d 588
c7c85101
ZN		 589 if (dev->primary->master) {
590 master_priv = dev->primary->master->driver_priv;
591 if (master_priv->sarea_priv)
592 master_priv->sarea_priv->last_dispatch =
593 READ_BREADCRUMB(dev_priv);
594 }
036a4a7d 595
c6df541c 596 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
1ec14ad3 597 notify_ring(dev, &dev_priv->ring[RCS]);
881f47b6 598 if (gt_iir & bsd_usr_interrupt)
1ec14ad3
CW		 599 notify_ring(dev, &dev_priv->ring[VCS]);
600 if (gt_iir & GT_BLT_USER_INTERRUPT)
601 notify_ring(dev, &dev_priv->ring[BCS]);
01c66889 602
c7c85101 603 if (de_iir & DE_GSE)
3b617967 604 intel_opregion_gse_intr(dev);
c650156a 605
f072d2e7 606 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 607 intel_prepare_page_flip(dev, 0);
2bbda389 608 intel_finish_page_flip_plane(dev, 0);
f072d2e7 609 }
013d5aa2 610
f072d2e7 611 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 612 intel_prepare_page_flip(dev, 1);
2bbda389 613 intel_finish_page_flip_plane(dev, 1);
f072d2e7 614 }
013d5aa2 615
f072d2e7 616 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 617 drm_handle_vblank(dev, 0);
618
f072d2e7 619 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 620 drm_handle_vblank(dev, 1);
621
c7c85101 622 /* check event from PCH */
776ad806
JB		 623 if (de_iir & DE_PCH_EVENT) {
624 if (pch_iir & hotplug_mask)
625 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
626 pch_irq_handler(dev);
627 }
036a4a7d 628
f97108d1 629 if (de_iir & DE_PCU_EVENT) {
7648fa99 630 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 631 i915_handle_rps_change(dev);
632 }
633
4912d041
BW		 634 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
635 /*
636 * IIR bits should never already be set because IMR should
637 * prevent an interrupt from being shown in IIR. The warning
638 * displays a case where we've unsafely cleared
639 * dev_priv->pm_iir. Although missing an interrupt of the same
640 * type is not a problem, it displays a problem in the logic.
641 *
642 * The mask bit in IMR is cleared by rps_work.
643 */
644 unsigned long flags;
645 spin_lock_irqsave(&dev_priv->rps_lock, flags);
646 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
647 I915_WRITE(GEN6_PMIMR, pm_iir);
648 dev_priv->pm_iir |= pm_iir;
649 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
650 queue_work(dev_priv->wq, &dev_priv->rps_work);
651 }
3b8d8d91 652
c7c85101
ZN		 653 /* should clear PCH hotplug event before clear CPU irq */
654 I915_WRITE(SDEIIR, pch_iir);
655 I915_WRITE(GTIIR, gt_iir);
656 I915_WRITE(DEIIR, de_iir);
4912d041 657 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 658
659done:
2d109a84 660 I915_WRITE(DEIER, de_ier);
3143a2bf 661 POSTING_READ(DEIER);
2d109a84 662
036a4a7d
ZW		 663 return ret;
664}
665
8a905236
JB		 666/**
667 * i915_error_work_func - do process context error handling work
668 * @work: work struct
669 *
670 * Fire an error uevent so userspace can see that a hang or error
671 * was detected.
672 */
673static void i915_error_work_func(struct work_struct *work)
674{
675 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
676 error_work);
677 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 678 char *error_event[] = { "ERROR=1", NULL };
679 char *reset_event[] = { "RESET=1", NULL };
680 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 681
f316a42c
BG		 682 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
683
ba1234d1 684 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 685 DRM_DEBUG_DRIVER("resetting chip\n");
686 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
687 if (!i915_reset(dev, GRDOM_RENDER)) {
688 atomic_set(&dev_priv->mm.wedged, 0);
689 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 690 }
30dbf0c0 691 complete_all(&dev_priv->error_completion);
f316a42c 692 }
8a905236
JB		 693}
694
3bd3c932 695#ifdef CONFIG_DEBUG_FS
9df30794 696static struct drm_i915_error_object *
bcfb2e28 697i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 698 struct drm_i915_gem_object *src)
9df30794
CW		 699{
700 struct drm_i915_error_object *dst;
9df30794 701 int page, page_count;
e56660dd 702 u32 reloc_offset;
9df30794 703
05394f39 704 if (src == NULL || src->pages == NULL)
9df30794
CW		 705 return NULL;
706
05394f39 707 page_count = src->base.size / PAGE_SIZE;
9df30794
CW		 708
709 dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC);
710 if (dst == NULL)
711 return NULL;
712
05394f39 713 reloc_offset = src->gtt_offset;
9df30794 714 for (page = 0; page < page_count; page++) {
788885ae 715 unsigned long flags;
e56660dd
CW		 716 void __iomem *s;
717 void *d;
788885ae 718
e56660dd 719 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 720 if (d == NULL)
721 goto unwind;
e56660dd 722
788885ae 723 local_irq_save(flags);
e56660dd 724 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3e4d3af5 725 reloc_offset);
e56660dd 726 memcpy_fromio(d, s, PAGE_SIZE);
3e4d3af5 727 io_mapping_unmap_atomic(s);
788885ae 728 local_irq_restore(flags);
e56660dd 729
9df30794 730 dst->pages[page] = d;
e56660dd
CW		 731
732 reloc_offset += PAGE_SIZE;
9df30794
CW		 733 }
734 dst->page_count = page_count;
05394f39 735 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 736
737 return dst;
738
739unwind:
740 while (page--)
741 kfree(dst->pages[page]);
742 kfree(dst);
743 return NULL;
744}
745
746static void
747i915_error_object_free(struct drm_i915_error_object *obj)
748{
749 int page;
750
751 if (obj == NULL)
752 return;
753
754 for (page = 0; page < obj->page_count; page++)
755 kfree(obj->pages[page]);
756
757 kfree(obj);
758}
759
760static void
761i915_error_state_free(struct drm_device *dev,
762 struct drm_i915_error_state *error)
763{
e2f973d5
CW		 764 int i;
765
766 for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++)
767 i915_error_object_free(error->batchbuffer[i]);
768
769 for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++)
770 i915_error_object_free(error->ringbuffer[i]);
771
9df30794 772 kfree(error->active_bo);
6ef3d427 773 kfree(error->overlay);
9df30794
CW		 774 kfree(error);
775}
776
c724e8a9
CW		 777static u32 capture_bo_list(struct drm_i915_error_buffer *err,
778 int count,
779 struct list_head *head)
780{
781 struct drm_i915_gem_object *obj;
782 int i = 0;
783
784 list_for_each_entry(obj, head, mm_list) {
785 err->size = obj->base.size;
786 err->name = obj->base.name;
787 err->seqno = obj->last_rendering_seqno;
788 err->gtt_offset = obj->gtt_offset;
789 err->read_domains = obj->base.read_domains;
790 err->write_domain = obj->base.write_domain;
791 err->fence_reg = obj->fence_reg;
792 err->pinned = 0;
793 if (obj->pin_count > 0)
794 err->pinned = 1;
795 if (obj->user_pin_count > 0)
796 err->pinned = -1;
797 err->tiling = obj->tiling_mode;
798 err->dirty = obj->dirty;
799 err->purgeable = obj->madv != I915_MADV_WILLNEED;
3685092b 800 err->ring = obj->ring ? obj->ring->id : 0;
93dfb40c 801 err->cache_level = obj->cache_level;
c724e8a9
CW		 802
803 if (++i == count)
804 break;
805
806 err++;
807 }
808
809 return i;
810}
811
748ebc60
CW		 812static void i915_gem_record_fences(struct drm_device *dev,
813 struct drm_i915_error_state *error)
814{
815 struct drm_i915_private *dev_priv = dev->dev_private;
816 int i;
817
818 /* Fences */
819 switch (INTEL_INFO(dev)->gen) {
820 case 6:
821 for (i = 0; i < 16; i++)
822 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
823 break;
824 case 5:
825 case 4:
826 for (i = 0; i < 16; i++)
827 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
828 break;
829 case 3:
830 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
831 for (i = 0; i < 8; i++)
832 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
833 case 2:
834 for (i = 0; i < 8; i++)
835 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
836 break;
837
838 }
839}
840
bcfb2e28
CW		 841static struct drm_i915_error_object *
842i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
843 struct intel_ring_buffer *ring)
844{
845 struct drm_i915_gem_object *obj;
846 u32 seqno;
847
848 if (!ring->get_seqno)
849 return NULL;
850
851 seqno = ring->get_seqno(ring);
852 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
853 if (obj->ring != ring)
854 continue;
855
c37d9a5d 856 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 857 continue;
858
859 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
860 continue;
861
862 /* We need to copy these to an anonymous buffer as the simplest
863 * method to avoid being overwritten by userspace.
864 */
865 return i915_error_object_create(dev_priv, obj);
866 }
867
868 return NULL;
869}
870
8a905236
JB		 871/**
872 * i915_capture_error_state - capture an error record for later analysis
873 * @dev: drm device
874 *
875 * Should be called when an error is detected (either a hang or an error
876 * interrupt) to capture error state from the time of the error. Fills
877 * out a structure which becomes available in debugfs for user level tools
878 * to pick up.
879 */
63eeaf38
JB		 880static void i915_capture_error_state(struct drm_device *dev)
881{
882 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 883 struct drm_i915_gem_object *obj;
63eeaf38
JB		 884 struct drm_i915_error_state *error;
885 unsigned long flags;
9db4a9c7 886 int i, pipe;
63eeaf38
JB		 887
888 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 889 error = dev_priv->first_error;
890 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
891 if (error)
892 return;
63eeaf38 893
9db4a9c7 894 /* Account for pipe specific data like PIPE*STAT */
63eeaf38
JB		 895 error = kmalloc(sizeof(*error), GFP_ATOMIC);
896 if (!error) {
9df30794
CW		 897 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
898 return;
63eeaf38
JB		 899 }
900
b6f7833b
CW		 901 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
902 dev->primary->index);
2fa772f3 903
1ec14ad3 904 error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]);
63eeaf38
JB		 905 error->eir = I915_READ(EIR);
906 error->pgtbl_er = I915_READ(PGTBL_ER);
9db4a9c7
JB		 907 for_each_pipe(pipe)
908 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
63eeaf38 909 error->instpm = I915_READ(INSTPM);
f406839f
CW		 910 error->error = 0;
911 if (INTEL_INFO(dev)->gen >= 6) {
912 error->error = I915_READ(ERROR_GEN6);
add354dd 913
1d8f38f4
CW		 914 error->bcs_acthd = I915_READ(BCS_ACTHD);
915 error->bcs_ipehr = I915_READ(BCS_IPEHR);
916 error->bcs_ipeir = I915_READ(BCS_IPEIR);
917 error->bcs_instdone = I915_READ(BCS_INSTDONE);
918 error->bcs_seqno = 0;
1ec14ad3
CW		 919 if (dev_priv->ring[BCS].get_seqno)
920 error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]);
add354dd
CW		 921
922 error->vcs_acthd = I915_READ(VCS_ACTHD);
923 error->vcs_ipehr = I915_READ(VCS_IPEHR);
924 error->vcs_ipeir = I915_READ(VCS_IPEIR);
925 error->vcs_instdone = I915_READ(VCS_INSTDONE);
926 error->vcs_seqno = 0;
1ec14ad3
CW		 927 if (dev_priv->ring[VCS].get_seqno)
928 error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]);
f406839f
CW		 929 }
930 if (INTEL_INFO(dev)->gen >= 4) {
63eeaf38
JB		 931 error->ipeir = I915_READ(IPEIR_I965);
932 error->ipehr = I915_READ(IPEHR_I965);
933 error->instdone = I915_READ(INSTDONE_I965);
934 error->instps = I915_READ(INSTPS);
935 error->instdone1 = I915_READ(INSTDONE1);
936 error->acthd = I915_READ(ACTHD_I965);
9df30794 937 error->bbaddr = I915_READ64(BB_ADDR);
f406839f
CW		 938 } else {
939 error->ipeir = I915_READ(IPEIR);
940 error->ipehr = I915_READ(IPEHR);
941 error->instdone = I915_READ(INSTDONE);
942 error->acthd = I915_READ(ACTHD);
943 error->bbaddr = 0;
63eeaf38 944 }
748ebc60 945 i915_gem_record_fences(dev, error);
63eeaf38 946
e2f973d5
CW		 947 /* Record the active batch and ring buffers */
948 for (i = 0; i < I915_NUM_RINGS; i++) {
bcfb2e28
CW		 949 error->batchbuffer[i] =
950 i915_error_first_batchbuffer(dev_priv,
951 &dev_priv->ring[i]);
9df30794 952
e2f973d5
CW		 953 error->ringbuffer[i] =
954 i915_error_object_create(dev_priv,
955 dev_priv->ring[i].obj);
956 }
9df30794 957
c724e8a9 958 /* Record buffers on the active and pinned lists. */
9df30794 959 error->active_bo = NULL;
c724e8a9 960 error->pinned_bo = NULL;
9df30794 961
bcfb2e28
CW		 962 i = 0;
963 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
964 i++;
965 error->active_bo_count = i;
05394f39 966 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
bcfb2e28
CW		 967 i++;
968 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 969
8e934dbf
CW		 970 error->active_bo = NULL;
971 error->pinned_bo = NULL;
bcfb2e28
CW		 972 if (i) {
973 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 974 GFP_ATOMIC);
c724e8a9
CW		 975 if (error->active_bo)
976 error->pinned_bo =
977 error->active_bo + error->active_bo_count;
9df30794
CW		 978 }
979
c724e8a9
CW		 980 if (error->active_bo)
981 error->active_bo_count =
982 capture_bo_list(error->active_bo,
983 error->active_bo_count,
984 &dev_priv->mm.active_list);
985
986 if (error->pinned_bo)
987 error->pinned_bo_count =
988 capture_bo_list(error->pinned_bo,
989 error->pinned_bo_count,
990 &dev_priv->mm.pinned_list);
991
9df30794
CW		 992 do_gettimeofday(&error->time);
993
6ef3d427 994 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 995 error->display = intel_display_capture_error_state(dev);
6ef3d427 996
9df30794
CW		 997 spin_lock_irqsave(&dev_priv->error_lock, flags);
998 if (dev_priv->first_error == NULL) {
999 dev_priv->first_error = error;
1000 error = NULL;
1001 }
63eeaf38 1002 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1003
1004 if (error)
1005 i915_error_state_free(dev, error);
1006}
1007
1008void i915_destroy_error_state(struct drm_device *dev)
1009{
1010 struct drm_i915_private *dev_priv = dev->dev_private;
1011 struct drm_i915_error_state *error;
1012
1013 spin_lock(&dev_priv->error_lock);
1014 error = dev_priv->first_error;
1015 dev_priv->first_error = NULL;
1016 spin_unlock(&dev_priv->error_lock);
1017
1018 if (error)
1019 i915_error_state_free(dev, error);
63eeaf38 1020}
3bd3c932
CW		 1021#else
1022#define i915_capture_error_state(x)
1023#endif
63eeaf38 1024
35aed2e6 1025static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1026{
1027 struct drm_i915_private *dev_priv = dev->dev_private;
1028 u32 eir = I915_READ(EIR);
9db4a9c7 1029 int pipe;
8a905236 1030
35aed2e6
CW		 1031 if (!eir)
1032 return;
8a905236
JB		 1033
1034 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
1035 eir);
1036
1037 if (IS_G4X(dev)) {
1038 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1039 u32 ipeir = I915_READ(IPEIR_I965);
1040
1041 printk(KERN_ERR " IPEIR: 0x%08x\n",
1042 I915_READ(IPEIR_I965));
1043 printk(KERN_ERR " IPEHR: 0x%08x\n",
1044 I915_READ(IPEHR_I965));
1045 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1046 I915_READ(INSTDONE_I965));
1047 printk(KERN_ERR " INSTPS: 0x%08x\n",
1048 I915_READ(INSTPS));
1049 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1050 I915_READ(INSTDONE1));
1051 printk(KERN_ERR " ACTHD: 0x%08x\n",
1052 I915_READ(ACTHD_I965));
1053 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1054 POSTING_READ(IPEIR_I965);
8a905236
JB		 1055 }
1056 if (eir & GM45_ERROR_PAGE_TABLE) {
1057 u32 pgtbl_err = I915_READ(PGTBL_ER);
1058 printk(KERN_ERR "page table error\n");
1059 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
1060 pgtbl_err);
1061 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1062 POSTING_READ(PGTBL_ER);
8a905236
JB		 1063 }
1064 }
1065
a6c45cf0 1066 if (!IS_GEN2(dev)) {
8a905236
JB		 1067 if (eir & I915_ERROR_PAGE_TABLE) {
1068 u32 pgtbl_err = I915_READ(PGTBL_ER);
1069 printk(KERN_ERR "page table error\n");
1070 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
1071 pgtbl_err);
1072 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1073 POSTING_READ(PGTBL_ER);
8a905236
JB		 1074 }
1075 }
1076
1077 if (eir & I915_ERROR_MEMORY_REFRESH) {
9db4a9c7
JB		 1078 printk(KERN_ERR "memory refresh error:\n");
1079 for_each_pipe(pipe)
1080 printk(KERN_ERR "pipe %c stat: 0x%08x\n",
1081 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1082 /* pipestat has already been acked */
1083 }
1084 if (eir & I915_ERROR_INSTRUCTION) {
1085 printk(KERN_ERR "instruction error\n");
1086 printk(KERN_ERR " INSTPM: 0x%08x\n",
1087 I915_READ(INSTPM));
a6c45cf0 1088 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1089 u32 ipeir = I915_READ(IPEIR);
1090
1091 printk(KERN_ERR " IPEIR: 0x%08x\n",
1092 I915_READ(IPEIR));
1093 printk(KERN_ERR " IPEHR: 0x%08x\n",
1094 I915_READ(IPEHR));
1095 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1096 I915_READ(INSTDONE));
1097 printk(KERN_ERR " ACTHD: 0x%08x\n",
1098 I915_READ(ACTHD));
1099 I915_WRITE(IPEIR, ipeir);
3143a2bf 1100 POSTING_READ(IPEIR);
8a905236
JB		 1101 } else {
1102 u32 ipeir = I915_READ(IPEIR_I965);
1103
1104 printk(KERN_ERR " IPEIR: 0x%08x\n",
1105 I915_READ(IPEIR_I965));
1106 printk(KERN_ERR " IPEHR: 0x%08x\n",
1107 I915_READ(IPEHR_I965));
1108 printk(KERN_ERR " INSTDONE: 0x%08x\n",
1109 I915_READ(INSTDONE_I965));
1110 printk(KERN_ERR " INSTPS: 0x%08x\n",
1111 I915_READ(INSTPS));
1112 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
1113 I915_READ(INSTDONE1));
1114 printk(KERN_ERR " ACTHD: 0x%08x\n",
1115 I915_READ(ACTHD_I965));
1116 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1117 POSTING_READ(IPEIR_I965);
8a905236
JB		 1118 }
1119 }
1120
1121 I915_WRITE(EIR, eir);
3143a2bf 1122 POSTING_READ(EIR);
8a905236
JB		 1123 eir = I915_READ(EIR);
1124 if (eir) {
1125 /*
1126 * some errors might have become stuck,
1127 * mask them.
1128 */
1129 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1130 I915_WRITE(EMR, I915_READ(EMR) | eir);
1131 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1132 }
35aed2e6
CW		 1133}
1134
1135/**
1136 * i915_handle_error - handle an error interrupt
1137 * @dev: drm device
1138 *
1139 * Do some basic checking of regsiter state at error interrupt time and
1140 * dump it to the syslog. Also call i915_capture_error_state() to make
1141 * sure we get a record and make it available in debugfs. Fire a uevent
1142 * so userspace knows something bad happened (should trigger collection
1143 * of a ring dump etc.).
1144 */
527f9e90 1145void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1146{
1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148
1149 i915_capture_error_state(dev);
1150 i915_report_and_clear_eir(dev);
8a905236 1151
ba1234d1 1152 if (wedged) {
30dbf0c0 1153 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1154 atomic_set(&dev_priv->mm.wedged, 1);
1155
11ed50ec
BG		 1156 /*
1157 * Wakeup waiting processes so they don't hang
1158 */
1ec14ad3 1159 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1160 if (HAS_BSD(dev))
1ec14ad3 1161 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1162 if (HAS_BLT(dev))
1ec14ad3 1163 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1164 }
1165
9c9fe1f8 1166 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1167}
1168
4e5359cd
SF		 1169static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1170{
1171 drm_i915_private_t *dev_priv = dev->dev_private;
1172 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1174 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1175 struct intel_unpin_work *work;
1176 unsigned long flags;
1177 bool stall_detected;
1178
1179 /* Ignore early vblank irqs */
1180 if (intel_crtc == NULL)
1181 return;
1182
1183 spin_lock_irqsave(&dev->event_lock, flags);
1184 work = intel_crtc->unpin_work;
1185
1186 if (work == NULL || work->pending || !work->enable_stall_check) {
1187 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1188 spin_unlock_irqrestore(&dev->event_lock, flags);
1189 return;
1190 }
1191
1192 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1193 obj = work->pending_flip_obj;
a6c45cf0 1194 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1195 int dspsurf = DSPSURF(intel_crtc->plane);
05394f39 1196 stall_detected = I915_READ(dspsurf) == obj->gtt_offset;
4e5359cd 1197 } else {
9db4a9c7 1198 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1199 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
4e5359cd
SF		 1200 crtc->y * crtc->fb->pitch +
1201 crtc->x * crtc->fb->bits_per_pixel/8);
1202 }
1203
1204 spin_unlock_irqrestore(&dev->event_lock, flags);
1205
1206 if (stall_detected) {
1207 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1208 intel_prepare_page_flip(dev, intel_crtc->plane);
1209 }
1210}
1211
f71d4af4 1212static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
1da177e4 1213{
84b1fd10 1214 struct drm_device *dev = (struct drm_device *) arg;
1da177e4 1215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 1216 struct drm_i915_master_private *master_priv;
cdfbc41f 1217 u32 iir, new_iir;
9db4a9c7 1218 u32 pipe_stats[I915_MAX_PIPES];
05eff845 1219 u32 vblank_status;
0a3e67a4 1220 int vblank = 0;
7c463586 1221 unsigned long irqflags;
05eff845 1222 int irq_received;
9db4a9c7
JB		 1223 int ret = IRQ_NONE, pipe;
1224 bool blc_event = false;
6e5fca53 1225
630681d9
EA		 1226 atomic_inc(&dev_priv->irq_received);
1227
ed4cb414 1228 iir = I915_READ(IIR);
a6b54f3f 1229
a6c45cf0 1230 if (INTEL_INFO(dev)->gen >= 4)
d874bcff 1231 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
e25e6601 1232 else
d874bcff 1233 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
af6061af 1234
05eff845
KP		 1235 for (;;) {
1236 irq_received = iir != 0;
1237
1238 /* Can't rely on pipestat interrupt bit in iir as it might
1239 * have been cleared after the pipestat interrupt was received.
1240 * It doesn't set the bit in iir again, but it still produces
1241 * interrupts (for non-MSI).
1242 */
1ec14ad3 1243 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8a905236 1244 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
ba1234d1 1245 i915_handle_error(dev, false);
8a905236 1246
9db4a9c7
JB		 1247 for_each_pipe(pipe) {
1248 int reg = PIPESTAT(pipe);
1249 pipe_stats[pipe] = I915_READ(reg);
1250
1251 /*
1252 * Clear the PIPE*STAT regs before the IIR
1253 */
1254 if (pipe_stats[pipe] & 0x8000ffff) {
1255 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1256 DRM_DEBUG_DRIVER("pipe %c underrun\n",
1257 pipe_name(pipe));
1258 I915_WRITE(reg, pipe_stats[pipe]);
1259 irq_received = 1;
1260 }
cdfbc41f 1261 }
1ec14ad3 1262 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
05eff845
KP		 1263
1264 if (!irq_received)
1265 break;
1266
1267 ret = IRQ_HANDLED;
8ee1c3db 1268
5ca58282
JB		 1269 /* Consume port. Then clear IIR or we'll miss events */
1270 if ((I915_HAS_HOTPLUG(dev)) &&
1271 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
1272 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1273
44d98a61 1274 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
5ca58282
JB		 1275 hotplug_status);
1276 if (hotplug_status & dev_priv->hotplug_supported_mask)
9c9fe1f8
EA		 1277 queue_work(dev_priv->wq,
1278 &dev_priv->hotplug_work);
5ca58282
JB		 1279
1280 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1281 I915_READ(PORT_HOTPLUG_STAT);
1282 }
1283
cdfbc41f
EA		 1284 I915_WRITE(IIR, iir);
1285 new_iir = I915_READ(IIR); /* Flush posted writes */
7c463586 1286
7c1c2871
DA		 1287 if (dev->primary->master) {
1288 master_priv = dev->primary->master->driver_priv;
1289 if (master_priv->sarea_priv)
1290 master_priv->sarea_priv->last_dispatch =
1291 READ_BREADCRUMB(dev_priv);
1292 }
0a3e67a4 1293
549f7365 1294 if (iir & I915_USER_INTERRUPT)
1ec14ad3
CW		 1295 notify_ring(dev, &dev_priv->ring[RCS]);
1296 if (iir & I915_BSD_USER_INTERRUPT)
1297 notify_ring(dev, &dev_priv->ring[VCS]);
d1b851fc 1298
1afe3e9d 1299 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
6b95a207 1300 intel_prepare_page_flip(dev, 0);
1afe3e9d
JB		 1301 if (dev_priv->flip_pending_is_done)
1302 intel_finish_page_flip_plane(dev, 0);
1303 }
6b95a207 1304
1afe3e9d 1305 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
70565d00 1306 intel_prepare_page_flip(dev, 1);
1afe3e9d
JB		 1307 if (dev_priv->flip_pending_is_done)
1308 intel_finish_page_flip_plane(dev, 1);
1afe3e9d 1309 }
6b95a207 1310
9db4a9c7
JB		 1311 for_each_pipe(pipe) {
1312 if (pipe_stats[pipe] & vblank_status &&
1313 drm_handle_vblank(dev, pipe)) {
1314 vblank++;
1315 if (!dev_priv->flip_pending_is_done) {
1316 i915_pageflip_stall_check(dev, pipe);
1317 intel_finish_page_flip(dev, pipe);
1318 }
4e5359cd 1319 }
7c463586 1320
9db4a9c7
JB		 1321 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1322 blc_event = true;
cdfbc41f 1323 }
7c463586 1324
9db4a9c7
JB		 1325
1326 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3b617967 1327 intel_opregion_asle_intr(dev);
cdfbc41f
EA		 1328
1329 /* With MSI, interrupts are only generated when iir
1330 * transitions from zero to nonzero. If another bit got
1331 * set while we were handling the existing iir bits, then
1332 * we would never get another interrupt.
1333 *
1334 * This is fine on non-MSI as well, as if we hit this path
1335 * we avoid exiting the interrupt handler only to generate
1336 * another one.
1337 *
1338 * Note that for MSI this could cause a stray interrupt report
1339 * if an interrupt landed in the time between writing IIR and
1340 * the posting read. This should be rare enough to never
1341 * trigger the 99% of 100,000 interrupts test for disabling
1342 * stray interrupts.
1343 */
1344 iir = new_iir;
05eff845 1345 }
0a3e67a4 1346
05eff845 1347 return ret;
1da177e4
LT		 1348}
1349
af6061af 1350static int i915_emit_irq(struct drm_device * dev)
1da177e4
LT		 1351{
1352 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 1353 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 1354
1355 i915_kernel_lost_context(dev);
1356
44d98a61 1357 DRM_DEBUG_DRIVER("\n");
1da177e4 1358
c99b058f 1359 dev_priv->counter++;
c29b669c 1360 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 1361 dev_priv->counter = 1;
7c1c2871
DA		 1362 if (master_priv->sarea_priv)
1363 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c 1364
e1f99ce6
CW		 1365 if (BEGIN_LP_RING(4) == 0) {
1366 OUT_RING(MI_STORE_DWORD_INDEX);
1367 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1368 OUT_RING(dev_priv->counter);
1369 OUT_RING(MI_USER_INTERRUPT);
1370 ADVANCE_LP_RING();
1371 }
bc5f4523 1372
c29b669c 1373 return dev_priv->counter;
1da177e4
LT		 1374}
1375
84b1fd10 1376static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4
LT		 1377{
1378 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 1379 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 1380 int ret = 0;
1ec14ad3 1381 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 1382
44d98a61 1383 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4
LT		 1384 READ_BREADCRUMB(dev_priv));
1385
ed4cb414 1386 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
7c1c2871
DA		 1387 if (master_priv->sarea_priv)
1388 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1da177e4 1389 return 0;
ed4cb414 1390 }
1da177e4 1391
7c1c2871
DA		 1392 if (master_priv->sarea_priv)
1393 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1da177e4 1394
b13c2b96
CW		 1395 if (ring->irq_get(ring)) {
1396 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1397 READ_BREADCRUMB(dev_priv) >= irq_nr);
1398 ring->irq_put(ring);
5a9a8d1a
CW		 1399 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1400 ret = -EBUSY;
1da177e4 1401
20caafa6 1402 if (ret == -EBUSY) {
3e684eae 1403 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4
LT		 1404 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1405 }
1406
af6061af
DA		 1407 return ret;
1408}
1409
1da177e4
LT		 1410/* Needs the lock as it touches the ring.
1411 */
c153f45f
EA		 1412int i915_irq_emit(struct drm_device *dev, void *data,
1413 struct drm_file *file_priv)
1da177e4 1414{
1da177e4 1415 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1416 drm_i915_irq_emit_t *emit = data;
1da177e4
LT		 1417 int result;
1418
1ec14ad3 1419 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
3e684eae 1420 DRM_ERROR("called with no initialization\n");
20caafa6 1421 return -EINVAL;
1da177e4 1422 }
299eb93c
EA		 1423
1424 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1425
546b0974 1426 mutex_lock(&dev->struct_mutex);
1da177e4 1427 result = i915_emit_irq(dev);
546b0974 1428 mutex_unlock(&dev->struct_mutex);
1da177e4 1429
c153f45f 1430 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4 1431 DRM_ERROR("copy_to_user\n");
20caafa6 1432 return -EFAULT;
1da177e4
LT		 1433 }
1434
1435 return 0;
1436}
1437
1438/* Doesn't need the hardware lock.
1439 */
c153f45f
EA		 1440int i915_irq_wait(struct drm_device *dev, void *data,
1441 struct drm_file *file_priv)
1da177e4 1442{
1da177e4 1443 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1444 drm_i915_irq_wait_t *irqwait = data;
1da177e4
LT		 1445
1446 if (!dev_priv) {
3e684eae 1447 DRM_ERROR("called with no initialization\n");
20caafa6 1448 return -EINVAL;
1da177e4
LT		 1449 }
1450
c153f45f 1451 return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4
LT		 1452}
1453
42f52ef8
KP		 1454/* Called from drm generic code, passed 'crtc' which
1455 * we use as a pipe index
1456 */
f71d4af4 1457static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1458{
1459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1460 unsigned long irqflags;
71e0ffa5 1461
5eddb70b 1462 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1463 return -EINVAL;
0a3e67a4 1464
1ec14ad3 1465 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1466 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1467 i915_enable_pipestat(dev_priv, pipe,
1468 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1469 else
7c463586
KP		 1470 i915_enable_pipestat(dev_priv, pipe,
1471 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1472
1473 /* maintain vblank delivery even in deep C-states */
1474 if (dev_priv->info->gen == 3)
1475 I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16);
1ec14ad3 1476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1477
0a3e67a4
JB		 1478 return 0;
1479}
1480
f71d4af4 1481static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags;
1485
1486 if (!i915_pipe_enabled(dev, pipe))
1487 return -EINVAL;
1488
1489 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1490 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1491 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1493
1494 return 0;
1495}
1496
f71d4af4 1497static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1498{
1499 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1500 unsigned long irqflags;
1501
1502 if (!i915_pipe_enabled(dev, pipe))
1503 return -EINVAL;
1504
1505 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1506 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1507 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1508 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1509
1510 return 0;
1511}
1512
42f52ef8
KP		 1513/* Called from drm generic code, passed 'crtc' which
1514 * we use as a pipe index
1515 */
f71d4af4 1516static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1517{
1518 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1519 unsigned long irqflags;
0a3e67a4 1520
1ec14ad3 1521 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e
CW		 1522 if (dev_priv->info->gen == 3)
1523 I915_WRITE(INSTPM,
1524 INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
1525
f796cf8f
JB		 1526 i915_disable_pipestat(dev_priv, pipe,
1527 PIPE_VBLANK_INTERRUPT_ENABLE |
1528 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1530}
1531
f71d4af4 1532static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1533{
1534 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1535 unsigned long irqflags;
1536
1537 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1538 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1539 DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
1ec14ad3 1540 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1541}
1542
f71d4af4 1543static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1544{
1545 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1546 unsigned long irqflags;
1547
1548 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1549 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1550 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1551 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1552}
1553
702880f2
DA		 1554/* Set the vblank monitor pipe
1555 */
c153f45f
EA		 1556int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1557 struct drm_file *file_priv)
702880f2 1558{
702880f2 1559 drm_i915_private_t *dev_priv = dev->dev_private;
702880f2
DA		 1560
1561 if (!dev_priv) {
3e684eae 1562 DRM_ERROR("called with no initialization\n");
20caafa6 1563 return -EINVAL;
702880f2
DA		 1564 }
1565
5b51694a 1566 return 0;
702880f2
DA		 1567}
1568
c153f45f
EA		 1569int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1570 struct drm_file *file_priv)
702880f2 1571{
702880f2 1572 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1573 drm_i915_vblank_pipe_t *pipe = data;
702880f2
DA		 1574
1575 if (!dev_priv) {
3e684eae 1576 DRM_ERROR("called with no initialization\n");
20caafa6 1577 return -EINVAL;
702880f2
DA		 1578 }
1579
0a3e67a4 1580 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
c153f45f 1581
702880f2
DA		 1582 return 0;
1583}
1584
a6b54f3f
MCA		 1585/**
1586 * Schedule buffer swap at given vertical blank.
1587 */
c153f45f
EA		 1588int i915_vblank_swap(struct drm_device *dev, void *data,
1589 struct drm_file *file_priv)
a6b54f3f 1590{
bd95e0a4
EA		 1591 /* The delayed swap mechanism was fundamentally racy, and has been
1592 * removed. The model was that the client requested a delayed flip/swap
1593 * from the kernel, then waited for vblank before continuing to perform
1594 * rendering. The problem was that the kernel might wake the client
1595 * up before it dispatched the vblank swap (since the lock has to be
1596 * held while touching the ringbuffer), in which case the client would
1597 * clear and start the next frame before the swap occurred, and
1598 * flicker would occur in addition to likely missing the vblank.
1599 *
1600 * In the absence of this ioctl, userland falls back to a correct path
1601 * of waiting for a vblank, then dispatching the swap on its own.
1602 * Context switching to userland and back is plenty fast enough for
1603 * meeting the requirements of vblank swapping.
0a3e67a4 1604 */
bd95e0a4 1605 return -EINVAL;
a6b54f3f
MCA		 1606}
1607
893eead0
CW		 1608static u32
1609ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1610{
893eead0
CW		 1611 return list_entry(ring->request_list.prev,
1612 struct drm_i915_gem_request, list)->seqno;
1613}
1614
1615static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1616{
1617 if (list_empty(&ring->request_list) ||
1618 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1619 /* Issue a wake-up to catch stuck h/w. */
b2223497 1620 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
893eead0
CW		 1621 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1622 ring->name,
b2223497 1623 ring->waiting_seqno,
893eead0
CW		 1624 ring->get_seqno(ring));
1625 wake_up_all(&ring->irq_queue);
1626 *err = true;
1627 }
1628 return true;
1629 }
1630 return false;
f65d9421
BG		 1631}
1632
1ec14ad3
CW		 1633static bool kick_ring(struct intel_ring_buffer *ring)
1634{
1635 struct drm_device *dev = ring->dev;
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637 u32 tmp = I915_READ_CTL(ring);
1638 if (tmp & RING_WAIT) {
1639 DRM_ERROR("Kicking stuck wait on %s\n",
1640 ring->name);
1641 I915_WRITE_CTL(ring, tmp);
1642 return true;
1643 }
1644 if (IS_GEN6(dev) &&
1645 (tmp & RING_WAIT_SEMAPHORE)) {
1646 DRM_ERROR("Kicking stuck semaphore on %s\n",
1647 ring->name);
1648 I915_WRITE_CTL(ring, tmp);
1649 return true;
1650 }
1651 return false;
1652}
1653
f65d9421
BG		 1654/**
1655 * This is called when the chip hasn't reported back with completed
1656 * batchbuffers in a long time. The first time this is called we simply record
1657 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1658 * again, we assume the chip is wedged and try to fix it.
1659 */
1660void i915_hangcheck_elapsed(unsigned long data)
1661{
1662 struct drm_device *dev = (struct drm_device *)data;
1663 drm_i915_private_t *dev_priv = dev->dev_private;
cbb465e7 1664 uint32_t acthd, instdone, instdone1;
893eead0
CW		 1665 bool err = false;
1666
1667 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1668 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1669 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1670 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
893eead0
CW		 1671 dev_priv->hangcheck_count = 0;
1672 if (err)
1673 goto repeat;
1674 return;
1675 }
b9201c14 1676
a6c45cf0 1677 if (INTEL_INFO(dev)->gen < 4) {
f65d9421 1678 acthd = I915_READ(ACTHD);
cbb465e7
CW		 1679 instdone = I915_READ(INSTDONE);
1680 instdone1 = 0;
1681 } else {
f65d9421 1682 acthd = I915_READ(ACTHD_I965);
cbb465e7
CW		 1683 instdone = I915_READ(INSTDONE_I965);
1684 instdone1 = I915_READ(INSTDONE1);
1685 }
f65d9421 1686
cbb465e7
CW		 1687 if (dev_priv->last_acthd == acthd &&
1688 dev_priv->last_instdone == instdone &&
1689 dev_priv->last_instdone1 == instdone1) {
1690 if (dev_priv->hangcheck_count++ > 1) {
1691 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
8c80b59b
CW		 1692
1693 if (!IS_GEN2(dev)) {
1694 /* Is the chip hanging on a WAIT_FOR_EVENT?
1695 * If so we can simply poke the RB_WAIT bit
1696 * and break the hang. This should work on
1697 * all but the second generation chipsets.
1698 */
1ec14ad3
CW		 1699
1700 if (kick_ring(&dev_priv->ring[RCS]))
1701 goto repeat;
1702
1703 if (HAS_BSD(dev) &&
1704 kick_ring(&dev_priv->ring[VCS]))
1705 goto repeat;
1706
1707 if (HAS_BLT(dev) &&
1708 kick_ring(&dev_priv->ring[BCS]))
893eead0 1709 goto repeat;
8c80b59b
CW		 1710 }
1711
cbb465e7
CW		 1712 i915_handle_error(dev, true);
1713 return;
1714 }
1715 } else {
1716 dev_priv->hangcheck_count = 0;
1717
1718 dev_priv->last_acthd = acthd;
1719 dev_priv->last_instdone = instdone;
1720 dev_priv->last_instdone1 = instdone1;
1721 }
f65d9421 1722
893eead0 1723repeat:
f65d9421 1724 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1725 mod_timer(&dev_priv->hangcheck_timer,
1726 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1727}
1728
1da177e4
LT		 1729/* drm_dma.h hooks
1730*/
f71d4af4 1731static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1732{
1733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1734
4697995b
JB		 1735 atomic_set(&dev_priv->irq_received, 0);
1736
1737 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1738 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
9e3c256d
JB		 1739 if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1740 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
4697995b 1741
036a4a7d 1742 I915_WRITE(HWSTAM, 0xeffe);
2b1ecb73 1743 if (IS_GEN6(dev) || IS_GEN7(dev)) {
498e720b
DB		 1744 /* Workaround stalls observed on Sandy Bridge GPUs by
1745 * making the blitter command streamer generate a
1746 * write to the Hardware Status Page for
1747 * MI_USER_INTERRUPT. This appears to serialize the
1748 * previous seqno write out before the interrupt
1749 * happens.
1750 */
1751 I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT);
ec6a890d 1752 I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT);
498e720b 1753 }
036a4a7d
ZW		 1754
1755 /* XXX hotplug from PCH */
1756
1757 I915_WRITE(DEIMR, 0xffffffff);
1758 I915_WRITE(DEIER, 0x0);
3143a2bf 1759 POSTING_READ(DEIER);
036a4a7d
ZW		 1760
1761 /* and GT */
1762 I915_WRITE(GTIMR, 0xffffffff);
1763 I915_WRITE(GTIER, 0x0);
3143a2bf 1764 POSTING_READ(GTIER);
c650156a
ZW		 1765
1766 /* south display irq */
1767 I915_WRITE(SDEIMR, 0xffffffff);
1768 I915_WRITE(SDEIER, 0x0);
3143a2bf 1769 POSTING_READ(SDEIER);
036a4a7d
ZW		 1770}
1771
f71d4af4 1772static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1773{
1774 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1775 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1776 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1777 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1778 u32 render_irqs;
2d7b8366 1779 u32 hotplug_mask;
036a4a7d 1780
4697995b
JB		 1781 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1782 if (HAS_BSD(dev))
1783 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1784 if (HAS_BLT(dev))
1785 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1786
1787 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1ec14ad3 1788 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1789
1790 /* should always can generate irq */
1791 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1792 I915_WRITE(DEIMR, dev_priv->irq_mask);
1793 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1794 POSTING_READ(DEIER);
036a4a7d 1795
1ec14ad3 1796 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1797
1798 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1799 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1800
1ec14ad3
CW		 1801 if (IS_GEN6(dev))
1802 render_irqs =
1803 GT_USER_INTERRUPT |
1804 GT_GEN6_BSD_USER_INTERRUPT |
1805 GT_BLT_USER_INTERRUPT;
1806 else
1807 render_irqs =
88f23b8f 1808 GT_USER_INTERRUPT |
c6df541c 1809 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1810 GT_BSD_USER_INTERRUPT;
1811 I915_WRITE(GTIER, render_irqs);
3143a2bf 1812 POSTING_READ(GTIER);
036a4a7d 1813
2d7b8366 1814 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1815 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1816 SDE_PORTB_HOTPLUG_CPT |
1817 SDE_PORTC_HOTPLUG_CPT |
1818 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1819 } else {
9035a97a
CW		 1820 hotplug_mask = (SDE_CRT_HOTPLUG |
1821 SDE_PORTB_HOTPLUG |
1822 SDE_PORTC_HOTPLUG |
1823 SDE_PORTD_HOTPLUG |
1824 SDE_AUX_MASK);
2d7b8366
YL		 1825 }
1826
1ec14ad3 1827 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1828
1829 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1830 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1831 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1832 POSTING_READ(SDEIER);
c650156a 1833
f97108d1
JB		 1834 if (IS_IRONLAKE_M(dev)) {
1835 /* Clear & enable PCU event interrupts */
1836 I915_WRITE(DEIIR, DE_PCU_EVENT);
1837 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1838 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1839 }
1840
036a4a7d
ZW		 1841 return 0;
1842}
1843
f71d4af4 1844static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1845{
1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1847 /* enable kind of interrupts always enabled */
1848 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1849 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1850 DE_PLANEB_FLIP_DONE_IVB;
1851 u32 render_irqs;
1852 u32 hotplug_mask;
1853
1854 DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
1855 if (HAS_BSD(dev))
1856 DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
1857 if (HAS_BLT(dev))
1858 DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
1859
1860 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1861 dev_priv->irq_mask = ~display_mask;
1862
1863 /* should always can generate irq */
1864 I915_WRITE(DEIIR, I915_READ(DEIIR));
1865 I915_WRITE(DEIMR, dev_priv->irq_mask);
1866 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1867 DE_PIPEB_VBLANK_IVB);
1868 POSTING_READ(DEIER);
1869
1870 dev_priv->gt_irq_mask = ~0;
1871
1872 I915_WRITE(GTIIR, I915_READ(GTIIR));
1873 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1874
1875 render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
1876 GT_BLT_USER_INTERRUPT;
1877 I915_WRITE(GTIER, render_irqs);
1878 POSTING_READ(GTIER);
1879
1880 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1881 SDE_PORTB_HOTPLUG_CPT |
1882 SDE_PORTC_HOTPLUG_CPT |
1883 SDE_PORTD_HOTPLUG_CPT);
1884 dev_priv->pch_irq_mask = ~hotplug_mask;
1885
1886 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1887 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1888 I915_WRITE(SDEIER, hotplug_mask);
1889 POSTING_READ(SDEIER);
1890
1891 return 0;
1892}
1893
f71d4af4 1894static void i915_driver_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1895{
1896 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1897 int pipe;
1da177e4 1898
79e53945
JB		 1899 atomic_set(&dev_priv->irq_received, 0);
1900
036a4a7d 1901 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
8a905236 1902 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
036a4a7d 1903
5ca58282
JB		 1904 if (I915_HAS_HOTPLUG(dev)) {
1905 I915_WRITE(PORT_HOTPLUG_EN, 0);
1906 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1907 }
1908
0a3e67a4 1909 I915_WRITE(HWSTAM, 0xeffe);
9db4a9c7
JB		 1910 for_each_pipe(pipe)
1911 I915_WRITE(PIPESTAT(pipe), 0);
0a3e67a4 1912 I915_WRITE(IMR, 0xffffffff);
ed4cb414 1913 I915_WRITE(IER, 0x0);
3143a2bf 1914 POSTING_READ(IER);
1da177e4
LT		 1915}
1916
b01f2c3a
JB		 1917/*
1918 * Must be called after intel_modeset_init or hotplug interrupts won't be
1919 * enabled correctly.
1920 */
f71d4af4 1921static int i915_driver_irq_postinstall(struct drm_device *dev)
1da177e4
LT		 1922{
1923 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5ca58282 1924 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
63eeaf38 1925 u32 error_mask;
0a3e67a4
JB		 1926
1927 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
0a3e67a4 1928
7c463586 1929 /* Unmask the interrupts that we always want on. */
1ec14ad3 1930 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
7c463586
KP		 1931
1932 dev_priv->pipestat[0] = 0;
1933 dev_priv->pipestat[1] = 0;
1934
5ca58282 1935 if (I915_HAS_HOTPLUG(dev)) {
5ca58282
JB		 1936 /* Enable in IER... */
1937 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1938 /* and unmask in IMR */
1ec14ad3 1939 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
5ca58282
JB		 1940 }
1941
63eeaf38
JB		 1942 /*
1943 * Enable some error detection, note the instruction error mask
1944 * bit is reserved, so we leave it masked.
1945 */
1946 if (IS_G4X(dev)) {
1947 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1948 GM45_ERROR_MEM_PRIV |
1949 GM45_ERROR_CP_PRIV |
1950 I915_ERROR_MEMORY_REFRESH);
1951 } else {
1952 error_mask = ~(I915_ERROR_PAGE_TABLE |
1953 I915_ERROR_MEMORY_REFRESH);
1954 }
1955 I915_WRITE(EMR, error_mask);
1956
1ec14ad3 1957 I915_WRITE(IMR, dev_priv->irq_mask);
c496fa1f 1958 I915_WRITE(IER, enable_mask);
3143a2bf 1959 POSTING_READ(IER);
ed4cb414 1960
c496fa1f
AJ		 1961 if (I915_HAS_HOTPLUG(dev)) {
1962 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1963
1964 /* Note HDMI and DP share bits */
1965 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1966 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1967 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1968 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1969 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1970 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1971 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1972 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1973 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1974 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2d1c9752 1975 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
c496fa1f 1976 hotplug_en |= CRT_HOTPLUG_INT_EN;
2d1c9752
AL		 1977
1978 /* Programming the CRT detection parameters tends
1979 to generate a spurious hotplug event about three
1980 seconds later. So just do it once.
1981 */
1982 if (IS_G4X(dev))
1983 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
1984 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1985 }
1986
c496fa1f
AJ		 1987 /* Ignore TV since it's buggy */
1988
1989 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1990 }
1991
3b617967 1992 intel_opregion_enable_asle(dev);
0a3e67a4
JB		 1993
1994 return 0;
1da177e4
LT		 1995}
1996
f71d4af4 1997static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1998{
1999 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2000
2001 if (!dev_priv)
2002 return;
2003
2004 dev_priv->vblank_pipe = 0;
2005
036a4a7d
ZW		 2006 I915_WRITE(HWSTAM, 0xffffffff);
2007
2008 I915_WRITE(DEIMR, 0xffffffff);
2009 I915_WRITE(DEIER, 0x0);
2010 I915_WRITE(DEIIR, I915_READ(DEIIR));
2011
2012 I915_WRITE(GTIMR, 0xffffffff);
2013 I915_WRITE(GTIER, 0x0);
2014 I915_WRITE(GTIIR, I915_READ(GTIIR));
2015}
2016
f71d4af4 2017static void i915_driver_irq_uninstall(struct drm_device * dev)
1da177e4
LT		 2018{
2019 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2020 int pipe;
91e3738e 2021
1da177e4
LT		 2022 if (!dev_priv)
2023 return;
2024
0a3e67a4
JB		 2025 dev_priv->vblank_pipe = 0;
2026
5ca58282
JB		 2027 if (I915_HAS_HOTPLUG(dev)) {
2028 I915_WRITE(PORT_HOTPLUG_EN, 0);
2029 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2030 }
2031
0a3e67a4 2032 I915_WRITE(HWSTAM, 0xffffffff);
9db4a9c7
JB		 2033 for_each_pipe(pipe)
2034 I915_WRITE(PIPESTAT(pipe), 0);
0a3e67a4 2035 I915_WRITE(IMR, 0xffffffff);
ed4cb414 2036 I915_WRITE(IER, 0x0);
af6061af 2037
9db4a9c7
JB		 2038 for_each_pipe(pipe)
2039 I915_WRITE(PIPESTAT(pipe),
2040 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
7c463586 2041 I915_WRITE(IIR, I915_READ(IIR));
1da177e4 2042}
f71d4af4
JB		 2043
2044void intel_irq_init(struct drm_device *dev)
2045{
2046 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2047 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2048 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
2049 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2050 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2051 }
2052
2053
2054 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2055 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2056
2057 if (IS_IVYBRIDGE(dev)) {
2058 /* Share pre & uninstall handlers with ILK/SNB */
2059 dev->driver->irq_handler = ivybridge_irq_handler;
2060 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2061 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2062 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2063 dev->driver->enable_vblank = ivybridge_enable_vblank;
2064 dev->driver->disable_vblank = ivybridge_disable_vblank;
2065 } else if (HAS_PCH_SPLIT(dev)) {
2066 dev->driver->irq_handler = ironlake_irq_handler;
2067 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2068 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2069 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2070 dev->driver->enable_vblank = ironlake_enable_vblank;
2071 dev->driver->disable_vblank = ironlake_disable_vblank;
2072 } else {
2073 dev->driver->irq_preinstall = i915_driver_irq_preinstall;
2074 dev->driver->irq_postinstall = i915_driver_irq_postinstall;
2075 dev->driver->irq_uninstall = i915_driver_irq_uninstall;
2076 dev->driver->irq_handler = i915_driver_irq_handler;
2077 dev->driver->enable_vblank = i915_enable_vblank;
2078 dev->driver->disable_vblank = i915_disable_vblank;
2079 }
2080}
Linux kernel - Deliverables
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