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drm/i915: convert CPU M/N timings to transcoder
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
760285e7
DH		 33#include <drm/drmP.h>
34#include <drm/i915_drm.h>
1da177e4 35#include "i915_drv.h"
1c5d22f7 36#include "i915_trace.h"
79e53945 37#include "intel_drv.h"
1da177e4 38
036a4a7d 39/* For display hotplug interrupt */
995b6762 40static void
f2b115e6 41ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 42{
1ec14ad3
CW		 43 if ((dev_priv->irq_mask & mask) != 0) {
44 dev_priv->irq_mask &= ~mask;
45 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 46 POSTING_READ(DEIMR);
036a4a7d
ZW		 47 }
48}
49
50static inline void
f2b115e6 51ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 52{
1ec14ad3
CW		 53 if ((dev_priv->irq_mask & mask) != mask) {
54 dev_priv->irq_mask |= mask;
55 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 56 POSTING_READ(DEIMR);
036a4a7d
ZW		 57 }
58}
59
7c463586
KP		 60void
61i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
62{
63 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 64 u32 reg = PIPESTAT(pipe);
7c463586
KP		 65
66 dev_priv->pipestat[pipe] |= mask;
67 /* Enable the interrupt, clear any pending status */
68 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 69 POSTING_READ(reg);
7c463586
KP		 70 }
71}
72
73void
74i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
75{
76 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 77 u32 reg = PIPESTAT(pipe);
7c463586
KP		 78
79 dev_priv->pipestat[pipe] &= ~mask;
80 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 81 POSTING_READ(reg);
7c463586
KP		 82 }
83}
84
01c66889
ZY		 85/**
86 * intel_enable_asle - enable ASLE interrupt for OpRegion
87 */
1ec14ad3 88void intel_enable_asle(struct drm_device *dev)
01c66889 89{
1ec14ad3
CW		 90 drm_i915_private_t *dev_priv = dev->dev_private;
91 unsigned long irqflags;
92
7e231dbe
JB		 93 /* FIXME: opregion/asle for VLV */
94 if (IS_VALLEYVIEW(dev))
95 return;
96
1ec14ad3 97 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 98
c619eed4 99 if (HAS_PCH_SPLIT(dev))
f2b115e6 100 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 101 else {
01c66889 102 i915_enable_pipestat(dev_priv, 1,
d874bcff 103 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 104 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 105 i915_enable_pipestat(dev_priv, 0,
d874bcff 106 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 107 }
1ec14ad3
CW		 108
109 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 110}
111
0a3e67a4
JB		 112/**
113 * i915_pipe_enabled - check if a pipe is enabled
114 * @dev: DRM device
115 * @pipe: pipe to check
116 *
117 * Reading certain registers when the pipe is disabled can hang the chip.
118 * Use this routine to make sure the PLL is running and the pipe is active
119 * before reading such registers if unsure.
120 */
121static int
122i915_pipe_enabled(struct drm_device *dev, int pipe)
123{
124 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
702e7a56
PZ		 125 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
126 pipe);
127
128 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
0a3e67a4
JB		 129}
130
42f52ef8
KP		 131/* Called from drm generic code, passed a 'crtc', which
132 * we use as a pipe index
133 */
f71d4af4 134static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 135{
136 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
137 unsigned long high_frame;
138 unsigned long low_frame;
5eddb70b 139 u32 high1, high2, low;
0a3e67a4
JB		 140
141 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 142 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 143 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 144 return 0;
145 }
146
9db4a9c7
JB		 147 high_frame = PIPEFRAME(pipe);
148 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 149
0a3e67a4
JB		 150 /*
151 * High & low register fields aren't synchronized, so make sure
152 * we get a low value that's stable across two reads of the high
153 * register.
154 */
155 do {
5eddb70b
CW		 156 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
157 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
158 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 159 } while (high1 != high2);
160
5eddb70b
CW		 161 high1 >>= PIPE_FRAME_HIGH_SHIFT;
162 low >>= PIPE_FRAME_LOW_SHIFT;
163 return (high1 << 8) | low;
0a3e67a4
JB		 164}
165
f71d4af4 166static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 167{
168 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 169 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 170
171 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 172 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 173 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 174 return 0;
175 }
176
177 return I915_READ(reg);
178}
179
f71d4af4 180static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 181 int *vpos, int *hpos)
182{
183 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
184 u32 vbl = 0, position = 0;
185 int vbl_start, vbl_end, htotal, vtotal;
186 bool in_vbl = true;
187 int ret = 0;
188
189 if (!i915_pipe_enabled(dev, pipe)) {
190 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 191 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 192 return 0;
193 }
194
195 /* Get vtotal. */
196 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
197
198 if (INTEL_INFO(dev)->gen >= 4) {
199 /* No obvious pixelcount register. Only query vertical
200 * scanout position from Display scan line register.
201 */
202 position = I915_READ(PIPEDSL(pipe));
203
204 /* Decode into vertical scanout position. Don't have
205 * horizontal scanout position.
206 */
207 *vpos = position & 0x1fff;
208 *hpos = 0;
209 } else {
210 /* Have access to pixelcount since start of frame.
211 * We can split this into vertical and horizontal
212 * scanout position.
213 */
214 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
215
216 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
217 *vpos = position / htotal;
218 *hpos = position - (*vpos * htotal);
219 }
220
221 /* Query vblank area. */
222 vbl = I915_READ(VBLANK(pipe));
223
224 /* Test position against vblank region. */
225 vbl_start = vbl & 0x1fff;
226 vbl_end = (vbl >> 16) & 0x1fff;
227
228 if ((*vpos < vbl_start) || (*vpos > vbl_end))
229 in_vbl = false;
230
231 /* Inside "upper part" of vblank area? Apply corrective offset: */
232 if (in_vbl && (*vpos >= vbl_start))
233 *vpos = *vpos - vtotal;
234
235 /* Readouts valid? */
236 if (vbl > 0)
237 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
238
239 /* In vblank? */
240 if (in_vbl)
241 ret |= DRM_SCANOUTPOS_INVBL;
242
243 return ret;
244}
245
f71d4af4 246static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 247 int *max_error,
248 struct timeval *vblank_time,
249 unsigned flags)
250{
4041b853
CW		 251 struct drm_i915_private *dev_priv = dev->dev_private;
252 struct drm_crtc *crtc;
0af7e4df 253
4041b853
CW		 254 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
255 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 256 return -EINVAL;
257 }
258
259 /* Get drm_crtc to timestamp: */
4041b853
CW		 260 crtc = intel_get_crtc_for_pipe(dev, pipe);
261 if (crtc == NULL) {
262 DRM_ERROR("Invalid crtc %d\n", pipe);
263 return -EINVAL;
264 }
265
266 if (!crtc->enabled) {
267 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
268 return -EBUSY;
269 }
0af7e4df
MK		 270
271 /* Helper routine in DRM core does all the work: */
4041b853
CW		 272 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
273 vblank_time, flags,
274 crtc);
0af7e4df
MK		 275}
276
5ca58282
JB		 277/*
278 * Handle hotplug events outside the interrupt handler proper.
279 */
280static void i915_hotplug_work_func(struct work_struct *work)
281{
282 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
283 hotplug_work);
284 struct drm_device *dev = dev_priv->dev;
c31c4ba3 285 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 286 struct intel_encoder *encoder;
287
a65e34c7 288 mutex_lock(&mode_config->mutex);
e67189ab
JB		 289 DRM_DEBUG_KMS("running encoder hotplug functions\n");
290
4ef69c7a
CW		 291 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
292 if (encoder->hot_plug)
293 encoder->hot_plug(encoder);
294
40ee3381
KP		 295 mutex_unlock(&mode_config->mutex);
296
5ca58282 297 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 298 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 299}
300
9270388e
DV		 301/* defined intel_pm.c */
302extern spinlock_t mchdev_lock;
303
73edd18f 304static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 305{
306 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 307 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 308 u8 new_delay;
309 unsigned long flags;
310
311 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 312
73edd18f
DV		 313 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
314
20e4d407 315 new_delay = dev_priv->ips.cur_delay;
9270388e 316
7648fa99 317 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 318 busy_up = I915_READ(RCPREVBSYTUPAVG);
319 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 320 max_avg = I915_READ(RCBMAXAVG);
321 min_avg = I915_READ(RCBMINAVG);
322
323 /* Handle RCS change request from hw */
b5b72e89 324 if (busy_up > max_avg) {
20e4d407
DV		 325 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
326 new_delay = dev_priv->ips.cur_delay - 1;
327 if (new_delay < dev_priv->ips.max_delay)
328 new_delay = dev_priv->ips.max_delay;
b5b72e89 329 } else if (busy_down < min_avg) {
20e4d407
DV		 330 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
331 new_delay = dev_priv->ips.cur_delay + 1;
332 if (new_delay > dev_priv->ips.min_delay)
333 new_delay = dev_priv->ips.min_delay;
f97108d1
JB		 334 }
335
7648fa99 336 if (ironlake_set_drps(dev, new_delay))
20e4d407 337 dev_priv->ips.cur_delay = new_delay;
f97108d1 338
9270388e
DV		 339 spin_unlock_irqrestore(&mchdev_lock, flags);
340
f97108d1
JB		 341 return;
342}
343
549f7365
CW		 344static void notify_ring(struct drm_device *dev,
345 struct intel_ring_buffer *ring)
346{
347 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 348
475553de
CW		 349 if (ring->obj == NULL)
350 return;
351
b2eadbc8 352 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 353
549f7365 354 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 355 if (i915_enable_hangcheck) {
356 dev_priv->hangcheck_count = 0;
357 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 358 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3e0dc6b0 359 }
549f7365
CW		 360}
361
4912d041 362static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 363{
4912d041 364 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 365 rps.work);
4912d041 366 u32 pm_iir, pm_imr;
7b9e0ae6 367 u8 new_delay;
4912d041 368
c6a828d3
DV		 369 spin_lock_irq(&dev_priv->rps.lock);
370 pm_iir = dev_priv->rps.pm_iir;
371 dev_priv->rps.pm_iir = 0;
4912d041 372 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 373 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 374 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 375
7b9e0ae6 376 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 377 return;
378
4912d041 379 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 380
381 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 382 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 383 else
c6a828d3 384 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 385
79249636
BW		 386 /* sysfs frequency interfaces may have snuck in while servicing the
387 * interrupt
388 */
389 if (!(new_delay > dev_priv->rps.max_delay ||
390 new_delay < dev_priv->rps.min_delay)) {
391 gen6_set_rps(dev_priv->dev, new_delay);
392 }
3b8d8d91 393
4912d041 394 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 395}
396
e3689190
BW		 397
398/**
399 * ivybridge_parity_work - Workqueue called when a parity error interrupt
400 * occurred.
401 * @work: workqueue struct
402 *
403 * Doesn't actually do anything except notify userspace. As a consequence of
404 * this event, userspace should try to remap the bad rows since statistically
405 * it is likely the same row is more likely to go bad again.
406 */
407static void ivybridge_parity_work(struct work_struct *work)
408{
409 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
410 parity_error_work);
411 u32 error_status, row, bank, subbank;
412 char *parity_event[5];
413 uint32_t misccpctl;
414 unsigned long flags;
415
416 /* We must turn off DOP level clock gating to access the L3 registers.
417 * In order to prevent a get/put style interface, acquire struct mutex
418 * any time we access those registers.
419 */
420 mutex_lock(&dev_priv->dev->struct_mutex);
421
422 misccpctl = I915_READ(GEN7_MISCCPCTL);
423 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
424 POSTING_READ(GEN7_MISCCPCTL);
425
426 error_status = I915_READ(GEN7_L3CDERRST1);
427 row = GEN7_PARITY_ERROR_ROW(error_status);
428 bank = GEN7_PARITY_ERROR_BANK(error_status);
429 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
430
431 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
432 GEN7_L3CDERRST1_ENABLE);
433 POSTING_READ(GEN7_L3CDERRST1);
434
435 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
436
437 spin_lock_irqsave(&dev_priv->irq_lock, flags);
438 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
439 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
440 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
441
442 mutex_unlock(&dev_priv->dev->struct_mutex);
443
444 parity_event[0] = "L3_PARITY_ERROR=1";
445 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
446 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
447 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
448 parity_event[4] = NULL;
449
450 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
451 KOBJ_CHANGE, parity_event);
452
453 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
454 row, bank, subbank);
455
456 kfree(parity_event[3]);
457 kfree(parity_event[2]);
458 kfree(parity_event[1]);
459}
460
d2ba8470 461static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 462{
463 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
464 unsigned long flags;
465
e1ef7cc2 466 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 467 return;
468
469 spin_lock_irqsave(&dev_priv->irq_lock, flags);
470 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
471 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
472 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
473
474 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
475}
476
e7b4c6b1
DV		 477static void snb_gt_irq_handler(struct drm_device *dev,
478 struct drm_i915_private *dev_priv,
479 u32 gt_iir)
480{
481
482 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
483 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
484 notify_ring(dev, &dev_priv->ring[RCS]);
485 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
486 notify_ring(dev, &dev_priv->ring[VCS]);
487 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
488 notify_ring(dev, &dev_priv->ring[BCS]);
489
490 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
491 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
492 GT_RENDER_CS_ERROR_INTERRUPT)) {
493 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
494 i915_handle_error(dev, false);
495 }
e3689190
BW		 496
497 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
498 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 499}
500
fc6826d1
CW		 501static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
502 u32 pm_iir)
503{
504 unsigned long flags;
505
506 /*
507 * IIR bits should never already be set because IMR should
508 * prevent an interrupt from being shown in IIR. The warning
509 * displays a case where we've unsafely cleared
c6a828d3 510 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 511 * type is not a problem, it displays a problem in the logic.
512 *
c6a828d3 513 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 514 */
515
c6a828d3 516 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 517 dev_priv->rps.pm_iir |= pm_iir;
518 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 519 POSTING_READ(GEN6_PMIMR);
c6a828d3 520 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 521
c6a828d3 522 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 523}
524
ff1f525e 525static irqreturn_t valleyview_irq_handler(int irq, void *arg)
7e231dbe
JB		 526{
527 struct drm_device *dev = (struct drm_device *) arg;
528 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
529 u32 iir, gt_iir, pm_iir;
530 irqreturn_t ret = IRQ_NONE;
531 unsigned long irqflags;
532 int pipe;
533 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 534 bool blc_event;
535
536 atomic_inc(&dev_priv->irq_received);
537
7e231dbe
JB		 538 while (true) {
539 iir = I915_READ(VLV_IIR);
540 gt_iir = I915_READ(GTIIR);
541 pm_iir = I915_READ(GEN6_PMIIR);
542
543 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
544 goto out;
545
546 ret = IRQ_HANDLED;
547
e7b4c6b1 548 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 549
550 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
551 for_each_pipe(pipe) {
552 int reg = PIPESTAT(pipe);
553 pipe_stats[pipe] = I915_READ(reg);
554
555 /*
556 * Clear the PIPE*STAT regs before the IIR
557 */
558 if (pipe_stats[pipe] & 0x8000ffff) {
559 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
560 DRM_DEBUG_DRIVER("pipe %c underrun\n",
561 pipe_name(pipe));
562 I915_WRITE(reg, pipe_stats[pipe]);
563 }
564 }
565 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
566
31acc7f5
JB		 567 for_each_pipe(pipe) {
568 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
569 drm_handle_vblank(dev, pipe);
570
571 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
572 intel_prepare_page_flip(dev, pipe);
573 intel_finish_page_flip(dev, pipe);
574 }
575 }
576
7e231dbe
JB		 577 /* Consume port. Then clear IIR or we'll miss events */
578 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
579 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
580
581 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
582 hotplug_status);
583 if (hotplug_status & dev_priv->hotplug_supported_mask)
584 queue_work(dev_priv->wq,
585 &dev_priv->hotplug_work);
586
587 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
588 I915_READ(PORT_HOTPLUG_STAT);
589 }
590
7e231dbe
JB		 591 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
592 blc_event = true;
593
fc6826d1
CW		 594 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
595 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 596
597 I915_WRITE(GTIIR, gt_iir);
598 I915_WRITE(GEN6_PMIIR, pm_iir);
599 I915_WRITE(VLV_IIR, iir);
600 }
601
602out:
603 return ret;
604}
605
23e81d69 606static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 607{
608 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 609 int pipe;
776ad806 610
76e43830
DV		 611 if (pch_iir & SDE_HOTPLUG_MASK)
612 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
613
776ad806
JB		 614 if (pch_iir & SDE_AUDIO_POWER_MASK)
615 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
616 (pch_iir & SDE_AUDIO_POWER_MASK) >>
617 SDE_AUDIO_POWER_SHIFT);
618
619 if (pch_iir & SDE_GMBUS)
620 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
621
622 if (pch_iir & SDE_AUDIO_HDCP_MASK)
623 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
624
625 if (pch_iir & SDE_AUDIO_TRANS_MASK)
626 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
627
628 if (pch_iir & SDE_POISON)
629 DRM_ERROR("PCH poison interrupt\n");
630
9db4a9c7
JB		 631 if (pch_iir & SDE_FDI_MASK)
632 for_each_pipe(pipe)
633 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
634 pipe_name(pipe),
635 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 636
637 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
638 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
639
640 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
641 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
642
643 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
644 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
645 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
646 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
647}
648
23e81d69
AJ		 649static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
650{
651 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
652 int pipe;
653
76e43830
DV		 654 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
655 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
656
23e81d69
AJ		 657 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
658 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
659 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
660 SDE_AUDIO_POWER_SHIFT_CPT);
661
662 if (pch_iir & SDE_AUX_MASK_CPT)
663 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
664
665 if (pch_iir & SDE_GMBUS_CPT)
666 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
667
668 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
669 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
670
671 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
672 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
673
674 if (pch_iir & SDE_FDI_MASK_CPT)
675 for_each_pipe(pipe)
676 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
677 pipe_name(pipe),
678 I915_READ(FDI_RX_IIR(pipe)));
679}
680
ff1f525e 681static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
b1f14ad0
JB		 682{
683 struct drm_device *dev = (struct drm_device *) arg;
684 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 685 u32 de_iir, gt_iir, de_ier, pm_iir;
686 irqreturn_t ret = IRQ_NONE;
687 int i;
b1f14ad0
JB		 688
689 atomic_inc(&dev_priv->irq_received);
690
691 /* disable master interrupt before clearing iir */
692 de_ier = I915_READ(DEIER);
693 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 694
b1f14ad0 695 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 696 if (gt_iir) {
697 snb_gt_irq_handler(dev, dev_priv, gt_iir);
698 I915_WRITE(GTIIR, gt_iir);
699 ret = IRQ_HANDLED;
b1f14ad0
JB		 700 }
701
0e43406b
CW		 702 de_iir = I915_READ(DEIIR);
703 if (de_iir) {
704 if (de_iir & DE_GSE_IVB)
705 intel_opregion_gse_intr(dev);
706
707 for (i = 0; i < 3; i++) {
74d44445
DV		 708 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
709 drm_handle_vblank(dev, i);
0e43406b
CW		 710 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
711 intel_prepare_page_flip(dev, i);
712 intel_finish_page_flip_plane(dev, i);
713 }
0e43406b 714 }
b615b57a 715
0e43406b
CW		 716 /* check event from PCH */
717 if (de_iir & DE_PCH_EVENT_IVB) {
718 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 719
23e81d69 720 cpt_irq_handler(dev, pch_iir);
b1f14ad0 721
0e43406b
CW		 722 /* clear PCH hotplug event before clear CPU irq */
723 I915_WRITE(SDEIIR, pch_iir);
724 }
b615b57a 725
0e43406b
CW		 726 I915_WRITE(DEIIR, de_iir);
727 ret = IRQ_HANDLED;
b1f14ad0
JB		 728 }
729
0e43406b
CW		 730 pm_iir = I915_READ(GEN6_PMIIR);
731 if (pm_iir) {
732 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
733 gen6_queue_rps_work(dev_priv, pm_iir);
734 I915_WRITE(GEN6_PMIIR, pm_iir);
735 ret = IRQ_HANDLED;
736 }
b1f14ad0 737
b1f14ad0
JB		 738 I915_WRITE(DEIER, de_ier);
739 POSTING_READ(DEIER);
740
741 return ret;
742}
743
e7b4c6b1
DV		 744static void ilk_gt_irq_handler(struct drm_device *dev,
745 struct drm_i915_private *dev_priv,
746 u32 gt_iir)
747{
748 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
749 notify_ring(dev, &dev_priv->ring[RCS]);
750 if (gt_iir & GT_BSD_USER_INTERRUPT)
751 notify_ring(dev, &dev_priv->ring[VCS]);
752}
753
ff1f525e 754static irqreturn_t ironlake_irq_handler(int irq, void *arg)
036a4a7d 755{
4697995b 756 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 757 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
758 int ret = IRQ_NONE;
3b8d8d91 759 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
881f47b6 760
4697995b
JB		 761 atomic_inc(&dev_priv->irq_received);
762
2d109a84
ZN		 763 /* disable master interrupt before clearing iir */
764 de_ier = I915_READ(DEIER);
765 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 766 POSTING_READ(DEIER);
2d109a84 767
036a4a7d
ZW		 768 de_iir = I915_READ(DEIIR);
769 gt_iir = I915_READ(GTIIR);
c650156a 770 pch_iir = I915_READ(SDEIIR);
3b8d8d91 771 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 772
3b8d8d91
JB		 773 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
774 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 775 goto done;
036a4a7d 776
c7c85101 777 ret = IRQ_HANDLED;
036a4a7d 778
e7b4c6b1
DV		 779 if (IS_GEN5(dev))
780 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
781 else
782 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 783
c7c85101 784 if (de_iir & DE_GSE)
3b617967 785 intel_opregion_gse_intr(dev);
c650156a 786
74d44445
DV		 787 if (de_iir & DE_PIPEA_VBLANK)
788 drm_handle_vblank(dev, 0);
789
790 if (de_iir & DE_PIPEB_VBLANK)
791 drm_handle_vblank(dev, 1);
792
f072d2e7 793 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 794 intel_prepare_page_flip(dev, 0);
2bbda389 795 intel_finish_page_flip_plane(dev, 0);
f072d2e7 796 }
013d5aa2 797
f072d2e7 798 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 799 intel_prepare_page_flip(dev, 1);
2bbda389 800 intel_finish_page_flip_plane(dev, 1);
f072d2e7 801 }
013d5aa2 802
c7c85101 803 /* check event from PCH */
776ad806 804 if (de_iir & DE_PCH_EVENT) {
23e81d69
AJ		 805 if (HAS_PCH_CPT(dev))
806 cpt_irq_handler(dev, pch_iir);
807 else
808 ibx_irq_handler(dev, pch_iir);
776ad806 809 }
036a4a7d 810
73edd18f
DV		 811 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
812 ironlake_handle_rps_change(dev);
f97108d1 813
fc6826d1
CW		 814 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
815 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 816
c7c85101
ZN		 817 /* should clear PCH hotplug event before clear CPU irq */
818 I915_WRITE(SDEIIR, pch_iir);
819 I915_WRITE(GTIIR, gt_iir);
820 I915_WRITE(DEIIR, de_iir);
4912d041 821 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 822
823done:
2d109a84 824 I915_WRITE(DEIER, de_ier);
3143a2bf 825 POSTING_READ(DEIER);
2d109a84 826
036a4a7d
ZW		 827 return ret;
828}
829
8a905236
JB		 830/**
831 * i915_error_work_func - do process context error handling work
832 * @work: work struct
833 *
834 * Fire an error uevent so userspace can see that a hang or error
835 * was detected.
836 */
837static void i915_error_work_func(struct work_struct *work)
838{
839 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
840 error_work);
841 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 842 char *error_event[] = { "ERROR=1", NULL };
843 char *reset_event[] = { "RESET=1", NULL };
844 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 845
f316a42c
BG		 846 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
847
ba1234d1 848 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 849 DRM_DEBUG_DRIVER("resetting chip\n");
850 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 851 if (!i915_reset(dev)) {
f803aa55
CW		 852 atomic_set(&dev_priv->mm.wedged, 0);
853 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 854 }
30dbf0c0 855 complete_all(&dev_priv->error_completion);
f316a42c 856 }
8a905236
JB		 857}
858
85f9e50d
DV		 859/* NB: please notice the memset */
860static void i915_get_extra_instdone(struct drm_device *dev,
861 uint32_t *instdone)
862{
863 struct drm_i915_private *dev_priv = dev->dev_private;
864 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
865
866 switch(INTEL_INFO(dev)->gen) {
867 case 2:
868 case 3:
869 instdone[0] = I915_READ(INSTDONE);
870 break;
871 case 4:
872 case 5:
873 case 6:
874 instdone[0] = I915_READ(INSTDONE_I965);
875 instdone[1] = I915_READ(INSTDONE1);
876 break;
877 default:
878 WARN_ONCE(1, "Unsupported platform\n");
879 case 7:
880 instdone[0] = I915_READ(GEN7_INSTDONE_1);
881 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
882 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
883 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
884 break;
885 }
886}
887
3bd3c932 888#ifdef CONFIG_DEBUG_FS
9df30794 889static struct drm_i915_error_object *
bcfb2e28 890i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 891 struct drm_i915_gem_object *src)
9df30794
CW		 892{
893 struct drm_i915_error_object *dst;
9da3da66 894 int i, count;
e56660dd 895 u32 reloc_offset;
9df30794 896
05394f39 897 if (src == NULL || src->pages == NULL)
9df30794
CW		 898 return NULL;
899
9da3da66 900 count = src->base.size / PAGE_SIZE;
9df30794 901
9da3da66 902 dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 903 if (dst == NULL)
904 return NULL;
905
05394f39 906 reloc_offset = src->gtt_offset;
9da3da66 907 for (i = 0; i < count; i++) {
788885ae 908 unsigned long flags;
e56660dd 909 void *d;
788885ae 910
e56660dd 911 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 912 if (d == NULL)
913 goto unwind;
e56660dd 914
788885ae 915 local_irq_save(flags);
74898d7e
DV		 916 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
917 src->has_global_gtt_mapping) {
172975aa
CW		 918 void __iomem *s;
919
920 /* Simply ignore tiling or any overlapping fence.
921 * It's part of the error state, and this hopefully
922 * captures what the GPU read.
923 */
924
925 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
926 reloc_offset);
927 memcpy_fromio(d, s, PAGE_SIZE);
928 io_mapping_unmap_atomic(s);
929 } else {
9da3da66 930 struct page *page;
172975aa
CW		 931 void *s;
932
9da3da66 933 page = i915_gem_object_get_page(src, i);
172975aa 934
9da3da66
CW		 935 drm_clflush_pages(&page, 1);
936
937 s = kmap_atomic(page);
172975aa
CW		 938 memcpy(d, s, PAGE_SIZE);
939 kunmap_atomic(s);
940
9da3da66 941 drm_clflush_pages(&page, 1);
172975aa 942 }
788885ae 943 local_irq_restore(flags);
e56660dd 944
9da3da66 945 dst->pages[i] = d;
e56660dd
CW		 946
947 reloc_offset += PAGE_SIZE;
9df30794 948 }
9da3da66 949 dst->page_count = count;
05394f39 950 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 951
952 return dst;
953
954unwind:
9da3da66
CW		 955 while (i--)
956 kfree(dst->pages[i]);
9df30794
CW		 957 kfree(dst);
958 return NULL;
959}
960
961static void
962i915_error_object_free(struct drm_i915_error_object *obj)
963{
964 int page;
965
966 if (obj == NULL)
967 return;
968
969 for (page = 0; page < obj->page_count; page++)
970 kfree(obj->pages[page]);
971
972 kfree(obj);
973}
974
742cbee8
DV		 975void
976i915_error_state_free(struct kref *error_ref)
9df30794 977{
742cbee8
DV		 978 struct drm_i915_error_state *error = container_of(error_ref,
979 typeof(*error), ref);
e2f973d5
CW		 980 int i;
981
52d39a21
CW		 982 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
983 i915_error_object_free(error->ring[i].batchbuffer);
984 i915_error_object_free(error->ring[i].ringbuffer);
985 kfree(error->ring[i].requests);
986 }
e2f973d5 987
9df30794 988 kfree(error->active_bo);
6ef3d427 989 kfree(error->overlay);
9df30794
CW		 990 kfree(error);
991}
1b50247a
CW		 992static void capture_bo(struct drm_i915_error_buffer *err,
993 struct drm_i915_gem_object *obj)
994{
995 err->size = obj->base.size;
996 err->name = obj->base.name;
0201f1ec
CW		 997 err->rseqno = obj->last_read_seqno;
998 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 999 err->gtt_offset = obj->gtt_offset;
1000 err->read_domains = obj->base.read_domains;
1001 err->write_domain = obj->base.write_domain;
1002 err->fence_reg = obj->fence_reg;
1003 err->pinned = 0;
1004 if (obj->pin_count > 0)
1005 err->pinned = 1;
1006 if (obj->user_pin_count > 0)
1007 err->pinned = -1;
1008 err->tiling = obj->tiling_mode;
1009 err->dirty = obj->dirty;
1010 err->purgeable = obj->madv != I915_MADV_WILLNEED;
1011 err->ring = obj->ring ? obj->ring->id : -1;
1012 err->cache_level = obj->cache_level;
1013}
9df30794 1014
1b50247a
CW		 1015static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1016 int count, struct list_head *head)
c724e8a9
CW		 1017{
1018 struct drm_i915_gem_object *obj;
1019 int i = 0;
1020
1021 list_for_each_entry(obj, head, mm_list) {
1b50247a 1022 capture_bo(err++, obj);
c724e8a9
CW		 1023 if (++i == count)
1024 break;
1b50247a
CW		 1025 }
1026
1027 return i;
1028}
1029
1030static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1031 int count, struct list_head *head)
1032{
1033 struct drm_i915_gem_object *obj;
1034 int i = 0;
1035
1036 list_for_each_entry(obj, head, gtt_list) {
1037 if (obj->pin_count == 0)
1038 continue;
c724e8a9 1039
1b50247a
CW		 1040 capture_bo(err++, obj);
1041 if (++i == count)
1042 break;
c724e8a9
CW		 1043 }
1044
1045 return i;
1046}
1047
748ebc60
CW		 1048static void i915_gem_record_fences(struct drm_device *dev,
1049 struct drm_i915_error_state *error)
1050{
1051 struct drm_i915_private *dev_priv = dev->dev_private;
1052 int i;
1053
1054 /* Fences */
1055 switch (INTEL_INFO(dev)->gen) {
775d17b6 1056 case 7:
748ebc60
CW		 1057 case 6:
1058 for (i = 0; i < 16; i++)
1059 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1060 break;
1061 case 5:
1062 case 4:
1063 for (i = 0; i < 16; i++)
1064 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1065 break;
1066 case 3:
1067 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1068 for (i = 0; i < 8; i++)
1069 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1070 case 2:
1071 for (i = 0; i < 8; i++)
1072 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1073 break;
1074
1075 }
1076}
1077
bcfb2e28
CW		 1078static struct drm_i915_error_object *
1079i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1080 struct intel_ring_buffer *ring)
1081{
1082 struct drm_i915_gem_object *obj;
1083 u32 seqno;
1084
1085 if (!ring->get_seqno)
1086 return NULL;
1087
b2eadbc8 1088 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1089 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1090 if (obj->ring != ring)
1091 continue;
1092
0201f1ec 1093 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1094 continue;
1095
1096 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1097 continue;
1098
1099 /* We need to copy these to an anonymous buffer as the simplest
1100 * method to avoid being overwritten by userspace.
1101 */
1102 return i915_error_object_create(dev_priv, obj);
1103 }
1104
1105 return NULL;
1106}
1107
d27b1e0e
DV		 1108static void i915_record_ring_state(struct drm_device *dev,
1109 struct drm_i915_error_state *error,
1110 struct intel_ring_buffer *ring)
1111{
1112 struct drm_i915_private *dev_priv = dev->dev_private;
1113
33f3f518 1114 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1115 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1116 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1117 error->semaphore_mboxes[ring->id][0]
1118 = I915_READ(RING_SYNC_0(ring->mmio_base));
1119 error->semaphore_mboxes[ring->id][1]
1120 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1121 }
c1cd90ed 1122
d27b1e0e 1123 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1124 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1125 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1126 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1127 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1128 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
050ee91f 1129 if (ring->id == RCS)
d27b1e0e 1130 error->bbaddr = I915_READ64(BB_ADDR);
d27b1e0e 1131 } else {
9d2f41fa 1132 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1133 error->ipeir[ring->id] = I915_READ(IPEIR);
1134 error->ipehr[ring->id] = I915_READ(IPEHR);
1135 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1136 }
1137
9574b3fe 1138 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1139 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1140 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1141 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1142 error->head[ring->id] = I915_READ_HEAD(ring);
1143 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1144
1145 error->cpu_ring_head[ring->id] = ring->head;
1146 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1147}
1148
52d39a21
CW		 1149static void i915_gem_record_rings(struct drm_device *dev,
1150 struct drm_i915_error_state *error)
1151{
1152 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1153 struct intel_ring_buffer *ring;
52d39a21
CW		 1154 struct drm_i915_gem_request *request;
1155 int i, count;
1156
b4519513 1157 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1158 i915_record_ring_state(dev, error, ring);
1159
1160 error->ring[i].batchbuffer =
1161 i915_error_first_batchbuffer(dev_priv, ring);
1162
1163 error->ring[i].ringbuffer =
1164 i915_error_object_create(dev_priv, ring->obj);
1165
1166 count = 0;
1167 list_for_each_entry(request, &ring->request_list, list)
1168 count++;
1169
1170 error->ring[i].num_requests = count;
1171 error->ring[i].requests =
1172 kmalloc(count*sizeof(struct drm_i915_error_request),
1173 GFP_ATOMIC);
1174 if (error->ring[i].requests == NULL) {
1175 error->ring[i].num_requests = 0;
1176 continue;
1177 }
1178
1179 count = 0;
1180 list_for_each_entry(request, &ring->request_list, list) {
1181 struct drm_i915_error_request *erq;
1182
1183 erq = &error->ring[i].requests[count++];
1184 erq->seqno = request->seqno;
1185 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1186 erq->tail = request->tail;
52d39a21
CW		 1187 }
1188 }
1189}
1190
8a905236
JB		 1191/**
1192 * i915_capture_error_state - capture an error record for later analysis
1193 * @dev: drm device
1194 *
1195 * Should be called when an error is detected (either a hang or an error
1196 * interrupt) to capture error state from the time of the error. Fills
1197 * out a structure which becomes available in debugfs for user level tools
1198 * to pick up.
1199 */
63eeaf38
JB		 1200static void i915_capture_error_state(struct drm_device *dev)
1201{
1202 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1203 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1204 struct drm_i915_error_state *error;
1205 unsigned long flags;
9db4a9c7 1206 int i, pipe;
63eeaf38
JB		 1207
1208 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1209 error = dev_priv->first_error;
1210 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1211 if (error)
1212 return;
63eeaf38 1213
9db4a9c7 1214 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1215 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1216 if (!error) {
9df30794
CW		 1217 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1218 return;
63eeaf38
JB		 1219 }
1220
b6f7833b
CW		 1221 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1222 dev->primary->index);
2fa772f3 1223
742cbee8 1224 kref_init(&error->ref);
63eeaf38
JB		 1225 error->eir = I915_READ(EIR);
1226 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1227 error->ccid = I915_READ(CCID);
be998e2e
BW		 1228
1229 if (HAS_PCH_SPLIT(dev))
1230 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1231 else if (IS_VALLEYVIEW(dev))
1232 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1233 else if (IS_GEN2(dev))
1234 error->ier = I915_READ16(IER);
1235 else
1236 error->ier = I915_READ(IER);
1237
9db4a9c7
JB		 1238 for_each_pipe(pipe)
1239 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1240
33f3f518 1241 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1242 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1243 error->done_reg = I915_READ(DONE_REG);
1244 }
d27b1e0e 1245
71e172e8
BW		 1246 if (INTEL_INFO(dev)->gen == 7)
1247 error->err_int = I915_READ(GEN7_ERR_INT);
1248
050ee91f
BW		 1249 i915_get_extra_instdone(dev, error->extra_instdone);
1250
748ebc60 1251 i915_gem_record_fences(dev, error);
52d39a21 1252 i915_gem_record_rings(dev, error);
9df30794 1253
c724e8a9 1254 /* Record buffers on the active and pinned lists. */
9df30794 1255 error->active_bo = NULL;
c724e8a9 1256 error->pinned_bo = NULL;
9df30794 1257
bcfb2e28
CW		 1258 i = 0;
1259 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1260 i++;
1261 error->active_bo_count = i;
6c085a72 1262 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1263 if (obj->pin_count)
1264 i++;
bcfb2e28 1265 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1266
8e934dbf
CW		 1267 error->active_bo = NULL;
1268 error->pinned_bo = NULL;
bcfb2e28
CW		 1269 if (i) {
1270 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1271 GFP_ATOMIC);
c724e8a9
CW		 1272 if (error->active_bo)
1273 error->pinned_bo =
1274 error->active_bo + error->active_bo_count;
9df30794
CW		 1275 }
1276
c724e8a9
CW		 1277 if (error->active_bo)
1278 error->active_bo_count =
1b50247a
CW		 1279 capture_active_bo(error->active_bo,
1280 error->active_bo_count,
1281 &dev_priv->mm.active_list);
c724e8a9
CW		 1282
1283 if (error->pinned_bo)
1284 error->pinned_bo_count =
1b50247a
CW		 1285 capture_pinned_bo(error->pinned_bo,
1286 error->pinned_bo_count,
6c085a72 1287 &dev_priv->mm.bound_list);
c724e8a9 1288
9df30794
CW		 1289 do_gettimeofday(&error->time);
1290
6ef3d427 1291 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1292 error->display = intel_display_capture_error_state(dev);
6ef3d427 1293
9df30794
CW		 1294 spin_lock_irqsave(&dev_priv->error_lock, flags);
1295 if (dev_priv->first_error == NULL) {
1296 dev_priv->first_error = error;
1297 error = NULL;
1298 }
63eeaf38 1299 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1300
1301 if (error)
742cbee8 1302 i915_error_state_free(&error->ref);
9df30794
CW		 1303}
1304
1305void i915_destroy_error_state(struct drm_device *dev)
1306{
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 struct drm_i915_error_state *error;
6dc0e816 1309 unsigned long flags;
9df30794 1310
6dc0e816 1311 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1312 error = dev_priv->first_error;
1313 dev_priv->first_error = NULL;
6dc0e816 1314 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1315
1316 if (error)
742cbee8 1317 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1318}
3bd3c932
CW		 1319#else
1320#define i915_capture_error_state(x)
1321#endif
63eeaf38 1322
35aed2e6 1323static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1324{
1325 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1326 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1327 u32 eir = I915_READ(EIR);
050ee91f 1328 int pipe, i;
8a905236 1329
35aed2e6
CW		 1330 if (!eir)
1331 return;
8a905236 1332
a70491cc 1333 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1334
bd9854f9
BW		 1335 i915_get_extra_instdone(dev, instdone);
1336
8a905236
JB		 1337 if (IS_G4X(dev)) {
1338 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1339 u32 ipeir = I915_READ(IPEIR_I965);
1340
a70491cc
JP		 1341 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1342 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
050ee91f
BW		 1343 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1344 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a70491cc 1345 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1346 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1347 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1348 POSTING_READ(IPEIR_I965);
8a905236
JB		 1349 }
1350 if (eir & GM45_ERROR_PAGE_TABLE) {
1351 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1352 pr_err("page table error\n");
1353 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1354 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1355 POSTING_READ(PGTBL_ER);
8a905236
JB		 1356 }
1357 }
1358
a6c45cf0 1359 if (!IS_GEN2(dev)) {
8a905236
JB		 1360 if (eir & I915_ERROR_PAGE_TABLE) {
1361 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1362 pr_err("page table error\n");
1363 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1364 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1365 POSTING_READ(PGTBL_ER);
8a905236
JB		 1366 }
1367 }
1368
1369 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1370 pr_err("memory refresh error:\n");
9db4a9c7 1371 for_each_pipe(pipe)
a70491cc 1372 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1373 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1374 /* pipestat has already been acked */
1375 }
1376 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1377 pr_err("instruction error\n");
1378 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
050ee91f
BW		 1379 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1380 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
a6c45cf0 1381 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1382 u32 ipeir = I915_READ(IPEIR);
1383
a70491cc
JP		 1384 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1385 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
a70491cc 1386 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1387 I915_WRITE(IPEIR, ipeir);
3143a2bf 1388 POSTING_READ(IPEIR);
8a905236
JB		 1389 } else {
1390 u32 ipeir = I915_READ(IPEIR_I965);
1391
a70491cc
JP		 1392 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1393 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
a70491cc 1394 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
a70491cc 1395 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1396 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1397 POSTING_READ(IPEIR_I965);
8a905236
JB		 1398 }
1399 }
1400
1401 I915_WRITE(EIR, eir);
3143a2bf 1402 POSTING_READ(EIR);
8a905236
JB		 1403 eir = I915_READ(EIR);
1404 if (eir) {
1405 /*
1406 * some errors might have become stuck,
1407 * mask them.
1408 */
1409 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1410 I915_WRITE(EMR, I915_READ(EMR) | eir);
1411 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1412 }
35aed2e6
CW		 1413}
1414
1415/**
1416 * i915_handle_error - handle an error interrupt
1417 * @dev: drm device
1418 *
1419 * Do some basic checking of regsiter state at error interrupt time and
1420 * dump it to the syslog. Also call i915_capture_error_state() to make
1421 * sure we get a record and make it available in debugfs. Fire a uevent
1422 * so userspace knows something bad happened (should trigger collection
1423 * of a ring dump etc.).
1424 */
527f9e90 1425void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1426{
1427 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1428 struct intel_ring_buffer *ring;
1429 int i;
35aed2e6
CW		 1430
1431 i915_capture_error_state(dev);
1432 i915_report_and_clear_eir(dev);
8a905236 1433
ba1234d1 1434 if (wedged) {
30dbf0c0 1435 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1436 atomic_set(&dev_priv->mm.wedged, 1);
1437
11ed50ec
BG		 1438 /*
1439 * Wakeup waiting processes so they don't hang
1440 */
b4519513
CW		 1441 for_each_ring(ring, dev_priv, i)
1442 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1443 }
1444
9c9fe1f8 1445 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1446}
1447
4e5359cd
SF		 1448static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1449{
1450 drm_i915_private_t *dev_priv = dev->dev_private;
1451 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1453 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1454 struct intel_unpin_work *work;
1455 unsigned long flags;
1456 bool stall_detected;
1457
1458 /* Ignore early vblank irqs */
1459 if (intel_crtc == NULL)
1460 return;
1461
1462 spin_lock_irqsave(&dev->event_lock, flags);
1463 work = intel_crtc->unpin_work;
1464
1465 if (work == NULL || work->pending || !work->enable_stall_check) {
1466 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1467 spin_unlock_irqrestore(&dev->event_lock, flags);
1468 return;
1469 }
1470
1471 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1472 obj = work->pending_flip_obj;
a6c45cf0 1473 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1474 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1475 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1476 obj->gtt_offset;
4e5359cd 1477 } else {
9db4a9c7 1478 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1479 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1480 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1481 crtc->x * crtc->fb->bits_per_pixel/8);
1482 }
1483
1484 spin_unlock_irqrestore(&dev->event_lock, flags);
1485
1486 if (stall_detected) {
1487 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1488 intel_prepare_page_flip(dev, intel_crtc->plane);
1489 }
1490}
1491
42f52ef8
KP		 1492/* Called from drm generic code, passed 'crtc' which
1493 * we use as a pipe index
1494 */
f71d4af4 1495static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1496{
1497 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1498 unsigned long irqflags;
71e0ffa5 1499
5eddb70b 1500 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1501 return -EINVAL;
0a3e67a4 1502
1ec14ad3 1503 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1504 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1505 i915_enable_pipestat(dev_priv, pipe,
1506 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1507 else
7c463586
KP		 1508 i915_enable_pipestat(dev_priv, pipe,
1509 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1510
1511 /* maintain vblank delivery even in deep C-states */
1512 if (dev_priv->info->gen == 3)
6b26c86d 1513 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1514 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1515
0a3e67a4
JB		 1516 return 0;
1517}
1518
f71d4af4 1519static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1520{
1521 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1522 unsigned long irqflags;
1523
1524 if (!i915_pipe_enabled(dev, pipe))
1525 return -EINVAL;
1526
1527 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1528 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1529 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1530 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1531
1532 return 0;
1533}
1534
f71d4af4 1535static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1536{
1537 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1538 unsigned long irqflags;
1539
1540 if (!i915_pipe_enabled(dev, pipe))
1541 return -EINVAL;
1542
1543 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1544 ironlake_enable_display_irq(dev_priv,
1545 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1546 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1547
1548 return 0;
1549}
1550
7e231dbe
JB		 1551static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1552{
1553 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1554 unsigned long irqflags;
31acc7f5 1555 u32 imr;
7e231dbe
JB		 1556
1557 if (!i915_pipe_enabled(dev, pipe))
1558 return -EINVAL;
1559
1560 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1561 imr = I915_READ(VLV_IMR);
31acc7f5 1562 if (pipe == 0)
7e231dbe 1563 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1564 else
7e231dbe 1565 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1566 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1567 i915_enable_pipestat(dev_priv, pipe,
1568 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1569 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1570
1571 return 0;
1572}
1573
42f52ef8
KP		 1574/* Called from drm generic code, passed 'crtc' which
1575 * we use as a pipe index
1576 */
f71d4af4 1577static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1578{
1579 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1580 unsigned long irqflags;
0a3e67a4 1581
1ec14ad3 1582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1583 if (dev_priv->info->gen == 3)
6b26c86d 1584 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1585
f796cf8f
JB		 1586 i915_disable_pipestat(dev_priv, pipe,
1587 PIPE_VBLANK_INTERRUPT_ENABLE |
1588 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1589 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1590}
1591
f71d4af4 1592static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1593{
1594 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1595 unsigned long irqflags;
1596
1597 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1598 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1599 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1600 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1601}
1602
f71d4af4 1603static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1604{
1605 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1606 unsigned long irqflags;
1607
1608 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1609 ironlake_disable_display_irq(dev_priv,
1610 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1611 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1612}
1613
7e231dbe
JB		 1614static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1615{
1616 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1617 unsigned long irqflags;
31acc7f5 1618 u32 imr;
7e231dbe
JB		 1619
1620 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1621 i915_disable_pipestat(dev_priv, pipe,
1622 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1623 imr = I915_READ(VLV_IMR);
31acc7f5 1624 if (pipe == 0)
7e231dbe 1625 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1626 else
7e231dbe 1627 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1628 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1629 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1630}
1631
893eead0
CW		 1632static u32
1633ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1634{
893eead0
CW		 1635 return list_entry(ring->request_list.prev,
1636 struct drm_i915_gem_request, list)->seqno;
1637}
1638
1639static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1640{
1641 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1642 i915_seqno_passed(ring->get_seqno(ring, false),
1643 ring_last_seqno(ring))) {
893eead0 1644 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1645 if (waitqueue_active(&ring->irq_queue)) {
1646 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1647 ring->name);
893eead0
CW		 1648 wake_up_all(&ring->irq_queue);
1649 *err = true;
1650 }
1651 return true;
1652 }
1653 return false;
f65d9421
BG		 1654}
1655
1ec14ad3
CW		 1656static bool kick_ring(struct intel_ring_buffer *ring)
1657{
1658 struct drm_device *dev = ring->dev;
1659 struct drm_i915_private *dev_priv = dev->dev_private;
1660 u32 tmp = I915_READ_CTL(ring);
1661 if (tmp & RING_WAIT) {
1662 DRM_ERROR("Kicking stuck wait on %s\n",
1663 ring->name);
1664 I915_WRITE_CTL(ring, tmp);
1665 return true;
1666 }
1ec14ad3
CW		 1667 return false;
1668}
1669
d1e61e7f
CW		 1670static bool i915_hangcheck_hung(struct drm_device *dev)
1671{
1672 drm_i915_private_t *dev_priv = dev->dev_private;
1673
1674 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1675 bool hung = true;
1676
d1e61e7f
CW		 1677 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1678 i915_handle_error(dev, true);
1679
1680 if (!IS_GEN2(dev)) {
b4519513
CW		 1681 struct intel_ring_buffer *ring;
1682 int i;
1683
d1e61e7f
CW		 1684 /* Is the chip hanging on a WAIT_FOR_EVENT?
1685 * If so we can simply poke the RB_WAIT bit
1686 * and break the hang. This should work on
1687 * all but the second generation chipsets.
1688 */
b4519513
CW		 1689 for_each_ring(ring, dev_priv, i)
1690 hung &= !kick_ring(ring);
d1e61e7f
CW		 1691 }
1692
b4519513 1693 return hung;
d1e61e7f
CW		 1694 }
1695
1696 return false;
1697}
1698
f65d9421
BG		 1699/**
1700 * This is called when the chip hasn't reported back with completed
1701 * batchbuffers in a long time. The first time this is called we simply record
1702 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1703 * again, we assume the chip is wedged and try to fix it.
1704 */
1705void i915_hangcheck_elapsed(unsigned long data)
1706{
1707 struct drm_device *dev = (struct drm_device *)data;
1708 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1709 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1710 struct intel_ring_buffer *ring;
1711 bool err = false, idle;
1712 int i;
893eead0 1713
3e0dc6b0
BW		 1714 if (!i915_enable_hangcheck)
1715 return;
1716
b4519513
CW		 1717 memset(acthd, 0, sizeof(acthd));
1718 idle = true;
1719 for_each_ring(ring, dev_priv, i) {
1720 idle &= i915_hangcheck_ring_idle(ring, &err);
1721 acthd[i] = intel_ring_get_active_head(ring);
1722 }
1723
893eead0 1724 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1725 if (idle) {
d1e61e7f
CW		 1726 if (err) {
1727 if (i915_hangcheck_hung(dev))
1728 return;
1729
893eead0 1730 goto repeat;
d1e61e7f
CW		 1731 }
1732
1733 dev_priv->hangcheck_count = 0;
893eead0
CW		 1734 return;
1735 }
b9201c14 1736
bd9854f9 1737 i915_get_extra_instdone(dev, instdone);
b4519513 1738 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
050ee91f 1739 memcmp(dev_priv->prev_instdone, instdone, sizeof(instdone)) == 0) {
d1e61e7f 1740 if (i915_hangcheck_hung(dev))
cbb465e7 1741 return;
cbb465e7
CW		 1742 } else {
1743 dev_priv->hangcheck_count = 0;
1744
b4519513 1745 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
050ee91f 1746 memcpy(dev_priv->prev_instdone, instdone, sizeof(instdone));
cbb465e7 1747 }
f65d9421 1748
893eead0 1749repeat:
f65d9421 1750 /* Reset timer case chip hangs without another request being added */
b3b079db 1751 mod_timer(&dev_priv->hangcheck_timer,
cecc21fe 1752 round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
f65d9421
BG		 1753}
1754
1da177e4
LT		 1755/* drm_dma.h hooks
1756*/
f71d4af4 1757static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1758{
1759 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1760
4697995b
JB		 1761 atomic_set(&dev_priv->irq_received, 0);
1762
036a4a7d 1763 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1764
036a4a7d
ZW		 1765 /* XXX hotplug from PCH */
1766
1767 I915_WRITE(DEIMR, 0xffffffff);
1768 I915_WRITE(DEIER, 0x0);
3143a2bf 1769 POSTING_READ(DEIER);
036a4a7d
ZW		 1770
1771 /* and GT */
1772 I915_WRITE(GTIMR, 0xffffffff);
1773 I915_WRITE(GTIER, 0x0);
3143a2bf 1774 POSTING_READ(GTIER);
c650156a
ZW		 1775
1776 /* south display irq */
1777 I915_WRITE(SDEIMR, 0xffffffff);
1778 I915_WRITE(SDEIER, 0x0);
3143a2bf 1779 POSTING_READ(SDEIER);
036a4a7d
ZW		 1780}
1781
7e231dbe
JB		 1782static void valleyview_irq_preinstall(struct drm_device *dev)
1783{
1784 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1785 int pipe;
1786
1787 atomic_set(&dev_priv->irq_received, 0);
1788
7e231dbe
JB		 1789 /* VLV magic */
1790 I915_WRITE(VLV_IMR, 0);
1791 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1792 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1793 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1794
7e231dbe
JB		 1795 /* and GT */
1796 I915_WRITE(GTIIR, I915_READ(GTIIR));
1797 I915_WRITE(GTIIR, I915_READ(GTIIR));
1798 I915_WRITE(GTIMR, 0xffffffff);
1799 I915_WRITE(GTIER, 0x0);
1800 POSTING_READ(GTIER);
1801
1802 I915_WRITE(DPINVGTT, 0xff);
1803
1804 I915_WRITE(PORT_HOTPLUG_EN, 0);
1805 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1806 for_each_pipe(pipe)
1807 I915_WRITE(PIPESTAT(pipe), 0xffff);
1808 I915_WRITE(VLV_IIR, 0xffffffff);
1809 I915_WRITE(VLV_IMR, 0xffffffff);
1810 I915_WRITE(VLV_IER, 0x0);
1811 POSTING_READ(VLV_IER);
1812}
1813
7fe0b973
KP		 1814/*
1815 * Enable digital hotplug on the PCH, and configure the DP short pulse
1816 * duration to 2ms (which is the minimum in the Display Port spec)
1817 *
1818 * This register is the same on all known PCH chips.
1819 */
1820
1821static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1822{
1823 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1824 u32 hotplug;
1825
1826 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1827 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1828 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1829 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1830 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1831 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1832}
1833
f71d4af4 1834static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1835{
1836 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1837 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1838 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1839 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1840 u32 render_irqs;
2d7b8366 1841 u32 hotplug_mask;
036a4a7d 1842
1ec14ad3 1843 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1844
1845 /* should always can generate irq */
1846 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1847 I915_WRITE(DEIMR, dev_priv->irq_mask);
1848 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1849 POSTING_READ(DEIER);
036a4a7d 1850
1ec14ad3 1851 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1852
1853 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1854 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1855
1ec14ad3
CW		 1856 if (IS_GEN6(dev))
1857 render_irqs =
1858 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1859 GEN6_BSD_USER_INTERRUPT |
1860 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1861 else
1862 render_irqs =
88f23b8f 1863 GT_USER_INTERRUPT |
c6df541c 1864 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1865 GT_BSD_USER_INTERRUPT;
1866 I915_WRITE(GTIER, render_irqs);
3143a2bf 1867 POSTING_READ(GTIER);
036a4a7d 1868
2d7b8366 1869 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1870 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1871 SDE_PORTB_HOTPLUG_CPT |
1872 SDE_PORTC_HOTPLUG_CPT |
1873 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1874 } else {
9035a97a
CW		 1875 hotplug_mask = (SDE_CRT_HOTPLUG |
1876 SDE_PORTB_HOTPLUG |
1877 SDE_PORTC_HOTPLUG |
1878 SDE_PORTD_HOTPLUG |
1879 SDE_AUX_MASK);
2d7b8366
YL		 1880 }
1881
1ec14ad3 1882 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1883
1884 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1885 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1886 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1887 POSTING_READ(SDEIER);
c650156a 1888
7fe0b973
KP		 1889 ironlake_enable_pch_hotplug(dev);
1890
f97108d1
JB		 1891 if (IS_IRONLAKE_M(dev)) {
1892 /* Clear & enable PCU event interrupts */
1893 I915_WRITE(DEIIR, DE_PCU_EVENT);
1894 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1895 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1896 }
1897
036a4a7d
ZW		 1898 return 0;
1899}
1900
f71d4af4 1901static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1902{
1903 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1904 /* enable kind of interrupts always enabled */
b615b57a
CW		 1905 u32 display_mask =
1906 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1907 DE_PLANEC_FLIP_DONE_IVB |
1908 DE_PLANEB_FLIP_DONE_IVB |
1909 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1910 u32 render_irqs;
1911 u32 hotplug_mask;
1912
b1f14ad0
JB		 1913 dev_priv->irq_mask = ~display_mask;
1914
1915 /* should always can generate irq */
1916 I915_WRITE(DEIIR, I915_READ(DEIIR));
1917 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1918 I915_WRITE(DEIER,
1919 display_mask |
1920 DE_PIPEC_VBLANK_IVB |
1921 DE_PIPEB_VBLANK_IVB |
1922 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1923 POSTING_READ(DEIER);
1924
15b9f80e 1925 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1926
1927 I915_WRITE(GTIIR, I915_READ(GTIIR));
1928 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1929
e2a1e2f0 1930 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1931 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1932 I915_WRITE(GTIER, render_irqs);
1933 POSTING_READ(GTIER);
1934
1935 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1936 SDE_PORTB_HOTPLUG_CPT |
1937 SDE_PORTC_HOTPLUG_CPT |
1938 SDE_PORTD_HOTPLUG_CPT);
1939 dev_priv->pch_irq_mask = ~hotplug_mask;
1940
1941 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1942 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1943 I915_WRITE(SDEIER, hotplug_mask);
1944 POSTING_READ(SDEIER);
1945
7fe0b973
KP		 1946 ironlake_enable_pch_hotplug(dev);
1947
b1f14ad0
JB		 1948 return 0;
1949}
1950
7e231dbe
JB		 1951static int valleyview_irq_postinstall(struct drm_device *dev)
1952{
1953 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1954 u32 enable_mask;
1955 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1956 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
3bcedbe5 1957 u32 render_irqs;
7e231dbe
JB		 1958 u16 msid;
1959
1960 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1961 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1962 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1963 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1964 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1965
31acc7f5
JB		 1966 /*
1967 *Leave vblank interrupts masked initially. enable/disable will
1968 * toggle them based on usage.
1969 */
1970 dev_priv->irq_mask = (~enable_mask) |
1971 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1972 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1973
7e231dbe
JB		 1974 dev_priv->pipestat[0] = 0;
1975 dev_priv->pipestat[1] = 0;
1976
7e231dbe
JB		 1977 /* Hack for broken MSIs on VLV */
1978 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1979 pci_read_config_word(dev->pdev, 0x98, &msid);
1980 msid &= 0xff; /* mask out delivery bits */
1981 msid |= (1<<14);
1982 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1983
1984 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1985 I915_WRITE(VLV_IER, enable_mask);
1986 I915_WRITE(VLV_IIR, 0xffffffff);
1987 I915_WRITE(PIPESTAT(0), 0xffff);
1988 I915_WRITE(PIPESTAT(1), 0xffff);
1989 POSTING_READ(VLV_IER);
1990
31acc7f5
JB		 1991 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1992 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1993
7e231dbe
JB		 1994 I915_WRITE(VLV_IIR, 0xffffffff);
1995 I915_WRITE(VLV_IIR, 0xffffffff);
1996
7e231dbe 1997 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5 1998 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
3bcedbe5
JB		 1999
2000 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2001 GEN6_BLITTER_USER_INTERRUPT;
2002 I915_WRITE(GTIER, render_irqs);
7e231dbe
JB		 2003 POSTING_READ(GTIER);
2004
2005 /* ack & enable invalid PTE error interrupts */
2006#if 0 /* FIXME: add support to irq handler for checking these bits */
2007 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2008 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2009#endif
2010
2011 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
7e231dbe
JB		 2012 /* Note HDMI and DP share bits */
2013 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2014 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2015 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2016 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2017 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2018 hotplug_en |= HDMID_HOTPLUG_INT_EN;
ae33cdcf 2019 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
7e231dbe 2020 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
ae33cdcf 2021 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
7e231dbe
JB		 2022 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2023 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2024 hotplug_en |= CRT_HOTPLUG_INT_EN;
2025 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2026 }
7e231dbe
JB		 2027
2028 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2029
2030 return 0;
2031}
2032
7e231dbe
JB		 2033static void valleyview_irq_uninstall(struct drm_device *dev)
2034{
2035 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2036 int pipe;
2037
2038 if (!dev_priv)
2039 return;
2040
7e231dbe
JB		 2041 for_each_pipe(pipe)
2042 I915_WRITE(PIPESTAT(pipe), 0xffff);
2043
2044 I915_WRITE(HWSTAM, 0xffffffff);
2045 I915_WRITE(PORT_HOTPLUG_EN, 0);
2046 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2047 for_each_pipe(pipe)
2048 I915_WRITE(PIPESTAT(pipe), 0xffff);
2049 I915_WRITE(VLV_IIR, 0xffffffff);
2050 I915_WRITE(VLV_IMR, 0xffffffff);
2051 I915_WRITE(VLV_IER, 0x0);
2052 POSTING_READ(VLV_IER);
2053}
2054
f71d4af4 2055static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2056{
2057 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2058
2059 if (!dev_priv)
2060 return;
2061
036a4a7d
ZW		 2062 I915_WRITE(HWSTAM, 0xffffffff);
2063
2064 I915_WRITE(DEIMR, 0xffffffff);
2065 I915_WRITE(DEIER, 0x0);
2066 I915_WRITE(DEIIR, I915_READ(DEIIR));
2067
2068 I915_WRITE(GTIMR, 0xffffffff);
2069 I915_WRITE(GTIER, 0x0);
2070 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2071
2072 I915_WRITE(SDEIMR, 0xffffffff);
2073 I915_WRITE(SDEIER, 0x0);
2074 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2075}
2076
a266c7d5 2077static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2078{
2079 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2080 int pipe;
91e3738e 2081
a266c7d5 2082 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2083
9db4a9c7
JB		 2084 for_each_pipe(pipe)
2085 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2086 I915_WRITE16(IMR, 0xffff);
2087 I915_WRITE16(IER, 0x0);
2088 POSTING_READ16(IER);
c2798b19
CW		 2089}
2090
2091static int i8xx_irq_postinstall(struct drm_device *dev)
2092{
2093 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2094
c2798b19
CW		 2095 dev_priv->pipestat[0] = 0;
2096 dev_priv->pipestat[1] = 0;
2097
2098 I915_WRITE16(EMR,
2099 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2100
2101 /* Unmask the interrupts that we always want on. */
2102 dev_priv->irq_mask =
2103 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2104 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2105 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2106 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2107 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2108 I915_WRITE16(IMR, dev_priv->irq_mask);
2109
2110 I915_WRITE16(IER,
2111 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2112 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2113 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2114 I915_USER_INTERRUPT);
2115 POSTING_READ16(IER);
2116
2117 return 0;
2118}
2119
ff1f525e 2120static irqreturn_t i8xx_irq_handler(int irq, void *arg)
c2798b19
CW		 2121{
2122 struct drm_device *dev = (struct drm_device *) arg;
2123 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2124 u16 iir, new_iir;
2125 u32 pipe_stats[2];
2126 unsigned long irqflags;
2127 int irq_received;
2128 int pipe;
2129 u16 flip_mask =
2130 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2131 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2132
2133 atomic_inc(&dev_priv->irq_received);
2134
2135 iir = I915_READ16(IIR);
2136 if (iir == 0)
2137 return IRQ_NONE;
2138
2139 while (iir & ~flip_mask) {
2140 /* Can't rely on pipestat interrupt bit in iir as it might
2141 * have been cleared after the pipestat interrupt was received.
2142 * It doesn't set the bit in iir again, but it still produces
2143 * interrupts (for non-MSI).
2144 */
2145 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2146 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2147 i915_handle_error(dev, false);
2148
2149 for_each_pipe(pipe) {
2150 int reg = PIPESTAT(pipe);
2151 pipe_stats[pipe] = I915_READ(reg);
2152
2153 /*
2154 * Clear the PIPE*STAT regs before the IIR
2155 */
2156 if (pipe_stats[pipe] & 0x8000ffff) {
2157 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2158 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2159 pipe_name(pipe));
2160 I915_WRITE(reg, pipe_stats[pipe]);
2161 irq_received = 1;
2162 }
2163 }
2164 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2165
2166 I915_WRITE16(IIR, iir & ~flip_mask);
2167 new_iir = I915_READ16(IIR); /* Flush posted writes */
2168
d05c617e 2169 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2170
2171 if (iir & I915_USER_INTERRUPT)
2172 notify_ring(dev, &dev_priv->ring[RCS]);
2173
2174 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2175 drm_handle_vblank(dev, 0)) {
2176 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2177 intel_prepare_page_flip(dev, 0);
2178 intel_finish_page_flip(dev, 0);
2179 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2180 }
2181 }
2182
2183 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2184 drm_handle_vblank(dev, 1)) {
2185 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2186 intel_prepare_page_flip(dev, 1);
2187 intel_finish_page_flip(dev, 1);
2188 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2189 }
2190 }
2191
2192 iir = new_iir;
2193 }
2194
2195 return IRQ_HANDLED;
2196}
2197
2198static void i8xx_irq_uninstall(struct drm_device * dev)
2199{
2200 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2201 int pipe;
2202
c2798b19
CW		 2203 for_each_pipe(pipe) {
2204 /* Clear enable bits; then clear status bits */
2205 I915_WRITE(PIPESTAT(pipe), 0);
2206 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2207 }
2208 I915_WRITE16(IMR, 0xffff);
2209 I915_WRITE16(IER, 0x0);
2210 I915_WRITE16(IIR, I915_READ16(IIR));
2211}
2212
a266c7d5
CW		 2213static void i915_irq_preinstall(struct drm_device * dev)
2214{
2215 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2216 int pipe;
2217
2218 atomic_set(&dev_priv->irq_received, 0);
2219
2220 if (I915_HAS_HOTPLUG(dev)) {
2221 I915_WRITE(PORT_HOTPLUG_EN, 0);
2222 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2223 }
2224
00d98ebd 2225 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2226 for_each_pipe(pipe)
2227 I915_WRITE(PIPESTAT(pipe), 0);
2228 I915_WRITE(IMR, 0xffffffff);
2229 I915_WRITE(IER, 0x0);
2230 POSTING_READ(IER);
2231}
2232
2233static int i915_irq_postinstall(struct drm_device *dev)
2234{
2235 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2236 u32 enable_mask;
a266c7d5 2237
a266c7d5
CW		 2238 dev_priv->pipestat[0] = 0;
2239 dev_priv->pipestat[1] = 0;
2240
38bde180
CW		 2241 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2242
2243 /* Unmask the interrupts that we always want on. */
2244 dev_priv->irq_mask =
2245 ~(I915_ASLE_INTERRUPT |
2246 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2247 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2248 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2249 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2250 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2251
2252 enable_mask =
2253 I915_ASLE_INTERRUPT |
2254 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2255 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2256 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2257 I915_USER_INTERRUPT;
2258
a266c7d5
CW		 2259 if (I915_HAS_HOTPLUG(dev)) {
2260 /* Enable in IER... */
2261 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2262 /* and unmask in IMR */
2263 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2264 }
2265
a266c7d5
CW		 2266 I915_WRITE(IMR, dev_priv->irq_mask);
2267 I915_WRITE(IER, enable_mask);
2268 POSTING_READ(IER);
2269
2270 if (I915_HAS_HOTPLUG(dev)) {
2271 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2272
a266c7d5
CW		 2273 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2274 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2275 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2276 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2277 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2278 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2279 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2280 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2281 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2282 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2283 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2284 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2285 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2286 }
2287
2288 /* Ignore TV since it's buggy */
2289
2290 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2291 }
2292
2293 intel_opregion_enable_asle(dev);
2294
2295 return 0;
2296}
2297
ff1f525e 2298static irqreturn_t i915_irq_handler(int irq, void *arg)
a266c7d5
CW		 2299{
2300 struct drm_device *dev = (struct drm_device *) arg;
2301 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2302 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2303 unsigned long irqflags;
38bde180
CW		 2304 u32 flip_mask =
2305 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2306 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2307 u32 flip[2] = {
2308 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2309 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2310 };
2311 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2312
2313 atomic_inc(&dev_priv->irq_received);
2314
2315 iir = I915_READ(IIR);
38bde180
CW		 2316 do {
2317 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2318 bool blc_event = false;
a266c7d5
CW		 2319
2320 /* Can't rely on pipestat interrupt bit in iir as it might
2321 * have been cleared after the pipestat interrupt was received.
2322 * It doesn't set the bit in iir again, but it still produces
2323 * interrupts (for non-MSI).
2324 */
2325 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2326 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2327 i915_handle_error(dev, false);
2328
2329 for_each_pipe(pipe) {
2330 int reg = PIPESTAT(pipe);
2331 pipe_stats[pipe] = I915_READ(reg);
2332
38bde180 2333 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2334 if (pipe_stats[pipe] & 0x8000ffff) {
2335 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2336 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2337 pipe_name(pipe));
2338 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2339 irq_received = true;
a266c7d5
CW		 2340 }
2341 }
2342 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2343
2344 if (!irq_received)
2345 break;
2346
a266c7d5
CW		 2347 /* Consume port. Then clear IIR or we'll miss events */
2348 if ((I915_HAS_HOTPLUG(dev)) &&
2349 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2350 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2351
2352 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2353 hotplug_status);
2354 if (hotplug_status & dev_priv->hotplug_supported_mask)
2355 queue_work(dev_priv->wq,
2356 &dev_priv->hotplug_work);
2357
2358 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2359 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2360 }
2361
38bde180 2362 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2363 new_iir = I915_READ(IIR); /* Flush posted writes */
2364
a266c7d5
CW		 2365 if (iir & I915_USER_INTERRUPT)
2366 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2367
a266c7d5 2368 for_each_pipe(pipe) {
38bde180
CW		 2369 int plane = pipe;
2370 if (IS_MOBILE(dev))
2371 plane = !plane;
8291ee90 2372 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2373 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2374 if (iir & flip[plane]) {
2375 intel_prepare_page_flip(dev, plane);
2376 intel_finish_page_flip(dev, pipe);
2377 flip_mask &= ~flip[plane];
2378 }
a266c7d5
CW		 2379 }
2380
2381 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2382 blc_event = true;
2383 }
2384
a266c7d5
CW		 2385 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2386 intel_opregion_asle_intr(dev);
2387
2388 /* With MSI, interrupts are only generated when iir
2389 * transitions from zero to nonzero. If another bit got
2390 * set while we were handling the existing iir bits, then
2391 * we would never get another interrupt.
2392 *
2393 * This is fine on non-MSI as well, as if we hit this path
2394 * we avoid exiting the interrupt handler only to generate
2395 * another one.
2396 *
2397 * Note that for MSI this could cause a stray interrupt report
2398 * if an interrupt landed in the time between writing IIR and
2399 * the posting read. This should be rare enough to never
2400 * trigger the 99% of 100,000 interrupts test for disabling
2401 * stray interrupts.
2402 */
38bde180 2403 ret = IRQ_HANDLED;
a266c7d5 2404 iir = new_iir;
38bde180 2405 } while (iir & ~flip_mask);
a266c7d5 2406
d05c617e 2407 i915_update_dri1_breadcrumb(dev);
8291ee90 2408
a266c7d5
CW		 2409 return ret;
2410}
2411
2412static void i915_irq_uninstall(struct drm_device * dev)
2413{
2414 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2415 int pipe;
2416
a266c7d5
CW		 2417 if (I915_HAS_HOTPLUG(dev)) {
2418 I915_WRITE(PORT_HOTPLUG_EN, 0);
2419 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2420 }
2421
00d98ebd 2422 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2423 for_each_pipe(pipe) {
2424 /* Clear enable bits; then clear status bits */
a266c7d5 2425 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2426 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2427 }
a266c7d5
CW		 2428 I915_WRITE(IMR, 0xffffffff);
2429 I915_WRITE(IER, 0x0);
2430
a266c7d5
CW		 2431 I915_WRITE(IIR, I915_READ(IIR));
2432}
2433
2434static void i965_irq_preinstall(struct drm_device * dev)
2435{
2436 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2437 int pipe;
2438
2439 atomic_set(&dev_priv->irq_received, 0);
2440
adca4730
CW		 2441 I915_WRITE(PORT_HOTPLUG_EN, 0);
2442 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2443
2444 I915_WRITE(HWSTAM, 0xeffe);
2445 for_each_pipe(pipe)
2446 I915_WRITE(PIPESTAT(pipe), 0);
2447 I915_WRITE(IMR, 0xffffffff);
2448 I915_WRITE(IER, 0x0);
2449 POSTING_READ(IER);
2450}
2451
2452static int i965_irq_postinstall(struct drm_device *dev)
2453{
2454 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2455 u32 hotplug_en;
bbba0a97 2456 u32 enable_mask;
a266c7d5
CW		 2457 u32 error_mask;
2458
a266c7d5 2459 /* Unmask the interrupts that we always want on. */
bbba0a97 2460 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2461 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2462 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2463 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2464 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2465 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2466 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2467
2468 enable_mask = ~dev_priv->irq_mask;
2469 enable_mask |= I915_USER_INTERRUPT;
2470
2471 if (IS_G4X(dev))
2472 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2473
2474 dev_priv->pipestat[0] = 0;
2475 dev_priv->pipestat[1] = 0;
2476
a266c7d5
CW		 2477 /*
2478 * Enable some error detection, note the instruction error mask
2479 * bit is reserved, so we leave it masked.
2480 */
2481 if (IS_G4X(dev)) {
2482 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2483 GM45_ERROR_MEM_PRIV |
2484 GM45_ERROR_CP_PRIV |
2485 I915_ERROR_MEMORY_REFRESH);
2486 } else {
2487 error_mask = ~(I915_ERROR_PAGE_TABLE |
2488 I915_ERROR_MEMORY_REFRESH);
2489 }
2490 I915_WRITE(EMR, error_mask);
2491
2492 I915_WRITE(IMR, dev_priv->irq_mask);
2493 I915_WRITE(IER, enable_mask);
2494 POSTING_READ(IER);
2495
adca4730
CW		 2496 /* Note HDMI and DP share hotplug bits */
2497 hotplug_en = 0;
2498 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2499 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2500 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2501 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2502 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2503 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2504 if (IS_G4X(dev)) {
2505 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2506 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2507 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2508 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2509 } else {
2510 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2511 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2512 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2513 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2514 }
adca4730
CW		 2515 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2516 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2517
adca4730
CW		 2518 /* Programming the CRT detection parameters tends
2519 to generate a spurious hotplug event about three
2520 seconds later. So just do it once.
2521 */
2522 if (IS_G4X(dev))
2523 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2524 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2525 }
a266c7d5 2526
adca4730 2527 /* Ignore TV since it's buggy */
a266c7d5 2528
adca4730 2529 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2530
2531 intel_opregion_enable_asle(dev);
2532
2533 return 0;
2534}
2535
ff1f525e 2536static irqreturn_t i965_irq_handler(int irq, void *arg)
a266c7d5
CW		 2537{
2538 struct drm_device *dev = (struct drm_device *) arg;
2539 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2540 u32 iir, new_iir;
2541 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2542 unsigned long irqflags;
2543 int irq_received;
2544 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2545
2546 atomic_inc(&dev_priv->irq_received);
2547
2548 iir = I915_READ(IIR);
2549
a266c7d5 2550 for (;;) {
2c8ba29f
CW		 2551 bool blc_event = false;
2552
a266c7d5
CW		 2553 irq_received = iir != 0;
2554
2555 /* Can't rely on pipestat interrupt bit in iir as it might
2556 * have been cleared after the pipestat interrupt was received.
2557 * It doesn't set the bit in iir again, but it still produces
2558 * interrupts (for non-MSI).
2559 */
2560 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2561 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2562 i915_handle_error(dev, false);
2563
2564 for_each_pipe(pipe) {
2565 int reg = PIPESTAT(pipe);
2566 pipe_stats[pipe] = I915_READ(reg);
2567
2568 /*
2569 * Clear the PIPE*STAT regs before the IIR
2570 */
2571 if (pipe_stats[pipe] & 0x8000ffff) {
2572 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2573 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2574 pipe_name(pipe));
2575 I915_WRITE(reg, pipe_stats[pipe]);
2576 irq_received = 1;
2577 }
2578 }
2579 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2580
2581 if (!irq_received)
2582 break;
2583
2584 ret = IRQ_HANDLED;
2585
2586 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2587 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2588 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2589
2590 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2591 hotplug_status);
2592 if (hotplug_status & dev_priv->hotplug_supported_mask)
2593 queue_work(dev_priv->wq,
2594 &dev_priv->hotplug_work);
2595
2596 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2597 I915_READ(PORT_HOTPLUG_STAT);
2598 }
2599
2600 I915_WRITE(IIR, iir);
2601 new_iir = I915_READ(IIR); /* Flush posted writes */
2602
a266c7d5
CW		 2603 if (iir & I915_USER_INTERRUPT)
2604 notify_ring(dev, &dev_priv->ring[RCS]);
2605 if (iir & I915_BSD_USER_INTERRUPT)
2606 notify_ring(dev, &dev_priv->ring[VCS]);
2607
4f7d1e79 2608 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2609 intel_prepare_page_flip(dev, 0);
a266c7d5 2610
4f7d1e79 2611 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2612 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2613
2614 for_each_pipe(pipe) {
2c8ba29f 2615 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2616 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2617 i915_pageflip_stall_check(dev, pipe);
2618 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2619 }
2620
2621 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2622 blc_event = true;
2623 }
2624
2625
2626 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2627 intel_opregion_asle_intr(dev);
2628
2629 /* With MSI, interrupts are only generated when iir
2630 * transitions from zero to nonzero. If another bit got
2631 * set while we were handling the existing iir bits, then
2632 * we would never get another interrupt.
2633 *
2634 * This is fine on non-MSI as well, as if we hit this path
2635 * we avoid exiting the interrupt handler only to generate
2636 * another one.
2637 *
2638 * Note that for MSI this could cause a stray interrupt report
2639 * if an interrupt landed in the time between writing IIR and
2640 * the posting read. This should be rare enough to never
2641 * trigger the 99% of 100,000 interrupts test for disabling
2642 * stray interrupts.
2643 */
2644 iir = new_iir;
2645 }
2646
d05c617e 2647 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2648
a266c7d5
CW		 2649 return ret;
2650}
2651
2652static void i965_irq_uninstall(struct drm_device * dev)
2653{
2654 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2655 int pipe;
2656
2657 if (!dev_priv)
2658 return;
2659
adca4730
CW		 2660 I915_WRITE(PORT_HOTPLUG_EN, 0);
2661 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2662
2663 I915_WRITE(HWSTAM, 0xffffffff);
2664 for_each_pipe(pipe)
2665 I915_WRITE(PIPESTAT(pipe), 0);
2666 I915_WRITE(IMR, 0xffffffff);
2667 I915_WRITE(IER, 0x0);
2668
2669 for_each_pipe(pipe)
2670 I915_WRITE(PIPESTAT(pipe),
2671 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2672 I915_WRITE(IIR, I915_READ(IIR));
2673}
2674
f71d4af4
JB		 2675void intel_irq_init(struct drm_device *dev)
2676{
8b2e326d
CW		 2677 struct drm_i915_private *dev_priv = dev->dev_private;
2678
2679 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2680 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2681 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
98fd81cd 2682 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2683
f71d4af4
JB		 2684 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2685 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2686 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2687 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2688 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2689 }
2690
c3613de9
KP		 2691 if (drm_core_check_feature(dev, DRIVER_MODESET))
2692 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2693 else
2694 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2695 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2696
7e231dbe
JB		 2697 if (IS_VALLEYVIEW(dev)) {
2698 dev->driver->irq_handler = valleyview_irq_handler;
2699 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2700 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2701 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2702 dev->driver->enable_vblank = valleyview_enable_vblank;
2703 dev->driver->disable_vblank = valleyview_disable_vblank;
2704 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2705 /* Share pre & uninstall handlers with ILK/SNB */
2706 dev->driver->irq_handler = ivybridge_irq_handler;
2707 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2708 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2709 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2710 dev->driver->enable_vblank = ivybridge_enable_vblank;
2711 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2712 } else if (IS_HASWELL(dev)) {
2713 /* Share interrupts handling with IVB */
2714 dev->driver->irq_handler = ivybridge_irq_handler;
2715 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2716 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2717 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2718 dev->driver->enable_vblank = ivybridge_enable_vblank;
2719 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2720 } else if (HAS_PCH_SPLIT(dev)) {
2721 dev->driver->irq_handler = ironlake_irq_handler;
2722 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2723 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2724 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2725 dev->driver->enable_vblank = ironlake_enable_vblank;
2726 dev->driver->disable_vblank = ironlake_disable_vblank;
2727 } else {
c2798b19
CW		 2728 if (INTEL_INFO(dev)->gen == 2) {
2729 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2730 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2731 dev->driver->irq_handler = i8xx_irq_handler;
2732 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5
CW		 2733 } else if (INTEL_INFO(dev)->gen == 3) {
2734 dev->driver->irq_preinstall = i915_irq_preinstall;
2735 dev->driver->irq_postinstall = i915_irq_postinstall;
2736 dev->driver->irq_uninstall = i915_irq_uninstall;
2737 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2738 } else {
a266c7d5
CW		 2739 dev->driver->irq_preinstall = i965_irq_preinstall;
2740 dev->driver->irq_postinstall = i965_irq_postinstall;
2741 dev->driver->irq_uninstall = i965_irq_uninstall;
2742 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2743 }
f71d4af4
JB		 2744 dev->driver->enable_vblank = i915_enable_vblank;
2745 dev->driver->disable_vblank = i915_disable_vblank;
2746 }
2747}
Linux kernel - Deliverables
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