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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | /* For display hotplug interrupt */ |
995b6762 | 68 | static void |
f2b115e6 | 69 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 70 | { |
1ec14ad3 CW |
71 | if ((dev_priv->irq_mask & mask) != 0) { |
72 | dev_priv->irq_mask &= ~mask; | |
73 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 74 | POSTING_READ(DEIMR); |
036a4a7d ZW |
75 | } |
76 | } | |
77 | ||
78 | static inline void | |
f2b115e6 | 79 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 80 | { |
1ec14ad3 CW |
81 | if ((dev_priv->irq_mask & mask) != mask) { |
82 | dev_priv->irq_mask |= mask; | |
83 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 84 | POSTING_READ(DEIMR); |
036a4a7d ZW |
85 | } |
86 | } | |
87 | ||
7c463586 KP |
88 | void |
89 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
90 | { | |
91 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
9db4a9c7 | 92 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
93 | |
94 | dev_priv->pipestat[pipe] |= mask; | |
95 | /* Enable the interrupt, clear any pending status */ | |
96 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 97 | POSTING_READ(reg); |
7c463586 KP |
98 | } |
99 | } | |
100 | ||
101 | void | |
102 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
103 | { | |
104 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
9db4a9c7 | 105 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
106 | |
107 | dev_priv->pipestat[pipe] &= ~mask; | |
108 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 109 | POSTING_READ(reg); |
7c463586 KP |
110 | } |
111 | } | |
112 | ||
01c66889 ZY |
113 | /** |
114 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
115 | */ | |
1ec14ad3 | 116 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 117 | { |
1ec14ad3 CW |
118 | drm_i915_private_t *dev_priv = dev->dev_private; |
119 | unsigned long irqflags; | |
120 | ||
121 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
01c66889 | 122 | |
c619eed4 | 123 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 124 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 125 | else { |
01c66889 | 126 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 127 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 128 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 129 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 130 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 131 | } |
1ec14ad3 CW |
132 | |
133 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
134 | } |
135 | ||
0a3e67a4 JB |
136 | /** |
137 | * i915_pipe_enabled - check if a pipe is enabled | |
138 | * @dev: DRM device | |
139 | * @pipe: pipe to check | |
140 | * | |
141 | * Reading certain registers when the pipe is disabled can hang the chip. | |
142 | * Use this routine to make sure the PLL is running and the pipe is active | |
143 | * before reading such registers if unsure. | |
144 | */ | |
145 | static int | |
146 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
147 | { | |
148 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 149 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
150 | } |
151 | ||
42f52ef8 KP |
152 | /* Called from drm generic code, passed a 'crtc', which |
153 | * we use as a pipe index | |
154 | */ | |
f71d4af4 | 155 | static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
156 | { |
157 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
158 | unsigned long high_frame; | |
159 | unsigned long low_frame; | |
5eddb70b | 160 | u32 high1, high2, low; |
0a3e67a4 JB |
161 | |
162 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 163 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 164 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
165 | return 0; |
166 | } | |
167 | ||
9db4a9c7 JB |
168 | high_frame = PIPEFRAME(pipe); |
169 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 170 | |
0a3e67a4 JB |
171 | /* |
172 | * High & low register fields aren't synchronized, so make sure | |
173 | * we get a low value that's stable across two reads of the high | |
174 | * register. | |
175 | */ | |
176 | do { | |
5eddb70b CW |
177 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
178 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
179 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
180 | } while (high1 != high2); |
181 | ||
5eddb70b CW |
182 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
183 | low >>= PIPE_FRAME_LOW_SHIFT; | |
184 | return (high1 << 8) | low; | |
0a3e67a4 JB |
185 | } |
186 | ||
f71d4af4 | 187 | static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
9880b7a5 JB |
188 | { |
189 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 190 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
191 | |
192 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 193 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 194 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
195 | return 0; |
196 | } | |
197 | ||
198 | return I915_READ(reg); | |
199 | } | |
200 | ||
f71d4af4 | 201 | static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
0af7e4df MK |
202 | int *vpos, int *hpos) |
203 | { | |
204 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
205 | u32 vbl = 0, position = 0; | |
206 | int vbl_start, vbl_end, htotal, vtotal; | |
207 | bool in_vbl = true; | |
208 | int ret = 0; | |
209 | ||
210 | if (!i915_pipe_enabled(dev, pipe)) { | |
211 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 212 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
213 | return 0; |
214 | } | |
215 | ||
216 | /* Get vtotal. */ | |
217 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); | |
218 | ||
219 | if (INTEL_INFO(dev)->gen >= 4) { | |
220 | /* No obvious pixelcount register. Only query vertical | |
221 | * scanout position from Display scan line register. | |
222 | */ | |
223 | position = I915_READ(PIPEDSL(pipe)); | |
224 | ||
225 | /* Decode into vertical scanout position. Don't have | |
226 | * horizontal scanout position. | |
227 | */ | |
228 | *vpos = position & 0x1fff; | |
229 | *hpos = 0; | |
230 | } else { | |
231 | /* Have access to pixelcount since start of frame. | |
232 | * We can split this into vertical and horizontal | |
233 | * scanout position. | |
234 | */ | |
235 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
236 | ||
237 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); | |
238 | *vpos = position / htotal; | |
239 | *hpos = position - (*vpos * htotal); | |
240 | } | |
241 | ||
242 | /* Query vblank area. */ | |
243 | vbl = I915_READ(VBLANK(pipe)); | |
244 | ||
245 | /* Test position against vblank region. */ | |
246 | vbl_start = vbl & 0x1fff; | |
247 | vbl_end = (vbl >> 16) & 0x1fff; | |
248 | ||
249 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
250 | in_vbl = false; | |
251 | ||
252 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
253 | if (in_vbl && (*vpos >= vbl_start)) | |
254 | *vpos = *vpos - vtotal; | |
255 | ||
256 | /* Readouts valid? */ | |
257 | if (vbl > 0) | |
258 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
259 | ||
260 | /* In vblank? */ | |
261 | if (in_vbl) | |
262 | ret |= DRM_SCANOUTPOS_INVBL; | |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
f71d4af4 | 267 | static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
268 | int *max_error, |
269 | struct timeval *vblank_time, | |
270 | unsigned flags) | |
271 | { | |
4041b853 CW |
272 | struct drm_i915_private *dev_priv = dev->dev_private; |
273 | struct drm_crtc *crtc; | |
0af7e4df | 274 | |
4041b853 CW |
275 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
276 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
0af7e4df MK |
277 | return -EINVAL; |
278 | } | |
279 | ||
280 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
281 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
282 | if (crtc == NULL) { | |
283 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | if (!crtc->enabled) { | |
288 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
289 | return -EBUSY; | |
290 | } | |
0af7e4df MK |
291 | |
292 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
293 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
294 | vblank_time, flags, | |
295 | crtc); | |
0af7e4df MK |
296 | } |
297 | ||
5ca58282 JB |
298 | /* |
299 | * Handle hotplug events outside the interrupt handler proper. | |
300 | */ | |
301 | static void i915_hotplug_work_func(struct work_struct *work) | |
302 | { | |
303 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
304 | hotplug_work); | |
305 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 306 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
307 | struct intel_encoder *encoder; |
308 | ||
a65e34c7 | 309 | mutex_lock(&mode_config->mutex); |
e67189ab JB |
310 | DRM_DEBUG_KMS("running encoder hotplug functions\n"); |
311 | ||
4ef69c7a CW |
312 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) |
313 | if (encoder->hot_plug) | |
314 | encoder->hot_plug(encoder); | |
315 | ||
40ee3381 KP |
316 | mutex_unlock(&mode_config->mutex); |
317 | ||
5ca58282 | 318 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 319 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
320 | } |
321 | ||
f97108d1 JB |
322 | static void i915_handle_rps_change(struct drm_device *dev) |
323 | { | |
324 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 325 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
326 | u8 new_delay = dev_priv->cur_delay; |
327 | ||
7648fa99 | 328 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
329 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
330 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
331 | max_avg = I915_READ(RCBMAXAVG); |
332 | min_avg = I915_READ(RCBMINAVG); | |
333 | ||
334 | /* Handle RCS change request from hw */ | |
b5b72e89 | 335 | if (busy_up > max_avg) { |
f97108d1 JB |
336 | if (dev_priv->cur_delay != dev_priv->max_delay) |
337 | new_delay = dev_priv->cur_delay - 1; | |
338 | if (new_delay < dev_priv->max_delay) | |
339 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 340 | } else if (busy_down < min_avg) { |
f97108d1 JB |
341 | if (dev_priv->cur_delay != dev_priv->min_delay) |
342 | new_delay = dev_priv->cur_delay + 1; | |
343 | if (new_delay > dev_priv->min_delay) | |
344 | new_delay = dev_priv->min_delay; | |
345 | } | |
346 | ||
7648fa99 JB |
347 | if (ironlake_set_drps(dev, new_delay)) |
348 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
349 | |
350 | return; | |
351 | } | |
352 | ||
549f7365 CW |
353 | static void notify_ring(struct drm_device *dev, |
354 | struct intel_ring_buffer *ring) | |
355 | { | |
356 | struct drm_i915_private *dev_priv = dev->dev_private; | |
475553de | 357 | u32 seqno; |
9862e600 | 358 | |
475553de CW |
359 | if (ring->obj == NULL) |
360 | return; | |
361 | ||
362 | seqno = ring->get_seqno(ring); | |
db53a302 | 363 | trace_i915_gem_request_complete(ring, seqno); |
9862e600 CW |
364 | |
365 | ring->irq_seqno = seqno; | |
549f7365 | 366 | wake_up_all(&ring->irq_queue); |
3e0dc6b0 BW |
367 | if (i915_enable_hangcheck) { |
368 | dev_priv->hangcheck_count = 0; | |
369 | mod_timer(&dev_priv->hangcheck_timer, | |
370 | jiffies + | |
371 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
372 | } | |
549f7365 CW |
373 | } |
374 | ||
4912d041 | 375 | static void gen6_pm_rps_work(struct work_struct *work) |
3b8d8d91 | 376 | { |
4912d041 BW |
377 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, |
378 | rps_work); | |
3b8d8d91 | 379 | u8 new_delay = dev_priv->cur_delay; |
4912d041 BW |
380 | u32 pm_iir, pm_imr; |
381 | ||
382 | spin_lock_irq(&dev_priv->rps_lock); | |
383 | pm_iir = dev_priv->pm_iir; | |
384 | dev_priv->pm_iir = 0; | |
385 | pm_imr = I915_READ(GEN6_PMIMR); | |
386 | spin_unlock_irq(&dev_priv->rps_lock); | |
3b8d8d91 | 387 | |
3b8d8d91 JB |
388 | if (!pm_iir) |
389 | return; | |
390 | ||
4912d041 | 391 | mutex_lock(&dev_priv->dev->struct_mutex); |
3b8d8d91 JB |
392 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { |
393 | if (dev_priv->cur_delay != dev_priv->max_delay) | |
394 | new_delay = dev_priv->cur_delay + 1; | |
395 | if (new_delay > dev_priv->max_delay) | |
396 | new_delay = dev_priv->max_delay; | |
397 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { | |
4912d041 | 398 | gen6_gt_force_wake_get(dev_priv); |
3b8d8d91 JB |
399 | if (dev_priv->cur_delay != dev_priv->min_delay) |
400 | new_delay = dev_priv->cur_delay - 1; | |
401 | if (new_delay < dev_priv->min_delay) { | |
402 | new_delay = dev_priv->min_delay; | |
403 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
404 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | | |
405 | ((new_delay << 16) & 0x3f0000)); | |
406 | } else { | |
407 | /* Make sure we continue to get down interrupts | |
408 | * until we hit the minimum frequency */ | |
409 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
410 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); | |
411 | } | |
4912d041 | 412 | gen6_gt_force_wake_put(dev_priv); |
3b8d8d91 JB |
413 | } |
414 | ||
4912d041 | 415 | gen6_set_rps(dev_priv->dev, new_delay); |
3b8d8d91 JB |
416 | dev_priv->cur_delay = new_delay; |
417 | ||
4912d041 BW |
418 | /* |
419 | * rps_lock not held here because clearing is non-destructive. There is | |
420 | * an *extremely* unlikely race with gen6_rps_enable() that is prevented | |
421 | * by holding struct_mutex for the duration of the write. | |
422 | */ | |
423 | I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir); | |
424 | mutex_unlock(&dev_priv->dev->struct_mutex); | |
3b8d8d91 JB |
425 | } |
426 | ||
776ad806 JB |
427 | static void pch_irq_handler(struct drm_device *dev) |
428 | { | |
429 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
430 | u32 pch_iir; | |
9db4a9c7 | 431 | int pipe; |
776ad806 JB |
432 | |
433 | pch_iir = I915_READ(SDEIIR); | |
434 | ||
435 | if (pch_iir & SDE_AUDIO_POWER_MASK) | |
436 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
437 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
438 | SDE_AUDIO_POWER_SHIFT); | |
439 | ||
440 | if (pch_iir & SDE_GMBUS) | |
441 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
442 | ||
443 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
444 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
445 | ||
446 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
447 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
448 | ||
449 | if (pch_iir & SDE_POISON) | |
450 | DRM_ERROR("PCH poison interrupt\n"); | |
451 | ||
9db4a9c7 JB |
452 | if (pch_iir & SDE_FDI_MASK) |
453 | for_each_pipe(pipe) | |
454 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
455 | pipe_name(pipe), | |
456 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
457 | |
458 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
459 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
460 | ||
461 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
462 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
463 | ||
464 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
465 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
466 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
467 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
468 | } | |
469 | ||
f71d4af4 | 470 | static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS) |
b1f14ad0 JB |
471 | { |
472 | struct drm_device *dev = (struct drm_device *) arg; | |
473 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
474 | int ret = IRQ_NONE; | |
475 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; | |
476 | struct drm_i915_master_private *master_priv; | |
477 | ||
478 | atomic_inc(&dev_priv->irq_received); | |
479 | ||
480 | /* disable master interrupt before clearing iir */ | |
481 | de_ier = I915_READ(DEIER); | |
482 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
483 | POSTING_READ(DEIER); | |
484 | ||
485 | de_iir = I915_READ(DEIIR); | |
486 | gt_iir = I915_READ(GTIIR); | |
487 | pch_iir = I915_READ(SDEIIR); | |
488 | pm_iir = I915_READ(GEN6_PMIIR); | |
489 | ||
490 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0) | |
491 | goto done; | |
492 | ||
493 | ret = IRQ_HANDLED; | |
494 | ||
495 | if (dev->primary->master) { | |
496 | master_priv = dev->primary->master->driver_priv; | |
497 | if (master_priv->sarea_priv) | |
498 | master_priv->sarea_priv->last_dispatch = | |
499 | READ_BREADCRUMB(dev_priv); | |
500 | } | |
501 | ||
502 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) | |
503 | notify_ring(dev, &dev_priv->ring[RCS]); | |
504 | if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT) | |
505 | notify_ring(dev, &dev_priv->ring[VCS]); | |
506 | if (gt_iir & GT_BLT_USER_INTERRUPT) | |
507 | notify_ring(dev, &dev_priv->ring[BCS]); | |
508 | ||
509 | if (de_iir & DE_GSE_IVB) | |
510 | intel_opregion_gse_intr(dev); | |
511 | ||
512 | if (de_iir & DE_PLANEA_FLIP_DONE_IVB) { | |
513 | intel_prepare_page_flip(dev, 0); | |
514 | intel_finish_page_flip_plane(dev, 0); | |
515 | } | |
516 | ||
517 | if (de_iir & DE_PLANEB_FLIP_DONE_IVB) { | |
518 | intel_prepare_page_flip(dev, 1); | |
519 | intel_finish_page_flip_plane(dev, 1); | |
520 | } | |
521 | ||
522 | if (de_iir & DE_PIPEA_VBLANK_IVB) | |
523 | drm_handle_vblank(dev, 0); | |
524 | ||
f6b07f45 | 525 | if (de_iir & DE_PIPEB_VBLANK_IVB) |
b1f14ad0 JB |
526 | drm_handle_vblank(dev, 1); |
527 | ||
528 | /* check event from PCH */ | |
529 | if (de_iir & DE_PCH_EVENT_IVB) { | |
530 | if (pch_iir & SDE_HOTPLUG_MASK_CPT) | |
531 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
532 | pch_irq_handler(dev); | |
533 | } | |
534 | ||
535 | if (pm_iir & GEN6_PM_DEFERRED_EVENTS) { | |
536 | unsigned long flags; | |
537 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
538 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
539 | I915_WRITE(GEN6_PMIMR, pm_iir); | |
540 | dev_priv->pm_iir |= pm_iir; | |
541 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); | |
542 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
543 | } | |
544 | ||
545 | /* should clear PCH hotplug event before clear CPU irq */ | |
546 | I915_WRITE(SDEIIR, pch_iir); | |
547 | I915_WRITE(GTIIR, gt_iir); | |
548 | I915_WRITE(DEIIR, de_iir); | |
549 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
550 | ||
551 | done: | |
552 | I915_WRITE(DEIER, de_ier); | |
553 | POSTING_READ(DEIER); | |
554 | ||
555 | return ret; | |
556 | } | |
557 | ||
f71d4af4 | 558 | static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS) |
036a4a7d | 559 | { |
4697995b | 560 | struct drm_device *dev = (struct drm_device *) arg; |
036a4a7d ZW |
561 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
562 | int ret = IRQ_NONE; | |
3b8d8d91 | 563 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
2d7b8366 | 564 | u32 hotplug_mask; |
036a4a7d | 565 | struct drm_i915_master_private *master_priv; |
881f47b6 XH |
566 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
567 | ||
4697995b JB |
568 | atomic_inc(&dev_priv->irq_received); |
569 | ||
881f47b6 XH |
570 | if (IS_GEN6(dev)) |
571 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 572 | |
2d109a84 ZN |
573 | /* disable master interrupt before clearing iir */ |
574 | de_ier = I915_READ(DEIER); | |
575 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 576 | POSTING_READ(DEIER); |
2d109a84 | 577 | |
036a4a7d ZW |
578 | de_iir = I915_READ(DEIIR); |
579 | gt_iir = I915_READ(GTIIR); | |
c650156a | 580 | pch_iir = I915_READ(SDEIIR); |
3b8d8d91 | 581 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 582 | |
3b8d8d91 JB |
583 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
584 | (!IS_GEN6(dev) || pm_iir == 0)) | |
c7c85101 | 585 | goto done; |
036a4a7d | 586 | |
2d7b8366 YL |
587 | if (HAS_PCH_CPT(dev)) |
588 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
589 | else | |
590 | hotplug_mask = SDE_HOTPLUG_MASK; | |
591 | ||
c7c85101 | 592 | ret = IRQ_HANDLED; |
036a4a7d | 593 | |
c7c85101 ZN |
594 | if (dev->primary->master) { |
595 | master_priv = dev->primary->master->driver_priv; | |
596 | if (master_priv->sarea_priv) | |
597 | master_priv->sarea_priv->last_dispatch = | |
598 | READ_BREADCRUMB(dev_priv); | |
599 | } | |
036a4a7d | 600 | |
c6df541c | 601 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
1ec14ad3 | 602 | notify_ring(dev, &dev_priv->ring[RCS]); |
881f47b6 | 603 | if (gt_iir & bsd_usr_interrupt) |
1ec14ad3 CW |
604 | notify_ring(dev, &dev_priv->ring[VCS]); |
605 | if (gt_iir & GT_BLT_USER_INTERRUPT) | |
606 | notify_ring(dev, &dev_priv->ring[BCS]); | |
01c66889 | 607 | |
c7c85101 | 608 | if (de_iir & DE_GSE) |
3b617967 | 609 | intel_opregion_gse_intr(dev); |
c650156a | 610 | |
f072d2e7 | 611 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 612 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 613 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 614 | } |
013d5aa2 | 615 | |
f072d2e7 | 616 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 617 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 618 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 619 | } |
013d5aa2 | 620 | |
f072d2e7 | 621 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
622 | drm_handle_vblank(dev, 0); |
623 | ||
f072d2e7 | 624 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
625 | drm_handle_vblank(dev, 1); |
626 | ||
c7c85101 | 627 | /* check event from PCH */ |
776ad806 JB |
628 | if (de_iir & DE_PCH_EVENT) { |
629 | if (pch_iir & hotplug_mask) | |
630 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
631 | pch_irq_handler(dev); | |
632 | } | |
036a4a7d | 633 | |
f97108d1 | 634 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 635 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
636 | i915_handle_rps_change(dev); |
637 | } | |
638 | ||
4912d041 BW |
639 | if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) { |
640 | /* | |
641 | * IIR bits should never already be set because IMR should | |
642 | * prevent an interrupt from being shown in IIR. The warning | |
643 | * displays a case where we've unsafely cleared | |
644 | * dev_priv->pm_iir. Although missing an interrupt of the same | |
645 | * type is not a problem, it displays a problem in the logic. | |
646 | * | |
647 | * The mask bit in IMR is cleared by rps_work. | |
648 | */ | |
649 | unsigned long flags; | |
650 | spin_lock_irqsave(&dev_priv->rps_lock, flags); | |
651 | WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n"); | |
652 | I915_WRITE(GEN6_PMIMR, pm_iir); | |
653 | dev_priv->pm_iir |= pm_iir; | |
654 | spin_unlock_irqrestore(&dev_priv->rps_lock, flags); | |
655 | queue_work(dev_priv->wq, &dev_priv->rps_work); | |
656 | } | |
3b8d8d91 | 657 | |
c7c85101 ZN |
658 | /* should clear PCH hotplug event before clear CPU irq */ |
659 | I915_WRITE(SDEIIR, pch_iir); | |
660 | I915_WRITE(GTIIR, gt_iir); | |
661 | I915_WRITE(DEIIR, de_iir); | |
4912d041 | 662 | I915_WRITE(GEN6_PMIIR, pm_iir); |
c7c85101 ZN |
663 | |
664 | done: | |
2d109a84 | 665 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 666 | POSTING_READ(DEIER); |
2d109a84 | 667 | |
036a4a7d ZW |
668 | return ret; |
669 | } | |
670 | ||
8a905236 JB |
671 | /** |
672 | * i915_error_work_func - do process context error handling work | |
673 | * @work: work struct | |
674 | * | |
675 | * Fire an error uevent so userspace can see that a hang or error | |
676 | * was detected. | |
677 | */ | |
678 | static void i915_error_work_func(struct work_struct *work) | |
679 | { | |
680 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
681 | error_work); | |
682 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
683 | char *error_event[] = { "ERROR=1", NULL }; |
684 | char *reset_event[] = { "RESET=1", NULL }; | |
685 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 686 | |
f316a42c BG |
687 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
688 | ||
ba1234d1 | 689 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
690 | DRM_DEBUG_DRIVER("resetting chip\n"); |
691 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
692 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
693 | atomic_set(&dev_priv->mm.wedged, 0); | |
694 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 695 | } |
30dbf0c0 | 696 | complete_all(&dev_priv->error_completion); |
f316a42c | 697 | } |
8a905236 JB |
698 | } |
699 | ||
3bd3c932 | 700 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 701 | static struct drm_i915_error_object * |
bcfb2e28 | 702 | i915_error_object_create(struct drm_i915_private *dev_priv, |
05394f39 | 703 | struct drm_i915_gem_object *src) |
9df30794 CW |
704 | { |
705 | struct drm_i915_error_object *dst; | |
9df30794 | 706 | int page, page_count; |
e56660dd | 707 | u32 reloc_offset; |
9df30794 | 708 | |
05394f39 | 709 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
710 | return NULL; |
711 | ||
05394f39 | 712 | page_count = src->base.size / PAGE_SIZE; |
9df30794 CW |
713 | |
714 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
715 | if (dst == NULL) | |
716 | return NULL; | |
717 | ||
05394f39 | 718 | reloc_offset = src->gtt_offset; |
9df30794 | 719 | for (page = 0; page < page_count; page++) { |
788885ae | 720 | unsigned long flags; |
e56660dd CW |
721 | void __iomem *s; |
722 | void *d; | |
788885ae | 723 | |
e56660dd | 724 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
725 | if (d == NULL) |
726 | goto unwind; | |
e56660dd | 727 | |
788885ae | 728 | local_irq_save(flags); |
e56660dd | 729 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3e4d3af5 | 730 | reloc_offset); |
e56660dd | 731 | memcpy_fromio(d, s, PAGE_SIZE); |
3e4d3af5 | 732 | io_mapping_unmap_atomic(s); |
788885ae | 733 | local_irq_restore(flags); |
e56660dd | 734 | |
9df30794 | 735 | dst->pages[page] = d; |
e56660dd CW |
736 | |
737 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
738 | } |
739 | dst->page_count = page_count; | |
05394f39 | 740 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
741 | |
742 | return dst; | |
743 | ||
744 | unwind: | |
745 | while (page--) | |
746 | kfree(dst->pages[page]); | |
747 | kfree(dst); | |
748 | return NULL; | |
749 | } | |
750 | ||
751 | static void | |
752 | i915_error_object_free(struct drm_i915_error_object *obj) | |
753 | { | |
754 | int page; | |
755 | ||
756 | if (obj == NULL) | |
757 | return; | |
758 | ||
759 | for (page = 0; page < obj->page_count; page++) | |
760 | kfree(obj->pages[page]); | |
761 | ||
762 | kfree(obj); | |
763 | } | |
764 | ||
765 | static void | |
766 | i915_error_state_free(struct drm_device *dev, | |
767 | struct drm_i915_error_state *error) | |
768 | { | |
e2f973d5 CW |
769 | int i; |
770 | ||
771 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) | |
772 | i915_error_object_free(error->batchbuffer[i]); | |
773 | ||
774 | for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) | |
775 | i915_error_object_free(error->ringbuffer[i]); | |
776 | ||
9df30794 | 777 | kfree(error->active_bo); |
6ef3d427 | 778 | kfree(error->overlay); |
9df30794 CW |
779 | kfree(error); |
780 | } | |
781 | ||
c724e8a9 CW |
782 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
783 | int count, | |
784 | struct list_head *head) | |
785 | { | |
786 | struct drm_i915_gem_object *obj; | |
787 | int i = 0; | |
788 | ||
789 | list_for_each_entry(obj, head, mm_list) { | |
790 | err->size = obj->base.size; | |
791 | err->name = obj->base.name; | |
792 | err->seqno = obj->last_rendering_seqno; | |
793 | err->gtt_offset = obj->gtt_offset; | |
794 | err->read_domains = obj->base.read_domains; | |
795 | err->write_domain = obj->base.write_domain; | |
796 | err->fence_reg = obj->fence_reg; | |
797 | err->pinned = 0; | |
798 | if (obj->pin_count > 0) | |
799 | err->pinned = 1; | |
800 | if (obj->user_pin_count > 0) | |
801 | err->pinned = -1; | |
802 | err->tiling = obj->tiling_mode; | |
803 | err->dirty = obj->dirty; | |
804 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
3685092b | 805 | err->ring = obj->ring ? obj->ring->id : 0; |
93dfb40c | 806 | err->cache_level = obj->cache_level; |
c724e8a9 CW |
807 | |
808 | if (++i == count) | |
809 | break; | |
810 | ||
811 | err++; | |
812 | } | |
813 | ||
814 | return i; | |
815 | } | |
816 | ||
748ebc60 CW |
817 | static void i915_gem_record_fences(struct drm_device *dev, |
818 | struct drm_i915_error_state *error) | |
819 | { | |
820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
821 | int i; | |
822 | ||
823 | /* Fences */ | |
824 | switch (INTEL_INFO(dev)->gen) { | |
825 | case 6: | |
826 | for (i = 0; i < 16; i++) | |
827 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
828 | break; | |
829 | case 5: | |
830 | case 4: | |
831 | for (i = 0; i < 16; i++) | |
832 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
833 | break; | |
834 | case 3: | |
835 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
836 | for (i = 0; i < 8; i++) | |
837 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
838 | case 2: | |
839 | for (i = 0; i < 8; i++) | |
840 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
841 | break; | |
842 | ||
843 | } | |
844 | } | |
845 | ||
bcfb2e28 CW |
846 | static struct drm_i915_error_object * |
847 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
848 | struct intel_ring_buffer *ring) | |
849 | { | |
850 | struct drm_i915_gem_object *obj; | |
851 | u32 seqno; | |
852 | ||
853 | if (!ring->get_seqno) | |
854 | return NULL; | |
855 | ||
856 | seqno = ring->get_seqno(ring); | |
857 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { | |
858 | if (obj->ring != ring) | |
859 | continue; | |
860 | ||
c37d9a5d | 861 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
bcfb2e28 CW |
862 | continue; |
863 | ||
864 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
865 | continue; | |
866 | ||
867 | /* We need to copy these to an anonymous buffer as the simplest | |
868 | * method to avoid being overwritten by userspace. | |
869 | */ | |
870 | return i915_error_object_create(dev_priv, obj); | |
871 | } | |
872 | ||
873 | return NULL; | |
874 | } | |
875 | ||
8a905236 JB |
876 | /** |
877 | * i915_capture_error_state - capture an error record for later analysis | |
878 | * @dev: drm device | |
879 | * | |
880 | * Should be called when an error is detected (either a hang or an error | |
881 | * interrupt) to capture error state from the time of the error. Fills | |
882 | * out a structure which becomes available in debugfs for user level tools | |
883 | * to pick up. | |
884 | */ | |
63eeaf38 JB |
885 | static void i915_capture_error_state(struct drm_device *dev) |
886 | { | |
887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 888 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
889 | struct drm_i915_error_state *error; |
890 | unsigned long flags; | |
9db4a9c7 | 891 | int i, pipe; |
63eeaf38 JB |
892 | |
893 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
894 | error = dev_priv->first_error; |
895 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
896 | if (error) | |
897 | return; | |
63eeaf38 | 898 | |
9db4a9c7 | 899 | /* Account for pipe specific data like PIPE*STAT */ |
63eeaf38 JB |
900 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
901 | if (!error) { | |
9df30794 CW |
902 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
903 | return; | |
63eeaf38 JB |
904 | } |
905 | ||
b6f7833b CW |
906 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
907 | dev->primary->index); | |
2fa772f3 | 908 | |
1ec14ad3 | 909 | error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); |
63eeaf38 JB |
910 | error->eir = I915_READ(EIR); |
911 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
9db4a9c7 JB |
912 | for_each_pipe(pipe) |
913 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
63eeaf38 | 914 | error->instpm = I915_READ(INSTPM); |
f406839f CW |
915 | error->error = 0; |
916 | if (INTEL_INFO(dev)->gen >= 6) { | |
917 | error->error = I915_READ(ERROR_GEN6); | |
add354dd | 918 | |
1d8f38f4 CW |
919 | error->bcs_acthd = I915_READ(BCS_ACTHD); |
920 | error->bcs_ipehr = I915_READ(BCS_IPEHR); | |
921 | error->bcs_ipeir = I915_READ(BCS_IPEIR); | |
922 | error->bcs_instdone = I915_READ(BCS_INSTDONE); | |
923 | error->bcs_seqno = 0; | |
1ec14ad3 CW |
924 | if (dev_priv->ring[BCS].get_seqno) |
925 | error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]); | |
add354dd CW |
926 | |
927 | error->vcs_acthd = I915_READ(VCS_ACTHD); | |
928 | error->vcs_ipehr = I915_READ(VCS_IPEHR); | |
929 | error->vcs_ipeir = I915_READ(VCS_IPEIR); | |
930 | error->vcs_instdone = I915_READ(VCS_INSTDONE); | |
931 | error->vcs_seqno = 0; | |
1ec14ad3 CW |
932 | if (dev_priv->ring[VCS].get_seqno) |
933 | error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]); | |
f406839f CW |
934 | } |
935 | if (INTEL_INFO(dev)->gen >= 4) { | |
63eeaf38 JB |
936 | error->ipeir = I915_READ(IPEIR_I965); |
937 | error->ipehr = I915_READ(IPEHR_I965); | |
938 | error->instdone = I915_READ(INSTDONE_I965); | |
939 | error->instps = I915_READ(INSTPS); | |
940 | error->instdone1 = I915_READ(INSTDONE1); | |
941 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 942 | error->bbaddr = I915_READ64(BB_ADDR); |
f406839f CW |
943 | } else { |
944 | error->ipeir = I915_READ(IPEIR); | |
945 | error->ipehr = I915_READ(IPEHR); | |
946 | error->instdone = I915_READ(INSTDONE); | |
947 | error->acthd = I915_READ(ACTHD); | |
948 | error->bbaddr = 0; | |
63eeaf38 | 949 | } |
748ebc60 | 950 | i915_gem_record_fences(dev, error); |
63eeaf38 | 951 | |
e2f973d5 CW |
952 | /* Record the active batch and ring buffers */ |
953 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
bcfb2e28 CW |
954 | error->batchbuffer[i] = |
955 | i915_error_first_batchbuffer(dev_priv, | |
956 | &dev_priv->ring[i]); | |
9df30794 | 957 | |
e2f973d5 CW |
958 | error->ringbuffer[i] = |
959 | i915_error_object_create(dev_priv, | |
960 | dev_priv->ring[i].obj); | |
961 | } | |
9df30794 | 962 | |
c724e8a9 | 963 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 964 | error->active_bo = NULL; |
c724e8a9 | 965 | error->pinned_bo = NULL; |
9df30794 | 966 | |
bcfb2e28 CW |
967 | i = 0; |
968 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
969 | i++; | |
970 | error->active_bo_count = i; | |
05394f39 | 971 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
bcfb2e28 CW |
972 | i++; |
973 | error->pinned_bo_count = i - error->active_bo_count; | |
c724e8a9 | 974 | |
8e934dbf CW |
975 | error->active_bo = NULL; |
976 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
977 | if (i) { |
978 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 979 | GFP_ATOMIC); |
c724e8a9 CW |
980 | if (error->active_bo) |
981 | error->pinned_bo = | |
982 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
983 | } |
984 | ||
c724e8a9 CW |
985 | if (error->active_bo) |
986 | error->active_bo_count = | |
987 | capture_bo_list(error->active_bo, | |
988 | error->active_bo_count, | |
989 | &dev_priv->mm.active_list); | |
990 | ||
991 | if (error->pinned_bo) | |
992 | error->pinned_bo_count = | |
993 | capture_bo_list(error->pinned_bo, | |
994 | error->pinned_bo_count, | |
995 | &dev_priv->mm.pinned_list); | |
996 | ||
9df30794 CW |
997 | do_gettimeofday(&error->time); |
998 | ||
6ef3d427 | 999 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 1000 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 1001 | |
9df30794 CW |
1002 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
1003 | if (dev_priv->first_error == NULL) { | |
1004 | dev_priv->first_error = error; | |
1005 | error = NULL; | |
1006 | } | |
63eeaf38 | 1007 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
1008 | |
1009 | if (error) | |
1010 | i915_error_state_free(dev, error); | |
1011 | } | |
1012 | ||
1013 | void i915_destroy_error_state(struct drm_device *dev) | |
1014 | { | |
1015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1016 | struct drm_i915_error_state *error; | |
1017 | ||
1018 | spin_lock(&dev_priv->error_lock); | |
1019 | error = dev_priv->first_error; | |
1020 | dev_priv->first_error = NULL; | |
1021 | spin_unlock(&dev_priv->error_lock); | |
1022 | ||
1023 | if (error) | |
1024 | i915_error_state_free(dev, error); | |
63eeaf38 | 1025 | } |
3bd3c932 CW |
1026 | #else |
1027 | #define i915_capture_error_state(x) | |
1028 | #endif | |
63eeaf38 | 1029 | |
35aed2e6 | 1030 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
1031 | { |
1032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1033 | u32 eir = I915_READ(EIR); | |
9db4a9c7 | 1034 | int pipe; |
8a905236 | 1035 | |
35aed2e6 CW |
1036 | if (!eir) |
1037 | return; | |
8a905236 JB |
1038 | |
1039 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
1040 | eir); | |
1041 | ||
1042 | if (IS_G4X(dev)) { | |
1043 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
1044 | u32 ipeir = I915_READ(IPEIR_I965); | |
1045 | ||
1046 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
1047 | I915_READ(IPEIR_I965)); | |
1048 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
1049 | I915_READ(IPEHR_I965)); | |
1050 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
1051 | I915_READ(INSTDONE_I965)); | |
1052 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
1053 | I915_READ(INSTPS)); | |
1054 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
1055 | I915_READ(INSTDONE1)); | |
1056 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1057 | I915_READ(ACTHD_I965)); | |
1058 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 1059 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1060 | } |
1061 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
1062 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
1063 | printk(KERN_ERR "page table error\n"); | |
1064 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
1065 | pgtbl_err); | |
1066 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 1067 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1068 | } |
1069 | } | |
1070 | ||
a6c45cf0 | 1071 | if (!IS_GEN2(dev)) { |
8a905236 JB |
1072 | if (eir & I915_ERROR_PAGE_TABLE) { |
1073 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
1074 | printk(KERN_ERR "page table error\n"); | |
1075 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
1076 | pgtbl_err); | |
1077 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 1078 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
1079 | } |
1080 | } | |
1081 | ||
1082 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
9db4a9c7 JB |
1083 | printk(KERN_ERR "memory refresh error:\n"); |
1084 | for_each_pipe(pipe) | |
1085 | printk(KERN_ERR "pipe %c stat: 0x%08x\n", | |
1086 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); | |
8a905236 JB |
1087 | /* pipestat has already been acked */ |
1088 | } | |
1089 | if (eir & I915_ERROR_INSTRUCTION) { | |
1090 | printk(KERN_ERR "instruction error\n"); | |
1091 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
1092 | I915_READ(INSTPM)); | |
a6c45cf0 | 1093 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
1094 | u32 ipeir = I915_READ(IPEIR); |
1095 | ||
1096 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
1097 | I915_READ(IPEIR)); | |
1098 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
1099 | I915_READ(IPEHR)); | |
1100 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
1101 | I915_READ(INSTDONE)); | |
1102 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1103 | I915_READ(ACTHD)); | |
1104 | I915_WRITE(IPEIR, ipeir); | |
3143a2bf | 1105 | POSTING_READ(IPEIR); |
8a905236 JB |
1106 | } else { |
1107 | u32 ipeir = I915_READ(IPEIR_I965); | |
1108 | ||
1109 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
1110 | I915_READ(IPEIR_I965)); | |
1111 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
1112 | I915_READ(IPEHR_I965)); | |
1113 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
1114 | I915_READ(INSTDONE_I965)); | |
1115 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
1116 | I915_READ(INSTPS)); | |
1117 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
1118 | I915_READ(INSTDONE1)); | |
1119 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
1120 | I915_READ(ACTHD_I965)); | |
1121 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 1122 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
1123 | } |
1124 | } | |
1125 | ||
1126 | I915_WRITE(EIR, eir); | |
3143a2bf | 1127 | POSTING_READ(EIR); |
8a905236 JB |
1128 | eir = I915_READ(EIR); |
1129 | if (eir) { | |
1130 | /* | |
1131 | * some errors might have become stuck, | |
1132 | * mask them. | |
1133 | */ | |
1134 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1135 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1136 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1137 | } | |
35aed2e6 CW |
1138 | } |
1139 | ||
1140 | /** | |
1141 | * i915_handle_error - handle an error interrupt | |
1142 | * @dev: drm device | |
1143 | * | |
1144 | * Do some basic checking of regsiter state at error interrupt time and | |
1145 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1146 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1147 | * so userspace knows something bad happened (should trigger collection | |
1148 | * of a ring dump etc.). | |
1149 | */ | |
527f9e90 | 1150 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1151 | { |
1152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1153 | ||
1154 | i915_capture_error_state(dev); | |
1155 | i915_report_and_clear_eir(dev); | |
8a905236 | 1156 | |
ba1234d1 | 1157 | if (wedged) { |
30dbf0c0 | 1158 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
1159 | atomic_set(&dev_priv->mm.wedged, 1); |
1160 | ||
11ed50ec BG |
1161 | /* |
1162 | * Wakeup waiting processes so they don't hang | |
1163 | */ | |
1ec14ad3 | 1164 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
f787a5f5 | 1165 | if (HAS_BSD(dev)) |
1ec14ad3 | 1166 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1167 | if (HAS_BLT(dev)) |
1ec14ad3 | 1168 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
11ed50ec BG |
1169 | } |
1170 | ||
9c9fe1f8 | 1171 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
1172 | } |
1173 | ||
4e5359cd SF |
1174 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
1175 | { | |
1176 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1177 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1179 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1180 | struct intel_unpin_work *work; |
1181 | unsigned long flags; | |
1182 | bool stall_detected; | |
1183 | ||
1184 | /* Ignore early vblank irqs */ | |
1185 | if (intel_crtc == NULL) | |
1186 | return; | |
1187 | ||
1188 | spin_lock_irqsave(&dev->event_lock, flags); | |
1189 | work = intel_crtc->unpin_work; | |
1190 | ||
1191 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
1192 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
1193 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1194 | return; | |
1195 | } | |
1196 | ||
1197 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1198 | obj = work->pending_flip_obj; |
a6c45cf0 | 1199 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1200 | int dspsurf = DSPSURF(intel_crtc->plane); |
05394f39 | 1201 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
4e5359cd | 1202 | } else { |
9db4a9c7 | 1203 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 1204 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
4e5359cd SF |
1205 | crtc->y * crtc->fb->pitch + |
1206 | crtc->x * crtc->fb->bits_per_pixel/8); | |
1207 | } | |
1208 | ||
1209 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1210 | ||
1211 | if (stall_detected) { | |
1212 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1213 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1214 | } | |
1215 | } | |
1216 | ||
f71d4af4 | 1217 | static irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
1da177e4 | 1218 | { |
84b1fd10 | 1219 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 1220 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 1221 | struct drm_i915_master_private *master_priv; |
cdfbc41f | 1222 | u32 iir, new_iir; |
9db4a9c7 | 1223 | u32 pipe_stats[I915_MAX_PIPES]; |
05eff845 | 1224 | u32 vblank_status; |
0a3e67a4 | 1225 | int vblank = 0; |
7c463586 | 1226 | unsigned long irqflags; |
05eff845 | 1227 | int irq_received; |
9db4a9c7 JB |
1228 | int ret = IRQ_NONE, pipe; |
1229 | bool blc_event = false; | |
6e5fca53 | 1230 | |
630681d9 EA |
1231 | atomic_inc(&dev_priv->irq_received); |
1232 | ||
ed4cb414 | 1233 | iir = I915_READ(IIR); |
a6b54f3f | 1234 | |
a6c45cf0 | 1235 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1236 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1237 | else |
d874bcff | 1238 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1239 | |
05eff845 KP |
1240 | for (;;) { |
1241 | irq_received = iir != 0; | |
1242 | ||
1243 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1244 | * have been cleared after the pipestat interrupt was received. | |
1245 | * It doesn't set the bit in iir again, but it still produces | |
1246 | * interrupts (for non-MSI). | |
1247 | */ | |
1ec14ad3 | 1248 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8a905236 | 1249 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1250 | i915_handle_error(dev, false); |
8a905236 | 1251 | |
9db4a9c7 JB |
1252 | for_each_pipe(pipe) { |
1253 | int reg = PIPESTAT(pipe); | |
1254 | pipe_stats[pipe] = I915_READ(reg); | |
1255 | ||
1256 | /* | |
1257 | * Clear the PIPE*STAT regs before the IIR | |
1258 | */ | |
1259 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1260 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1261 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1262 | pipe_name(pipe)); | |
1263 | I915_WRITE(reg, pipe_stats[pipe]); | |
1264 | irq_received = 1; | |
1265 | } | |
cdfbc41f | 1266 | } |
1ec14ad3 | 1267 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
05eff845 KP |
1268 | |
1269 | if (!irq_received) | |
1270 | break; | |
1271 | ||
1272 | ret = IRQ_HANDLED; | |
8ee1c3db | 1273 | |
5ca58282 JB |
1274 | /* Consume port. Then clear IIR or we'll miss events */ |
1275 | if ((I915_HAS_HOTPLUG(dev)) && | |
1276 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1277 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1278 | ||
44d98a61 | 1279 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1280 | hotplug_status); |
1281 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1282 | queue_work(dev_priv->wq, |
1283 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1284 | |
1285 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1286 | I915_READ(PORT_HOTPLUG_STAT); | |
1287 | } | |
1288 | ||
cdfbc41f EA |
1289 | I915_WRITE(IIR, iir); |
1290 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1291 | |
7c1c2871 DA |
1292 | if (dev->primary->master) { |
1293 | master_priv = dev->primary->master->driver_priv; | |
1294 | if (master_priv->sarea_priv) | |
1295 | master_priv->sarea_priv->last_dispatch = | |
1296 | READ_BREADCRUMB(dev_priv); | |
1297 | } | |
0a3e67a4 | 1298 | |
549f7365 | 1299 | if (iir & I915_USER_INTERRUPT) |
1ec14ad3 CW |
1300 | notify_ring(dev, &dev_priv->ring[RCS]); |
1301 | if (iir & I915_BSD_USER_INTERRUPT) | |
1302 | notify_ring(dev, &dev_priv->ring[VCS]); | |
d1b851fc | 1303 | |
1afe3e9d | 1304 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1305 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1306 | if (dev_priv->flip_pending_is_done) |
1307 | intel_finish_page_flip_plane(dev, 0); | |
1308 | } | |
6b95a207 | 1309 | |
1afe3e9d | 1310 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1311 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1312 | if (dev_priv->flip_pending_is_done) |
1313 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1314 | } |
6b95a207 | 1315 | |
9db4a9c7 JB |
1316 | for_each_pipe(pipe) { |
1317 | if (pipe_stats[pipe] & vblank_status && | |
1318 | drm_handle_vblank(dev, pipe)) { | |
1319 | vblank++; | |
1320 | if (!dev_priv->flip_pending_is_done) { | |
1321 | i915_pageflip_stall_check(dev, pipe); | |
1322 | intel_finish_page_flip(dev, pipe); | |
1323 | } | |
4e5359cd | 1324 | } |
7c463586 | 1325 | |
9db4a9c7 JB |
1326 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
1327 | blc_event = true; | |
cdfbc41f | 1328 | } |
7c463586 | 1329 | |
9db4a9c7 JB |
1330 | |
1331 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3b617967 | 1332 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1333 | |
1334 | /* With MSI, interrupts are only generated when iir | |
1335 | * transitions from zero to nonzero. If another bit got | |
1336 | * set while we were handling the existing iir bits, then | |
1337 | * we would never get another interrupt. | |
1338 | * | |
1339 | * This is fine on non-MSI as well, as if we hit this path | |
1340 | * we avoid exiting the interrupt handler only to generate | |
1341 | * another one. | |
1342 | * | |
1343 | * Note that for MSI this could cause a stray interrupt report | |
1344 | * if an interrupt landed in the time between writing IIR and | |
1345 | * the posting read. This should be rare enough to never | |
1346 | * trigger the 99% of 100,000 interrupts test for disabling | |
1347 | * stray interrupts. | |
1348 | */ | |
1349 | iir = new_iir; | |
05eff845 | 1350 | } |
0a3e67a4 | 1351 | |
05eff845 | 1352 | return ret; |
1da177e4 LT |
1353 | } |
1354 | ||
af6061af | 1355 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1356 | { |
1357 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1358 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1359 | |
1360 | i915_kernel_lost_context(dev); | |
1361 | ||
44d98a61 | 1362 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1363 | |
c99b058f | 1364 | dev_priv->counter++; |
c29b669c | 1365 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1366 | dev_priv->counter = 1; |
7c1c2871 DA |
1367 | if (master_priv->sarea_priv) |
1368 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1369 | |
e1f99ce6 CW |
1370 | if (BEGIN_LP_RING(4) == 0) { |
1371 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1372 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1373 | OUT_RING(dev_priv->counter); | |
1374 | OUT_RING(MI_USER_INTERRUPT); | |
1375 | ADVANCE_LP_RING(); | |
1376 | } | |
bc5f4523 | 1377 | |
c29b669c | 1378 | return dev_priv->counter; |
1da177e4 LT |
1379 | } |
1380 | ||
84b1fd10 | 1381 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1382 | { |
1383 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1384 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1385 | int ret = 0; |
1ec14ad3 | 1386 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 1387 | |
44d98a61 | 1388 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1389 | READ_BREADCRUMB(dev_priv)); |
1390 | ||
ed4cb414 | 1391 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1392 | if (master_priv->sarea_priv) |
1393 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1394 | return 0; |
ed4cb414 | 1395 | } |
1da177e4 | 1396 | |
7c1c2871 DA |
1397 | if (master_priv->sarea_priv) |
1398 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1399 | |
b13c2b96 CW |
1400 | if (ring->irq_get(ring)) { |
1401 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
1402 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
1403 | ring->irq_put(ring); | |
5a9a8d1a CW |
1404 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
1405 | ret = -EBUSY; | |
1da177e4 | 1406 | |
20caafa6 | 1407 | if (ret == -EBUSY) { |
3e684eae | 1408 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1409 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1410 | } | |
1411 | ||
af6061af DA |
1412 | return ret; |
1413 | } | |
1414 | ||
1da177e4 LT |
1415 | /* Needs the lock as it touches the ring. |
1416 | */ | |
c153f45f EA |
1417 | int i915_irq_emit(struct drm_device *dev, void *data, |
1418 | struct drm_file *file_priv) | |
1da177e4 | 1419 | { |
1da177e4 | 1420 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1421 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1422 | int result; |
1423 | ||
1ec14ad3 | 1424 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
3e684eae | 1425 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1426 | return -EINVAL; |
1da177e4 | 1427 | } |
299eb93c EA |
1428 | |
1429 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1430 | ||
546b0974 | 1431 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1432 | result = i915_emit_irq(dev); |
546b0974 | 1433 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1434 | |
c153f45f | 1435 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1436 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1437 | return -EFAULT; |
1da177e4 LT |
1438 | } |
1439 | ||
1440 | return 0; | |
1441 | } | |
1442 | ||
1443 | /* Doesn't need the hardware lock. | |
1444 | */ | |
c153f45f EA |
1445 | int i915_irq_wait(struct drm_device *dev, void *data, |
1446 | struct drm_file *file_priv) | |
1da177e4 | 1447 | { |
1da177e4 | 1448 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1449 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1450 | |
1451 | if (!dev_priv) { | |
3e684eae | 1452 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1453 | return -EINVAL; |
1da177e4 LT |
1454 | } |
1455 | ||
c153f45f | 1456 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1457 | } |
1458 | ||
42f52ef8 KP |
1459 | /* Called from drm generic code, passed 'crtc' which |
1460 | * we use as a pipe index | |
1461 | */ | |
f71d4af4 | 1462 | static int i915_enable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1463 | { |
1464 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1465 | unsigned long irqflags; |
71e0ffa5 | 1466 | |
5eddb70b | 1467 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1468 | return -EINVAL; |
0a3e67a4 | 1469 | |
1ec14ad3 | 1470 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
f796cf8f | 1471 | if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1472 | i915_enable_pipestat(dev_priv, pipe, |
1473 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1474 | else |
7c463586 KP |
1475 | i915_enable_pipestat(dev_priv, pipe, |
1476 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
8692d00e CW |
1477 | |
1478 | /* maintain vblank delivery even in deep C-states */ | |
1479 | if (dev_priv->info->gen == 3) | |
1480 | I915_WRITE(INSTPM, INSTPM_AGPBUSY_DIS << 16); | |
1ec14ad3 | 1481 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
8692d00e | 1482 | |
0a3e67a4 JB |
1483 | return 0; |
1484 | } | |
1485 | ||
f71d4af4 | 1486 | static int ironlake_enable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1487 | { |
1488 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1489 | unsigned long irqflags; | |
1490 | ||
1491 | if (!i915_pipe_enabled(dev, pipe)) | |
1492 | return -EINVAL; | |
1493 | ||
1494 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1495 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
1496 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1497 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1498 | ||
1499 | return 0; | |
1500 | } | |
1501 | ||
f71d4af4 | 1502 | static int ivybridge_enable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1503 | { |
1504 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1505 | unsigned long irqflags; | |
1506 | ||
1507 | if (!i915_pipe_enabled(dev, pipe)) | |
1508 | return -EINVAL; | |
1509 | ||
1510 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1511 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? | |
1512 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | |
1513 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1514 | ||
1515 | return 0; | |
1516 | } | |
1517 | ||
42f52ef8 KP |
1518 | /* Called from drm generic code, passed 'crtc' which |
1519 | * we use as a pipe index | |
1520 | */ | |
f71d4af4 | 1521 | static void i915_disable_vblank(struct drm_device *dev, int pipe) |
0a3e67a4 JB |
1522 | { |
1523 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1524 | unsigned long irqflags; |
0a3e67a4 | 1525 | |
1ec14ad3 | 1526 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8692d00e CW |
1527 | if (dev_priv->info->gen == 3) |
1528 | I915_WRITE(INSTPM, | |
1529 | INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS); | |
1530 | ||
f796cf8f JB |
1531 | i915_disable_pipestat(dev_priv, pipe, |
1532 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1533 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1534 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1535 | } | |
1536 | ||
f71d4af4 | 1537 | static void ironlake_disable_vblank(struct drm_device *dev, int pipe) |
f796cf8f JB |
1538 | { |
1539 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1540 | unsigned long irqflags; | |
1541 | ||
1542 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1543 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
1544 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1ec14ad3 | 1545 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1546 | } |
1547 | ||
f71d4af4 | 1548 | static void ivybridge_disable_vblank(struct drm_device *dev, int pipe) |
b1f14ad0 JB |
1549 | { |
1550 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1551 | unsigned long irqflags; | |
1552 | ||
1553 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
1554 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? | |
1555 | DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB); | |
1556 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
1557 | } | |
1558 | ||
702880f2 DA |
1559 | /* Set the vblank monitor pipe |
1560 | */ | |
c153f45f EA |
1561 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1562 | struct drm_file *file_priv) | |
702880f2 | 1563 | { |
702880f2 | 1564 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1565 | |
1566 | if (!dev_priv) { | |
3e684eae | 1567 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1568 | return -EINVAL; |
702880f2 DA |
1569 | } |
1570 | ||
5b51694a | 1571 | return 0; |
702880f2 DA |
1572 | } |
1573 | ||
c153f45f EA |
1574 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1575 | struct drm_file *file_priv) | |
702880f2 | 1576 | { |
702880f2 | 1577 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1578 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1579 | |
1580 | if (!dev_priv) { | |
3e684eae | 1581 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1582 | return -EINVAL; |
702880f2 DA |
1583 | } |
1584 | ||
0a3e67a4 | 1585 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1586 | |
702880f2 DA |
1587 | return 0; |
1588 | } | |
1589 | ||
a6b54f3f MCA |
1590 | /** |
1591 | * Schedule buffer swap at given vertical blank. | |
1592 | */ | |
c153f45f EA |
1593 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1594 | struct drm_file *file_priv) | |
a6b54f3f | 1595 | { |
bd95e0a4 EA |
1596 | /* The delayed swap mechanism was fundamentally racy, and has been |
1597 | * removed. The model was that the client requested a delayed flip/swap | |
1598 | * from the kernel, then waited for vblank before continuing to perform | |
1599 | * rendering. The problem was that the kernel might wake the client | |
1600 | * up before it dispatched the vblank swap (since the lock has to be | |
1601 | * held while touching the ringbuffer), in which case the client would | |
1602 | * clear and start the next frame before the swap occurred, and | |
1603 | * flicker would occur in addition to likely missing the vblank. | |
1604 | * | |
1605 | * In the absence of this ioctl, userland falls back to a correct path | |
1606 | * of waiting for a vblank, then dispatching the swap on its own. | |
1607 | * Context switching to userland and back is plenty fast enough for | |
1608 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1609 | */ |
bd95e0a4 | 1610 | return -EINVAL; |
a6b54f3f MCA |
1611 | } |
1612 | ||
893eead0 CW |
1613 | static u32 |
1614 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1615 | { |
893eead0 CW |
1616 | return list_entry(ring->request_list.prev, |
1617 | struct drm_i915_gem_request, list)->seqno; | |
1618 | } | |
1619 | ||
1620 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1621 | { | |
1622 | if (list_empty(&ring->request_list) || | |
1623 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1624 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1625 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1626 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1627 | ring->name, | |
b2223497 | 1628 | ring->waiting_seqno, |
893eead0 CW |
1629 | ring->get_seqno(ring)); |
1630 | wake_up_all(&ring->irq_queue); | |
1631 | *err = true; | |
1632 | } | |
1633 | return true; | |
1634 | } | |
1635 | return false; | |
f65d9421 BG |
1636 | } |
1637 | ||
1ec14ad3 CW |
1638 | static bool kick_ring(struct intel_ring_buffer *ring) |
1639 | { | |
1640 | struct drm_device *dev = ring->dev; | |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1642 | u32 tmp = I915_READ_CTL(ring); | |
1643 | if (tmp & RING_WAIT) { | |
1644 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1645 | ring->name); | |
1646 | I915_WRITE_CTL(ring, tmp); | |
1647 | return true; | |
1648 | } | |
1649 | if (IS_GEN6(dev) && | |
1650 | (tmp & RING_WAIT_SEMAPHORE)) { | |
1651 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
1652 | ring->name); | |
1653 | I915_WRITE_CTL(ring, tmp); | |
1654 | return true; | |
1655 | } | |
1656 | return false; | |
1657 | } | |
1658 | ||
f65d9421 BG |
1659 | /** |
1660 | * This is called when the chip hasn't reported back with completed | |
1661 | * batchbuffers in a long time. The first time this is called we simply record | |
1662 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1663 | * again, we assume the chip is wedged and try to fix it. | |
1664 | */ | |
1665 | void i915_hangcheck_elapsed(unsigned long data) | |
1666 | { | |
1667 | struct drm_device *dev = (struct drm_device *)data; | |
1668 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1669 | uint32_t acthd, instdone, instdone1; |
893eead0 CW |
1670 | bool err = false; |
1671 | ||
3e0dc6b0 BW |
1672 | if (!i915_enable_hangcheck) |
1673 | return; | |
1674 | ||
893eead0 | 1675 | /* If all work is done then ACTHD clearly hasn't advanced. */ |
1ec14ad3 CW |
1676 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
1677 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && | |
1678 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { | |
893eead0 CW |
1679 | dev_priv->hangcheck_count = 0; |
1680 | if (err) | |
1681 | goto repeat; | |
1682 | return; | |
1683 | } | |
b9201c14 | 1684 | |
a6c45cf0 | 1685 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1686 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1687 | instdone = I915_READ(INSTDONE); |
1688 | instdone1 = 0; | |
1689 | } else { | |
f65d9421 | 1690 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1691 | instdone = I915_READ(INSTDONE_I965); |
1692 | instdone1 = I915_READ(INSTDONE1); | |
1693 | } | |
f65d9421 | 1694 | |
cbb465e7 CW |
1695 | if (dev_priv->last_acthd == acthd && |
1696 | dev_priv->last_instdone == instdone && | |
1697 | dev_priv->last_instdone1 == instdone1) { | |
1698 | if (dev_priv->hangcheck_count++ > 1) { | |
1699 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1700 | |
1701 | if (!IS_GEN2(dev)) { | |
1702 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1703 | * If so we can simply poke the RB_WAIT bit | |
1704 | * and break the hang. This should work on | |
1705 | * all but the second generation chipsets. | |
1706 | */ | |
1ec14ad3 CW |
1707 | |
1708 | if (kick_ring(&dev_priv->ring[RCS])) | |
1709 | goto repeat; | |
1710 | ||
1711 | if (HAS_BSD(dev) && | |
1712 | kick_ring(&dev_priv->ring[VCS])) | |
1713 | goto repeat; | |
1714 | ||
1715 | if (HAS_BLT(dev) && | |
1716 | kick_ring(&dev_priv->ring[BCS])) | |
893eead0 | 1717 | goto repeat; |
8c80b59b CW |
1718 | } |
1719 | ||
cbb465e7 CW |
1720 | i915_handle_error(dev, true); |
1721 | return; | |
1722 | } | |
1723 | } else { | |
1724 | dev_priv->hangcheck_count = 0; | |
1725 | ||
1726 | dev_priv->last_acthd = acthd; | |
1727 | dev_priv->last_instdone = instdone; | |
1728 | dev_priv->last_instdone1 = instdone1; | |
1729 | } | |
f65d9421 | 1730 | |
893eead0 | 1731 | repeat: |
f65d9421 | 1732 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1733 | mod_timer(&dev_priv->hangcheck_timer, |
1734 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1735 | } |
1736 | ||
1da177e4 LT |
1737 | /* drm_dma.h hooks |
1738 | */ | |
f71d4af4 | 1739 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1740 | { |
1741 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1742 | ||
4697995b JB |
1743 | atomic_set(&dev_priv->irq_received, 0); |
1744 | ||
1745 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); | |
1746 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); | |
9e3c256d JB |
1747 | if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
1748 | INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); | |
4697995b | 1749 | |
036a4a7d | 1750 | I915_WRITE(HWSTAM, 0xeffe); |
2b1ecb73 | 1751 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
498e720b DB |
1752 | /* Workaround stalls observed on Sandy Bridge GPUs by |
1753 | * making the blitter command streamer generate a | |
1754 | * write to the Hardware Status Page for | |
1755 | * MI_USER_INTERRUPT. This appears to serialize the | |
1756 | * previous seqno write out before the interrupt | |
1757 | * happens. | |
1758 | */ | |
1759 | I915_WRITE(GEN6_BLITTER_HWSTAM, ~GEN6_BLITTER_USER_INTERRUPT); | |
ec6a890d | 1760 | I915_WRITE(GEN6_BSD_HWSTAM, ~GEN6_BSD_USER_INTERRUPT); |
498e720b | 1761 | } |
036a4a7d ZW |
1762 | |
1763 | /* XXX hotplug from PCH */ | |
1764 | ||
1765 | I915_WRITE(DEIMR, 0xffffffff); | |
1766 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1767 | POSTING_READ(DEIER); |
036a4a7d ZW |
1768 | |
1769 | /* and GT */ | |
1770 | I915_WRITE(GTIMR, 0xffffffff); | |
1771 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1772 | POSTING_READ(GTIER); |
c650156a ZW |
1773 | |
1774 | /* south display irq */ | |
1775 | I915_WRITE(SDEIMR, 0xffffffff); | |
1776 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1777 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1778 | } |
1779 | ||
f71d4af4 | 1780 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1781 | { |
1782 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1783 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1784 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1785 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
1ec14ad3 | 1786 | u32 render_irqs; |
2d7b8366 | 1787 | u32 hotplug_mask; |
036a4a7d | 1788 | |
4697995b JB |
1789 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
1790 | if (HAS_BSD(dev)) | |
1791 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
1792 | if (HAS_BLT(dev)) | |
1793 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
1794 | ||
1795 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
1ec14ad3 | 1796 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
1797 | |
1798 | /* should always can generate irq */ | |
1799 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
1800 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
1801 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 1802 | POSTING_READ(DEIER); |
036a4a7d | 1803 | |
1ec14ad3 | 1804 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
1805 | |
1806 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 1807 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 1808 | |
1ec14ad3 CW |
1809 | if (IS_GEN6(dev)) |
1810 | render_irqs = | |
1811 | GT_USER_INTERRUPT | | |
1812 | GT_GEN6_BSD_USER_INTERRUPT | | |
1813 | GT_BLT_USER_INTERRUPT; | |
1814 | else | |
1815 | render_irqs = | |
88f23b8f | 1816 | GT_USER_INTERRUPT | |
c6df541c | 1817 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
1818 | GT_BSD_USER_INTERRUPT; |
1819 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 1820 | POSTING_READ(GTIER); |
036a4a7d | 1821 | |
2d7b8366 | 1822 | if (HAS_PCH_CPT(dev)) { |
9035a97a CW |
1823 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | |
1824 | SDE_PORTB_HOTPLUG_CPT | | |
1825 | SDE_PORTC_HOTPLUG_CPT | | |
1826 | SDE_PORTD_HOTPLUG_CPT); | |
2d7b8366 | 1827 | } else { |
9035a97a CW |
1828 | hotplug_mask = (SDE_CRT_HOTPLUG | |
1829 | SDE_PORTB_HOTPLUG | | |
1830 | SDE_PORTC_HOTPLUG | | |
1831 | SDE_PORTD_HOTPLUG | | |
1832 | SDE_AUX_MASK); | |
2d7b8366 YL |
1833 | } |
1834 | ||
1ec14ad3 | 1835 | dev_priv->pch_irq_mask = ~hotplug_mask; |
c650156a ZW |
1836 | |
1837 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1ec14ad3 CW |
1838 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
1839 | I915_WRITE(SDEIER, hotplug_mask); | |
3143a2bf | 1840 | POSTING_READ(SDEIER); |
c650156a | 1841 | |
f97108d1 JB |
1842 | if (IS_IRONLAKE_M(dev)) { |
1843 | /* Clear & enable PCU event interrupts */ | |
1844 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1845 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1846 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1847 | } | |
1848 | ||
036a4a7d ZW |
1849 | return 0; |
1850 | } | |
1851 | ||
f71d4af4 | 1852 | static int ivybridge_irq_postinstall(struct drm_device *dev) |
b1f14ad0 JB |
1853 | { |
1854 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1855 | /* enable kind of interrupts always enabled */ | |
1856 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | | |
1857 | DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB | | |
1858 | DE_PLANEB_FLIP_DONE_IVB; | |
1859 | u32 render_irqs; | |
1860 | u32 hotplug_mask; | |
1861 | ||
1862 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); | |
1863 | if (HAS_BSD(dev)) | |
1864 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); | |
1865 | if (HAS_BLT(dev)) | |
1866 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); | |
1867 | ||
1868 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
1869 | dev_priv->irq_mask = ~display_mask; | |
1870 | ||
1871 | /* should always can generate irq */ | |
1872 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1873 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
1874 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB | | |
1875 | DE_PIPEB_VBLANK_IVB); | |
1876 | POSTING_READ(DEIER); | |
1877 | ||
1878 | dev_priv->gt_irq_mask = ~0; | |
1879 | ||
1880 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1881 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
1882 | ||
1883 | render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT | | |
1884 | GT_BLT_USER_INTERRUPT; | |
1885 | I915_WRITE(GTIER, render_irqs); | |
1886 | POSTING_READ(GTIER); | |
1887 | ||
1888 | hotplug_mask = (SDE_CRT_HOTPLUG_CPT | | |
1889 | SDE_PORTB_HOTPLUG_CPT | | |
1890 | SDE_PORTC_HOTPLUG_CPT | | |
1891 | SDE_PORTD_HOTPLUG_CPT); | |
1892 | dev_priv->pch_irq_mask = ~hotplug_mask; | |
1893 | ||
1894 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1895 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); | |
1896 | I915_WRITE(SDEIER, hotplug_mask); | |
1897 | POSTING_READ(SDEIER); | |
1898 | ||
1899 | return 0; | |
1900 | } | |
1901 | ||
f71d4af4 | 1902 | static void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1903 | { |
1904 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1905 | int pipe; |
1da177e4 | 1906 | |
79e53945 JB |
1907 | atomic_set(&dev_priv->irq_received, 0); |
1908 | ||
036a4a7d | 1909 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1910 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1911 | |
5ca58282 JB |
1912 | if (I915_HAS_HOTPLUG(dev)) { |
1913 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1914 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1915 | } | |
1916 | ||
0a3e67a4 | 1917 | I915_WRITE(HWSTAM, 0xeffe); |
9db4a9c7 JB |
1918 | for_each_pipe(pipe) |
1919 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 1920 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1921 | I915_WRITE(IER, 0x0); |
3143a2bf | 1922 | POSTING_READ(IER); |
1da177e4 LT |
1923 | } |
1924 | ||
b01f2c3a JB |
1925 | /* |
1926 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1927 | * enabled correctly. | |
1928 | */ | |
f71d4af4 | 1929 | static int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1930 | { |
1931 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1932 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1933 | u32 error_mask; |
0a3e67a4 JB |
1934 | |
1935 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; | |
0a3e67a4 | 1936 | |
7c463586 | 1937 | /* Unmask the interrupts that we always want on. */ |
1ec14ad3 | 1938 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
7c463586 KP |
1939 | |
1940 | dev_priv->pipestat[0] = 0; | |
1941 | dev_priv->pipestat[1] = 0; | |
1942 | ||
5ca58282 | 1943 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1944 | /* Enable in IER... */ |
1945 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1946 | /* and unmask in IMR */ | |
1ec14ad3 | 1947 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1948 | } |
1949 | ||
63eeaf38 JB |
1950 | /* |
1951 | * Enable some error detection, note the instruction error mask | |
1952 | * bit is reserved, so we leave it masked. | |
1953 | */ | |
1954 | if (IS_G4X(dev)) { | |
1955 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1956 | GM45_ERROR_MEM_PRIV | | |
1957 | GM45_ERROR_CP_PRIV | | |
1958 | I915_ERROR_MEMORY_REFRESH); | |
1959 | } else { | |
1960 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1961 | I915_ERROR_MEMORY_REFRESH); | |
1962 | } | |
1963 | I915_WRITE(EMR, error_mask); | |
1964 | ||
1ec14ad3 | 1965 | I915_WRITE(IMR, dev_priv->irq_mask); |
c496fa1f | 1966 | I915_WRITE(IER, enable_mask); |
3143a2bf | 1967 | POSTING_READ(IER); |
ed4cb414 | 1968 | |
c496fa1f AJ |
1969 | if (I915_HAS_HOTPLUG(dev)) { |
1970 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1971 | ||
1972 | /* Note HDMI and DP share bits */ | |
1973 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1974 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1975 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1976 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1977 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1978 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1979 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1980 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1981 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1982 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1983 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1984 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1985 | |
1986 | /* Programming the CRT detection parameters tends | |
1987 | to generate a spurious hotplug event about three | |
1988 | seconds later. So just do it once. | |
1989 | */ | |
1990 | if (IS_G4X(dev)) | |
1991 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1992 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1993 | } | |
1994 | ||
c496fa1f AJ |
1995 | /* Ignore TV since it's buggy */ |
1996 | ||
1997 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1998 | } | |
1999 | ||
3b617967 | 2000 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
2001 | |
2002 | return 0; | |
1da177e4 LT |
2003 | } |
2004 | ||
f71d4af4 | 2005 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
2006 | { |
2007 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
4697995b JB |
2008 | |
2009 | if (!dev_priv) | |
2010 | return; | |
2011 | ||
2012 | dev_priv->vblank_pipe = 0; | |
2013 | ||
036a4a7d ZW |
2014 | I915_WRITE(HWSTAM, 0xffffffff); |
2015 | ||
2016 | I915_WRITE(DEIMR, 0xffffffff); | |
2017 | I915_WRITE(DEIER, 0x0); | |
2018 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
2019 | ||
2020 | I915_WRITE(GTIMR, 0xffffffff); | |
2021 | I915_WRITE(GTIER, 0x0); | |
2022 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
2023 | } | |
2024 | ||
f71d4af4 | 2025 | static void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
2026 | { |
2027 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 2028 | int pipe; |
91e3738e | 2029 | |
1da177e4 LT |
2030 | if (!dev_priv) |
2031 | return; | |
2032 | ||
0a3e67a4 JB |
2033 | dev_priv->vblank_pipe = 0; |
2034 | ||
5ca58282 JB |
2035 | if (I915_HAS_HOTPLUG(dev)) { |
2036 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
2037 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
2038 | } | |
2039 | ||
0a3e67a4 | 2040 | I915_WRITE(HWSTAM, 0xffffffff); |
9db4a9c7 JB |
2041 | for_each_pipe(pipe) |
2042 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 2043 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 2044 | I915_WRITE(IER, 0x0); |
af6061af | 2045 | |
9db4a9c7 JB |
2046 | for_each_pipe(pipe) |
2047 | I915_WRITE(PIPESTAT(pipe), | |
2048 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
7c463586 | 2049 | I915_WRITE(IIR, I915_READ(IIR)); |
1da177e4 | 2050 | } |
f71d4af4 JB |
2051 | |
2052 | void intel_irq_init(struct drm_device *dev) | |
2053 | { | |
2054 | dev->driver->get_vblank_counter = i915_get_vblank_counter; | |
2055 | dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */ | |
2056 | if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) { | |
2057 | dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */ | |
2058 | dev->driver->get_vblank_counter = gm45_get_vblank_counter; | |
2059 | } | |
2060 | ||
c3613de9 KP |
2061 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
2062 | dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp; | |
2063 | else | |
2064 | dev->driver->get_vblank_timestamp = NULL; | |
f71d4af4 JB |
2065 | dev->driver->get_scanout_position = i915_get_crtc_scanoutpos; |
2066 | ||
2067 | if (IS_IVYBRIDGE(dev)) { | |
2068 | /* Share pre & uninstall handlers with ILK/SNB */ | |
2069 | dev->driver->irq_handler = ivybridge_irq_handler; | |
2070 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2071 | dev->driver->irq_postinstall = ivybridge_irq_postinstall; | |
2072 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2073 | dev->driver->enable_vblank = ivybridge_enable_vblank; | |
2074 | dev->driver->disable_vblank = ivybridge_disable_vblank; | |
2075 | } else if (HAS_PCH_SPLIT(dev)) { | |
2076 | dev->driver->irq_handler = ironlake_irq_handler; | |
2077 | dev->driver->irq_preinstall = ironlake_irq_preinstall; | |
2078 | dev->driver->irq_postinstall = ironlake_irq_postinstall; | |
2079 | dev->driver->irq_uninstall = ironlake_irq_uninstall; | |
2080 | dev->driver->enable_vblank = ironlake_enable_vblank; | |
2081 | dev->driver->disable_vblank = ironlake_disable_vblank; | |
2082 | } else { | |
2083 | dev->driver->irq_preinstall = i915_driver_irq_preinstall; | |
2084 | dev->driver->irq_postinstall = i915_driver_irq_postinstall; | |
2085 | dev->driver->irq_uninstall = i915_driver_irq_uninstall; | |
2086 | dev->driver->irq_handler = i915_driver_irq_handler; | |
2087 | dev->driver->enable_vblank = i915_enable_vblank; | |
2088 | dev->driver->disable_vblank = i915_disable_vblank; | |
2089 | } | |
2090 | } |