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drm/i915: Add new INSTDONE registers
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
9270388e
DV		 299/* defined intel_pm.c */
300extern spinlock_t mchdev_lock;
301
73edd18f 302static void ironlake_handle_rps_change(struct drm_device *dev)
f97108d1
JB		 303{
304 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 305 u32 busy_up, busy_down, max_avg, min_avg;
9270388e
DV		 306 u8 new_delay;
307 unsigned long flags;
308
309 spin_lock_irqsave(&mchdev_lock, flags);
f97108d1 310
73edd18f
DV		 311 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
312
9270388e
DV		 313 new_delay = dev_priv->cur_delay;
314
7648fa99 315 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 316 busy_up = I915_READ(RCPREVBSYTUPAVG);
317 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 318 max_avg = I915_READ(RCBMAXAVG);
319 min_avg = I915_READ(RCBMINAVG);
320
321 /* Handle RCS change request from hw */
b5b72e89 322 if (busy_up > max_avg) {
f97108d1
JB		 323 if (dev_priv->cur_delay != dev_priv->max_delay)
324 new_delay = dev_priv->cur_delay - 1;
325 if (new_delay < dev_priv->max_delay)
326 new_delay = dev_priv->max_delay;
b5b72e89 327 } else if (busy_down < min_avg) {
f97108d1
JB		 328 if (dev_priv->cur_delay != dev_priv->min_delay)
329 new_delay = dev_priv->cur_delay + 1;
330 if (new_delay > dev_priv->min_delay)
331 new_delay = dev_priv->min_delay;
332 }
333
7648fa99
JB		 334 if (ironlake_set_drps(dev, new_delay))
335 dev_priv->cur_delay = new_delay;
f97108d1 336
9270388e
DV		 337 spin_unlock_irqrestore(&mchdev_lock, flags);
338
f97108d1
JB		 339 return;
340}
341
549f7365
CW		 342static void notify_ring(struct drm_device *dev,
343 struct intel_ring_buffer *ring)
344{
345 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 346
475553de
CW		 347 if (ring->obj == NULL)
348 return;
349
b2eadbc8 350 trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
9862e600 351
549f7365 352 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 353 if (i915_enable_hangcheck) {
354 dev_priv->hangcheck_count = 0;
355 mod_timer(&dev_priv->hangcheck_timer,
356 jiffies +
357 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
358 }
549f7365
CW		 359}
360
4912d041 361static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 362{
4912d041 363 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
c6a828d3 364 rps.work);
4912d041 365 u32 pm_iir, pm_imr;
7b9e0ae6 366 u8 new_delay;
4912d041 367
c6a828d3
DV		 368 spin_lock_irq(&dev_priv->rps.lock);
369 pm_iir = dev_priv->rps.pm_iir;
370 dev_priv->rps.pm_iir = 0;
4912d041 371 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 372 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 373 spin_unlock_irq(&dev_priv->rps.lock);
3b8d8d91 374
7b9e0ae6 375 if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
3b8d8d91
JB		 376 return;
377
4912d041 378 mutex_lock(&dev_priv->dev->struct_mutex);
7b9e0ae6
CW		 379
380 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
c6a828d3 381 new_delay = dev_priv->rps.cur_delay + 1;
7b9e0ae6 382 else
c6a828d3 383 new_delay = dev_priv->rps.cur_delay - 1;
3b8d8d91 384
4912d041 385 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91 386
4912d041 387 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 388}
389
e3689190
BW		 390
391/**
392 * ivybridge_parity_work - Workqueue called when a parity error interrupt
393 * occurred.
394 * @work: workqueue struct
395 *
396 * Doesn't actually do anything except notify userspace. As a consequence of
397 * this event, userspace should try to remap the bad rows since statistically
398 * it is likely the same row is more likely to go bad again.
399 */
400static void ivybridge_parity_work(struct work_struct *work)
401{
402 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
403 parity_error_work);
404 u32 error_status, row, bank, subbank;
405 char *parity_event[5];
406 uint32_t misccpctl;
407 unsigned long flags;
408
409 /* We must turn off DOP level clock gating to access the L3 registers.
410 * In order to prevent a get/put style interface, acquire struct mutex
411 * any time we access those registers.
412 */
413 mutex_lock(&dev_priv->dev->struct_mutex);
414
415 misccpctl = I915_READ(GEN7_MISCCPCTL);
416 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
417 POSTING_READ(GEN7_MISCCPCTL);
418
419 error_status = I915_READ(GEN7_L3CDERRST1);
420 row = GEN7_PARITY_ERROR_ROW(error_status);
421 bank = GEN7_PARITY_ERROR_BANK(error_status);
422 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
423
424 I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
425 GEN7_L3CDERRST1_ENABLE);
426 POSTING_READ(GEN7_L3CDERRST1);
427
428 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
429
430 spin_lock_irqsave(&dev_priv->irq_lock, flags);
431 dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
432 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
433 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
434
435 mutex_unlock(&dev_priv->dev->struct_mutex);
436
437 parity_event[0] = "L3_PARITY_ERROR=1";
438 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
439 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
440 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
441 parity_event[4] = NULL;
442
443 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
444 KOBJ_CHANGE, parity_event);
445
446 DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
447 row, bank, subbank);
448
449 kfree(parity_event[3]);
450 kfree(parity_event[2]);
451 kfree(parity_event[1]);
452}
453
d2ba8470 454static void ivybridge_handle_parity_error(struct drm_device *dev)
e3689190
BW		 455{
456 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
457 unsigned long flags;
458
e1ef7cc2 459 if (!HAS_L3_GPU_CACHE(dev))
e3689190
BW		 460 return;
461
462 spin_lock_irqsave(&dev_priv->irq_lock, flags);
463 dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
464 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
465 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
466
467 queue_work(dev_priv->wq, &dev_priv->parity_error_work);
468}
469
e7b4c6b1
DV		 470static void snb_gt_irq_handler(struct drm_device *dev,
471 struct drm_i915_private *dev_priv,
472 u32 gt_iir)
473{
474
475 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
476 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
477 notify_ring(dev, &dev_priv->ring[RCS]);
478 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
479 notify_ring(dev, &dev_priv->ring[VCS]);
480 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
481 notify_ring(dev, &dev_priv->ring[BCS]);
482
483 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
484 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
485 GT_RENDER_CS_ERROR_INTERRUPT)) {
486 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
487 i915_handle_error(dev, false);
488 }
e3689190
BW		 489
490 if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
491 ivybridge_handle_parity_error(dev);
e7b4c6b1
DV		 492}
493
fc6826d1
CW		 494static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
495 u32 pm_iir)
496{
497 unsigned long flags;
498
499 /*
500 * IIR bits should never already be set because IMR should
501 * prevent an interrupt from being shown in IIR. The warning
502 * displays a case where we've unsafely cleared
c6a828d3 503 * dev_priv->rps.pm_iir. Although missing an interrupt of the same
fc6826d1
CW		 504 * type is not a problem, it displays a problem in the logic.
505 *
c6a828d3 506 * The mask bit in IMR is cleared by dev_priv->rps.work.
fc6826d1
CW		 507 */
508
c6a828d3 509 spin_lock_irqsave(&dev_priv->rps.lock, flags);
c6a828d3
DV		 510 dev_priv->rps.pm_iir |= pm_iir;
511 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
fc6826d1 512 POSTING_READ(GEN6_PMIMR);
c6a828d3 513 spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
fc6826d1 514
c6a828d3 515 queue_work(dev_priv->wq, &dev_priv->rps.work);
fc6826d1
CW		 516}
517
7e231dbe
JB		 518static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
519{
520 struct drm_device *dev = (struct drm_device *) arg;
521 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
522 u32 iir, gt_iir, pm_iir;
523 irqreturn_t ret = IRQ_NONE;
524 unsigned long irqflags;
525 int pipe;
526 u32 pipe_stats[I915_MAX_PIPES];
7e231dbe
JB		 527 bool blc_event;
528
529 atomic_inc(&dev_priv->irq_received);
530
7e231dbe
JB		 531 while (true) {
532 iir = I915_READ(VLV_IIR);
533 gt_iir = I915_READ(GTIIR);
534 pm_iir = I915_READ(GEN6_PMIIR);
535
536 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
537 goto out;
538
539 ret = IRQ_HANDLED;
540
e7b4c6b1 541 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 542
543 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
544 for_each_pipe(pipe) {
545 int reg = PIPESTAT(pipe);
546 pipe_stats[pipe] = I915_READ(reg);
547
548 /*
549 * Clear the PIPE*STAT regs before the IIR
550 */
551 if (pipe_stats[pipe] & 0x8000ffff) {
552 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
553 DRM_DEBUG_DRIVER("pipe %c underrun\n",
554 pipe_name(pipe));
555 I915_WRITE(reg, pipe_stats[pipe]);
556 }
557 }
558 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
559
31acc7f5
JB		 560 for_each_pipe(pipe) {
561 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
562 drm_handle_vblank(dev, pipe);
563
564 if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
565 intel_prepare_page_flip(dev, pipe);
566 intel_finish_page_flip(dev, pipe);
567 }
568 }
569
7e231dbe
JB		 570 /* Consume port. Then clear IIR or we'll miss events */
571 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
572 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
573
574 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
575 hotplug_status);
576 if (hotplug_status & dev_priv->hotplug_supported_mask)
577 queue_work(dev_priv->wq,
578 &dev_priv->hotplug_work);
579
580 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
581 I915_READ(PORT_HOTPLUG_STAT);
582 }
583
7e231dbe
JB		 584 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
585 blc_event = true;
586
fc6826d1
CW		 587 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
588 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 589
590 I915_WRITE(GTIIR, gt_iir);
591 I915_WRITE(GEN6_PMIIR, pm_iir);
592 I915_WRITE(VLV_IIR, iir);
593 }
594
595out:
596 return ret;
597}
598
23e81d69 599static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
776ad806
JB		 600{
601 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 602 int pipe;
776ad806 603
776ad806
JB		 604 if (pch_iir & SDE_AUDIO_POWER_MASK)
605 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
606 (pch_iir & SDE_AUDIO_POWER_MASK) >>
607 SDE_AUDIO_POWER_SHIFT);
608
609 if (pch_iir & SDE_GMBUS)
610 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
611
612 if (pch_iir & SDE_AUDIO_HDCP_MASK)
613 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
614
615 if (pch_iir & SDE_AUDIO_TRANS_MASK)
616 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
617
618 if (pch_iir & SDE_POISON)
619 DRM_ERROR("PCH poison interrupt\n");
620
9db4a9c7
JB		 621 if (pch_iir & SDE_FDI_MASK)
622 for_each_pipe(pipe)
623 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
624 pipe_name(pipe),
625 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 626
627 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
628 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
629
630 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
631 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
632
633 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
634 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
635 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
636 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
637}
638
23e81d69
AJ		 639static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
640{
641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
642 int pipe;
643
644 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
645 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
646 (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
647 SDE_AUDIO_POWER_SHIFT_CPT);
648
649 if (pch_iir & SDE_AUX_MASK_CPT)
650 DRM_DEBUG_DRIVER("AUX channel interrupt\n");
651
652 if (pch_iir & SDE_GMBUS_CPT)
653 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
654
655 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
656 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
657
658 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
659 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
660
661 if (pch_iir & SDE_FDI_MASK_CPT)
662 for_each_pipe(pipe)
663 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
664 pipe_name(pipe),
665 I915_READ(FDI_RX_IIR(pipe)));
666}
667
f71d4af4 668static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 669{
670 struct drm_device *dev = (struct drm_device *) arg;
671 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
0e43406b
CW		 672 u32 de_iir, gt_iir, de_ier, pm_iir;
673 irqreturn_t ret = IRQ_NONE;
674 int i;
b1f14ad0
JB		 675
676 atomic_inc(&dev_priv->irq_received);
677
678 /* disable master interrupt before clearing iir */
679 de_ier = I915_READ(DEIER);
680 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
b1f14ad0 681
b1f14ad0 682 gt_iir = I915_READ(GTIIR);
0e43406b
CW		 683 if (gt_iir) {
684 snb_gt_irq_handler(dev, dev_priv, gt_iir);
685 I915_WRITE(GTIIR, gt_iir);
686 ret = IRQ_HANDLED;
b1f14ad0
JB		 687 }
688
0e43406b
CW		 689 de_iir = I915_READ(DEIIR);
690 if (de_iir) {
691 if (de_iir & DE_GSE_IVB)
692 intel_opregion_gse_intr(dev);
693
694 for (i = 0; i < 3; i++) {
695 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
696 intel_prepare_page_flip(dev, i);
697 intel_finish_page_flip_plane(dev, i);
698 }
699 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
700 drm_handle_vblank(dev, i);
701 }
b615b57a 702
0e43406b
CW		 703 /* check event from PCH */
704 if (de_iir & DE_PCH_EVENT_IVB) {
705 u32 pch_iir = I915_READ(SDEIIR);
b1f14ad0 706
0e43406b
CW		 707 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
708 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69 709 cpt_irq_handler(dev, pch_iir);
b1f14ad0 710
0e43406b
CW		 711 /* clear PCH hotplug event before clear CPU irq */
712 I915_WRITE(SDEIIR, pch_iir);
713 }
b615b57a 714
0e43406b
CW		 715 I915_WRITE(DEIIR, de_iir);
716 ret = IRQ_HANDLED;
b1f14ad0
JB		 717 }
718
0e43406b
CW		 719 pm_iir = I915_READ(GEN6_PMIIR);
720 if (pm_iir) {
721 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
722 gen6_queue_rps_work(dev_priv, pm_iir);
723 I915_WRITE(GEN6_PMIIR, pm_iir);
724 ret = IRQ_HANDLED;
725 }
b1f14ad0 726
b1f14ad0
JB		 727 I915_WRITE(DEIER, de_ier);
728 POSTING_READ(DEIER);
729
730 return ret;
731}
732
e7b4c6b1
DV		 733static void ilk_gt_irq_handler(struct drm_device *dev,
734 struct drm_i915_private *dev_priv,
735 u32 gt_iir)
736{
737 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
738 notify_ring(dev, &dev_priv->ring[RCS]);
739 if (gt_iir & GT_BSD_USER_INTERRUPT)
740 notify_ring(dev, &dev_priv->ring[VCS]);
741}
742
f71d4af4 743static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 744{
4697995b 745 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 746 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
747 int ret = IRQ_NONE;
3b8d8d91 748 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 749 u32 hotplug_mask;
881f47b6 750
4697995b
JB		 751 atomic_inc(&dev_priv->irq_received);
752
2d109a84
ZN		 753 /* disable master interrupt before clearing iir */
754 de_ier = I915_READ(DEIER);
755 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 756 POSTING_READ(DEIER);
2d109a84 757
036a4a7d
ZW		 758 de_iir = I915_READ(DEIIR);
759 gt_iir = I915_READ(GTIIR);
c650156a 760 pch_iir = I915_READ(SDEIIR);
3b8d8d91 761 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 762
3b8d8d91
JB		 763 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
764 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 765 goto done;
036a4a7d 766
2d7b8366
YL		 767 if (HAS_PCH_CPT(dev))
768 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
769 else
770 hotplug_mask = SDE_HOTPLUG_MASK;
771
c7c85101 772 ret = IRQ_HANDLED;
036a4a7d 773
e7b4c6b1
DV		 774 if (IS_GEN5(dev))
775 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
776 else
777 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 778
c7c85101 779 if (de_iir & DE_GSE)
3b617967 780 intel_opregion_gse_intr(dev);
c650156a 781
f072d2e7 782 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 783 intel_prepare_page_flip(dev, 0);
2bbda389 784 intel_finish_page_flip_plane(dev, 0);
f072d2e7 785 }
013d5aa2 786
f072d2e7 787 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 788 intel_prepare_page_flip(dev, 1);
2bbda389 789 intel_finish_page_flip_plane(dev, 1);
f072d2e7 790 }
013d5aa2 791
f072d2e7 792 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 793 drm_handle_vblank(dev, 0);
794
f072d2e7 795 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 796 drm_handle_vblank(dev, 1);
797
c7c85101 798 /* check event from PCH */
776ad806
JB		 799 if (de_iir & DE_PCH_EVENT) {
800 if (pch_iir & hotplug_mask)
801 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
23e81d69
AJ		 802 if (HAS_PCH_CPT(dev))
803 cpt_irq_handler(dev, pch_iir);
804 else
805 ibx_irq_handler(dev, pch_iir);
776ad806 806 }
036a4a7d 807
73edd18f
DV		 808 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
809 ironlake_handle_rps_change(dev);
f97108d1 810
fc6826d1
CW		 811 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
812 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 813
c7c85101
ZN		 814 /* should clear PCH hotplug event before clear CPU irq */
815 I915_WRITE(SDEIIR, pch_iir);
816 I915_WRITE(GTIIR, gt_iir);
817 I915_WRITE(DEIIR, de_iir);
4912d041 818 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 819
820done:
2d109a84 821 I915_WRITE(DEIER, de_ier);
3143a2bf 822 POSTING_READ(DEIER);
2d109a84 823
036a4a7d
ZW		 824 return ret;
825}
826
8a905236
JB		 827/**
828 * i915_error_work_func - do process context error handling work
829 * @work: work struct
830 *
831 * Fire an error uevent so userspace can see that a hang or error
832 * was detected.
833 */
834static void i915_error_work_func(struct work_struct *work)
835{
836 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
837 error_work);
838 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 839 char *error_event[] = { "ERROR=1", NULL };
840 char *reset_event[] = { "RESET=1", NULL };
841 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 842
f316a42c
BG		 843 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
844
ba1234d1 845 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 846 DRM_DEBUG_DRIVER("resetting chip\n");
847 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
d4b8bb2a 848 if (!i915_reset(dev)) {
f803aa55
CW		 849 atomic_set(&dev_priv->mm.wedged, 0);
850 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 851 }
30dbf0c0 852 complete_all(&dev_priv->error_completion);
f316a42c 853 }
8a905236
JB		 854}
855
3bd3c932 856#ifdef CONFIG_DEBUG_FS
9df30794 857static struct drm_i915_error_object *
bcfb2e28 858i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 859 struct drm_i915_gem_object *src)
9df30794
CW		 860{
861 struct drm_i915_error_object *dst;
9df30794 862 int page, page_count;
e56660dd 863 u32 reloc_offset;
9df30794 864
05394f39 865 if (src == NULL || src->pages == NULL)
9df30794
CW		 866 return NULL;
867
05394f39 868 page_count = src->base.size / PAGE_SIZE;
9df30794 869
0206e353 870 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 871 if (dst == NULL)
872 return NULL;
873
05394f39 874 reloc_offset = src->gtt_offset;
9df30794 875 for (page = 0; page < page_count; page++) {
788885ae 876 unsigned long flags;
e56660dd 877 void *d;
788885ae 878
e56660dd 879 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 880 if (d == NULL)
881 goto unwind;
e56660dd 882
788885ae 883 local_irq_save(flags);
74898d7e
DV		 884 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
885 src->has_global_gtt_mapping) {
172975aa
CW		 886 void __iomem *s;
887
888 /* Simply ignore tiling or any overlapping fence.
889 * It's part of the error state, and this hopefully
890 * captures what the GPU read.
891 */
892
893 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
894 reloc_offset);
895 memcpy_fromio(d, s, PAGE_SIZE);
896 io_mapping_unmap_atomic(s);
897 } else {
898 void *s;
899
900 drm_clflush_pages(&src->pages[page], 1);
901
902 s = kmap_atomic(src->pages[page]);
903 memcpy(d, s, PAGE_SIZE);
904 kunmap_atomic(s);
905
906 drm_clflush_pages(&src->pages[page], 1);
907 }
788885ae 908 local_irq_restore(flags);
e56660dd 909
9df30794 910 dst->pages[page] = d;
e56660dd
CW		 911
912 reloc_offset += PAGE_SIZE;
9df30794
CW		 913 }
914 dst->page_count = page_count;
05394f39 915 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 916
917 return dst;
918
919unwind:
920 while (page--)
921 kfree(dst->pages[page]);
922 kfree(dst);
923 return NULL;
924}
925
926static void
927i915_error_object_free(struct drm_i915_error_object *obj)
928{
929 int page;
930
931 if (obj == NULL)
932 return;
933
934 for (page = 0; page < obj->page_count; page++)
935 kfree(obj->pages[page]);
936
937 kfree(obj);
938}
939
742cbee8
DV		 940void
941i915_error_state_free(struct kref *error_ref)
9df30794 942{
742cbee8
DV		 943 struct drm_i915_error_state *error = container_of(error_ref,
944 typeof(*error), ref);
e2f973d5
CW		 945 int i;
946
52d39a21
CW		 947 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
948 i915_error_object_free(error->ring[i].batchbuffer);
949 i915_error_object_free(error->ring[i].ringbuffer);
950 kfree(error->ring[i].requests);
951 }
e2f973d5 952
9df30794 953 kfree(error->active_bo);
6ef3d427 954 kfree(error->overlay);
9df30794
CW		 955 kfree(error);
956}
1b50247a
CW		 957static void capture_bo(struct drm_i915_error_buffer *err,
958 struct drm_i915_gem_object *obj)
959{
960 err->size = obj->base.size;
961 err->name = obj->base.name;
0201f1ec
CW		 962 err->rseqno = obj->last_read_seqno;
963 err->wseqno = obj->last_write_seqno;
1b50247a
CW		 964 err->gtt_offset = obj->gtt_offset;
965 err->read_domains = obj->base.read_domains;
966 err->write_domain = obj->base.write_domain;
967 err->fence_reg = obj->fence_reg;
968 err->pinned = 0;
969 if (obj->pin_count > 0)
970 err->pinned = 1;
971 if (obj->user_pin_count > 0)
972 err->pinned = -1;
973 err->tiling = obj->tiling_mode;
974 err->dirty = obj->dirty;
975 err->purgeable = obj->madv != I915_MADV_WILLNEED;
976 err->ring = obj->ring ? obj->ring->id : -1;
977 err->cache_level = obj->cache_level;
978}
9df30794 979
1b50247a
CW		 980static u32 capture_active_bo(struct drm_i915_error_buffer *err,
981 int count, struct list_head *head)
c724e8a9
CW		 982{
983 struct drm_i915_gem_object *obj;
984 int i = 0;
985
986 list_for_each_entry(obj, head, mm_list) {
1b50247a 987 capture_bo(err++, obj);
c724e8a9
CW		 988 if (++i == count)
989 break;
1b50247a
CW		 990 }
991
992 return i;
993}
994
995static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
996 int count, struct list_head *head)
997{
998 struct drm_i915_gem_object *obj;
999 int i = 0;
1000
1001 list_for_each_entry(obj, head, gtt_list) {
1002 if (obj->pin_count == 0)
1003 continue;
c724e8a9 1004
1b50247a
CW		 1005 capture_bo(err++, obj);
1006 if (++i == count)
1007 break;
c724e8a9
CW		 1008 }
1009
1010 return i;
1011}
1012
748ebc60
CW		 1013static void i915_gem_record_fences(struct drm_device *dev,
1014 struct drm_i915_error_state *error)
1015{
1016 struct drm_i915_private *dev_priv = dev->dev_private;
1017 int i;
1018
1019 /* Fences */
1020 switch (INTEL_INFO(dev)->gen) {
775d17b6 1021 case 7:
748ebc60
CW		 1022 case 6:
1023 for (i = 0; i < 16; i++)
1024 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1025 break;
1026 case 5:
1027 case 4:
1028 for (i = 0; i < 16; i++)
1029 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1030 break;
1031 case 3:
1032 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1033 for (i = 0; i < 8; i++)
1034 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1035 case 2:
1036 for (i = 0; i < 8; i++)
1037 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1038 break;
1039
1040 }
1041}
1042
bcfb2e28
CW		 1043static struct drm_i915_error_object *
1044i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1045 struct intel_ring_buffer *ring)
1046{
1047 struct drm_i915_gem_object *obj;
1048 u32 seqno;
1049
1050 if (!ring->get_seqno)
1051 return NULL;
1052
b2eadbc8 1053 seqno = ring->get_seqno(ring, false);
bcfb2e28
CW		 1054 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1055 if (obj->ring != ring)
1056 continue;
1057
0201f1ec 1058 if (i915_seqno_passed(seqno, obj->last_read_seqno))
bcfb2e28
CW		 1059 continue;
1060
1061 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1062 continue;
1063
1064 /* We need to copy these to an anonymous buffer as the simplest
1065 * method to avoid being overwritten by userspace.
1066 */
1067 return i915_error_object_create(dev_priv, obj);
1068 }
1069
1070 return NULL;
1071}
1072
bd9854f9
BW		 1073/* NB: please notice the memset */
1074static void i915_get_extra_instdone(struct drm_device *dev,
1075 uint32_t *instdone)
1076{
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1079
1080 if (INTEL_INFO(dev)->gen < 4) {
1081 instdone[0] = I915_READ(INSTDONE);
1082 instdone[1] = 0;
1083 } else {
1084 instdone[0] = I915_READ(INSTDONE_I965);
1085 instdone[1] = I915_READ(INSTDONE1);
1086 }
1087}
1088
1089
d27b1e0e
DV		 1090static void i915_record_ring_state(struct drm_device *dev,
1091 struct drm_i915_error_state *error,
1092 struct intel_ring_buffer *ring)
1093{
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095
33f3f518 1096 if (INTEL_INFO(dev)->gen >= 6) {
12f55818 1097 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
33f3f518 1098 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1099 error->semaphore_mboxes[ring->id][0]
1100 = I915_READ(RING_SYNC_0(ring->mmio_base));
1101 error->semaphore_mboxes[ring->id][1]
1102 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1103 }
c1cd90ed 1104
d27b1e0e 1105 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1106 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1107 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1108 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1109 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1110 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1111 if (ring->id == RCS) {
d27b1e0e
DV		 1112 error->instdone1 = I915_READ(INSTDONE1);
1113 error->bbaddr = I915_READ64(BB_ADDR);
1114 }
1115 } else {
9d2f41fa 1116 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1117 error->ipeir[ring->id] = I915_READ(IPEIR);
1118 error->ipehr[ring->id] = I915_READ(IPEHR);
1119 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1120 }
1121
9574b3fe 1122 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1123 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
b2eadbc8 1124 error->seqno[ring->id] = ring->get_seqno(ring, false);
d27b1e0e 1125 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1126 error->head[ring->id] = I915_READ_HEAD(ring);
1127 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1128
1129 error->cpu_ring_head[ring->id] = ring->head;
1130 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1131}
1132
52d39a21
CW		 1133static void i915_gem_record_rings(struct drm_device *dev,
1134 struct drm_i915_error_state *error)
1135{
1136 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 1137 struct intel_ring_buffer *ring;
52d39a21
CW		 1138 struct drm_i915_gem_request *request;
1139 int i, count;
1140
b4519513 1141 for_each_ring(ring, dev_priv, i) {
52d39a21
CW		 1142 i915_record_ring_state(dev, error, ring);
1143
1144 error->ring[i].batchbuffer =
1145 i915_error_first_batchbuffer(dev_priv, ring);
1146
1147 error->ring[i].ringbuffer =
1148 i915_error_object_create(dev_priv, ring->obj);
1149
1150 count = 0;
1151 list_for_each_entry(request, &ring->request_list, list)
1152 count++;
1153
1154 error->ring[i].num_requests = count;
1155 error->ring[i].requests =
1156 kmalloc(count*sizeof(struct drm_i915_error_request),
1157 GFP_ATOMIC);
1158 if (error->ring[i].requests == NULL) {
1159 error->ring[i].num_requests = 0;
1160 continue;
1161 }
1162
1163 count = 0;
1164 list_for_each_entry(request, &ring->request_list, list) {
1165 struct drm_i915_error_request *erq;
1166
1167 erq = &error->ring[i].requests[count++];
1168 erq->seqno = request->seqno;
1169 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1170 erq->tail = request->tail;
52d39a21
CW		 1171 }
1172 }
1173}
1174
8a905236
JB		 1175/**
1176 * i915_capture_error_state - capture an error record for later analysis
1177 * @dev: drm device
1178 *
1179 * Should be called when an error is detected (either a hang or an error
1180 * interrupt) to capture error state from the time of the error. Fills
1181 * out a structure which becomes available in debugfs for user level tools
1182 * to pick up.
1183 */
63eeaf38
JB		 1184static void i915_capture_error_state(struct drm_device *dev)
1185{
1186 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1187 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1188 struct drm_i915_error_state *error;
1189 unsigned long flags;
9db4a9c7 1190 int i, pipe;
63eeaf38
JB		 1191
1192 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1193 error = dev_priv->first_error;
1194 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1195 if (error)
1196 return;
63eeaf38 1197
9db4a9c7 1198 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1199 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1200 if (!error) {
9df30794
CW		 1201 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1202 return;
63eeaf38
JB		 1203 }
1204
b6f7833b
CW		 1205 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1206 dev->primary->index);
2fa772f3 1207
742cbee8 1208 kref_init(&error->ref);
63eeaf38
JB		 1209 error->eir = I915_READ(EIR);
1210 error->pgtbl_er = I915_READ(PGTBL_ER);
b9a3906b 1211 error->ccid = I915_READ(CCID);
be998e2e
BW		 1212
1213 if (HAS_PCH_SPLIT(dev))
1214 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1215 else if (IS_VALLEYVIEW(dev))
1216 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1217 else if (IS_GEN2(dev))
1218 error->ier = I915_READ16(IER);
1219 else
1220 error->ier = I915_READ(IER);
1221
9db4a9c7
JB		 1222 for_each_pipe(pipe)
1223 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1224
33f3f518 1225 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1226 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1227 error->done_reg = I915_READ(DONE_REG);
1228 }
d27b1e0e 1229
71e172e8
BW		 1230 if (INTEL_INFO(dev)->gen == 7)
1231 error->err_int = I915_READ(GEN7_ERR_INT);
1232
748ebc60 1233 i915_gem_record_fences(dev, error);
52d39a21 1234 i915_gem_record_rings(dev, error);
9df30794 1235
c724e8a9 1236 /* Record buffers on the active and pinned lists. */
9df30794 1237 error->active_bo = NULL;
c724e8a9 1238 error->pinned_bo = NULL;
9df30794 1239
bcfb2e28
CW		 1240 i = 0;
1241 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1242 i++;
1243 error->active_bo_count = i;
6c085a72 1244 list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1b50247a
CW		 1245 if (obj->pin_count)
1246 i++;
bcfb2e28 1247 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1248
8e934dbf
CW		 1249 error->active_bo = NULL;
1250 error->pinned_bo = NULL;
bcfb2e28
CW		 1251 if (i) {
1252 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1253 GFP_ATOMIC);
c724e8a9
CW		 1254 if (error->active_bo)
1255 error->pinned_bo =
1256 error->active_bo + error->active_bo_count;
9df30794
CW		 1257 }
1258
c724e8a9
CW		 1259 if (error->active_bo)
1260 error->active_bo_count =
1b50247a
CW		 1261 capture_active_bo(error->active_bo,
1262 error->active_bo_count,
1263 &dev_priv->mm.active_list);
c724e8a9
CW		 1264
1265 if (error->pinned_bo)
1266 error->pinned_bo_count =
1b50247a
CW		 1267 capture_pinned_bo(error->pinned_bo,
1268 error->pinned_bo_count,
6c085a72 1269 &dev_priv->mm.bound_list);
c724e8a9 1270
9df30794
CW		 1271 do_gettimeofday(&error->time);
1272
6ef3d427 1273 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1274 error->display = intel_display_capture_error_state(dev);
6ef3d427 1275
9df30794
CW		 1276 spin_lock_irqsave(&dev_priv->error_lock, flags);
1277 if (dev_priv->first_error == NULL) {
1278 dev_priv->first_error = error;
1279 error = NULL;
1280 }
63eeaf38 1281 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1282
1283 if (error)
742cbee8 1284 i915_error_state_free(&error->ref);
9df30794
CW		 1285}
1286
1287void i915_destroy_error_state(struct drm_device *dev)
1288{
1289 struct drm_i915_private *dev_priv = dev->dev_private;
1290 struct drm_i915_error_state *error;
6dc0e816 1291 unsigned long flags;
9df30794 1292
6dc0e816 1293 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1294 error = dev_priv->first_error;
1295 dev_priv->first_error = NULL;
6dc0e816 1296 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1297
1298 if (error)
742cbee8 1299 kref_put(&error->ref, i915_error_state_free);
63eeaf38 1300}
3bd3c932
CW		 1301#else
1302#define i915_capture_error_state(x)
1303#endif
63eeaf38 1304
35aed2e6 1305static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1306{
1307 struct drm_i915_private *dev_priv = dev->dev_private;
bd9854f9 1308 uint32_t instdone[I915_NUM_INSTDONE_REG];
8a905236 1309 u32 eir = I915_READ(EIR);
9db4a9c7 1310 int pipe;
8a905236 1311
35aed2e6
CW		 1312 if (!eir)
1313 return;
8a905236 1314
a70491cc 1315 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236 1316
bd9854f9
BW		 1317 i915_get_extra_instdone(dev, instdone);
1318
8a905236
JB		 1319 if (IS_G4X(dev)) {
1320 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1321 u32 ipeir = I915_READ(IPEIR_I965);
1322
a70491cc
JP		 1323 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1324 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
bd9854f9 1325 pr_err(" INSTDONE: 0x%08x\n", instdone[0]);
a70491cc 1326 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
bd9854f9 1327 pr_err(" INSTDONE1: 0x%08x\n", instdone[1]);
a70491cc 1328 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1329 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1330 POSTING_READ(IPEIR_I965);
8a905236
JB		 1331 }
1332 if (eir & GM45_ERROR_PAGE_TABLE) {
1333 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1334 pr_err("page table error\n");
1335 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1336 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1337 POSTING_READ(PGTBL_ER);
8a905236
JB		 1338 }
1339 }
1340
a6c45cf0 1341 if (!IS_GEN2(dev)) {
8a905236
JB		 1342 if (eir & I915_ERROR_PAGE_TABLE) {
1343 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1344 pr_err("page table error\n");
1345 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1346 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1347 POSTING_READ(PGTBL_ER);
8a905236
JB		 1348 }
1349 }
1350
1351 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1352 pr_err("memory refresh error:\n");
9db4a9c7 1353 for_each_pipe(pipe)
a70491cc 1354 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1355 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1356 /* pipestat has already been acked */
1357 }
1358 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1359 pr_err("instruction error\n");
1360 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1361 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1362 u32 ipeir = I915_READ(IPEIR);
1363
a70491cc
JP		 1364 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1365 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
bd9854f9 1366 pr_err(" INSTDONE: 0x%08x\n", instdone[0]);
a70491cc 1367 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1368 I915_WRITE(IPEIR, ipeir);
3143a2bf 1369 POSTING_READ(IPEIR);
8a905236
JB		 1370 } else {
1371 u32 ipeir = I915_READ(IPEIR_I965);
1372
a70491cc
JP		 1373 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1374 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
bd9854f9 1375 pr_err(" INSTDONE: 0x%08x\n", instdone[0]);
a70491cc 1376 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
bd9854f9 1377 pr_err(" INSTDONE1: 0x%08x\n", instdone[1]);
a70491cc 1378 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1379 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1380 POSTING_READ(IPEIR_I965);
8a905236
JB		 1381 }
1382 }
1383
1384 I915_WRITE(EIR, eir);
3143a2bf 1385 POSTING_READ(EIR);
8a905236
JB		 1386 eir = I915_READ(EIR);
1387 if (eir) {
1388 /*
1389 * some errors might have become stuck,
1390 * mask them.
1391 */
1392 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1393 I915_WRITE(EMR, I915_READ(EMR) | eir);
1394 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1395 }
35aed2e6
CW		 1396}
1397
1398/**
1399 * i915_handle_error - handle an error interrupt
1400 * @dev: drm device
1401 *
1402 * Do some basic checking of regsiter state at error interrupt time and
1403 * dump it to the syslog. Also call i915_capture_error_state() to make
1404 * sure we get a record and make it available in debugfs. Fire a uevent
1405 * so userspace knows something bad happened (should trigger collection
1406 * of a ring dump etc.).
1407 */
527f9e90 1408void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1409{
1410 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513
CW		 1411 struct intel_ring_buffer *ring;
1412 int i;
35aed2e6
CW		 1413
1414 i915_capture_error_state(dev);
1415 i915_report_and_clear_eir(dev);
8a905236 1416
ba1234d1 1417 if (wedged) {
30dbf0c0 1418 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1419 atomic_set(&dev_priv->mm.wedged, 1);
1420
11ed50ec
BG		 1421 /*
1422 * Wakeup waiting processes so they don't hang
1423 */
b4519513
CW		 1424 for_each_ring(ring, dev_priv, i)
1425 wake_up_all(&ring->irq_queue);
11ed50ec
BG		 1426 }
1427
9c9fe1f8 1428 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1429}
1430
4e5359cd
SF		 1431static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1432{
1433 drm_i915_private_t *dev_priv = dev->dev_private;
1434 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1436 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1437 struct intel_unpin_work *work;
1438 unsigned long flags;
1439 bool stall_detected;
1440
1441 /* Ignore early vblank irqs */
1442 if (intel_crtc == NULL)
1443 return;
1444
1445 spin_lock_irqsave(&dev->event_lock, flags);
1446 work = intel_crtc->unpin_work;
1447
1448 if (work == NULL || work->pending || !work->enable_stall_check) {
1449 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1450 spin_unlock_irqrestore(&dev->event_lock, flags);
1451 return;
1452 }
1453
1454 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1455 obj = work->pending_flip_obj;
a6c45cf0 1456 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1457 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1458 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1459 obj->gtt_offset;
4e5359cd 1460 } else {
9db4a9c7 1461 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1462 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1463 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1464 crtc->x * crtc->fb->bits_per_pixel/8);
1465 }
1466
1467 spin_unlock_irqrestore(&dev->event_lock, flags);
1468
1469 if (stall_detected) {
1470 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1471 intel_prepare_page_flip(dev, intel_crtc->plane);
1472 }
1473}
1474
42f52ef8
KP		 1475/* Called from drm generic code, passed 'crtc' which
1476 * we use as a pipe index
1477 */
f71d4af4 1478static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1479{
1480 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1481 unsigned long irqflags;
71e0ffa5 1482
5eddb70b 1483 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1484 return -EINVAL;
0a3e67a4 1485
1ec14ad3 1486 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1487 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1488 i915_enable_pipestat(dev_priv, pipe,
1489 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1490 else
7c463586
KP		 1491 i915_enable_pipestat(dev_priv, pipe,
1492 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1493
1494 /* maintain vblank delivery even in deep C-states */
1495 if (dev_priv->info->gen == 3)
6b26c86d 1496 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1497 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1498
0a3e67a4
JB		 1499 return 0;
1500}
1501
f71d4af4 1502static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1503{
1504 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1505 unsigned long irqflags;
1506
1507 if (!i915_pipe_enabled(dev, pipe))
1508 return -EINVAL;
1509
1510 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1511 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1512 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1513 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1514
1515 return 0;
1516}
1517
f71d4af4 1518static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1519{
1520 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1521 unsigned long irqflags;
1522
1523 if (!i915_pipe_enabled(dev, pipe))
1524 return -EINVAL;
1525
1526 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1527 ironlake_enable_display_irq(dev_priv,
1528 DE_PIPEA_VBLANK_IVB << (5 * pipe));
b1f14ad0
JB		 1529 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1530
1531 return 0;
1532}
1533
7e231dbe
JB		 1534static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1535{
1536 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1537 unsigned long irqflags;
31acc7f5 1538 u32 imr;
7e231dbe
JB		 1539
1540 if (!i915_pipe_enabled(dev, pipe))
1541 return -EINVAL;
1542
1543 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
7e231dbe 1544 imr = I915_READ(VLV_IMR);
31acc7f5 1545 if (pipe == 0)
7e231dbe 1546 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1547 else
7e231dbe 1548 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1549 I915_WRITE(VLV_IMR, imr);
31acc7f5
JB		 1550 i915_enable_pipestat(dev_priv, pipe,
1551 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe
JB		 1552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1553
1554 return 0;
1555}
1556
42f52ef8
KP		 1557/* Called from drm generic code, passed 'crtc' which
1558 * we use as a pipe index
1559 */
f71d4af4 1560static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1561{
1562 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1563 unsigned long irqflags;
0a3e67a4 1564
1ec14ad3 1565 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1566 if (dev_priv->info->gen == 3)
6b26c86d 1567 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1568
f796cf8f
JB		 1569 i915_disable_pipestat(dev_priv, pipe,
1570 PIPE_VBLANK_INTERRUPT_ENABLE |
1571 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1572 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1573}
1574
f71d4af4 1575static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1576{
1577 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1578 unsigned long irqflags;
1579
1580 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1581 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1582 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1583 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1584}
1585
f71d4af4 1586static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1587{
1588 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1589 unsigned long irqflags;
1590
1591 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
b615b57a
CW		 1592 ironlake_disable_display_irq(dev_priv,
1593 DE_PIPEA_VBLANK_IVB << (pipe * 5));
b1f14ad0
JB		 1594 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1595}
1596
7e231dbe
JB		 1597static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1598{
1599 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1600 unsigned long irqflags;
31acc7f5 1601 u32 imr;
7e231dbe
JB		 1602
1603 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
31acc7f5
JB		 1604 i915_disable_pipestat(dev_priv, pipe,
1605 PIPE_START_VBLANK_INTERRUPT_ENABLE);
7e231dbe 1606 imr = I915_READ(VLV_IMR);
31acc7f5 1607 if (pipe == 0)
7e231dbe 1608 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
31acc7f5 1609 else
7e231dbe 1610 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1611 I915_WRITE(VLV_IMR, imr);
7e231dbe
JB		 1612 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1613}
1614
893eead0
CW		 1615static u32
1616ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1617{
893eead0
CW		 1618 return list_entry(ring->request_list.prev,
1619 struct drm_i915_gem_request, list)->seqno;
1620}
1621
1622static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1623{
1624 if (list_empty(&ring->request_list) ||
b2eadbc8
CW		 1625 i915_seqno_passed(ring->get_seqno(ring, false),
1626 ring_last_seqno(ring))) {
893eead0 1627 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1628 if (waitqueue_active(&ring->irq_queue)) {
1629 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1630 ring->name);
893eead0
CW		 1631 wake_up_all(&ring->irq_queue);
1632 *err = true;
1633 }
1634 return true;
1635 }
1636 return false;
f65d9421
BG		 1637}
1638
1ec14ad3
CW		 1639static bool kick_ring(struct intel_ring_buffer *ring)
1640{
1641 struct drm_device *dev = ring->dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 u32 tmp = I915_READ_CTL(ring);
1644 if (tmp & RING_WAIT) {
1645 DRM_ERROR("Kicking stuck wait on %s\n",
1646 ring->name);
1647 I915_WRITE_CTL(ring, tmp);
1648 return true;
1649 }
1ec14ad3
CW		 1650 return false;
1651}
1652
d1e61e7f
CW		 1653static bool i915_hangcheck_hung(struct drm_device *dev)
1654{
1655 drm_i915_private_t *dev_priv = dev->dev_private;
1656
1657 if (dev_priv->hangcheck_count++ > 1) {
b4519513
CW		 1658 bool hung = true;
1659
d1e61e7f
CW		 1660 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1661 i915_handle_error(dev, true);
1662
1663 if (!IS_GEN2(dev)) {
b4519513
CW		 1664 struct intel_ring_buffer *ring;
1665 int i;
1666
d1e61e7f
CW		 1667 /* Is the chip hanging on a WAIT_FOR_EVENT?
1668 * If so we can simply poke the RB_WAIT bit
1669 * and break the hang. This should work on
1670 * all but the second generation chipsets.
1671 */
b4519513
CW		 1672 for_each_ring(ring, dev_priv, i)
1673 hung &= !kick_ring(ring);
d1e61e7f
CW		 1674 }
1675
b4519513 1676 return hung;
d1e61e7f
CW		 1677 }
1678
1679 return false;
1680}
1681
f65d9421
BG		 1682/**
1683 * This is called when the chip hasn't reported back with completed
1684 * batchbuffers in a long time. The first time this is called we simply record
1685 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1686 * again, we assume the chip is wedged and try to fix it.
1687 */
1688void i915_hangcheck_elapsed(unsigned long data)
1689{
1690 struct drm_device *dev = (struct drm_device *)data;
1691 drm_i915_private_t *dev_priv = dev->dev_private;
bd9854f9 1692 uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
b4519513
CW		 1693 struct intel_ring_buffer *ring;
1694 bool err = false, idle;
1695 int i;
893eead0 1696
3e0dc6b0
BW		 1697 if (!i915_enable_hangcheck)
1698 return;
1699
b4519513
CW		 1700 memset(acthd, 0, sizeof(acthd));
1701 idle = true;
1702 for_each_ring(ring, dev_priv, i) {
1703 idle &= i915_hangcheck_ring_idle(ring, &err);
1704 acthd[i] = intel_ring_get_active_head(ring);
1705 }
1706
893eead0 1707 /* If all work is done then ACTHD clearly hasn't advanced. */
b4519513 1708 if (idle) {
d1e61e7f
CW		 1709 if (err) {
1710 if (i915_hangcheck_hung(dev))
1711 return;
1712
893eead0 1713 goto repeat;
d1e61e7f
CW		 1714 }
1715
1716 dev_priv->hangcheck_count = 0;
893eead0
CW		 1717 return;
1718 }
b9201c14 1719
bd9854f9 1720 i915_get_extra_instdone(dev, instdone);
b4519513
CW		 1721
1722 if (memcmp(dev_priv->last_acthd, acthd, sizeof(acthd)) == 0 &&
bd9854f9
BW		 1723 dev_priv->last_instdone == instdone[0] &&
1724 dev_priv->last_instdone1 == instdone[1]) {
d1e61e7f 1725 if (i915_hangcheck_hung(dev))
cbb465e7 1726 return;
cbb465e7
CW		 1727 } else {
1728 dev_priv->hangcheck_count = 0;
1729
b4519513 1730 memcpy(dev_priv->last_acthd, acthd, sizeof(acthd));
bd9854f9
BW		 1731 dev_priv->last_instdone = instdone[0];
1732 dev_priv->last_instdone1 = instdone[1];
cbb465e7 1733 }
f65d9421 1734
893eead0 1735repeat:
f65d9421 1736 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1737 mod_timer(&dev_priv->hangcheck_timer,
1738 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1739}
1740
1da177e4
LT		 1741/* drm_dma.h hooks
1742*/
f71d4af4 1743static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1744{
1745 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1746
4697995b
JB		 1747 atomic_set(&dev_priv->irq_received, 0);
1748
036a4a7d 1749 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1750
036a4a7d
ZW		 1751 /* XXX hotplug from PCH */
1752
1753 I915_WRITE(DEIMR, 0xffffffff);
1754 I915_WRITE(DEIER, 0x0);
3143a2bf 1755 POSTING_READ(DEIER);
036a4a7d
ZW		 1756
1757 /* and GT */
1758 I915_WRITE(GTIMR, 0xffffffff);
1759 I915_WRITE(GTIER, 0x0);
3143a2bf 1760 POSTING_READ(GTIER);
c650156a
ZW		 1761
1762 /* south display irq */
1763 I915_WRITE(SDEIMR, 0xffffffff);
1764 I915_WRITE(SDEIER, 0x0);
3143a2bf 1765 POSTING_READ(SDEIER);
036a4a7d
ZW		 1766}
1767
7e231dbe
JB		 1768static void valleyview_irq_preinstall(struct drm_device *dev)
1769{
1770 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1771 int pipe;
1772
1773 atomic_set(&dev_priv->irq_received, 0);
1774
7e231dbe
JB		 1775 /* VLV magic */
1776 I915_WRITE(VLV_IMR, 0);
1777 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1778 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1779 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1780
7e231dbe
JB		 1781 /* and GT */
1782 I915_WRITE(GTIIR, I915_READ(GTIIR));
1783 I915_WRITE(GTIIR, I915_READ(GTIIR));
1784 I915_WRITE(GTIMR, 0xffffffff);
1785 I915_WRITE(GTIER, 0x0);
1786 POSTING_READ(GTIER);
1787
1788 I915_WRITE(DPINVGTT, 0xff);
1789
1790 I915_WRITE(PORT_HOTPLUG_EN, 0);
1791 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1792 for_each_pipe(pipe)
1793 I915_WRITE(PIPESTAT(pipe), 0xffff);
1794 I915_WRITE(VLV_IIR, 0xffffffff);
1795 I915_WRITE(VLV_IMR, 0xffffffff);
1796 I915_WRITE(VLV_IER, 0x0);
1797 POSTING_READ(VLV_IER);
1798}
1799
7fe0b973
KP		 1800/*
1801 * Enable digital hotplug on the PCH, and configure the DP short pulse
1802 * duration to 2ms (which is the minimum in the Display Port spec)
1803 *
1804 * This register is the same on all known PCH chips.
1805 */
1806
1807static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1808{
1809 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1810 u32 hotplug;
1811
1812 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1813 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1814 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1815 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1816 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1817 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1818}
1819
f71d4af4 1820static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1821{
1822 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1823 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1824 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1825 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1826 u32 render_irqs;
2d7b8366 1827 u32 hotplug_mask;
036a4a7d 1828
1ec14ad3 1829 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1830
1831 /* should always can generate irq */
1832 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1833 I915_WRITE(DEIMR, dev_priv->irq_mask);
1834 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1835 POSTING_READ(DEIER);
036a4a7d 1836
1ec14ad3 1837 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1838
1839 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1840 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1841
1ec14ad3
CW		 1842 if (IS_GEN6(dev))
1843 render_irqs =
1844 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1845 GEN6_BSD_USER_INTERRUPT |
1846 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1847 else
1848 render_irqs =
88f23b8f 1849 GT_USER_INTERRUPT |
c6df541c 1850 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1851 GT_BSD_USER_INTERRUPT;
1852 I915_WRITE(GTIER, render_irqs);
3143a2bf 1853 POSTING_READ(GTIER);
036a4a7d 1854
2d7b8366 1855 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1856 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1857 SDE_PORTB_HOTPLUG_CPT |
1858 SDE_PORTC_HOTPLUG_CPT |
1859 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1860 } else {
9035a97a
CW		 1861 hotplug_mask = (SDE_CRT_HOTPLUG |
1862 SDE_PORTB_HOTPLUG |
1863 SDE_PORTC_HOTPLUG |
1864 SDE_PORTD_HOTPLUG |
1865 SDE_AUX_MASK);
2d7b8366
YL		 1866 }
1867
1ec14ad3 1868 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1869
1870 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1871 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1872 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1873 POSTING_READ(SDEIER);
c650156a 1874
7fe0b973
KP		 1875 ironlake_enable_pch_hotplug(dev);
1876
f97108d1
JB		 1877 if (IS_IRONLAKE_M(dev)) {
1878 /* Clear & enable PCU event interrupts */
1879 I915_WRITE(DEIIR, DE_PCU_EVENT);
1880 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1881 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1882 }
1883
036a4a7d
ZW		 1884 return 0;
1885}
1886
f71d4af4 1887static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1888{
1889 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1890 /* enable kind of interrupts always enabled */
b615b57a
CW		 1891 u32 display_mask =
1892 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
1893 DE_PLANEC_FLIP_DONE_IVB |
1894 DE_PLANEB_FLIP_DONE_IVB |
1895 DE_PLANEA_FLIP_DONE_IVB;
b1f14ad0
JB		 1896 u32 render_irqs;
1897 u32 hotplug_mask;
1898
b1f14ad0
JB		 1899 dev_priv->irq_mask = ~display_mask;
1900
1901 /* should always can generate irq */
1902 I915_WRITE(DEIIR, I915_READ(DEIIR));
1903 I915_WRITE(DEIMR, dev_priv->irq_mask);
b615b57a
CW		 1904 I915_WRITE(DEIER,
1905 display_mask |
1906 DE_PIPEC_VBLANK_IVB |
1907 DE_PIPEB_VBLANK_IVB |
1908 DE_PIPEA_VBLANK_IVB);
b1f14ad0
JB		 1909 POSTING_READ(DEIER);
1910
15b9f80e 1911 dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1912
1913 I915_WRITE(GTIIR, I915_READ(GTIIR));
1914 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1915
e2a1e2f0 1916 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
15b9f80e 1917 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
b1f14ad0
JB		 1918 I915_WRITE(GTIER, render_irqs);
1919 POSTING_READ(GTIER);
1920
1921 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1922 SDE_PORTB_HOTPLUG_CPT |
1923 SDE_PORTC_HOTPLUG_CPT |
1924 SDE_PORTD_HOTPLUG_CPT);
1925 dev_priv->pch_irq_mask = ~hotplug_mask;
1926
1927 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1928 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1929 I915_WRITE(SDEIER, hotplug_mask);
1930 POSTING_READ(SDEIER);
1931
7fe0b973
KP		 1932 ironlake_enable_pch_hotplug(dev);
1933
b1f14ad0
JB		 1934 return 0;
1935}
1936
7e231dbe
JB		 1937static int valleyview_irq_postinstall(struct drm_device *dev)
1938{
1939 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7e231dbe
JB		 1940 u32 enable_mask;
1941 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
31acc7f5 1942 u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
7e231dbe
JB		 1943 u16 msid;
1944
1945 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
31acc7f5
JB		 1946 enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1947 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1948 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
7e231dbe
JB		 1949 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1950
31acc7f5
JB		 1951 /*
1952 *Leave vblank interrupts masked initially. enable/disable will
1953 * toggle them based on usage.
1954 */
1955 dev_priv->irq_mask = (~enable_mask) |
1956 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1957 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
7e231dbe 1958
7e231dbe
JB		 1959 dev_priv->pipestat[0] = 0;
1960 dev_priv->pipestat[1] = 0;
1961
7e231dbe
JB		 1962 /* Hack for broken MSIs on VLV */
1963 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1964 pci_read_config_word(dev->pdev, 0x98, &msid);
1965 msid &= 0xff; /* mask out delivery bits */
1966 msid |= (1<<14);
1967 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1968
1969 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1970 I915_WRITE(VLV_IER, enable_mask);
1971 I915_WRITE(VLV_IIR, 0xffffffff);
1972 I915_WRITE(PIPESTAT(0), 0xffff);
1973 I915_WRITE(PIPESTAT(1), 0xffff);
1974 POSTING_READ(VLV_IER);
1975
31acc7f5
JB		 1976 i915_enable_pipestat(dev_priv, 0, pipestat_enable);
1977 i915_enable_pipestat(dev_priv, 1, pipestat_enable);
1978
7e231dbe
JB		 1979 I915_WRITE(VLV_IIR, 0xffffffff);
1980 I915_WRITE(VLV_IIR, 0xffffffff);
1981
31acc7f5 1982 dev_priv->gt_irq_mask = ~0;
7e231dbe
JB		 1983
1984 I915_WRITE(GTIIR, I915_READ(GTIIR));
1985 I915_WRITE(GTIIR, I915_READ(GTIIR));
31acc7f5
JB		 1986 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1987 I915_WRITE(GTIER, GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1988 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
1989 GT_GEN6_BLT_USER_INTERRUPT |
1990 GT_GEN6_BSD_USER_INTERRUPT |
1991 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1992 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1993 GT_PIPE_NOTIFY |
1994 GT_RENDER_CS_ERROR_INTERRUPT |
1995 GT_SYNC_STATUS |
1996 GT_USER_INTERRUPT);
7e231dbe
JB		 1997 POSTING_READ(GTIER);
1998
1999 /* ack & enable invalid PTE error interrupts */
2000#if 0 /* FIXME: add support to irq handler for checking these bits */
2001 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2002 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2003#endif
2004
2005 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2006#if 0 /* FIXME: check register definitions; some have moved */
2007 /* Note HDMI and DP share bits */
2008 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2009 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2010 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2011 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2012 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2013 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2014 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2015 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2016 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2017 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2018 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2019 hotplug_en |= CRT_HOTPLUG_INT_EN;
2020 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2021 }
2022#endif
2023
2024 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2025
2026 return 0;
2027}
2028
7e231dbe
JB		 2029static void valleyview_irq_uninstall(struct drm_device *dev)
2030{
2031 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2032 int pipe;
2033
2034 if (!dev_priv)
2035 return;
2036
7e231dbe
JB		 2037 for_each_pipe(pipe)
2038 I915_WRITE(PIPESTAT(pipe), 0xffff);
2039
2040 I915_WRITE(HWSTAM, 0xffffffff);
2041 I915_WRITE(PORT_HOTPLUG_EN, 0);
2042 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2043 for_each_pipe(pipe)
2044 I915_WRITE(PIPESTAT(pipe), 0xffff);
2045 I915_WRITE(VLV_IIR, 0xffffffff);
2046 I915_WRITE(VLV_IMR, 0xffffffff);
2047 I915_WRITE(VLV_IER, 0x0);
2048 POSTING_READ(VLV_IER);
2049}
2050
f71d4af4 2051static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2052{
2053 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2054
2055 if (!dev_priv)
2056 return;
2057
036a4a7d
ZW		 2058 I915_WRITE(HWSTAM, 0xffffffff);
2059
2060 I915_WRITE(DEIMR, 0xffffffff);
2061 I915_WRITE(DEIER, 0x0);
2062 I915_WRITE(DEIIR, I915_READ(DEIIR));
2063
2064 I915_WRITE(GTIMR, 0xffffffff);
2065 I915_WRITE(GTIER, 0x0);
2066 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2067
2068 I915_WRITE(SDEIMR, 0xffffffff);
2069 I915_WRITE(SDEIER, 0x0);
2070 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2071}
2072
a266c7d5 2073static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2074{
2075 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2076 int pipe;
91e3738e 2077
a266c7d5 2078 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2079
9db4a9c7
JB		 2080 for_each_pipe(pipe)
2081 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2082 I915_WRITE16(IMR, 0xffff);
2083 I915_WRITE16(IER, 0x0);
2084 POSTING_READ16(IER);
c2798b19
CW		 2085}
2086
2087static int i8xx_irq_postinstall(struct drm_device *dev)
2088{
2089 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2090
c2798b19
CW		 2091 dev_priv->pipestat[0] = 0;
2092 dev_priv->pipestat[1] = 0;
2093
2094 I915_WRITE16(EMR,
2095 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2096
2097 /* Unmask the interrupts that we always want on. */
2098 dev_priv->irq_mask =
2099 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2100 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2101 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2102 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2103 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2104 I915_WRITE16(IMR, dev_priv->irq_mask);
2105
2106 I915_WRITE16(IER,
2107 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2108 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2109 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2110 I915_USER_INTERRUPT);
2111 POSTING_READ16(IER);
2112
2113 return 0;
2114}
2115
2116static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2117{
2118 struct drm_device *dev = (struct drm_device *) arg;
2119 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2120 u16 iir, new_iir;
2121 u32 pipe_stats[2];
2122 unsigned long irqflags;
2123 int irq_received;
2124 int pipe;
2125 u16 flip_mask =
2126 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2127 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2128
2129 atomic_inc(&dev_priv->irq_received);
2130
2131 iir = I915_READ16(IIR);
2132 if (iir == 0)
2133 return IRQ_NONE;
2134
2135 while (iir & ~flip_mask) {
2136 /* Can't rely on pipestat interrupt bit in iir as it might
2137 * have been cleared after the pipestat interrupt was received.
2138 * It doesn't set the bit in iir again, but it still produces
2139 * interrupts (for non-MSI).
2140 */
2141 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2142 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2143 i915_handle_error(dev, false);
2144
2145 for_each_pipe(pipe) {
2146 int reg = PIPESTAT(pipe);
2147 pipe_stats[pipe] = I915_READ(reg);
2148
2149 /*
2150 * Clear the PIPE*STAT regs before the IIR
2151 */
2152 if (pipe_stats[pipe] & 0x8000ffff) {
2153 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2154 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2155 pipe_name(pipe));
2156 I915_WRITE(reg, pipe_stats[pipe]);
2157 irq_received = 1;
2158 }
2159 }
2160 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2161
2162 I915_WRITE16(IIR, iir & ~flip_mask);
2163 new_iir = I915_READ16(IIR); /* Flush posted writes */
2164
d05c617e 2165 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2166
2167 if (iir & I915_USER_INTERRUPT)
2168 notify_ring(dev, &dev_priv->ring[RCS]);
2169
2170 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2171 drm_handle_vblank(dev, 0)) {
2172 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2173 intel_prepare_page_flip(dev, 0);
2174 intel_finish_page_flip(dev, 0);
2175 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2176 }
2177 }
2178
2179 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2180 drm_handle_vblank(dev, 1)) {
2181 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2182 intel_prepare_page_flip(dev, 1);
2183 intel_finish_page_flip(dev, 1);
2184 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2185 }
2186 }
2187
2188 iir = new_iir;
2189 }
2190
2191 return IRQ_HANDLED;
2192}
2193
2194static void i8xx_irq_uninstall(struct drm_device * dev)
2195{
2196 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2197 int pipe;
2198
c2798b19
CW		 2199 for_each_pipe(pipe) {
2200 /* Clear enable bits; then clear status bits */
2201 I915_WRITE(PIPESTAT(pipe), 0);
2202 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2203 }
2204 I915_WRITE16(IMR, 0xffff);
2205 I915_WRITE16(IER, 0x0);
2206 I915_WRITE16(IIR, I915_READ16(IIR));
2207}
2208
a266c7d5
CW		 2209static void i915_irq_preinstall(struct drm_device * dev)
2210{
2211 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2212 int pipe;
2213
2214 atomic_set(&dev_priv->irq_received, 0);
2215
2216 if (I915_HAS_HOTPLUG(dev)) {
2217 I915_WRITE(PORT_HOTPLUG_EN, 0);
2218 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2219 }
2220
00d98ebd 2221 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2222 for_each_pipe(pipe)
2223 I915_WRITE(PIPESTAT(pipe), 0);
2224 I915_WRITE(IMR, 0xffffffff);
2225 I915_WRITE(IER, 0x0);
2226 POSTING_READ(IER);
2227}
2228
2229static int i915_irq_postinstall(struct drm_device *dev)
2230{
2231 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2232 u32 enable_mask;
a266c7d5 2233
a266c7d5
CW		 2234 dev_priv->pipestat[0] = 0;
2235 dev_priv->pipestat[1] = 0;
2236
38bde180
CW		 2237 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2238
2239 /* Unmask the interrupts that we always want on. */
2240 dev_priv->irq_mask =
2241 ~(I915_ASLE_INTERRUPT |
2242 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2243 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2244 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2245 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2246 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2247
2248 enable_mask =
2249 I915_ASLE_INTERRUPT |
2250 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2251 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2252 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2253 I915_USER_INTERRUPT;
2254
a266c7d5
CW		 2255 if (I915_HAS_HOTPLUG(dev)) {
2256 /* Enable in IER... */
2257 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2258 /* and unmask in IMR */
2259 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2260 }
2261
a266c7d5
CW		 2262 I915_WRITE(IMR, dev_priv->irq_mask);
2263 I915_WRITE(IER, enable_mask);
2264 POSTING_READ(IER);
2265
2266 if (I915_HAS_HOTPLUG(dev)) {
2267 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2268
a266c7d5
CW		 2269 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2270 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2271 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2272 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2273 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2274 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e 2275 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
a266c7d5 2276 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
084b612e 2277 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
a266c7d5
CW		 2278 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2279 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2280 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2281 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2282 }
2283
2284 /* Ignore TV since it's buggy */
2285
2286 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2287 }
2288
2289 intel_opregion_enable_asle(dev);
2290
2291 return 0;
2292}
2293
2294static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2295{
2296 struct drm_device *dev = (struct drm_device *) arg;
2297 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2298 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2299 unsigned long irqflags;
38bde180
CW		 2300 u32 flip_mask =
2301 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2302 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2303 u32 flip[2] = {
2304 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2305 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2306 };
2307 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2308
2309 atomic_inc(&dev_priv->irq_received);
2310
2311 iir = I915_READ(IIR);
38bde180
CW		 2312 do {
2313 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2314 bool blc_event = false;
a266c7d5
CW		 2315
2316 /* Can't rely on pipestat interrupt bit in iir as it might
2317 * have been cleared after the pipestat interrupt was received.
2318 * It doesn't set the bit in iir again, but it still produces
2319 * interrupts (for non-MSI).
2320 */
2321 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2322 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2323 i915_handle_error(dev, false);
2324
2325 for_each_pipe(pipe) {
2326 int reg = PIPESTAT(pipe);
2327 pipe_stats[pipe] = I915_READ(reg);
2328
38bde180 2329 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2330 if (pipe_stats[pipe] & 0x8000ffff) {
2331 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2332 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2333 pipe_name(pipe));
2334 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2335 irq_received = true;
a266c7d5
CW		 2336 }
2337 }
2338 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2339
2340 if (!irq_received)
2341 break;
2342
a266c7d5
CW		 2343 /* Consume port. Then clear IIR or we'll miss events */
2344 if ((I915_HAS_HOTPLUG(dev)) &&
2345 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2346 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2347
2348 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2349 hotplug_status);
2350 if (hotplug_status & dev_priv->hotplug_supported_mask)
2351 queue_work(dev_priv->wq,
2352 &dev_priv->hotplug_work);
2353
2354 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2355 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2356 }
2357
38bde180 2358 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2359 new_iir = I915_READ(IIR); /* Flush posted writes */
2360
a266c7d5
CW		 2361 if (iir & I915_USER_INTERRUPT)
2362 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2363
a266c7d5 2364 for_each_pipe(pipe) {
38bde180
CW		 2365 int plane = pipe;
2366 if (IS_MOBILE(dev))
2367 plane = !plane;
8291ee90 2368 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2369 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2370 if (iir & flip[plane]) {
2371 intel_prepare_page_flip(dev, plane);
2372 intel_finish_page_flip(dev, pipe);
2373 flip_mask &= ~flip[plane];
2374 }
a266c7d5
CW		 2375 }
2376
2377 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2378 blc_event = true;
2379 }
2380
a266c7d5
CW		 2381 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2382 intel_opregion_asle_intr(dev);
2383
2384 /* With MSI, interrupts are only generated when iir
2385 * transitions from zero to nonzero. If another bit got
2386 * set while we were handling the existing iir bits, then
2387 * we would never get another interrupt.
2388 *
2389 * This is fine on non-MSI as well, as if we hit this path
2390 * we avoid exiting the interrupt handler only to generate
2391 * another one.
2392 *
2393 * Note that for MSI this could cause a stray interrupt report
2394 * if an interrupt landed in the time between writing IIR and
2395 * the posting read. This should be rare enough to never
2396 * trigger the 99% of 100,000 interrupts test for disabling
2397 * stray interrupts.
2398 */
38bde180 2399 ret = IRQ_HANDLED;
a266c7d5 2400 iir = new_iir;
38bde180 2401 } while (iir & ~flip_mask);
a266c7d5 2402
d05c617e 2403 i915_update_dri1_breadcrumb(dev);
8291ee90 2404
a266c7d5
CW		 2405 return ret;
2406}
2407
2408static void i915_irq_uninstall(struct drm_device * dev)
2409{
2410 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2411 int pipe;
2412
a266c7d5
CW		 2413 if (I915_HAS_HOTPLUG(dev)) {
2414 I915_WRITE(PORT_HOTPLUG_EN, 0);
2415 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2416 }
2417
00d98ebd 2418 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2419 for_each_pipe(pipe) {
2420 /* Clear enable bits; then clear status bits */
a266c7d5 2421 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2422 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2423 }
a266c7d5
CW		 2424 I915_WRITE(IMR, 0xffffffff);
2425 I915_WRITE(IER, 0x0);
2426
a266c7d5
CW		 2427 I915_WRITE(IIR, I915_READ(IIR));
2428}
2429
2430static void i965_irq_preinstall(struct drm_device * dev)
2431{
2432 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2433 int pipe;
2434
2435 atomic_set(&dev_priv->irq_received, 0);
2436
adca4730
CW		 2437 I915_WRITE(PORT_HOTPLUG_EN, 0);
2438 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2439
2440 I915_WRITE(HWSTAM, 0xeffe);
2441 for_each_pipe(pipe)
2442 I915_WRITE(PIPESTAT(pipe), 0);
2443 I915_WRITE(IMR, 0xffffffff);
2444 I915_WRITE(IER, 0x0);
2445 POSTING_READ(IER);
2446}
2447
2448static int i965_irq_postinstall(struct drm_device *dev)
2449{
2450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
adca4730 2451 u32 hotplug_en;
bbba0a97 2452 u32 enable_mask;
a266c7d5
CW		 2453 u32 error_mask;
2454
a266c7d5 2455 /* Unmask the interrupts that we always want on. */
bbba0a97 2456 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
adca4730 2457 I915_DISPLAY_PORT_INTERRUPT |
bbba0a97
CW		 2458 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2459 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2460 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2461 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2462 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2463
2464 enable_mask = ~dev_priv->irq_mask;
2465 enable_mask |= I915_USER_INTERRUPT;
2466
2467 if (IS_G4X(dev))
2468 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2469
2470 dev_priv->pipestat[0] = 0;
2471 dev_priv->pipestat[1] = 0;
2472
a266c7d5
CW		 2473 /*
2474 * Enable some error detection, note the instruction error mask
2475 * bit is reserved, so we leave it masked.
2476 */
2477 if (IS_G4X(dev)) {
2478 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2479 GM45_ERROR_MEM_PRIV |
2480 GM45_ERROR_CP_PRIV |
2481 I915_ERROR_MEMORY_REFRESH);
2482 } else {
2483 error_mask = ~(I915_ERROR_PAGE_TABLE |
2484 I915_ERROR_MEMORY_REFRESH);
2485 }
2486 I915_WRITE(EMR, error_mask);
2487
2488 I915_WRITE(IMR, dev_priv->irq_mask);
2489 I915_WRITE(IER, enable_mask);
2490 POSTING_READ(IER);
2491
adca4730
CW		 2492 /* Note HDMI and DP share hotplug bits */
2493 hotplug_en = 0;
2494 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2495 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2496 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2497 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2498 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2499 hotplug_en |= HDMID_HOTPLUG_INT_EN;
084b612e
CW		 2500 if (IS_G4X(dev)) {
2501 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2502 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2503 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2504 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2505 } else {
2506 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2507 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2508 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2509 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2510 }
adca4730
CW		 2511 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2512 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5 2513
adca4730
CW		 2514 /* Programming the CRT detection parameters tends
2515 to generate a spurious hotplug event about three
2516 seconds later. So just do it once.
2517 */
2518 if (IS_G4X(dev))
2519 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2520 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2521 }
a266c7d5 2522
adca4730 2523 /* Ignore TV since it's buggy */
a266c7d5 2524
adca4730 2525 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
a266c7d5
CW		 2526
2527 intel_opregion_enable_asle(dev);
2528
2529 return 0;
2530}
2531
2532static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2533{
2534 struct drm_device *dev = (struct drm_device *) arg;
2535 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2536 u32 iir, new_iir;
2537 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2538 unsigned long irqflags;
2539 int irq_received;
2540 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2541
2542 atomic_inc(&dev_priv->irq_received);
2543
2544 iir = I915_READ(IIR);
2545
a266c7d5 2546 for (;;) {
2c8ba29f
CW		 2547 bool blc_event = false;
2548
a266c7d5
CW		 2549 irq_received = iir != 0;
2550
2551 /* Can't rely on pipestat interrupt bit in iir as it might
2552 * have been cleared after the pipestat interrupt was received.
2553 * It doesn't set the bit in iir again, but it still produces
2554 * interrupts (for non-MSI).
2555 */
2556 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2557 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2558 i915_handle_error(dev, false);
2559
2560 for_each_pipe(pipe) {
2561 int reg = PIPESTAT(pipe);
2562 pipe_stats[pipe] = I915_READ(reg);
2563
2564 /*
2565 * Clear the PIPE*STAT regs before the IIR
2566 */
2567 if (pipe_stats[pipe] & 0x8000ffff) {
2568 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2569 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2570 pipe_name(pipe));
2571 I915_WRITE(reg, pipe_stats[pipe]);
2572 irq_received = 1;
2573 }
2574 }
2575 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2576
2577 if (!irq_received)
2578 break;
2579
2580 ret = IRQ_HANDLED;
2581
2582 /* Consume port. Then clear IIR or we'll miss events */
adca4730 2583 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
a266c7d5
CW		 2584 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2585
2586 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2587 hotplug_status);
2588 if (hotplug_status & dev_priv->hotplug_supported_mask)
2589 queue_work(dev_priv->wq,
2590 &dev_priv->hotplug_work);
2591
2592 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2593 I915_READ(PORT_HOTPLUG_STAT);
2594 }
2595
2596 I915_WRITE(IIR, iir);
2597 new_iir = I915_READ(IIR); /* Flush posted writes */
2598
a266c7d5
CW		 2599 if (iir & I915_USER_INTERRUPT)
2600 notify_ring(dev, &dev_priv->ring[RCS]);
2601 if (iir & I915_BSD_USER_INTERRUPT)
2602 notify_ring(dev, &dev_priv->ring[VCS]);
2603
4f7d1e79 2604 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2605 intel_prepare_page_flip(dev, 0);
a266c7d5 2606
4f7d1e79 2607 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2608 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2609
2610 for_each_pipe(pipe) {
2c8ba29f 2611 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2612 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2613 i915_pageflip_stall_check(dev, pipe);
2614 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2615 }
2616
2617 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2618 blc_event = true;
2619 }
2620
2621
2622 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2623 intel_opregion_asle_intr(dev);
2624
2625 /* With MSI, interrupts are only generated when iir
2626 * transitions from zero to nonzero. If another bit got
2627 * set while we were handling the existing iir bits, then
2628 * we would never get another interrupt.
2629 *
2630 * This is fine on non-MSI as well, as if we hit this path
2631 * we avoid exiting the interrupt handler only to generate
2632 * another one.
2633 *
2634 * Note that for MSI this could cause a stray interrupt report
2635 * if an interrupt landed in the time between writing IIR and
2636 * the posting read. This should be rare enough to never
2637 * trigger the 99% of 100,000 interrupts test for disabling
2638 * stray interrupts.
2639 */
2640 iir = new_iir;
2641 }
2642
d05c617e 2643 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2644
a266c7d5
CW		 2645 return ret;
2646}
2647
2648static void i965_irq_uninstall(struct drm_device * dev)
2649{
2650 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2651 int pipe;
2652
2653 if (!dev_priv)
2654 return;
2655
adca4730
CW		 2656 I915_WRITE(PORT_HOTPLUG_EN, 0);
2657 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
a266c7d5
CW		 2658
2659 I915_WRITE(HWSTAM, 0xffffffff);
2660 for_each_pipe(pipe)
2661 I915_WRITE(PIPESTAT(pipe), 0);
2662 I915_WRITE(IMR, 0xffffffff);
2663 I915_WRITE(IER, 0x0);
2664
2665 for_each_pipe(pipe)
2666 I915_WRITE(PIPESTAT(pipe),
2667 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2668 I915_WRITE(IIR, I915_READ(IIR));
2669}
2670
f71d4af4
JB		 2671void intel_irq_init(struct drm_device *dev)
2672{
8b2e326d
CW		 2673 struct drm_i915_private *dev_priv = dev->dev_private;
2674
2675 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2676 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
c6a828d3 2677 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
98fd81cd 2678 INIT_WORK(&dev_priv->parity_error_work, ivybridge_parity_work);
8b2e326d 2679
f71d4af4
JB		 2680 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2681 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7d4e146f 2682 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
f71d4af4
JB		 2683 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2684 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2685 }
2686
c3613de9
KP		 2687 if (drm_core_check_feature(dev, DRIVER_MODESET))
2688 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2689 else
2690 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2691 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2692
7e231dbe
JB		 2693 if (IS_VALLEYVIEW(dev)) {
2694 dev->driver->irq_handler = valleyview_irq_handler;
2695 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2696 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2697 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2698 dev->driver->enable_vblank = valleyview_enable_vblank;
2699 dev->driver->disable_vblank = valleyview_disable_vblank;
2700 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2701 /* Share pre & uninstall handlers with ILK/SNB */
2702 dev->driver->irq_handler = ivybridge_irq_handler;
2703 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2704 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2705 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2706 dev->driver->enable_vblank = ivybridge_enable_vblank;
2707 dev->driver->disable_vblank = ivybridge_disable_vblank;
7d4e146f
ED		 2708 } else if (IS_HASWELL(dev)) {
2709 /* Share interrupts handling with IVB */
2710 dev->driver->irq_handler = ivybridge_irq_handler;
2711 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2712 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2713 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2714 dev->driver->enable_vblank = ivybridge_enable_vblank;
2715 dev->driver->disable_vblank = ivybridge_disable_vblank;
f71d4af4
JB		 2716 } else if (HAS_PCH_SPLIT(dev)) {
2717 dev->driver->irq_handler = ironlake_irq_handler;
2718 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2719 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2720 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2721 dev->driver->enable_vblank = ironlake_enable_vblank;
2722 dev->driver->disable_vblank = ironlake_disable_vblank;
2723 } else {
c2798b19
CW		 2724 if (INTEL_INFO(dev)->gen == 2) {
2725 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2726 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2727 dev->driver->irq_handler = i8xx_irq_handler;
2728 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2729 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2730 /* IIR "flip pending" means done if this bit is set */
2731 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2732
a266c7d5
CW		 2733 dev->driver->irq_preinstall = i915_irq_preinstall;
2734 dev->driver->irq_postinstall = i915_irq_postinstall;
2735 dev->driver->irq_uninstall = i915_irq_uninstall;
2736 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2737 } else {
a266c7d5
CW		 2738 dev->driver->irq_preinstall = i965_irq_preinstall;
2739 dev->driver->irq_postinstall = i965_irq_postinstall;
2740 dev->driver->irq_uninstall = i965_irq_uninstall;
2741 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2742 }
f71d4af4
JB		 2743 dev->driver->enable_vblank = i915_enable_vblank;
2744 dev->driver->disable_vblank = i915_disable_vblank;
2745 }
2746}
Linux kernel - Deliverables
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