Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | void |
f2b115e6 | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
69 | { |
70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
71 | dev_priv->gt_irq_mask_reg &= ~mask; | |
72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
73 | (void) I915_READ(GTIMR); | |
74 | } | |
75 | } | |
76 | ||
62fdfeaf | 77 | void |
f2b115e6 | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
79 | { |
80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
81 | dev_priv->gt_irq_mask_reg |= mask; | |
82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
83 | (void) I915_READ(GTIMR); | |
84 | } | |
85 | } | |
86 | ||
87 | /* For display hotplug interrupt */ | |
88 | void | |
f2b115e6 | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
90 | { |
91 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
92 | dev_priv->irq_mask_reg &= ~mask; | |
93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
94 | (void) I915_READ(DEIMR); | |
95 | } | |
96 | } | |
97 | ||
98 | static inline void | |
f2b115e6 | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
100 | { |
101 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
102 | dev_priv->irq_mask_reg |= mask; | |
103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
104 | (void) I915_READ(DEIMR); | |
105 | } | |
106 | } | |
107 | ||
8ee1c3db | 108 | void |
ed4cb414 EA |
109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
110 | { | |
111 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
112 | dev_priv->irq_mask_reg &= ~mask; | |
113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
114 | (void) I915_READ(IMR); | |
115 | } | |
116 | } | |
117 | ||
62fdfeaf | 118 | void |
ed4cb414 EA |
119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
120 | { | |
121 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
122 | dev_priv->irq_mask_reg |= mask; | |
123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
124 | (void) I915_READ(IMR); | |
125 | } | |
126 | } | |
127 | ||
7c463586 KP |
128 | static inline u32 |
129 | i915_pipestat(int pipe) | |
130 | { | |
131 | if (pipe == 0) | |
132 | return PIPEASTAT; | |
133 | if (pipe == 1) | |
134 | return PIPEBSTAT; | |
9c84ba4e | 135 | BUG(); |
7c463586 KP |
136 | } |
137 | ||
138 | void | |
139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
140 | { | |
141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
142 | u32 reg = i915_pipestat(pipe); | |
143 | ||
144 | dev_priv->pipestat[pipe] |= mask; | |
145 | /* Enable the interrupt, clear any pending status */ | |
146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
147 | (void) I915_READ(reg); | |
148 | } | |
149 | } | |
150 | ||
151 | void | |
152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
153 | { | |
154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
155 | u32 reg = i915_pipestat(pipe); | |
156 | ||
157 | dev_priv->pipestat[pipe] &= ~mask; | |
158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
159 | (void) I915_READ(reg); | |
160 | } | |
161 | } | |
162 | ||
01c66889 ZY |
163 | /** |
164 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
165 | */ | |
166 | void intel_enable_asle (struct drm_device *dev) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | ||
c619eed4 | 170 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 172 | else { |
01c66889 | 173 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca ZY |
175 | if (IS_I965G(dev)) |
176 | i915_enable_pipestat(dev_priv, 0, | |
d874bcff | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 178 | } |
01c66889 ZY |
179 | } |
180 | ||
0a3e67a4 JB |
181 | /** |
182 | * i915_pipe_enabled - check if a pipe is enabled | |
183 | * @dev: DRM device | |
184 | * @pipe: pipe to check | |
185 | * | |
186 | * Reading certain registers when the pipe is disabled can hang the chip. | |
187 | * Use this routine to make sure the PLL is running and the pipe is active | |
188 | * before reading such registers if unsure. | |
189 | */ | |
190 | static int | |
191 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
192 | { | |
193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
194 | unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF; | |
195 | ||
196 | if (I915_READ(pipeconf) & PIPEACONF_ENABLE) | |
197 | return 1; | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
42f52ef8 KP |
202 | /* Called from drm generic code, passed a 'crtc', which |
203 | * we use as a pipe index | |
204 | */ | |
205 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
206 | { |
207 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
208 | unsigned long high_frame; | |
209 | unsigned long low_frame; | |
210 | u32 high1, high2, low, count; | |
0a3e67a4 | 211 | |
0a3e67a4 JB |
212 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
213 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
214 | ||
215 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
216 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
217 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
218 | return 0; |
219 | } | |
220 | ||
221 | /* | |
222 | * High & low register fields aren't synchronized, so make sure | |
223 | * we get a low value that's stable across two reads of the high | |
224 | * register. | |
225 | */ | |
226 | do { | |
227 | high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
228 | PIPE_FRAME_HIGH_SHIFT); | |
229 | low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> | |
230 | PIPE_FRAME_LOW_SHIFT); | |
231 | high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> | |
232 | PIPE_FRAME_HIGH_SHIFT); | |
233 | } while (high1 != high2); | |
234 | ||
235 | count = (high1 << 8) | low; | |
236 | ||
237 | return count; | |
238 | } | |
239 | ||
9880b7a5 JB |
240 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
241 | { | |
242 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
243 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
244 | ||
245 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
246 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
247 | "pipe %d\n", pipe); | |
9880b7a5 JB |
248 | return 0; |
249 | } | |
250 | ||
251 | return I915_READ(reg); | |
252 | } | |
253 | ||
5ca58282 JB |
254 | /* |
255 | * Handle hotplug events outside the interrupt handler proper. | |
256 | */ | |
257 | static void i915_hotplug_work_func(struct work_struct *work) | |
258 | { | |
259 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
260 | hotplug_work); | |
261 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 262 | struct drm_mode_config *mode_config = &dev->mode_config; |
5bf4c9c4 | 263 | struct drm_encoder *encoder; |
c31c4ba3 | 264 | |
5bf4c9c4 ZW |
265 | if (mode_config->num_encoder) { |
266 | list_for_each_entry(encoder, &mode_config->encoder_list, head) { | |
267 | struct intel_encoder *intel_encoder = enc_to_intel_encoder(encoder); | |
c31c4ba3 | 268 | |
21d40d37 EA |
269 | if (intel_encoder->hot_plug) |
270 | (*intel_encoder->hot_plug) (intel_encoder); | |
c31c4ba3 KP |
271 | } |
272 | } | |
5ca58282 | 273 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 274 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
275 | } |
276 | ||
f97108d1 JB |
277 | static void i915_handle_rps_change(struct drm_device *dev) |
278 | { | |
279 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 280 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
281 | u8 new_delay = dev_priv->cur_delay; |
282 | ||
7648fa99 | 283 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
284 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
285 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
286 | max_avg = I915_READ(RCBMAXAVG); |
287 | min_avg = I915_READ(RCBMINAVG); | |
288 | ||
289 | /* Handle RCS change request from hw */ | |
b5b72e89 | 290 | if (busy_up > max_avg) { |
f97108d1 JB |
291 | if (dev_priv->cur_delay != dev_priv->max_delay) |
292 | new_delay = dev_priv->cur_delay - 1; | |
293 | if (new_delay < dev_priv->max_delay) | |
294 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 295 | } else if (busy_down < min_avg) { |
f97108d1 JB |
296 | if (dev_priv->cur_delay != dev_priv->min_delay) |
297 | new_delay = dev_priv->cur_delay + 1; | |
298 | if (new_delay > dev_priv->min_delay) | |
299 | new_delay = dev_priv->min_delay; | |
300 | } | |
301 | ||
7648fa99 JB |
302 | if (ironlake_set_drps(dev, new_delay)) |
303 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
304 | |
305 | return; | |
306 | } | |
307 | ||
f2b115e6 | 308 | irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
309 | { |
310 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
311 | int ret = IRQ_NONE; | |
3ff99164 | 312 | u32 de_iir, gt_iir, de_ier, pch_iir; |
036a4a7d | 313 | struct drm_i915_master_private *master_priv; |
852835f3 | 314 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
036a4a7d | 315 | |
2d109a84 ZN |
316 | /* disable master interrupt before clearing iir */ |
317 | de_ier = I915_READ(DEIER); | |
318 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
319 | (void)I915_READ(DEIER); | |
320 | ||
036a4a7d ZW |
321 | de_iir = I915_READ(DEIIR); |
322 | gt_iir = I915_READ(GTIIR); | |
c650156a | 323 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 324 | |
c7c85101 ZN |
325 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
326 | goto done; | |
036a4a7d | 327 | |
c7c85101 | 328 | ret = IRQ_HANDLED; |
036a4a7d | 329 | |
c7c85101 ZN |
330 | if (dev->primary->master) { |
331 | master_priv = dev->primary->master->driver_priv; | |
332 | if (master_priv->sarea_priv) | |
333 | master_priv->sarea_priv->last_dispatch = | |
334 | READ_BREADCRUMB(dev_priv); | |
335 | } | |
036a4a7d | 336 | |
e552eb70 | 337 | if (gt_iir & GT_PIPE_NOTIFY) { |
852835f3 ZN |
338 | u32 seqno = render_ring->get_gem_seqno(dev, render_ring); |
339 | render_ring->irq_gem_seqno = seqno; | |
c7c85101 | 340 | trace_i915_gem_request_complete(dev, seqno); |
852835f3 | 341 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); |
c7c85101 ZN |
342 | dev_priv->hangcheck_count = 0; |
343 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
344 | } | |
d1b851fc ZN |
345 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
346 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | |
347 | ||
01c66889 | 348 | |
c7c85101 | 349 | if (de_iir & DE_GSE) |
3b617967 | 350 | intel_opregion_gse_intr(dev); |
c650156a | 351 | |
f072d2e7 | 352 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 353 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 354 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 355 | } |
013d5aa2 | 356 | |
f072d2e7 | 357 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 358 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 359 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 360 | } |
013d5aa2 | 361 | |
f072d2e7 | 362 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
363 | drm_handle_vblank(dev, 0); |
364 | ||
f072d2e7 | 365 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
366 | drm_handle_vblank(dev, 1); |
367 | ||
c7c85101 ZN |
368 | /* check event from PCH */ |
369 | if ((de_iir & DE_PCH_EVENT) && | |
370 | (pch_iir & SDE_HOTPLUG_MASK)) { | |
371 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
036a4a7d ZW |
372 | } |
373 | ||
f97108d1 | 374 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 375 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
376 | i915_handle_rps_change(dev); |
377 | } | |
378 | ||
c7c85101 ZN |
379 | /* should clear PCH hotplug event before clear CPU irq */ |
380 | I915_WRITE(SDEIIR, pch_iir); | |
381 | I915_WRITE(GTIIR, gt_iir); | |
382 | I915_WRITE(DEIIR, de_iir); | |
383 | ||
384 | done: | |
2d109a84 ZN |
385 | I915_WRITE(DEIER, de_ier); |
386 | (void)I915_READ(DEIER); | |
387 | ||
036a4a7d ZW |
388 | return ret; |
389 | } | |
390 | ||
8a905236 JB |
391 | /** |
392 | * i915_error_work_func - do process context error handling work | |
393 | * @work: work struct | |
394 | * | |
395 | * Fire an error uevent so userspace can see that a hang or error | |
396 | * was detected. | |
397 | */ | |
398 | static void i915_error_work_func(struct work_struct *work) | |
399 | { | |
400 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
401 | error_work); | |
402 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
403 | char *error_event[] = { "ERROR=1", NULL }; |
404 | char *reset_event[] = { "RESET=1", NULL }; | |
405 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 406 | |
44d98a61 | 407 | DRM_DEBUG_DRIVER("generating error event\n"); |
f316a42c BG |
408 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
409 | ||
ba1234d1 | 410 | if (atomic_read(&dev_priv->mm.wedged)) { |
f316a42c | 411 | if (IS_I965G(dev)) { |
44d98a61 | 412 | DRM_DEBUG_DRIVER("resetting chip\n"); |
f316a42c BG |
413 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); |
414 | if (!i965_reset(dev, GDRST_RENDER)) { | |
ba1234d1 | 415 | atomic_set(&dev_priv->mm.wedged, 0); |
f316a42c BG |
416 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); |
417 | } | |
418 | } else { | |
44d98a61 | 419 | DRM_DEBUG_DRIVER("reboot required\n"); |
f316a42c BG |
420 | } |
421 | } | |
8a905236 JB |
422 | } |
423 | ||
3bd3c932 | 424 | #ifdef CONFIG_DEBUG_FS |
9df30794 CW |
425 | static struct drm_i915_error_object * |
426 | i915_error_object_create(struct drm_device *dev, | |
427 | struct drm_gem_object *src) | |
428 | { | |
e56660dd | 429 | drm_i915_private_t *dev_priv = dev->dev_private; |
9df30794 CW |
430 | struct drm_i915_error_object *dst; |
431 | struct drm_i915_gem_object *src_priv; | |
432 | int page, page_count; | |
e56660dd | 433 | u32 reloc_offset; |
9df30794 CW |
434 | |
435 | if (src == NULL) | |
436 | return NULL; | |
437 | ||
23010e43 | 438 | src_priv = to_intel_bo(src); |
9df30794 CW |
439 | if (src_priv->pages == NULL) |
440 | return NULL; | |
441 | ||
442 | page_count = src->size / PAGE_SIZE; | |
443 | ||
444 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
445 | if (dst == NULL) | |
446 | return NULL; | |
447 | ||
e56660dd | 448 | reloc_offset = src_priv->gtt_offset; |
9df30794 | 449 | for (page = 0; page < page_count; page++) { |
788885ae | 450 | unsigned long flags; |
e56660dd CW |
451 | void __iomem *s; |
452 | void *d; | |
788885ae | 453 | |
e56660dd | 454 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
455 | if (d == NULL) |
456 | goto unwind; | |
e56660dd | 457 | |
788885ae | 458 | local_irq_save(flags); |
e56660dd CW |
459 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
460 | reloc_offset, | |
461 | KM_IRQ0); | |
462 | memcpy_fromio(d, s, PAGE_SIZE); | |
463 | io_mapping_unmap_atomic(s, KM_IRQ0); | |
788885ae | 464 | local_irq_restore(flags); |
e56660dd | 465 | |
9df30794 | 466 | dst->pages[page] = d; |
e56660dd CW |
467 | |
468 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
469 | } |
470 | dst->page_count = page_count; | |
471 | dst->gtt_offset = src_priv->gtt_offset; | |
472 | ||
473 | return dst; | |
474 | ||
475 | unwind: | |
476 | while (page--) | |
477 | kfree(dst->pages[page]); | |
478 | kfree(dst); | |
479 | return NULL; | |
480 | } | |
481 | ||
482 | static void | |
483 | i915_error_object_free(struct drm_i915_error_object *obj) | |
484 | { | |
485 | int page; | |
486 | ||
487 | if (obj == NULL) | |
488 | return; | |
489 | ||
490 | for (page = 0; page < obj->page_count; page++) | |
491 | kfree(obj->pages[page]); | |
492 | ||
493 | kfree(obj); | |
494 | } | |
495 | ||
496 | static void | |
497 | i915_error_state_free(struct drm_device *dev, | |
498 | struct drm_i915_error_state *error) | |
499 | { | |
500 | i915_error_object_free(error->batchbuffer[0]); | |
501 | i915_error_object_free(error->batchbuffer[1]); | |
502 | i915_error_object_free(error->ringbuffer); | |
503 | kfree(error->active_bo); | |
6ef3d427 | 504 | kfree(error->overlay); |
9df30794 CW |
505 | kfree(error); |
506 | } | |
507 | ||
508 | static u32 | |
509 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) | |
510 | { | |
511 | u32 cmd; | |
512 | ||
513 | if (IS_I830(dev) || IS_845G(dev)) | |
514 | cmd = MI_BATCH_BUFFER; | |
515 | else if (IS_I965G(dev)) | |
516 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | | |
517 | MI_BATCH_NON_SECURE_I965); | |
518 | else | |
519 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); | |
520 | ||
521 | return ring[0] == cmd ? ring[1] : 0; | |
522 | } | |
523 | ||
524 | static u32 | |
525 | i915_ringbuffer_last_batch(struct drm_device *dev) | |
526 | { | |
527 | struct drm_i915_private *dev_priv = dev->dev_private; | |
528 | u32 head, bbaddr; | |
529 | u32 *ring; | |
530 | ||
531 | /* Locate the current position in the ringbuffer and walk back | |
532 | * to find the most recently dispatched batch buffer. | |
533 | */ | |
534 | bbaddr = 0; | |
535 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
d3301d86 | 536 | ring = (u32 *)(dev_priv->render_ring.virtual_start + head); |
9df30794 | 537 | |
d3301d86 | 538 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
9df30794 CW |
539 | bbaddr = i915_get_bbaddr(dev, ring); |
540 | if (bbaddr) | |
541 | break; | |
542 | } | |
543 | ||
544 | if (bbaddr == 0) { | |
8187a2b7 ZN |
545 | ring = (u32 *)(dev_priv->render_ring.virtual_start |
546 | + dev_priv->render_ring.size); | |
d3301d86 | 547 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
9df30794 CW |
548 | bbaddr = i915_get_bbaddr(dev, ring); |
549 | if (bbaddr) | |
550 | break; | |
551 | } | |
552 | } | |
553 | ||
554 | return bbaddr; | |
555 | } | |
556 | ||
8a905236 JB |
557 | /** |
558 | * i915_capture_error_state - capture an error record for later analysis | |
559 | * @dev: drm device | |
560 | * | |
561 | * Should be called when an error is detected (either a hang or an error | |
562 | * interrupt) to capture error state from the time of the error. Fills | |
563 | * out a structure which becomes available in debugfs for user level tools | |
564 | * to pick up. | |
565 | */ | |
63eeaf38 JB |
566 | static void i915_capture_error_state(struct drm_device *dev) |
567 | { | |
568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9df30794 | 569 | struct drm_i915_gem_object *obj_priv; |
63eeaf38 | 570 | struct drm_i915_error_state *error; |
9df30794 | 571 | struct drm_gem_object *batchbuffer[2]; |
63eeaf38 | 572 | unsigned long flags; |
9df30794 CW |
573 | u32 bbaddr; |
574 | int count; | |
63eeaf38 JB |
575 | |
576 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
577 | error = dev_priv->first_error; |
578 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
579 | if (error) | |
580 | return; | |
63eeaf38 JB |
581 | |
582 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
583 | if (!error) { | |
9df30794 CW |
584 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
585 | return; | |
63eeaf38 JB |
586 | } |
587 | ||
852835f3 | 588 | error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring); |
63eeaf38 JB |
589 | error->eir = I915_READ(EIR); |
590 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
591 | error->pipeastat = I915_READ(PIPEASTAT); | |
592 | error->pipebstat = I915_READ(PIPEBSTAT); | |
593 | error->instpm = I915_READ(INSTPM); | |
594 | if (!IS_I965G(dev)) { | |
595 | error->ipeir = I915_READ(IPEIR); | |
596 | error->ipehr = I915_READ(IPEHR); | |
597 | error->instdone = I915_READ(INSTDONE); | |
598 | error->acthd = I915_READ(ACTHD); | |
9df30794 | 599 | error->bbaddr = 0; |
63eeaf38 JB |
600 | } else { |
601 | error->ipeir = I915_READ(IPEIR_I965); | |
602 | error->ipehr = I915_READ(IPEHR_I965); | |
603 | error->instdone = I915_READ(INSTDONE_I965); | |
604 | error->instps = I915_READ(INSTPS); | |
605 | error->instdone1 = I915_READ(INSTDONE1); | |
606 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 607 | error->bbaddr = I915_READ64(BB_ADDR); |
63eeaf38 JB |
608 | } |
609 | ||
9df30794 | 610 | bbaddr = i915_ringbuffer_last_batch(dev); |
8a905236 | 611 | |
9df30794 CW |
612 | /* Grab the current batchbuffer, most likely to have crashed. */ |
613 | batchbuffer[0] = NULL; | |
614 | batchbuffer[1] = NULL; | |
615 | count = 0; | |
852835f3 ZN |
616 | list_for_each_entry(obj_priv, |
617 | &dev_priv->render_ring.active_list, list) { | |
618 | ||
a8089e84 | 619 | struct drm_gem_object *obj = &obj_priv->base; |
63eeaf38 | 620 | |
9df30794 CW |
621 | if (batchbuffer[0] == NULL && |
622 | bbaddr >= obj_priv->gtt_offset && | |
623 | bbaddr < obj_priv->gtt_offset + obj->size) | |
624 | batchbuffer[0] = obj; | |
625 | ||
626 | if (batchbuffer[1] == NULL && | |
627 | error->acthd >= obj_priv->gtt_offset && | |
e56660dd | 628 | error->acthd < obj_priv->gtt_offset + obj->size) |
9df30794 CW |
629 | batchbuffer[1] = obj; |
630 | ||
631 | count++; | |
632 | } | |
e56660dd CW |
633 | /* Scan the other lists for completeness for those bizarre errors. */ |
634 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
635 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { | |
636 | struct drm_gem_object *obj = &obj_priv->base; | |
637 | ||
638 | if (batchbuffer[0] == NULL && | |
639 | bbaddr >= obj_priv->gtt_offset && | |
640 | bbaddr < obj_priv->gtt_offset + obj->size) | |
641 | batchbuffer[0] = obj; | |
642 | ||
643 | if (batchbuffer[1] == NULL && | |
644 | error->acthd >= obj_priv->gtt_offset && | |
645 | error->acthd < obj_priv->gtt_offset + obj->size) | |
646 | batchbuffer[1] = obj; | |
647 | ||
648 | if (batchbuffer[0] && batchbuffer[1]) | |
649 | break; | |
650 | } | |
651 | } | |
652 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
653 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { | |
654 | struct drm_gem_object *obj = &obj_priv->base; | |
655 | ||
656 | if (batchbuffer[0] == NULL && | |
657 | bbaddr >= obj_priv->gtt_offset && | |
658 | bbaddr < obj_priv->gtt_offset + obj->size) | |
659 | batchbuffer[0] = obj; | |
660 | ||
661 | if (batchbuffer[1] == NULL && | |
662 | error->acthd >= obj_priv->gtt_offset && | |
663 | error->acthd < obj_priv->gtt_offset + obj->size) | |
664 | batchbuffer[1] = obj; | |
665 | ||
666 | if (batchbuffer[0] && batchbuffer[1]) | |
667 | break; | |
668 | } | |
669 | } | |
9df30794 CW |
670 | |
671 | /* We need to copy these to an anonymous buffer as the simplest | |
672 | * method to avoid being overwritten by userpace. | |
673 | */ | |
674 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); | |
e56660dd CW |
675 | if (batchbuffer[1] != batchbuffer[0]) |
676 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); | |
677 | else | |
678 | error->batchbuffer[1] = NULL; | |
9df30794 CW |
679 | |
680 | /* Record the ringbuffer */ | |
8187a2b7 ZN |
681 | error->ringbuffer = i915_error_object_create(dev, |
682 | dev_priv->render_ring.gem_object); | |
9df30794 CW |
683 | |
684 | /* Record buffers on the active list. */ | |
685 | error->active_bo = NULL; | |
686 | error->active_bo_count = 0; | |
687 | ||
688 | if (count) | |
689 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, | |
690 | GFP_ATOMIC); | |
691 | ||
692 | if (error->active_bo) { | |
693 | int i = 0; | |
852835f3 ZN |
694 | list_for_each_entry(obj_priv, |
695 | &dev_priv->render_ring.active_list, list) { | |
a8089e84 | 696 | struct drm_gem_object *obj = &obj_priv->base; |
9df30794 CW |
697 | |
698 | error->active_bo[i].size = obj->size; | |
699 | error->active_bo[i].name = obj->name; | |
700 | error->active_bo[i].seqno = obj_priv->last_rendering_seqno; | |
701 | error->active_bo[i].gtt_offset = obj_priv->gtt_offset; | |
702 | error->active_bo[i].read_domains = obj->read_domains; | |
703 | error->active_bo[i].write_domain = obj->write_domain; | |
704 | error->active_bo[i].fence_reg = obj_priv->fence_reg; | |
705 | error->active_bo[i].pinned = 0; | |
706 | if (obj_priv->pin_count > 0) | |
707 | error->active_bo[i].pinned = 1; | |
708 | if (obj_priv->user_pin_count > 0) | |
709 | error->active_bo[i].pinned = -1; | |
710 | error->active_bo[i].tiling = obj_priv->tiling_mode; | |
711 | error->active_bo[i].dirty = obj_priv->dirty; | |
712 | error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED; | |
713 | ||
714 | if (++i == count) | |
715 | break; | |
716 | } | |
717 | error->active_bo_count = i; | |
718 | } | |
719 | ||
720 | do_gettimeofday(&error->time); | |
721 | ||
6ef3d427 CW |
722 | error->overlay = intel_overlay_capture_error_state(dev); |
723 | ||
9df30794 CW |
724 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
725 | if (dev_priv->first_error == NULL) { | |
726 | dev_priv->first_error = error; | |
727 | error = NULL; | |
728 | } | |
63eeaf38 | 729 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
730 | |
731 | if (error) | |
732 | i915_error_state_free(dev, error); | |
733 | } | |
734 | ||
735 | void i915_destroy_error_state(struct drm_device *dev) | |
736 | { | |
737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
738 | struct drm_i915_error_state *error; | |
739 | ||
740 | spin_lock(&dev_priv->error_lock); | |
741 | error = dev_priv->first_error; | |
742 | dev_priv->first_error = NULL; | |
743 | spin_unlock(&dev_priv->error_lock); | |
744 | ||
745 | if (error) | |
746 | i915_error_state_free(dev, error); | |
63eeaf38 | 747 | } |
3bd3c932 CW |
748 | #else |
749 | #define i915_capture_error_state(x) | |
750 | #endif | |
63eeaf38 | 751 | |
35aed2e6 | 752 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
753 | { |
754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
755 | u32 eir = I915_READ(EIR); | |
8a905236 | 756 | |
35aed2e6 CW |
757 | if (!eir) |
758 | return; | |
8a905236 JB |
759 | |
760 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
761 | eir); | |
762 | ||
763 | if (IS_G4X(dev)) { | |
764 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
765 | u32 ipeir = I915_READ(IPEIR_I965); | |
766 | ||
767 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
768 | I915_READ(IPEIR_I965)); | |
769 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
770 | I915_READ(IPEHR_I965)); | |
771 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
772 | I915_READ(INSTDONE_I965)); | |
773 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
774 | I915_READ(INSTPS)); | |
775 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
776 | I915_READ(INSTDONE1)); | |
777 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
778 | I915_READ(ACTHD_I965)); | |
779 | I915_WRITE(IPEIR_I965, ipeir); | |
780 | (void)I915_READ(IPEIR_I965); | |
781 | } | |
782 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
783 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
784 | printk(KERN_ERR "page table error\n"); | |
785 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
786 | pgtbl_err); | |
787 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
788 | (void)I915_READ(PGTBL_ER); | |
789 | } | |
790 | } | |
791 | ||
792 | if (IS_I9XX(dev)) { | |
793 | if (eir & I915_ERROR_PAGE_TABLE) { | |
794 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
795 | printk(KERN_ERR "page table error\n"); | |
796 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
797 | pgtbl_err); | |
798 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
799 | (void)I915_READ(PGTBL_ER); | |
800 | } | |
801 | } | |
802 | ||
803 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
35aed2e6 CW |
804 | u32 pipea_stats = I915_READ(PIPEASTAT); |
805 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
806 | ||
8a905236 JB |
807 | printk(KERN_ERR "memory refresh error\n"); |
808 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
809 | pipea_stats); | |
810 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
811 | pipeb_stats); | |
812 | /* pipestat has already been acked */ | |
813 | } | |
814 | if (eir & I915_ERROR_INSTRUCTION) { | |
815 | printk(KERN_ERR "instruction error\n"); | |
816 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
817 | I915_READ(INSTPM)); | |
818 | if (!IS_I965G(dev)) { | |
819 | u32 ipeir = I915_READ(IPEIR); | |
820 | ||
821 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
822 | I915_READ(IPEIR)); | |
823 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
824 | I915_READ(IPEHR)); | |
825 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
826 | I915_READ(INSTDONE)); | |
827 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
828 | I915_READ(ACTHD)); | |
829 | I915_WRITE(IPEIR, ipeir); | |
830 | (void)I915_READ(IPEIR); | |
831 | } else { | |
832 | u32 ipeir = I915_READ(IPEIR_I965); | |
833 | ||
834 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
835 | I915_READ(IPEIR_I965)); | |
836 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
837 | I915_READ(IPEHR_I965)); | |
838 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
839 | I915_READ(INSTDONE_I965)); | |
840 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
841 | I915_READ(INSTPS)); | |
842 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
843 | I915_READ(INSTDONE1)); | |
844 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
845 | I915_READ(ACTHD_I965)); | |
846 | I915_WRITE(IPEIR_I965, ipeir); | |
847 | (void)I915_READ(IPEIR_I965); | |
848 | } | |
849 | } | |
850 | ||
851 | I915_WRITE(EIR, eir); | |
852 | (void)I915_READ(EIR); | |
853 | eir = I915_READ(EIR); | |
854 | if (eir) { | |
855 | /* | |
856 | * some errors might have become stuck, | |
857 | * mask them. | |
858 | */ | |
859 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
860 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
861 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
862 | } | |
35aed2e6 CW |
863 | } |
864 | ||
865 | /** | |
866 | * i915_handle_error - handle an error interrupt | |
867 | * @dev: drm device | |
868 | * | |
869 | * Do some basic checking of regsiter state at error interrupt time and | |
870 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
871 | * sure we get a record and make it available in debugfs. Fire a uevent | |
872 | * so userspace knows something bad happened (should trigger collection | |
873 | * of a ring dump etc.). | |
874 | */ | |
875 | static void i915_handle_error(struct drm_device *dev, bool wedged) | |
876 | { | |
877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
878 | ||
879 | i915_capture_error_state(dev); | |
880 | i915_report_and_clear_eir(dev); | |
8a905236 | 881 | |
ba1234d1 BG |
882 | if (wedged) { |
883 | atomic_set(&dev_priv->mm.wedged, 1); | |
884 | ||
11ed50ec BG |
885 | /* |
886 | * Wakeup waiting processes so they don't hang | |
887 | */ | |
852835f3 | 888 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); |
11ed50ec BG |
889 | } |
890 | ||
9c9fe1f8 | 891 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
892 | } |
893 | ||
4e5359cd SF |
894 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
895 | { | |
896 | drm_i915_private_t *dev_priv = dev->dev_private; | |
897 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
899 | struct drm_i915_gem_object *obj_priv; | |
900 | struct intel_unpin_work *work; | |
901 | unsigned long flags; | |
902 | bool stall_detected; | |
903 | ||
904 | /* Ignore early vblank irqs */ | |
905 | if (intel_crtc == NULL) | |
906 | return; | |
907 | ||
908 | spin_lock_irqsave(&dev->event_lock, flags); | |
909 | work = intel_crtc->unpin_work; | |
910 | ||
911 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
912 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
913 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
914 | return; | |
915 | } | |
916 | ||
917 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
918 | obj_priv = to_intel_bo(work->pending_flip_obj); | |
919 | if(IS_I965G(dev)) { | |
920 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; | |
921 | stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset; | |
922 | } else { | |
923 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; | |
924 | stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset + | |
925 | crtc->y * crtc->fb->pitch + | |
926 | crtc->x * crtc->fb->bits_per_pixel/8); | |
927 | } | |
928 | ||
929 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
930 | ||
931 | if (stall_detected) { | |
932 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
933 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
934 | } | |
935 | } | |
936 | ||
1da177e4 LT |
937 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
938 | { | |
84b1fd10 | 939 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 940 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 941 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
942 | u32 iir, new_iir; |
943 | u32 pipea_stats, pipeb_stats; | |
05eff845 | 944 | u32 vblank_status; |
0a3e67a4 | 945 | int vblank = 0; |
7c463586 | 946 | unsigned long irqflags; |
05eff845 KP |
947 | int irq_received; |
948 | int ret = IRQ_NONE; | |
852835f3 | 949 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
6e5fca53 | 950 | |
630681d9 EA |
951 | atomic_inc(&dev_priv->irq_received); |
952 | ||
bad720ff | 953 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 954 | return ironlake_irq_handler(dev); |
036a4a7d | 955 | |
ed4cb414 | 956 | iir = I915_READ(IIR); |
a6b54f3f | 957 | |
e25e6601 | 958 | if (IS_I965G(dev)) |
d874bcff | 959 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 960 | else |
d874bcff | 961 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 962 | |
05eff845 KP |
963 | for (;;) { |
964 | irq_received = iir != 0; | |
965 | ||
966 | /* Can't rely on pipestat interrupt bit in iir as it might | |
967 | * have been cleared after the pipestat interrupt was received. | |
968 | * It doesn't set the bit in iir again, but it still produces | |
969 | * interrupts (for non-MSI). | |
970 | */ | |
971 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
972 | pipea_stats = I915_READ(PIPEASTAT); | |
973 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 974 | |
8a905236 | 975 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 976 | i915_handle_error(dev, false); |
8a905236 | 977 | |
cdfbc41f EA |
978 | /* |
979 | * Clear the PIPE(A|B)STAT regs before the IIR | |
980 | */ | |
05eff845 | 981 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 982 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 983 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 984 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 985 | irq_received = 1; |
cdfbc41f | 986 | } |
1da177e4 | 987 | |
05eff845 | 988 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 989 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 990 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 991 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 992 | irq_received = 1; |
cdfbc41f | 993 | } |
05eff845 KP |
994 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
995 | ||
996 | if (!irq_received) | |
997 | break; | |
998 | ||
999 | ret = IRQ_HANDLED; | |
8ee1c3db | 1000 | |
5ca58282 JB |
1001 | /* Consume port. Then clear IIR or we'll miss events */ |
1002 | if ((I915_HAS_HOTPLUG(dev)) && | |
1003 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1004 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1005 | ||
44d98a61 | 1006 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1007 | hotplug_status); |
1008 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1009 | queue_work(dev_priv->wq, |
1010 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1011 | |
1012 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1013 | I915_READ(PORT_HOTPLUG_STAT); | |
1014 | } | |
1015 | ||
cdfbc41f EA |
1016 | I915_WRITE(IIR, iir); |
1017 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1018 | |
7c1c2871 DA |
1019 | if (dev->primary->master) { |
1020 | master_priv = dev->primary->master->driver_priv; | |
1021 | if (master_priv->sarea_priv) | |
1022 | master_priv->sarea_priv->last_dispatch = | |
1023 | READ_BREADCRUMB(dev_priv); | |
1024 | } | |
0a3e67a4 | 1025 | |
cdfbc41f | 1026 | if (iir & I915_USER_INTERRUPT) { |
852835f3 ZN |
1027 | u32 seqno = |
1028 | render_ring->get_gem_seqno(dev, render_ring); | |
1029 | render_ring->irq_gem_seqno = seqno; | |
1c5d22f7 | 1030 | trace_i915_gem_request_complete(dev, seqno); |
852835f3 | 1031 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); |
f65d9421 BG |
1032 | dev_priv->hangcheck_count = 0; |
1033 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
cdfbc41f | 1034 | } |
673a394b | 1035 | |
d1b851fc ZN |
1036 | if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) |
1037 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | |
1038 | ||
1afe3e9d | 1039 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1040 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1041 | if (dev_priv->flip_pending_is_done) |
1042 | intel_finish_page_flip_plane(dev, 0); | |
1043 | } | |
6b95a207 | 1044 | |
1afe3e9d | 1045 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1046 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1047 | if (dev_priv->flip_pending_is_done) |
1048 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1049 | } |
6b95a207 | 1050 | |
05eff845 | 1051 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
1052 | vblank++; |
1053 | drm_handle_vblank(dev, 0); | |
4e5359cd SF |
1054 | if (!dev_priv->flip_pending_is_done) { |
1055 | i915_pageflip_stall_check(dev, 0); | |
1afe3e9d | 1056 | intel_finish_page_flip(dev, 0); |
4e5359cd | 1057 | } |
cdfbc41f | 1058 | } |
7c463586 | 1059 | |
05eff845 | 1060 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
1061 | vblank++; |
1062 | drm_handle_vblank(dev, 1); | |
4e5359cd SF |
1063 | if (!dev_priv->flip_pending_is_done) { |
1064 | i915_pageflip_stall_check(dev, 1); | |
1afe3e9d | 1065 | intel_finish_page_flip(dev, 1); |
4e5359cd | 1066 | } |
cdfbc41f | 1067 | } |
7c463586 | 1068 | |
d874bcff JB |
1069 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
1070 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f | 1071 | (iir & I915_ASLE_INTERRUPT)) |
3b617967 | 1072 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1073 | |
1074 | /* With MSI, interrupts are only generated when iir | |
1075 | * transitions from zero to nonzero. If another bit got | |
1076 | * set while we were handling the existing iir bits, then | |
1077 | * we would never get another interrupt. | |
1078 | * | |
1079 | * This is fine on non-MSI as well, as if we hit this path | |
1080 | * we avoid exiting the interrupt handler only to generate | |
1081 | * another one. | |
1082 | * | |
1083 | * Note that for MSI this could cause a stray interrupt report | |
1084 | * if an interrupt landed in the time between writing IIR and | |
1085 | * the posting read. This should be rare enough to never | |
1086 | * trigger the 99% of 100,000 interrupts test for disabling | |
1087 | * stray interrupts. | |
1088 | */ | |
1089 | iir = new_iir; | |
05eff845 | 1090 | } |
0a3e67a4 | 1091 | |
05eff845 | 1092 | return ret; |
1da177e4 LT |
1093 | } |
1094 | ||
af6061af | 1095 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1096 | { |
1097 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1098 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1099 | |
1100 | i915_kernel_lost_context(dev); | |
1101 | ||
44d98a61 | 1102 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1103 | |
c99b058f | 1104 | dev_priv->counter++; |
c29b669c | 1105 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1106 | dev_priv->counter = 1; |
7c1c2871 DA |
1107 | if (master_priv->sarea_priv) |
1108 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1109 | |
0baf823a | 1110 | BEGIN_LP_RING(4); |
585fb111 | 1111 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 1112 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 1113 | OUT_RING(dev_priv->counter); |
585fb111 | 1114 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 1115 | ADVANCE_LP_RING(); |
bc5f4523 | 1116 | |
c29b669c | 1117 | return dev_priv->counter; |
1da177e4 LT |
1118 | } |
1119 | ||
9d34e5db CW |
1120 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1121 | { | |
1122 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8187a2b7 | 1123 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
9d34e5db CW |
1124 | |
1125 | if (dev_priv->trace_irq_seqno == 0) | |
8187a2b7 | 1126 | render_ring->user_irq_get(dev, render_ring); |
9d34e5db CW |
1127 | |
1128 | dev_priv->trace_irq_seqno = seqno; | |
1129 | } | |
1130 | ||
84b1fd10 | 1131 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1132 | { |
1133 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1134 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1135 | int ret = 0; |
8187a2b7 | 1136 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
1da177e4 | 1137 | |
44d98a61 | 1138 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1139 | READ_BREADCRUMB(dev_priv)); |
1140 | ||
ed4cb414 | 1141 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1142 | if (master_priv->sarea_priv) |
1143 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1144 | return 0; |
ed4cb414 | 1145 | } |
1da177e4 | 1146 | |
7c1c2871 DA |
1147 | if (master_priv->sarea_priv) |
1148 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1149 | |
8187a2b7 | 1150 | render_ring->user_irq_get(dev, render_ring); |
852835f3 | 1151 | DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, |
1da177e4 | 1152 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
8187a2b7 | 1153 | render_ring->user_irq_put(dev, render_ring); |
1da177e4 | 1154 | |
20caafa6 | 1155 | if (ret == -EBUSY) { |
3e684eae | 1156 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1157 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1158 | } | |
1159 | ||
af6061af DA |
1160 | return ret; |
1161 | } | |
1162 | ||
1da177e4 LT |
1163 | /* Needs the lock as it touches the ring. |
1164 | */ | |
c153f45f EA |
1165 | int i915_irq_emit(struct drm_device *dev, void *data, |
1166 | struct drm_file *file_priv) | |
1da177e4 | 1167 | { |
1da177e4 | 1168 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1169 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1170 | int result; |
1171 | ||
d3301d86 | 1172 | if (!dev_priv || !dev_priv->render_ring.virtual_start) { |
3e684eae | 1173 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1174 | return -EINVAL; |
1da177e4 | 1175 | } |
299eb93c EA |
1176 | |
1177 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1178 | ||
546b0974 | 1179 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1180 | result = i915_emit_irq(dev); |
546b0974 | 1181 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1182 | |
c153f45f | 1183 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1184 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1185 | return -EFAULT; |
1da177e4 LT |
1186 | } |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | /* Doesn't need the hardware lock. | |
1192 | */ | |
c153f45f EA |
1193 | int i915_irq_wait(struct drm_device *dev, void *data, |
1194 | struct drm_file *file_priv) | |
1da177e4 | 1195 | { |
1da177e4 | 1196 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1197 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1198 | |
1199 | if (!dev_priv) { | |
3e684eae | 1200 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1201 | return -EINVAL; |
1da177e4 LT |
1202 | } |
1203 | ||
c153f45f | 1204 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1205 | } |
1206 | ||
42f52ef8 KP |
1207 | /* Called from drm generic code, passed 'crtc' which |
1208 | * we use as a pipe index | |
1209 | */ | |
1210 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1211 | { |
1212 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1213 | unsigned long irqflags; |
71e0ffa5 JB |
1214 | int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF; |
1215 | u32 pipeconf; | |
1216 | ||
1217 | pipeconf = I915_READ(pipeconf_reg); | |
1218 | if (!(pipeconf & PIPEACONF_ENABLE)) | |
1219 | return -EINVAL; | |
0a3e67a4 | 1220 | |
e9d21d7f | 1221 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1222 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1223 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
1224 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1225 | else if (IS_I965G(dev)) | |
7c463586 KP |
1226 | i915_enable_pipestat(dev_priv, pipe, |
1227 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1228 | else |
7c463586 KP |
1229 | i915_enable_pipestat(dev_priv, pipe, |
1230 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1231 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1232 | return 0; |
1233 | } | |
1234 | ||
42f52ef8 KP |
1235 | /* Called from drm generic code, passed 'crtc' which |
1236 | * we use as a pipe index | |
1237 | */ | |
1238 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1239 | { |
1240 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1241 | unsigned long irqflags; |
0a3e67a4 | 1242 | |
e9d21d7f | 1243 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1244 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1245 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
1246 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1247 | else | |
1248 | i915_disable_pipestat(dev_priv, pipe, | |
1249 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1250 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1251 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1252 | } |
1253 | ||
79e53945 JB |
1254 | void i915_enable_interrupt (struct drm_device *dev) |
1255 | { | |
1256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 1257 | |
bad720ff | 1258 | if (!HAS_PCH_SPLIT(dev)) |
3b617967 | 1259 | intel_opregion_enable_asle(dev); |
79e53945 JB |
1260 | dev_priv->irq_enabled = 1; |
1261 | } | |
1262 | ||
1263 | ||
702880f2 DA |
1264 | /* Set the vblank monitor pipe |
1265 | */ | |
c153f45f EA |
1266 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1267 | struct drm_file *file_priv) | |
702880f2 | 1268 | { |
702880f2 | 1269 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1270 | |
1271 | if (!dev_priv) { | |
3e684eae | 1272 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1273 | return -EINVAL; |
702880f2 DA |
1274 | } |
1275 | ||
5b51694a | 1276 | return 0; |
702880f2 DA |
1277 | } |
1278 | ||
c153f45f EA |
1279 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1280 | struct drm_file *file_priv) | |
702880f2 | 1281 | { |
702880f2 | 1282 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1283 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1284 | |
1285 | if (!dev_priv) { | |
3e684eae | 1286 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1287 | return -EINVAL; |
702880f2 DA |
1288 | } |
1289 | ||
0a3e67a4 | 1290 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1291 | |
702880f2 DA |
1292 | return 0; |
1293 | } | |
1294 | ||
a6b54f3f MCA |
1295 | /** |
1296 | * Schedule buffer swap at given vertical blank. | |
1297 | */ | |
c153f45f EA |
1298 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1299 | struct drm_file *file_priv) | |
a6b54f3f | 1300 | { |
bd95e0a4 EA |
1301 | /* The delayed swap mechanism was fundamentally racy, and has been |
1302 | * removed. The model was that the client requested a delayed flip/swap | |
1303 | * from the kernel, then waited for vblank before continuing to perform | |
1304 | * rendering. The problem was that the kernel might wake the client | |
1305 | * up before it dispatched the vblank swap (since the lock has to be | |
1306 | * held while touching the ringbuffer), in which case the client would | |
1307 | * clear and start the next frame before the swap occurred, and | |
1308 | * flicker would occur in addition to likely missing the vblank. | |
1309 | * | |
1310 | * In the absence of this ioctl, userland falls back to a correct path | |
1311 | * of waiting for a vblank, then dispatching the swap on its own. | |
1312 | * Context switching to userland and back is plenty fast enough for | |
1313 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1314 | */ |
bd95e0a4 | 1315 | return -EINVAL; |
a6b54f3f MCA |
1316 | } |
1317 | ||
852835f3 ZN |
1318 | struct drm_i915_gem_request * |
1319 | i915_get_tail_request(struct drm_device *dev) | |
1320 | { | |
f65d9421 | 1321 | drm_i915_private_t *dev_priv = dev->dev_private; |
852835f3 ZN |
1322 | return list_entry(dev_priv->render_ring.request_list.prev, |
1323 | struct drm_i915_gem_request, list); | |
f65d9421 BG |
1324 | } |
1325 | ||
1326 | /** | |
1327 | * This is called when the chip hasn't reported back with completed | |
1328 | * batchbuffers in a long time. The first time this is called we simply record | |
1329 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1330 | * again, we assume the chip is wedged and try to fix it. | |
1331 | */ | |
1332 | void i915_hangcheck_elapsed(unsigned long data) | |
1333 | { | |
1334 | struct drm_device *dev = (struct drm_device *)data; | |
1335 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1336 | uint32_t acthd, instdone, instdone1; |
b9201c14 EA |
1337 | |
1338 | /* No reset support on this chip yet. */ | |
1339 | if (IS_GEN6(dev)) | |
1340 | return; | |
1341 | ||
cbb465e7 | 1342 | if (!IS_I965G(dev)) { |
f65d9421 | 1343 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1344 | instdone = I915_READ(INSTDONE); |
1345 | instdone1 = 0; | |
1346 | } else { | |
f65d9421 | 1347 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1348 | instdone = I915_READ(INSTDONE_I965); |
1349 | instdone1 = I915_READ(INSTDONE1); | |
1350 | } | |
f65d9421 BG |
1351 | |
1352 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
852835f3 ZN |
1353 | if (list_empty(&dev_priv->render_ring.request_list) || |
1354 | i915_seqno_passed(i915_get_gem_seqno(dev, | |
1355 | &dev_priv->render_ring), | |
1356 | i915_get_tail_request(dev)->seqno)) { | |
f65d9421 | 1357 | dev_priv->hangcheck_count = 0; |
e78d73b1 CW |
1358 | |
1359 | /* Issue a wake-up to catch stuck h/w. */ | |
1360 | if (dev_priv->render_ring.waiting_gem_seqno | | |
1361 | dev_priv->bsd_ring.waiting_gem_seqno) { | |
1362 | DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); | |
1363 | if (dev_priv->render_ring.waiting_gem_seqno) | |
1364 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); | |
1365 | if (dev_priv->bsd_ring.waiting_gem_seqno) | |
1366 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | |
1367 | } | |
f65d9421 BG |
1368 | return; |
1369 | } | |
1370 | ||
cbb465e7 CW |
1371 | if (dev_priv->last_acthd == acthd && |
1372 | dev_priv->last_instdone == instdone && | |
1373 | dev_priv->last_instdone1 == instdone1) { | |
1374 | if (dev_priv->hangcheck_count++ > 1) { | |
1375 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
1376 | i915_handle_error(dev, true); | |
1377 | return; | |
1378 | } | |
1379 | } else { | |
1380 | dev_priv->hangcheck_count = 0; | |
1381 | ||
1382 | dev_priv->last_acthd = acthd; | |
1383 | dev_priv->last_instdone = instdone; | |
1384 | dev_priv->last_instdone1 = instdone1; | |
1385 | } | |
f65d9421 BG |
1386 | |
1387 | /* Reset timer case chip hangs without another request being added */ | |
1388 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
f65d9421 BG |
1389 | } |
1390 | ||
1da177e4 LT |
1391 | /* drm_dma.h hooks |
1392 | */ | |
f2b115e6 | 1393 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1394 | { |
1395 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1396 | ||
1397 | I915_WRITE(HWSTAM, 0xeffe); | |
1398 | ||
1399 | /* XXX hotplug from PCH */ | |
1400 | ||
1401 | I915_WRITE(DEIMR, 0xffffffff); | |
1402 | I915_WRITE(DEIER, 0x0); | |
1403 | (void) I915_READ(DEIER); | |
1404 | ||
1405 | /* and GT */ | |
1406 | I915_WRITE(GTIMR, 0xffffffff); | |
1407 | I915_WRITE(GTIER, 0x0); | |
1408 | (void) I915_READ(GTIER); | |
c650156a ZW |
1409 | |
1410 | /* south display irq */ | |
1411 | I915_WRITE(SDEIMR, 0xffffffff); | |
1412 | I915_WRITE(SDEIER, 0x0); | |
1413 | (void) I915_READ(SDEIER); | |
036a4a7d ZW |
1414 | } |
1415 | ||
f2b115e6 | 1416 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1417 | { |
1418 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1419 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1420 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1421 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
d1b851fc | 1422 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
c650156a ZW |
1423 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1424 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
036a4a7d ZW |
1425 | |
1426 | dev_priv->irq_mask_reg = ~display_mask; | |
643ced9b | 1427 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
036a4a7d ZW |
1428 | |
1429 | /* should always can generate irq */ | |
1430 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1431 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1432 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1433 | (void) I915_READ(DEIER); | |
1434 | ||
3fdef020 ZW |
1435 | /* Gen6 only needs render pipe_control now */ |
1436 | if (IS_GEN6(dev)) | |
1437 | render_mask = GT_PIPE_NOTIFY; | |
1438 | ||
852835f3 | 1439 | dev_priv->gt_irq_mask_reg = ~render_mask; |
036a4a7d ZW |
1440 | dev_priv->gt_irq_enable_reg = render_mask; |
1441 | ||
1442 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1443 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
3fdef020 ZW |
1444 | if (IS_GEN6(dev)) |
1445 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); | |
036a4a7d ZW |
1446 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
1447 | (void) I915_READ(GTIER); | |
1448 | ||
c650156a ZW |
1449 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1450 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1451 | ||
1452 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1453 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1454 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
1455 | (void) I915_READ(SDEIER); | |
1456 | ||
f97108d1 JB |
1457 | if (IS_IRONLAKE_M(dev)) { |
1458 | /* Clear & enable PCU event interrupts */ | |
1459 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1460 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1461 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1462 | } | |
1463 | ||
036a4a7d ZW |
1464 | return 0; |
1465 | } | |
1466 | ||
84b1fd10 | 1467 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1468 | { |
1469 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1470 | ||
79e53945 JB |
1471 | atomic_set(&dev_priv->irq_received, 0); |
1472 | ||
036a4a7d | 1473 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1474 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1475 | |
bad720ff | 1476 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1477 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1478 | return; |
1479 | } | |
1480 | ||
5ca58282 JB |
1481 | if (I915_HAS_HOTPLUG(dev)) { |
1482 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1483 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1484 | } | |
1485 | ||
0a3e67a4 | 1486 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1487 | I915_WRITE(PIPEASTAT, 0); |
1488 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1489 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1490 | I915_WRITE(IER, 0x0); |
7c463586 | 1491 | (void) I915_READ(IER); |
1da177e4 LT |
1492 | } |
1493 | ||
b01f2c3a JB |
1494 | /* |
1495 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1496 | * enabled correctly. | |
1497 | */ | |
0a3e67a4 | 1498 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1499 | { |
1500 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1501 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1502 | u32 error_mask; |
0a3e67a4 | 1503 | |
852835f3 | 1504 | DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); |
036a4a7d | 1505 | |
d1b851fc ZN |
1506 | if (HAS_BSD(dev)) |
1507 | DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue); | |
1508 | ||
0a3e67a4 | 1509 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1510 | |
bad720ff | 1511 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1512 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1513 | |
7c463586 KP |
1514 | /* Unmask the interrupts that we always want on. */ |
1515 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1516 | ||
1517 | dev_priv->pipestat[0] = 0; | |
1518 | dev_priv->pipestat[1] = 0; | |
1519 | ||
5ca58282 | 1520 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1521 | /* Enable in IER... */ |
1522 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1523 | /* and unmask in IMR */ | |
c496fa1f | 1524 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1525 | } |
1526 | ||
63eeaf38 JB |
1527 | /* |
1528 | * Enable some error detection, note the instruction error mask | |
1529 | * bit is reserved, so we leave it masked. | |
1530 | */ | |
1531 | if (IS_G4X(dev)) { | |
1532 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1533 | GM45_ERROR_MEM_PRIV | | |
1534 | GM45_ERROR_CP_PRIV | | |
1535 | I915_ERROR_MEMORY_REFRESH); | |
1536 | } else { | |
1537 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1538 | I915_ERROR_MEMORY_REFRESH); | |
1539 | } | |
1540 | I915_WRITE(EMR, error_mask); | |
1541 | ||
7c463586 | 1542 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
c496fa1f | 1543 | I915_WRITE(IER, enable_mask); |
ed4cb414 EA |
1544 | (void) I915_READ(IER); |
1545 | ||
c496fa1f AJ |
1546 | if (I915_HAS_HOTPLUG(dev)) { |
1547 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1548 | ||
1549 | /* Note HDMI and DP share bits */ | |
1550 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1551 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1552 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1553 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1554 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1555 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1556 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1557 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1558 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1559 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1560 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1561 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1562 | |
1563 | /* Programming the CRT detection parameters tends | |
1564 | to generate a spurious hotplug event about three | |
1565 | seconds later. So just do it once. | |
1566 | */ | |
1567 | if (IS_G4X(dev)) | |
1568 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1569 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1570 | } | |
1571 | ||
c496fa1f AJ |
1572 | /* Ignore TV since it's buggy */ |
1573 | ||
1574 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1575 | } | |
1576 | ||
3b617967 | 1577 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1578 | |
1579 | return 0; | |
1da177e4 LT |
1580 | } |
1581 | ||
f2b115e6 | 1582 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1583 | { |
1584 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1585 | I915_WRITE(HWSTAM, 0xffffffff); | |
1586 | ||
1587 | I915_WRITE(DEIMR, 0xffffffff); | |
1588 | I915_WRITE(DEIER, 0x0); | |
1589 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1590 | ||
1591 | I915_WRITE(GTIMR, 0xffffffff); | |
1592 | I915_WRITE(GTIER, 0x0); | |
1593 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1594 | } | |
1595 | ||
84b1fd10 | 1596 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1597 | { |
1598 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1599 | |
1da177e4 LT |
1600 | if (!dev_priv) |
1601 | return; | |
1602 | ||
0a3e67a4 JB |
1603 | dev_priv->vblank_pipe = 0; |
1604 | ||
bad720ff | 1605 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1606 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1607 | return; |
1608 | } | |
1609 | ||
5ca58282 JB |
1610 | if (I915_HAS_HOTPLUG(dev)) { |
1611 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1612 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1613 | } | |
1614 | ||
0a3e67a4 | 1615 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1616 | I915_WRITE(PIPEASTAT, 0); |
1617 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1618 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1619 | I915_WRITE(IER, 0x0); |
af6061af | 1620 | |
7c463586 KP |
1621 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1622 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1623 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1624 | } |