Commit | Line | Data |
---|---|---|
7d57382e EA |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2009 Intel Corporation | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Jesse Barnes <jesse.barnes@intel.com> | |
27 | */ | |
28 | ||
29 | #include <linux/i2c.h> | |
5a0e3ad6 | 30 | #include <linux/slab.h> |
7d57382e | 31 | #include <linux/delay.h> |
178f736a | 32 | #include <linux/hdmi.h> |
760285e7 DH |
33 | #include <drm/drmP.h> |
34 | #include <drm/drm_crtc.h> | |
35 | #include <drm/drm_edid.h> | |
7d57382e | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
7d57382e EA |
38 | #include "i915_drv.h" |
39 | ||
30add22d PZ |
40 | static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi) |
41 | { | |
da63a9f2 | 42 | return hdmi_to_dig_port(intel_hdmi)->base.base.dev; |
30add22d PZ |
43 | } |
44 | ||
afba0188 DV |
45 | static void |
46 | assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) | |
47 | { | |
30add22d | 48 | struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi); |
afba0188 DV |
49 | struct drm_i915_private *dev_priv = dev->dev_private; |
50 | uint32_t enabled_bits; | |
51 | ||
affa9354 | 52 | enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; |
afba0188 | 53 | |
b242b7f7 | 54 | WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, |
afba0188 DV |
55 | "HDMI port enabled, expecting disabled\n"); |
56 | } | |
57 | ||
f5bbfca3 | 58 | struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
da63a9f2 PZ |
60 | struct intel_digital_port *intel_dig_port = |
61 | container_of(encoder, struct intel_digital_port, base.base); | |
62 | return &intel_dig_port->hdmi; | |
ea5b213a CW |
63 | } |
64 | ||
df0e9248 CW |
65 | static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector) |
66 | { | |
da63a9f2 | 67 | return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base); |
df0e9248 CW |
68 | } |
69 | ||
178f736a | 70 | static u32 g4x_infoframe_index(enum hdmi_infoframe_type type) |
3c17fe4b | 71 | { |
178f736a DL |
72 | switch (type) { |
73 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 74 | return VIDEO_DIP_SELECT_AVI; |
178f736a | 75 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 76 | return VIDEO_DIP_SELECT_SPD; |
c8bb75af LD |
77 | case HDMI_INFOFRAME_TYPE_VENDOR: |
78 | return VIDEO_DIP_SELECT_VENDOR; | |
45187ace | 79 | default: |
178f736a | 80 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 81 | return 0; |
45187ace | 82 | } |
45187ace JB |
83 | } |
84 | ||
178f736a | 85 | static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type) |
45187ace | 86 | { |
178f736a DL |
87 | switch (type) { |
88 | case HDMI_INFOFRAME_TYPE_AVI: | |
ed517fbb | 89 | return VIDEO_DIP_ENABLE_AVI; |
178f736a | 90 | case HDMI_INFOFRAME_TYPE_SPD: |
ed517fbb | 91 | return VIDEO_DIP_ENABLE_SPD; |
c8bb75af LD |
92 | case HDMI_INFOFRAME_TYPE_VENDOR: |
93 | return VIDEO_DIP_ENABLE_VENDOR; | |
fa193ff7 | 94 | default: |
178f736a | 95 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
ed517fbb | 96 | return 0; |
fa193ff7 | 97 | } |
fa193ff7 PZ |
98 | } |
99 | ||
178f736a | 100 | static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type) |
2da8af54 | 101 | { |
178f736a DL |
102 | switch (type) { |
103 | case HDMI_INFOFRAME_TYPE_AVI: | |
2da8af54 | 104 | return VIDEO_DIP_ENABLE_AVI_HSW; |
178f736a | 105 | case HDMI_INFOFRAME_TYPE_SPD: |
2da8af54 | 106 | return VIDEO_DIP_ENABLE_SPD_HSW; |
c8bb75af LD |
107 | case HDMI_INFOFRAME_TYPE_VENDOR: |
108 | return VIDEO_DIP_ENABLE_VS_HSW; | |
2da8af54 | 109 | default: |
178f736a | 110 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
111 | return 0; |
112 | } | |
113 | } | |
114 | ||
178f736a | 115 | static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type, |
a57c774a AK |
116 | enum transcoder cpu_transcoder, |
117 | struct drm_i915_private *dev_priv) | |
2da8af54 | 118 | { |
178f736a DL |
119 | switch (type) { |
120 | case HDMI_INFOFRAME_TYPE_AVI: | |
7d9bcebe | 121 | return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder); |
178f736a | 122 | case HDMI_INFOFRAME_TYPE_SPD: |
7d9bcebe | 123 | return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder); |
c8bb75af LD |
124 | case HDMI_INFOFRAME_TYPE_VENDOR: |
125 | return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder); | |
2da8af54 | 126 | default: |
178f736a | 127 | DRM_DEBUG_DRIVER("unknown info frame type %d\n", type); |
2da8af54 PZ |
128 | return 0; |
129 | } | |
130 | } | |
131 | ||
a3da1df7 | 132 | static void g4x_write_infoframe(struct drm_encoder *encoder, |
178f736a | 133 | enum hdmi_infoframe_type type, |
fff63867 | 134 | const void *frame, ssize_t len) |
45187ace | 135 | { |
fff63867 | 136 | const uint32_t *data = frame; |
3c17fe4b DH |
137 | struct drm_device *dev = encoder->dev; |
138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
22509ec8 | 139 | u32 val = I915_READ(VIDEO_DIP_CTL); |
178f736a | 140 | int i; |
3c17fe4b | 141 | |
822974ae PZ |
142 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
143 | ||
1d4f85ac | 144 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 145 | val |= g4x_infoframe_index(type); |
22509ec8 | 146 | |
178f736a | 147 | val &= ~g4x_infoframe_enable(type); |
45187ace | 148 | |
22509ec8 | 149 | I915_WRITE(VIDEO_DIP_CTL, val); |
3c17fe4b | 150 | |
9d9740f0 | 151 | mmiowb(); |
45187ace | 152 | for (i = 0; i < len; i += 4) { |
3c17fe4b DH |
153 | I915_WRITE(VIDEO_DIP_DATA, *data); |
154 | data++; | |
155 | } | |
adf00b26 PZ |
156 | /* Write every possible data byte to force correct ECC calculation. */ |
157 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
158 | I915_WRITE(VIDEO_DIP_DATA, 0); | |
9d9740f0 | 159 | mmiowb(); |
3c17fe4b | 160 | |
178f736a | 161 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 162 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 163 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 164 | |
22509ec8 | 165 | I915_WRITE(VIDEO_DIP_CTL, val); |
9d9740f0 | 166 | POSTING_READ(VIDEO_DIP_CTL); |
3c17fe4b DH |
167 | } |
168 | ||
fdf1250a | 169 | static void ibx_write_infoframe(struct drm_encoder *encoder, |
178f736a | 170 | enum hdmi_infoframe_type type, |
fff63867 | 171 | const void *frame, ssize_t len) |
fdf1250a | 172 | { |
fff63867 | 173 | const uint32_t *data = frame; |
fdf1250a PZ |
174 | struct drm_device *dev = encoder->dev; |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 176 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 177 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
fdf1250a PZ |
178 | u32 val = I915_READ(reg); |
179 | ||
822974ae PZ |
180 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
181 | ||
fdf1250a | 182 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 183 | val |= g4x_infoframe_index(type); |
fdf1250a | 184 | |
178f736a | 185 | val &= ~g4x_infoframe_enable(type); |
fdf1250a PZ |
186 | |
187 | I915_WRITE(reg, val); | |
188 | ||
9d9740f0 | 189 | mmiowb(); |
fdf1250a PZ |
190 | for (i = 0; i < len; i += 4) { |
191 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
192 | data++; | |
193 | } | |
adf00b26 PZ |
194 | /* Write every possible data byte to force correct ECC calculation. */ |
195 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
196 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 197 | mmiowb(); |
fdf1250a | 198 | |
178f736a | 199 | val |= g4x_infoframe_enable(type); |
fdf1250a | 200 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 201 | val |= VIDEO_DIP_FREQ_VSYNC; |
fdf1250a PZ |
202 | |
203 | I915_WRITE(reg, val); | |
9d9740f0 | 204 | POSTING_READ(reg); |
fdf1250a PZ |
205 | } |
206 | ||
207 | static void cpt_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 208 | enum hdmi_infoframe_type type, |
fff63867 | 209 | const void *frame, ssize_t len) |
b055c8f3 | 210 | { |
fff63867 | 211 | const uint32_t *data = frame; |
b055c8f3 JB |
212 | struct drm_device *dev = encoder->dev; |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 214 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 215 | int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 216 | u32 val = I915_READ(reg); |
b055c8f3 | 217 | |
822974ae PZ |
218 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
219 | ||
64a8fc01 | 220 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 221 | val |= g4x_infoframe_index(type); |
45187ace | 222 | |
ecb97851 PZ |
223 | /* The DIP control register spec says that we need to update the AVI |
224 | * infoframe without clearing its enable bit */ | |
178f736a DL |
225 | if (type != HDMI_INFOFRAME_TYPE_AVI) |
226 | val &= ~g4x_infoframe_enable(type); | |
ecb97851 | 227 | |
22509ec8 | 228 | I915_WRITE(reg, val); |
45187ace | 229 | |
9d9740f0 | 230 | mmiowb(); |
45187ace | 231 | for (i = 0; i < len; i += 4) { |
b055c8f3 JB |
232 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); |
233 | data++; | |
234 | } | |
adf00b26 PZ |
235 | /* Write every possible data byte to force correct ECC calculation. */ |
236 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
237 | I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 238 | mmiowb(); |
b055c8f3 | 239 | |
178f736a | 240 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 241 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 242 | val |= VIDEO_DIP_FREQ_VSYNC; |
45187ace | 243 | |
22509ec8 | 244 | I915_WRITE(reg, val); |
9d9740f0 | 245 | POSTING_READ(reg); |
45187ace | 246 | } |
90b107c8 SK |
247 | |
248 | static void vlv_write_infoframe(struct drm_encoder *encoder, | |
178f736a | 249 | enum hdmi_infoframe_type type, |
fff63867 | 250 | const void *frame, ssize_t len) |
90b107c8 | 251 | { |
fff63867 | 252 | const uint32_t *data = frame; |
90b107c8 SK |
253 | struct drm_device *dev = encoder->dev; |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ed517fbb | 255 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
178f736a | 256 | int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
22509ec8 | 257 | u32 val = I915_READ(reg); |
90b107c8 | 258 | |
822974ae PZ |
259 | WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); |
260 | ||
90b107c8 | 261 | val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ |
178f736a | 262 | val |= g4x_infoframe_index(type); |
22509ec8 | 263 | |
178f736a | 264 | val &= ~g4x_infoframe_enable(type); |
90b107c8 | 265 | |
22509ec8 | 266 | I915_WRITE(reg, val); |
90b107c8 | 267 | |
9d9740f0 | 268 | mmiowb(); |
90b107c8 SK |
269 | for (i = 0; i < len; i += 4) { |
270 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data); | |
271 | data++; | |
272 | } | |
adf00b26 PZ |
273 | /* Write every possible data byte to force correct ECC calculation. */ |
274 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
275 | I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0); | |
9d9740f0 | 276 | mmiowb(); |
90b107c8 | 277 | |
178f736a | 278 | val |= g4x_infoframe_enable(type); |
60c5ea2d | 279 | val &= ~VIDEO_DIP_FREQ_MASK; |
4b24c933 | 280 | val |= VIDEO_DIP_FREQ_VSYNC; |
90b107c8 | 281 | |
22509ec8 | 282 | I915_WRITE(reg, val); |
9d9740f0 | 283 | POSTING_READ(reg); |
90b107c8 SK |
284 | } |
285 | ||
8c5f5f7c | 286 | static void hsw_write_infoframe(struct drm_encoder *encoder, |
178f736a | 287 | enum hdmi_infoframe_type type, |
fff63867 | 288 | const void *frame, ssize_t len) |
8c5f5f7c | 289 | { |
fff63867 | 290 | const uint32_t *data = frame; |
2da8af54 PZ |
291 | struct drm_device *dev = encoder->dev; |
292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
293 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
3b117c8f | 294 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
178f736a DL |
295 | u32 data_reg; |
296 | int i; | |
2da8af54 | 297 | u32 val = I915_READ(ctl_reg); |
8c5f5f7c | 298 | |
178f736a | 299 | data_reg = hsw_infoframe_data_reg(type, |
a57c774a AK |
300 | intel_crtc->config.cpu_transcoder, |
301 | dev_priv); | |
2da8af54 PZ |
302 | if (data_reg == 0) |
303 | return; | |
304 | ||
178f736a | 305 | val &= ~hsw_infoframe_enable(type); |
2da8af54 PZ |
306 | I915_WRITE(ctl_reg, val); |
307 | ||
9d9740f0 | 308 | mmiowb(); |
2da8af54 PZ |
309 | for (i = 0; i < len; i += 4) { |
310 | I915_WRITE(data_reg + i, *data); | |
311 | data++; | |
312 | } | |
adf00b26 PZ |
313 | /* Write every possible data byte to force correct ECC calculation. */ |
314 | for (; i < VIDEO_DIP_DATA_SIZE; i += 4) | |
315 | I915_WRITE(data_reg + i, 0); | |
9d9740f0 | 316 | mmiowb(); |
8c5f5f7c | 317 | |
178f736a | 318 | val |= hsw_infoframe_enable(type); |
2da8af54 | 319 | I915_WRITE(ctl_reg, val); |
9d9740f0 | 320 | POSTING_READ(ctl_reg); |
8c5f5f7c ED |
321 | } |
322 | ||
5adaea79 DL |
323 | /* |
324 | * The data we write to the DIP data buffer registers is 1 byte bigger than the | |
325 | * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting | |
326 | * at 0). It's also a byte used by DisplayPort so the same DIP registers can be | |
327 | * used for both technologies. | |
328 | * | |
329 | * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0 | |
330 | * DW1: DB3 | DB2 | DB1 | DB0 | |
331 | * DW2: DB7 | DB6 | DB5 | DB4 | |
332 | * DW3: ... | |
333 | * | |
334 | * (HB is Header Byte, DB is Data Byte) | |
335 | * | |
336 | * The hdmi pack() functions don't know about that hardware specific hole so we | |
337 | * trick them by giving an offset into the buffer and moving back the header | |
338 | * bytes by one. | |
339 | */ | |
9198ee5b DL |
340 | static void intel_write_infoframe(struct drm_encoder *encoder, |
341 | union hdmi_infoframe *frame) | |
45187ace JB |
342 | { |
343 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
5adaea79 DL |
344 | uint8_t buffer[VIDEO_DIP_DATA_SIZE]; |
345 | ssize_t len; | |
45187ace | 346 | |
5adaea79 DL |
347 | /* see comment above for the reason for this offset */ |
348 | len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1); | |
349 | if (len < 0) | |
350 | return; | |
351 | ||
352 | /* Insert the 'hole' (see big comment above) at position 3 */ | |
353 | buffer[0] = buffer[1]; | |
354 | buffer[1] = buffer[2]; | |
355 | buffer[2] = buffer[3]; | |
356 | buffer[3] = 0; | |
357 | len++; | |
45187ace | 358 | |
5adaea79 | 359 | intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len); |
45187ace JB |
360 | } |
361 | ||
687f4d06 | 362 | static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder, |
c846b619 | 363 | struct drm_display_mode *adjusted_mode) |
45187ace | 364 | { |
abedc077 | 365 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
50f3b016 | 366 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
5adaea79 DL |
367 | union hdmi_infoframe frame; |
368 | int ret; | |
45187ace | 369 | |
94a11ddc VK |
370 | /* Set user selected PAR to incoming mode's member */ |
371 | adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio; | |
372 | ||
5adaea79 DL |
373 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, |
374 | adjusted_mode); | |
375 | if (ret < 0) { | |
376 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
377 | return; | |
378 | } | |
c846b619 | 379 | |
abedc077 | 380 | if (intel_hdmi->rgb_quant_range_selectable) { |
50f3b016 | 381 | if (intel_crtc->config.limited_color_range) |
5adaea79 DL |
382 | frame.avi.quantization_range = |
383 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 384 | else |
5adaea79 DL |
385 | frame.avi.quantization_range = |
386 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
387 | } |
388 | ||
9198ee5b | 389 | intel_write_infoframe(encoder, &frame); |
b055c8f3 JB |
390 | } |
391 | ||
687f4d06 | 392 | static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder) |
c0864cb3 | 393 | { |
5adaea79 DL |
394 | union hdmi_infoframe frame; |
395 | int ret; | |
396 | ||
397 | ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx"); | |
398 | if (ret < 0) { | |
399 | DRM_ERROR("couldn't fill SPD infoframe\n"); | |
400 | return; | |
401 | } | |
c0864cb3 | 402 | |
5adaea79 | 403 | frame.spd.sdi = HDMI_SPD_SDI_PC; |
c0864cb3 | 404 | |
9198ee5b | 405 | intel_write_infoframe(encoder, &frame); |
c0864cb3 JB |
406 | } |
407 | ||
c8bb75af LD |
408 | static void |
409 | intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder, | |
410 | struct drm_display_mode *adjusted_mode) | |
411 | { | |
412 | union hdmi_infoframe frame; | |
413 | int ret; | |
414 | ||
415 | ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, | |
416 | adjusted_mode); | |
417 | if (ret < 0) | |
418 | return; | |
419 | ||
420 | intel_write_infoframe(encoder, &frame); | |
421 | } | |
422 | ||
687f4d06 | 423 | static void g4x_set_infoframes(struct drm_encoder *encoder, |
6897b4b5 | 424 | bool enable, |
687f4d06 PZ |
425 | struct drm_display_mode *adjusted_mode) |
426 | { | |
0c14c7f9 | 427 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
69fde0a6 VS |
428 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
429 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
430 | u32 reg = VIDEO_DIP_CTL; |
431 | u32 val = I915_READ(reg); | |
822cdc52 | 432 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 433 | |
afba0188 DV |
434 | assert_hdmi_port_disabled(intel_hdmi); |
435 | ||
0c14c7f9 PZ |
436 | /* If the registers were not initialized yet, they might be zeroes, |
437 | * which means we're selecting the AVI DIP and we're setting its | |
438 | * frequency to once. This seems to really confuse the HW and make | |
439 | * things stop working (the register spec says the AVI always needs to | |
440 | * be sent every VSync). So here we avoid writing to the register more | |
441 | * than we need and also explicitly select the AVI DIP and explicitly | |
442 | * set its frequency to every VSync. Avoiding to write it twice seems to | |
443 | * be enough to solve the problem, but being defensive shouldn't hurt us | |
444 | * either. */ | |
445 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
446 | ||
6897b4b5 | 447 | if (!enable) { |
0c14c7f9 PZ |
448 | if (!(val & VIDEO_DIP_ENABLE)) |
449 | return; | |
450 | val &= ~VIDEO_DIP_ENABLE; | |
451 | I915_WRITE(reg, val); | |
9d9740f0 | 452 | POSTING_READ(reg); |
0c14c7f9 PZ |
453 | return; |
454 | } | |
455 | ||
72b78c9d PZ |
456 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
457 | if (val & VIDEO_DIP_ENABLE) { | |
458 | val &= ~VIDEO_DIP_ENABLE; | |
459 | I915_WRITE(reg, val); | |
9d9740f0 | 460 | POSTING_READ(reg); |
72b78c9d PZ |
461 | } |
462 | val &= ~VIDEO_DIP_PORT_MASK; | |
463 | val |= port; | |
464 | } | |
465 | ||
822974ae | 466 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 | 467 | val &= ~VIDEO_DIP_ENABLE_VENDOR; |
822974ae | 468 | |
f278d972 | 469 | I915_WRITE(reg, val); |
9d9740f0 | 470 | POSTING_READ(reg); |
f278d972 | 471 | |
687f4d06 PZ |
472 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
473 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 474 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
475 | } |
476 | ||
477 | static void ibx_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 478 | bool enable, |
687f4d06 PZ |
479 | struct drm_display_mode *adjusted_mode) |
480 | { | |
0c14c7f9 PZ |
481 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
482 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
69fde0a6 VS |
483 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
484 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
0c14c7f9 PZ |
485 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
486 | u32 val = I915_READ(reg); | |
822cdc52 | 487 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 488 | |
afba0188 DV |
489 | assert_hdmi_port_disabled(intel_hdmi); |
490 | ||
0c14c7f9 PZ |
491 | /* See the big comment in g4x_set_infoframes() */ |
492 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
493 | ||
6897b4b5 | 494 | if (!enable) { |
0c14c7f9 PZ |
495 | if (!(val & VIDEO_DIP_ENABLE)) |
496 | return; | |
497 | val &= ~VIDEO_DIP_ENABLE; | |
498 | I915_WRITE(reg, val); | |
9d9740f0 | 499 | POSTING_READ(reg); |
0c14c7f9 PZ |
500 | return; |
501 | } | |
502 | ||
72b78c9d PZ |
503 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
504 | if (val & VIDEO_DIP_ENABLE) { | |
505 | val &= ~VIDEO_DIP_ENABLE; | |
506 | I915_WRITE(reg, val); | |
9d9740f0 | 507 | POSTING_READ(reg); |
72b78c9d PZ |
508 | } |
509 | val &= ~VIDEO_DIP_PORT_MASK; | |
510 | val |= port; | |
511 | } | |
512 | ||
822974ae | 513 | val |= VIDEO_DIP_ENABLE; |
0dd87d20 PZ |
514 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
515 | VIDEO_DIP_ENABLE_GCP); | |
822974ae | 516 | |
f278d972 | 517 | I915_WRITE(reg, val); |
9d9740f0 | 518 | POSTING_READ(reg); |
f278d972 | 519 | |
687f4d06 PZ |
520 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
521 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 522 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
523 | } |
524 | ||
525 | static void cpt_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 526 | bool enable, |
687f4d06 PZ |
527 | struct drm_display_mode *adjusted_mode) |
528 | { | |
0c14c7f9 PZ |
529 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
530 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
531 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
532 | u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | |
533 | u32 val = I915_READ(reg); | |
534 | ||
afba0188 DV |
535 | assert_hdmi_port_disabled(intel_hdmi); |
536 | ||
0c14c7f9 PZ |
537 | /* See the big comment in g4x_set_infoframes() */ |
538 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
539 | ||
6897b4b5 | 540 | if (!enable) { |
0c14c7f9 PZ |
541 | if (!(val & VIDEO_DIP_ENABLE)) |
542 | return; | |
543 | val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI); | |
544 | I915_WRITE(reg, val); | |
9d9740f0 | 545 | POSTING_READ(reg); |
0c14c7f9 PZ |
546 | return; |
547 | } | |
548 | ||
822974ae PZ |
549 | /* Set both together, unset both together: see the spec. */ |
550 | val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI; | |
0dd87d20 PZ |
551 | val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT | |
552 | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
553 | |
554 | I915_WRITE(reg, val); | |
9d9740f0 | 555 | POSTING_READ(reg); |
822974ae | 556 | |
687f4d06 PZ |
557 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
558 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 559 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
560 | } |
561 | ||
562 | static void vlv_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 563 | bool enable, |
687f4d06 PZ |
564 | struct drm_display_mode *adjusted_mode) |
565 | { | |
0c14c7f9 | 566 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
6a2b8021 | 567 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
0c14c7f9 PZ |
568 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
569 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
570 | u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | |
571 | u32 val = I915_READ(reg); | |
6a2b8021 | 572 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); |
0c14c7f9 | 573 | |
afba0188 DV |
574 | assert_hdmi_port_disabled(intel_hdmi); |
575 | ||
0c14c7f9 PZ |
576 | /* See the big comment in g4x_set_infoframes() */ |
577 | val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC; | |
578 | ||
6897b4b5 | 579 | if (!enable) { |
0c14c7f9 PZ |
580 | if (!(val & VIDEO_DIP_ENABLE)) |
581 | return; | |
582 | val &= ~VIDEO_DIP_ENABLE; | |
583 | I915_WRITE(reg, val); | |
9d9740f0 | 584 | POSTING_READ(reg); |
0c14c7f9 PZ |
585 | return; |
586 | } | |
587 | ||
6a2b8021 JB |
588 | if (port != (val & VIDEO_DIP_PORT_MASK)) { |
589 | if (val & VIDEO_DIP_ENABLE) { | |
590 | val &= ~VIDEO_DIP_ENABLE; | |
591 | I915_WRITE(reg, val); | |
592 | POSTING_READ(reg); | |
593 | } | |
594 | val &= ~VIDEO_DIP_PORT_MASK; | |
595 | val |= port; | |
596 | } | |
597 | ||
822974ae | 598 | val |= VIDEO_DIP_ENABLE; |
4d47dfb8 JB |
599 | val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR | |
600 | VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP); | |
822974ae PZ |
601 | |
602 | I915_WRITE(reg, val); | |
9d9740f0 | 603 | POSTING_READ(reg); |
822974ae | 604 | |
687f4d06 PZ |
605 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
606 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 607 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
608 | } |
609 | ||
610 | static void hsw_set_infoframes(struct drm_encoder *encoder, | |
6897b4b5 | 611 | bool enable, |
687f4d06 PZ |
612 | struct drm_display_mode *adjusted_mode) |
613 | { | |
0c14c7f9 PZ |
614 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
615 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
616 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
3b117c8f | 617 | u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); |
0dd87d20 | 618 | u32 val = I915_READ(reg); |
0c14c7f9 | 619 | |
afba0188 DV |
620 | assert_hdmi_port_disabled(intel_hdmi); |
621 | ||
6897b4b5 | 622 | if (!enable) { |
0c14c7f9 | 623 | I915_WRITE(reg, 0); |
9d9740f0 | 624 | POSTING_READ(reg); |
0c14c7f9 PZ |
625 | return; |
626 | } | |
627 | ||
0dd87d20 PZ |
628 | val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW | |
629 | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW); | |
630 | ||
631 | I915_WRITE(reg, val); | |
9d9740f0 | 632 | POSTING_READ(reg); |
0dd87d20 | 633 | |
687f4d06 PZ |
634 | intel_hdmi_set_avi_infoframe(encoder, adjusted_mode); |
635 | intel_hdmi_set_spd_infoframe(encoder); | |
c8bb75af | 636 | intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode); |
687f4d06 PZ |
637 | } |
638 | ||
4cde8a21 | 639 | static void intel_hdmi_prepare(struct intel_encoder *encoder) |
7d57382e | 640 | { |
c59423a3 | 641 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 642 | struct drm_i915_private *dev_priv = dev->dev_private; |
c59423a3 DV |
643 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
644 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
645 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; | |
b242b7f7 | 646 | u32 hdmi_val; |
7d57382e | 647 | |
b242b7f7 | 648 | hdmi_val = SDVO_ENCODING_HDMI; |
2af2c490 | 649 | if (!HAS_PCH_SPLIT(dev)) |
b242b7f7 | 650 | hdmi_val |= intel_hdmi->color_range; |
b599c0bc | 651 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
b242b7f7 | 652 | hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH; |
b599c0bc | 653 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
b242b7f7 | 654 | hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH; |
7d57382e | 655 | |
c59423a3 | 656 | if (crtc->config.pipe_bpp > 24) |
4f3a8bc7 | 657 | hdmi_val |= HDMI_COLOR_FORMAT_12bpc; |
020f6704 | 658 | else |
4f3a8bc7 | 659 | hdmi_val |= SDVO_COLOR_FORMAT_8bpc; |
020f6704 | 660 | |
6897b4b5 | 661 | if (crtc->config.has_hdmi_sink) |
dc0fa718 | 662 | hdmi_val |= HDMI_MODE_SELECT_HDMI; |
2e3d6006 | 663 | |
9ed109a7 | 664 | if (crtc->config.has_audio) { |
6897b4b5 | 665 | WARN_ON(!crtc->config.has_hdmi_sink); |
e0dac65e | 666 | DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n", |
c59423a3 | 667 | pipe_name(crtc->pipe)); |
b242b7f7 | 668 | hdmi_val |= SDVO_AUDIO_ENABLE; |
c59423a3 | 669 | intel_write_eld(&encoder->base, adjusted_mode); |
3c17fe4b | 670 | } |
7d57382e | 671 | |
75770564 | 672 | if (HAS_PCH_CPT(dev)) |
c59423a3 | 673 | hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
44f37d1f CML |
674 | else if (IS_CHERRYVIEW(dev)) |
675 | hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe); | |
dc0fa718 | 676 | else |
c59423a3 | 677 | hdmi_val |= SDVO_PIPE_SEL(crtc->pipe); |
7d57382e | 678 | |
b242b7f7 PZ |
679 | I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val); |
680 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e EA |
681 | } |
682 | ||
85234cdc DV |
683 | static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder, |
684 | enum pipe *pipe) | |
7d57382e | 685 | { |
85234cdc | 686 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 687 | struct drm_i915_private *dev_priv = dev->dev_private; |
85234cdc | 688 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
6d129bea | 689 | enum intel_display_power_domain power_domain; |
85234cdc DV |
690 | u32 tmp; |
691 | ||
6d129bea ID |
692 | power_domain = intel_display_port_power_domain(encoder); |
693 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
694 | return false; | |
695 | ||
b242b7f7 | 696 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
85234cdc DV |
697 | |
698 | if (!(tmp & SDVO_ENABLE)) | |
699 | return false; | |
700 | ||
701 | if (HAS_PCH_CPT(dev)) | |
702 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
71485e0a VS |
703 | else if (IS_CHERRYVIEW(dev)) |
704 | *pipe = SDVO_PORT_TO_PIPE_CHV(tmp); | |
85234cdc DV |
705 | else |
706 | *pipe = PORT_TO_PIPE(tmp); | |
707 | ||
708 | return true; | |
709 | } | |
710 | ||
045ac3b5 JB |
711 | static void intel_hdmi_get_config(struct intel_encoder *encoder, |
712 | struct intel_crtc_config *pipe_config) | |
713 | { | |
714 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
715 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
716 | u32 tmp, flags = 0; | |
18442d08 | 717 | int dotclock; |
045ac3b5 JB |
718 | |
719 | tmp = I915_READ(intel_hdmi->hdmi_reg); | |
720 | ||
721 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | |
722 | flags |= DRM_MODE_FLAG_PHSYNC; | |
723 | else | |
724 | flags |= DRM_MODE_FLAG_NHSYNC; | |
725 | ||
726 | if (tmp & SDVO_VSYNC_ACTIVE_HIGH) | |
727 | flags |= DRM_MODE_FLAG_PVSYNC; | |
728 | else | |
729 | flags |= DRM_MODE_FLAG_NVSYNC; | |
730 | ||
6897b4b5 DV |
731 | if (tmp & HDMI_MODE_SELECT_HDMI) |
732 | pipe_config->has_hdmi_sink = true; | |
733 | ||
9ed109a7 DV |
734 | if (tmp & HDMI_MODE_SELECT_HDMI) |
735 | pipe_config->has_audio = true; | |
736 | ||
045ac3b5 | 737 | pipe_config->adjusted_mode.flags |= flags; |
18442d08 VS |
738 | |
739 | if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc) | |
740 | dotclock = pipe_config->port_clock * 2 / 3; | |
741 | else | |
742 | dotclock = pipe_config->port_clock; | |
743 | ||
744 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
745 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
746 | ||
241bfc38 | 747 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
748 | } |
749 | ||
5ab432ef | 750 | static void intel_enable_hdmi(struct intel_encoder *encoder) |
7d57382e | 751 | { |
5ab432ef | 752 | struct drm_device *dev = encoder->base.dev; |
7d57382e | 753 | struct drm_i915_private *dev_priv = dev->dev_private; |
dc0fa718 | 754 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
5ab432ef | 755 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
7d57382e | 756 | u32 temp; |
2deed761 WF |
757 | u32 enable_bits = SDVO_ENABLE; |
758 | ||
9ed109a7 | 759 | if (intel_crtc->config.has_audio) |
2deed761 | 760 | enable_bits |= SDVO_AUDIO_ENABLE; |
7d57382e | 761 | |
b242b7f7 | 762 | temp = I915_READ(intel_hdmi->hdmi_reg); |
d8a2d0e0 | 763 | |
7a87c289 | 764 | /* HW workaround for IBX, we need to move the port to transcoder A |
dc0fa718 PZ |
765 | * before disabling it, so restore the transcoder select bit here. */ |
766 | if (HAS_PCH_IBX(dev)) | |
767 | enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
7a87c289 | 768 | |
d8a2d0e0 ZW |
769 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
770 | * we do this anyway which shows more stable in testing. | |
771 | */ | |
c619eed4 | 772 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
773 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
774 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
775 | } |
776 | ||
5ab432ef DV |
777 | temp |= enable_bits; |
778 | ||
b242b7f7 PZ |
779 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
780 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
781 | |
782 | /* HW workaround, need to write this twice for issue that may result | |
783 | * in first write getting masked. | |
784 | */ | |
785 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
786 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
787 | POSTING_READ(intel_hdmi->hdmi_reg); | |
7d57382e | 788 | } |
b76cf76b | 789 | } |
89b667f8 | 790 | |
b76cf76b JN |
791 | static void vlv_enable_hdmi(struct intel_encoder *encoder) |
792 | { | |
5ab432ef DV |
793 | } |
794 | ||
795 | static void intel_disable_hdmi(struct intel_encoder *encoder) | |
796 | { | |
797 | struct drm_device *dev = encoder->base.dev; | |
798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
799 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
800 | u32 temp; | |
3cce574f | 801 | u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE; |
5ab432ef | 802 | |
b242b7f7 | 803 | temp = I915_READ(intel_hdmi->hdmi_reg); |
5ab432ef DV |
804 | |
805 | /* HW workaround for IBX, we need to move the port to transcoder A | |
806 | * before disabling it. */ | |
807 | if (HAS_PCH_IBX(dev)) { | |
808 | struct drm_crtc *crtc = encoder->base.crtc; | |
809 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
810 | ||
811 | if (temp & SDVO_PIPE_B_SELECT) { | |
812 | temp &= ~SDVO_PIPE_B_SELECT; | |
b242b7f7 PZ |
813 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
814 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
815 | |
816 | /* Again we need to write this twice. */ | |
b242b7f7 PZ |
817 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
818 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
819 | |
820 | /* Transcoder selection bits only update | |
821 | * effectively on vblank. */ | |
822 | if (crtc) | |
823 | intel_wait_for_vblank(dev, pipe); | |
824 | else | |
825 | msleep(50); | |
826 | } | |
7d57382e | 827 | } |
d8a2d0e0 | 828 | |
5ab432ef DV |
829 | /* HW workaround, need to toggle enable bit off and on for 12bpc, but |
830 | * we do this anyway which shows more stable in testing. | |
831 | */ | |
832 | if (HAS_PCH_SPLIT(dev)) { | |
b242b7f7 PZ |
833 | I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE); |
834 | POSTING_READ(intel_hdmi->hdmi_reg); | |
5ab432ef DV |
835 | } |
836 | ||
837 | temp &= ~enable_bits; | |
d8a2d0e0 | 838 | |
b242b7f7 PZ |
839 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
840 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 ZW |
841 | |
842 | /* HW workaround, need to write this twice for issue that may result | |
843 | * in first write getting masked. | |
844 | */ | |
c619eed4 | 845 | if (HAS_PCH_SPLIT(dev)) { |
b242b7f7 PZ |
846 | I915_WRITE(intel_hdmi->hdmi_reg, temp); |
847 | POSTING_READ(intel_hdmi->hdmi_reg); | |
d8a2d0e0 | 848 | } |
7d57382e EA |
849 | } |
850 | ||
40478455 | 851 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
7d148ef5 DV |
852 | { |
853 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | |
854 | ||
40478455 | 855 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
7d148ef5 | 856 | return 165000; |
e3c33578 | 857 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
7d148ef5 DV |
858 | return 300000; |
859 | else | |
860 | return 225000; | |
861 | } | |
862 | ||
c19de8eb DL |
863 | static enum drm_mode_status |
864 | intel_hdmi_mode_valid(struct drm_connector *connector, | |
865 | struct drm_display_mode *mode) | |
7d57382e | 866 | { |
40478455 VS |
867 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), |
868 | true)) | |
7d57382e EA |
869 | return MODE_CLOCK_HIGH; |
870 | if (mode->clock < 20000) | |
5cbba41d | 871 | return MODE_CLOCK_LOW; |
7d57382e EA |
872 | |
873 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
874 | return MODE_NO_DBLESCAN; | |
875 | ||
876 | return MODE_OK; | |
877 | } | |
878 | ||
71800632 VS |
879 | static bool hdmi_12bpc_possible(struct intel_crtc *crtc) |
880 | { | |
881 | struct drm_device *dev = crtc->base.dev; | |
882 | struct intel_encoder *encoder; | |
883 | int count = 0, count_hdmi = 0; | |
884 | ||
f227ae9e | 885 | if (HAS_GMCH_DISPLAY(dev)) |
71800632 VS |
886 | return false; |
887 | ||
888 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) { | |
889 | if (encoder->new_crtc != crtc) | |
890 | continue; | |
891 | ||
892 | count_hdmi += encoder->type == INTEL_OUTPUT_HDMI; | |
893 | count++; | |
894 | } | |
895 | ||
896 | /* | |
897 | * HDMI 12bpc affects the clocks, so it's only possible | |
898 | * when not cloning with other encoder types. | |
899 | */ | |
900 | return count_hdmi > 0 && count_hdmi == count; | |
901 | } | |
902 | ||
5bfe2ac0 DV |
903 | bool intel_hdmi_compute_config(struct intel_encoder *encoder, |
904 | struct intel_crtc_config *pipe_config) | |
7d57382e | 905 | { |
5bfe2ac0 DV |
906 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
907 | struct drm_device *dev = encoder->base.dev; | |
908 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
241bfc38 | 909 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
40478455 | 910 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
e29c22c0 | 911 | int desired_bpp; |
3685a8f3 | 912 | |
6897b4b5 DV |
913 | pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; |
914 | ||
55bc60db VS |
915 | if (intel_hdmi->color_range_auto) { |
916 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
6897b4b5 | 917 | if (pipe_config->has_hdmi_sink && |
18316c8c | 918 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 919 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
920 | else |
921 | intel_hdmi->color_range = 0; | |
922 | } | |
923 | ||
3685a8f3 | 924 | if (intel_hdmi->color_range) |
50f3b016 | 925 | pipe_config->limited_color_range = true; |
3685a8f3 | 926 | |
5bfe2ac0 DV |
927 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) |
928 | pipe_config->has_pch_encoder = true; | |
929 | ||
9ed109a7 DV |
930 | if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio) |
931 | pipe_config->has_audio = true; | |
932 | ||
4e53c2e0 DV |
933 | /* |
934 | * HDMI is either 12 or 8, so if the display lets 10bpc sneak | |
935 | * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi | |
325b9d04 DV |
936 | * outputs. We also need to check that the higher clock still fits |
937 | * within limits. | |
4e53c2e0 | 938 | */ |
6897b4b5 | 939 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && |
71800632 VS |
940 | clock_12bpc <= portclock_limit && |
941 | hdmi_12bpc_possible(encoder->new_crtc)) { | |
e29c22c0 DV |
942 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
943 | desired_bpp = 12*3; | |
325b9d04 DV |
944 | |
945 | /* Need to adjust the port link by 1.5x for 12bpc. */ | |
ff9a6750 | 946 | pipe_config->port_clock = clock_12bpc; |
4e53c2e0 | 947 | } else { |
e29c22c0 DV |
948 | DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n"); |
949 | desired_bpp = 8*3; | |
950 | } | |
951 | ||
952 | if (!pipe_config->bw_constrained) { | |
953 | DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp); | |
954 | pipe_config->pipe_bpp = desired_bpp; | |
4e53c2e0 DV |
955 | } |
956 | ||
241bfc38 | 957 | if (adjusted_mode->crtc_clock > portclock_limit) { |
325b9d04 DV |
958 | DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n"); |
959 | return false; | |
960 | } | |
961 | ||
7d57382e EA |
962 | return true; |
963 | } | |
964 | ||
aa93d632 | 965 | static enum drm_connector_status |
930a9e28 | 966 | intel_hdmi_detect(struct drm_connector *connector, bool force) |
9dff6af8 | 967 | { |
b0ea7d37 | 968 | struct drm_device *dev = connector->dev; |
df0e9248 | 969 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); |
d63885da PZ |
970 | struct intel_digital_port *intel_dig_port = |
971 | hdmi_to_dig_port(intel_hdmi); | |
972 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
b0ea7d37 | 973 | struct drm_i915_private *dev_priv = dev->dev_private; |
f899fc64 | 974 | struct edid *edid; |
671dedd2 | 975 | enum intel_display_power_domain power_domain; |
aa93d632 | 976 | enum drm_connector_status status = connector_status_disconnected; |
9dff6af8 | 977 | |
164c8598 | 978 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 979 | connector->base.id, connector->name); |
164c8598 | 980 | |
671dedd2 ID |
981 | power_domain = intel_display_port_power_domain(intel_encoder); |
982 | intel_display_power_get(dev_priv, power_domain); | |
983 | ||
ea5b213a | 984 | intel_hdmi->has_hdmi_sink = false; |
2e3d6006 | 985 | intel_hdmi->has_audio = false; |
abedc077 | 986 | intel_hdmi->rgb_quant_range_selectable = false; |
f899fc64 | 987 | edid = drm_get_edid(connector, |
3bd7d909 DK |
988 | intel_gmbus_get_adapter(dev_priv, |
989 | intel_hdmi->ddc_bus)); | |
2ded9e27 | 990 | |
aa93d632 | 991 | if (edid) { |
be9f1c4f | 992 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
aa93d632 | 993 | status = connector_status_connected; |
b1d7e4b4 WF |
994 | if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI) |
995 | intel_hdmi->has_hdmi_sink = | |
996 | drm_detect_hdmi_monitor(edid); | |
2e3d6006 | 997 | intel_hdmi->has_audio = drm_detect_monitor_audio(edid); |
abedc077 VS |
998 | intel_hdmi->rgb_quant_range_selectable = |
999 | drm_rgb_quant_range_selectable(edid); | |
aa93d632 | 1000 | } |
aa93d632 | 1001 | kfree(edid); |
9dff6af8 | 1002 | } |
30ad48b7 | 1003 | |
55b7d6e8 | 1004 | if (status == connector_status_connected) { |
b1d7e4b4 WF |
1005 | if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO) |
1006 | intel_hdmi->has_audio = | |
1007 | (intel_hdmi->force_audio == HDMI_AUDIO_ON); | |
d63885da | 1008 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
55b7d6e8 CW |
1009 | } |
1010 | ||
671dedd2 ID |
1011 | intel_display_power_put(dev_priv, power_domain); |
1012 | ||
2ded9e27 | 1013 | return status; |
7d57382e EA |
1014 | } |
1015 | ||
1016 | static int intel_hdmi_get_modes(struct drm_connector *connector) | |
1017 | { | |
671dedd2 ID |
1018 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
1019 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
f899fc64 | 1020 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
671dedd2 ID |
1021 | enum intel_display_power_domain power_domain; |
1022 | int ret; | |
7d57382e EA |
1023 | |
1024 | /* We should parse the EDID data and find out if it's an HDMI sink so | |
1025 | * we can send audio to it. | |
1026 | */ | |
1027 | ||
671dedd2 ID |
1028 | power_domain = intel_display_port_power_domain(intel_encoder); |
1029 | intel_display_power_get(dev_priv, power_domain); | |
1030 | ||
1031 | ret = intel_ddc_get_modes(connector, | |
3bd7d909 DK |
1032 | intel_gmbus_get_adapter(dev_priv, |
1033 | intel_hdmi->ddc_bus)); | |
671dedd2 ID |
1034 | |
1035 | intel_display_power_put(dev_priv, power_domain); | |
1036 | ||
1037 | return ret; | |
7d57382e EA |
1038 | } |
1039 | ||
1aad7ac0 CW |
1040 | static bool |
1041 | intel_hdmi_detect_audio(struct drm_connector *connector) | |
1042 | { | |
671dedd2 ID |
1043 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
1044 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base); | |
1aad7ac0 | 1045 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
671dedd2 | 1046 | enum intel_display_power_domain power_domain; |
1aad7ac0 CW |
1047 | struct edid *edid; |
1048 | bool has_audio = false; | |
1049 | ||
671dedd2 ID |
1050 | power_domain = intel_display_port_power_domain(intel_encoder); |
1051 | intel_display_power_get(dev_priv, power_domain); | |
1052 | ||
1aad7ac0 | 1053 | edid = drm_get_edid(connector, |
3bd7d909 DK |
1054 | intel_gmbus_get_adapter(dev_priv, |
1055 | intel_hdmi->ddc_bus)); | |
1aad7ac0 CW |
1056 | if (edid) { |
1057 | if (edid->input & DRM_EDID_INPUT_DIGITAL) | |
1058 | has_audio = drm_detect_monitor_audio(edid); | |
1aad7ac0 CW |
1059 | kfree(edid); |
1060 | } | |
1061 | ||
671dedd2 ID |
1062 | intel_display_power_put(dev_priv, power_domain); |
1063 | ||
1aad7ac0 CW |
1064 | return has_audio; |
1065 | } | |
1066 | ||
55b7d6e8 CW |
1067 | static int |
1068 | intel_hdmi_set_property(struct drm_connector *connector, | |
ed517fbb PZ |
1069 | struct drm_property *property, |
1070 | uint64_t val) | |
55b7d6e8 CW |
1071 | { |
1072 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | |
da63a9f2 PZ |
1073 | struct intel_digital_port *intel_dig_port = |
1074 | hdmi_to_dig_port(intel_hdmi); | |
e953fd7b | 1075 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
55b7d6e8 CW |
1076 | int ret; |
1077 | ||
662595df | 1078 | ret = drm_object_property_set_value(&connector->base, property, val); |
55b7d6e8 CW |
1079 | if (ret) |
1080 | return ret; | |
1081 | ||
3f43c48d | 1082 | if (property == dev_priv->force_audio_property) { |
b1d7e4b4 | 1083 | enum hdmi_force_audio i = val; |
1aad7ac0 CW |
1084 | bool has_audio; |
1085 | ||
1086 | if (i == intel_hdmi->force_audio) | |
55b7d6e8 CW |
1087 | return 0; |
1088 | ||
1aad7ac0 | 1089 | intel_hdmi->force_audio = i; |
55b7d6e8 | 1090 | |
b1d7e4b4 | 1091 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1092 | has_audio = intel_hdmi_detect_audio(connector); |
1093 | else | |
b1d7e4b4 | 1094 | has_audio = (i == HDMI_AUDIO_ON); |
1aad7ac0 | 1095 | |
b1d7e4b4 WF |
1096 | if (i == HDMI_AUDIO_OFF_DVI) |
1097 | intel_hdmi->has_hdmi_sink = 0; | |
55b7d6e8 | 1098 | |
1aad7ac0 | 1099 | intel_hdmi->has_audio = has_audio; |
55b7d6e8 CW |
1100 | goto done; |
1101 | } | |
1102 | ||
e953fd7b | 1103 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
1104 | bool old_auto = intel_hdmi->color_range_auto; |
1105 | uint32_t old_range = intel_hdmi->color_range; | |
1106 | ||
55bc60db VS |
1107 | switch (val) { |
1108 | case INTEL_BROADCAST_RGB_AUTO: | |
1109 | intel_hdmi->color_range_auto = true; | |
1110 | break; | |
1111 | case INTEL_BROADCAST_RGB_FULL: | |
1112 | intel_hdmi->color_range_auto = false; | |
1113 | intel_hdmi->color_range = 0; | |
1114 | break; | |
1115 | case INTEL_BROADCAST_RGB_LIMITED: | |
1116 | intel_hdmi->color_range_auto = false; | |
4f3a8bc7 | 1117 | intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1118 | break; |
1119 | default: | |
1120 | return -EINVAL; | |
1121 | } | |
ae4edb80 DV |
1122 | |
1123 | if (old_auto == intel_hdmi->color_range_auto && | |
1124 | old_range == intel_hdmi->color_range) | |
1125 | return 0; | |
1126 | ||
e953fd7b CW |
1127 | goto done; |
1128 | } | |
1129 | ||
94a11ddc VK |
1130 | if (property == connector->dev->mode_config.aspect_ratio_property) { |
1131 | switch (val) { | |
1132 | case DRM_MODE_PICTURE_ASPECT_NONE: | |
1133 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
1134 | break; | |
1135 | case DRM_MODE_PICTURE_ASPECT_4_3: | |
1136 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3; | |
1137 | break; | |
1138 | case DRM_MODE_PICTURE_ASPECT_16_9: | |
1139 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9; | |
1140 | break; | |
1141 | default: | |
1142 | return -EINVAL; | |
1143 | } | |
1144 | goto done; | |
1145 | } | |
1146 | ||
55b7d6e8 CW |
1147 | return -EINVAL; |
1148 | ||
1149 | done: | |
c0c36b94 CW |
1150 | if (intel_dig_port->base.base.crtc) |
1151 | intel_crtc_restore_mode(intel_dig_port->base.base.crtc); | |
55b7d6e8 CW |
1152 | |
1153 | return 0; | |
1154 | } | |
1155 | ||
13732ba7 JB |
1156 | static void intel_hdmi_pre_enable(struct intel_encoder *encoder) |
1157 | { | |
1158 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base); | |
1159 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1160 | struct drm_display_mode *adjusted_mode = | |
1161 | &intel_crtc->config.adjusted_mode; | |
1162 | ||
4cde8a21 DV |
1163 | intel_hdmi_prepare(encoder); |
1164 | ||
6897b4b5 DV |
1165 | intel_hdmi->set_infoframes(&encoder->base, |
1166 | intel_crtc->config.has_hdmi_sink, | |
1167 | adjusted_mode); | |
13732ba7 JB |
1168 | } |
1169 | ||
9514ac6e | 1170 | static void vlv_hdmi_pre_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1171 | { |
1172 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
13732ba7 | 1173 | struct intel_hdmi *intel_hdmi = &dport->hdmi; |
89b667f8 JB |
1174 | struct drm_device *dev = encoder->base.dev; |
1175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1176 | struct intel_crtc *intel_crtc = | |
1177 | to_intel_crtc(encoder->base.crtc); | |
13732ba7 JB |
1178 | struct drm_display_mode *adjusted_mode = |
1179 | &intel_crtc->config.adjusted_mode; | |
e4607fcf | 1180 | enum dpio_channel port = vlv_dport_to_channel(dport); |
89b667f8 JB |
1181 | int pipe = intel_crtc->pipe; |
1182 | u32 val; | |
1183 | ||
89b667f8 | 1184 | /* Enable clock channels for this port */ |
0980a60f | 1185 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1186 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
89b667f8 JB |
1187 | val = 0; |
1188 | if (pipe) | |
1189 | val |= (1<<21); | |
1190 | else | |
1191 | val &= ~(1<<21); | |
1192 | val |= 0x001000c4; | |
ab3c759a | 1193 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
89b667f8 JB |
1194 | |
1195 | /* HDMI 1.0V-2dB */ | |
ab3c759a CML |
1196 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); |
1197 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); | |
1198 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); | |
1199 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); | |
1200 | vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); | |
1201 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); | |
1202 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1203 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
89b667f8 JB |
1204 | |
1205 | /* Program lane clock */ | |
ab3c759a CML |
1206 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
1207 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); | |
0980a60f | 1208 | mutex_unlock(&dev_priv->dpio_lock); |
b76cf76b | 1209 | |
6897b4b5 DV |
1210 | intel_hdmi->set_infoframes(&encoder->base, |
1211 | intel_crtc->config.has_hdmi_sink, | |
1212 | adjusted_mode); | |
13732ba7 | 1213 | |
b76cf76b JN |
1214 | intel_enable_hdmi(encoder); |
1215 | ||
e4607fcf | 1216 | vlv_wait_port_ready(dev_priv, dport); |
89b667f8 JB |
1217 | } |
1218 | ||
9514ac6e | 1219 | static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
89b667f8 JB |
1220 | { |
1221 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1222 | struct drm_device *dev = encoder->base.dev; | |
1223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5e69f97f CML |
1224 | struct intel_crtc *intel_crtc = |
1225 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1226 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1227 | int pipe = intel_crtc->pipe; |
89b667f8 | 1228 | |
4cde8a21 DV |
1229 | intel_hdmi_prepare(encoder); |
1230 | ||
89b667f8 | 1231 | /* Program Tx lane resets to default */ |
0980a60f | 1232 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 1233 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
89b667f8 JB |
1234 | DPIO_PCS_TX_LANE2_RESET | |
1235 | DPIO_PCS_TX_LANE1_RESET); | |
ab3c759a | 1236 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
89b667f8 JB |
1237 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
1238 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | | |
1239 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | | |
1240 | DPIO_PCS_CLK_SOFT_RESET); | |
1241 | ||
1242 | /* Fix up inter-pair skew failure */ | |
ab3c759a CML |
1243 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
1244 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); | |
1245 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); | |
1246 | ||
1247 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); | |
1248 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); | |
0980a60f | 1249 | mutex_unlock(&dev_priv->dpio_lock); |
89b667f8 JB |
1250 | } |
1251 | ||
9197c88b VS |
1252 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder) |
1253 | { | |
1254 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1255 | struct drm_device *dev = encoder->base.dev; | |
1256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1257 | struct intel_crtc *intel_crtc = | |
1258 | to_intel_crtc(encoder->base.crtc); | |
1259 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1260 | enum pipe pipe = intel_crtc->pipe; | |
1261 | u32 val; | |
1262 | ||
625695f8 VS |
1263 | intel_hdmi_prepare(encoder); |
1264 | ||
9197c88b VS |
1265 | mutex_lock(&dev_priv->dpio_lock); |
1266 | ||
b9e5ac3c VS |
1267 | /* program left/right clock distribution */ |
1268 | if (pipe != PIPE_B) { | |
1269 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1270 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1271 | if (ch == DPIO_CH0) | |
1272 | val |= CHV_BUFLEFTENA1_FORCE; | |
1273 | if (ch == DPIO_CH1) | |
1274 | val |= CHV_BUFRIGHTENA1_FORCE; | |
1275 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1276 | } else { | |
1277 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1278 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1279 | if (ch == DPIO_CH0) | |
1280 | val |= CHV_BUFLEFTENA2_FORCE; | |
1281 | if (ch == DPIO_CH1) | |
1282 | val |= CHV_BUFRIGHTENA2_FORCE; | |
1283 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1284 | } | |
1285 | ||
9197c88b VS |
1286 | /* program clock channel usage */ |
1287 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); | |
1288 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1289 | if (pipe != PIPE_B) | |
1290 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1291 | else | |
1292 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1293 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); | |
1294 | ||
1295 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); | |
1296 | val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; | |
1297 | if (pipe != PIPE_B) | |
1298 | val &= ~CHV_PCS_USEDCLKCHANNEL; | |
1299 | else | |
1300 | val |= CHV_PCS_USEDCLKCHANNEL; | |
1301 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); | |
1302 | ||
1303 | /* | |
1304 | * This a a bit weird since generally CL | |
1305 | * matches the pipe, but here we need to | |
1306 | * pick the CL based on the port. | |
1307 | */ | |
1308 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); | |
1309 | if (pipe != PIPE_B) | |
1310 | val &= ~CHV_CMN_USEDCLKCHANNEL; | |
1311 | else | |
1312 | val |= CHV_CMN_USEDCLKCHANNEL; | |
1313 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); | |
1314 | ||
1315 | mutex_unlock(&dev_priv->dpio_lock); | |
1316 | } | |
1317 | ||
9514ac6e | 1318 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder) |
89b667f8 JB |
1319 | { |
1320 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1321 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
5e69f97f CML |
1322 | struct intel_crtc *intel_crtc = |
1323 | to_intel_crtc(encoder->base.crtc); | |
e4607fcf | 1324 | enum dpio_channel port = vlv_dport_to_channel(dport); |
5e69f97f | 1325 | int pipe = intel_crtc->pipe; |
89b667f8 JB |
1326 | |
1327 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | |
1328 | mutex_lock(&dev_priv->dpio_lock); | |
ab3c759a CML |
1329 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); |
1330 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); | |
89b667f8 JB |
1331 | mutex_unlock(&dev_priv->dpio_lock); |
1332 | } | |
1333 | ||
580d3811 VS |
1334 | static void chv_hdmi_post_disable(struct intel_encoder *encoder) |
1335 | { | |
1336 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1337 | struct drm_device *dev = encoder->base.dev; | |
1338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1339 | struct intel_crtc *intel_crtc = | |
1340 | to_intel_crtc(encoder->base.crtc); | |
1341 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1342 | enum pipe pipe = intel_crtc->pipe; | |
1343 | u32 val; | |
1344 | ||
1345 | mutex_lock(&dev_priv->dpio_lock); | |
1346 | ||
1347 | /* Propagate soft reset to data lane reset */ | |
97fd4d5c | 1348 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1349 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c | 1350 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
d2152b25 | 1351 | |
97fd4d5c VS |
1352 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); |
1353 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1354 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1355 | ||
1356 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1357 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1358 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
1359 | ||
1360 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); | |
580d3811 | 1361 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1362 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
580d3811 VS |
1363 | |
1364 | mutex_unlock(&dev_priv->dpio_lock); | |
1365 | } | |
1366 | ||
e4a1d846 CML |
1367 | static void chv_hdmi_pre_enable(struct intel_encoder *encoder) |
1368 | { | |
1369 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | |
1370 | struct drm_device *dev = encoder->base.dev; | |
1371 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1372 | struct intel_crtc *intel_crtc = | |
1373 | to_intel_crtc(encoder->base.crtc); | |
1374 | enum dpio_channel ch = vlv_dport_to_channel(dport); | |
1375 | int pipe = intel_crtc->pipe; | |
1376 | int data, i; | |
1377 | u32 val; | |
1378 | ||
e4a1d846 | 1379 | mutex_lock(&dev_priv->dpio_lock); |
949c1d43 VS |
1380 | |
1381 | /* Deassert soft data lane reset*/ | |
97fd4d5c | 1382 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); |
d2152b25 | 1383 | val |= CHV_PCS_REQ_SOFTRESET_EN; |
97fd4d5c VS |
1384 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); |
1385 | ||
1386 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); | |
1387 | val |= CHV_PCS_REQ_SOFTRESET_EN; | |
1388 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); | |
1389 | ||
1390 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); | |
1391 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); | |
1392 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); | |
d2152b25 | 1393 | |
97fd4d5c | 1394 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); |
949c1d43 | 1395 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
97fd4d5c | 1396 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); |
949c1d43 VS |
1397 | |
1398 | /* Program Tx latency optimal setting */ | |
e4a1d846 CML |
1399 | for (i = 0; i < 4; i++) { |
1400 | /* Set the latency optimal bit */ | |
1401 | data = (i == 1) ? 0x0 : 0x6; | |
1402 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), | |
1403 | data << DPIO_FRC_LATENCY_SHFIT); | |
1404 | ||
1405 | /* Set the upar bit */ | |
1406 | data = (i == 1) ? 0x0 : 0x1; | |
1407 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), | |
1408 | data << DPIO_UPAR_SHIFT); | |
1409 | } | |
1410 | ||
1411 | /* Data lane stagger programming */ | |
1412 | /* FIXME: Fix up value only after power analysis */ | |
1413 | ||
1414 | /* Clear calc init */ | |
1966e59e VS |
1415 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1416 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
1417 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1418 | ||
1419 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1420 | val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); | |
1421 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1422 | |
1423 | /* FIXME: Program the support xxx V-dB */ | |
1424 | /* Use 800mV-0dB */ | |
f72df8db VS |
1425 | for (i = 0; i < 4; i++) { |
1426 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); | |
1427 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; | |
1428 | val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT; | |
1429 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); | |
1430 | } | |
e4a1d846 | 1431 | |
f72df8db VS |
1432 | for (i = 0; i < 4; i++) { |
1433 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); | |
1434 | val &= ~DPIO_SWING_MARGIN_MASK; | |
1435 | val |= 102 << DPIO_SWING_MARGIN_SHIFT; | |
1436 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); | |
1437 | } | |
e4a1d846 CML |
1438 | |
1439 | /* Disable unique transition scale */ | |
f72df8db VS |
1440 | for (i = 0; i < 4; i++) { |
1441 | val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); | |
1442 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; | |
1443 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); | |
1444 | } | |
e4a1d846 CML |
1445 | |
1446 | /* Additional steps for 1200mV-0dB */ | |
1447 | #if 0 | |
1448 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); | |
1449 | if (ch) | |
1450 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1; | |
1451 | else | |
1452 | val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0; | |
1453 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); | |
1454 | ||
1455 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), | |
1456 | vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) | | |
1457 | (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT)); | |
1458 | #endif | |
1459 | /* Start swing calculation */ | |
1966e59e VS |
1460 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); |
1461 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1462 | vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); | |
1463 | ||
1464 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); | |
1465 | val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; | |
1466 | vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); | |
e4a1d846 CML |
1467 | |
1468 | /* LRC Bypass */ | |
1469 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1470 | val |= DPIO_LRC_BYPASS; | |
1471 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); | |
1472 | ||
1473 | mutex_unlock(&dev_priv->dpio_lock); | |
1474 | ||
1475 | intel_enable_hdmi(encoder); | |
1476 | ||
1477 | vlv_wait_port_ready(dev_priv, dport); | |
1478 | } | |
1479 | ||
7d57382e EA |
1480 | static void intel_hdmi_destroy(struct drm_connector *connector) |
1481 | { | |
7d57382e | 1482 | drm_connector_cleanup(connector); |
674e2d08 | 1483 | kfree(connector); |
7d57382e EA |
1484 | } |
1485 | ||
7d57382e | 1486 | static const struct drm_connector_funcs intel_hdmi_connector_funcs = { |
5ab432ef | 1487 | .dpms = intel_connector_dpms, |
7d57382e EA |
1488 | .detect = intel_hdmi_detect, |
1489 | .fill_modes = drm_helper_probe_single_connector_modes, | |
55b7d6e8 | 1490 | .set_property = intel_hdmi_set_property, |
7d57382e EA |
1491 | .destroy = intel_hdmi_destroy, |
1492 | }; | |
1493 | ||
1494 | static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = { | |
1495 | .get_modes = intel_hdmi_get_modes, | |
1496 | .mode_valid = intel_hdmi_mode_valid, | |
df0e9248 | 1497 | .best_encoder = intel_best_encoder, |
7d57382e EA |
1498 | }; |
1499 | ||
7d57382e | 1500 | static const struct drm_encoder_funcs intel_hdmi_enc_funcs = { |
ea5b213a | 1501 | .destroy = intel_encoder_destroy, |
7d57382e EA |
1502 | }; |
1503 | ||
94a11ddc VK |
1504 | static void |
1505 | intel_attach_aspect_ratio_property(struct drm_connector *connector) | |
1506 | { | |
1507 | if (!drm_mode_create_aspect_ratio_property(connector->dev)) | |
1508 | drm_object_attach_property(&connector->base, | |
1509 | connector->dev->mode_config.aspect_ratio_property, | |
1510 | DRM_MODE_PICTURE_ASPECT_NONE); | |
1511 | } | |
1512 | ||
55b7d6e8 CW |
1513 | static void |
1514 | intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) | |
1515 | { | |
3f43c48d | 1516 | intel_attach_force_audio_property(connector); |
e953fd7b | 1517 | intel_attach_broadcast_rgb_property(connector); |
55bc60db | 1518 | intel_hdmi->color_range_auto = true; |
94a11ddc VK |
1519 | intel_attach_aspect_ratio_property(connector); |
1520 | intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE; | |
55b7d6e8 CW |
1521 | } |
1522 | ||
00c09d70 PZ |
1523 | void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, |
1524 | struct intel_connector *intel_connector) | |
7d57382e | 1525 | { |
b9cb234c PZ |
1526 | struct drm_connector *connector = &intel_connector->base; |
1527 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | |
1528 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | |
1529 | struct drm_device *dev = intel_encoder->base.dev; | |
7d57382e | 1530 | struct drm_i915_private *dev_priv = dev->dev_private; |
174edf1f | 1531 | enum port port = intel_dig_port->port; |
373a3cf7 | 1532 | |
7d57382e | 1533 | drm_connector_init(dev, connector, &intel_hdmi_connector_funcs, |
8d91104a | 1534 | DRM_MODE_CONNECTOR_HDMIA); |
7d57382e EA |
1535 | drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); |
1536 | ||
c3febcc4 | 1537 | connector->interlace_allowed = 1; |
7d57382e | 1538 | connector->doublescan_allowed = 0; |
573e74ad | 1539 | connector->stereo_allowed = 1; |
66a9278e | 1540 | |
08d644ad DV |
1541 | switch (port) { |
1542 | case PORT_B: | |
f899fc64 | 1543 | intel_hdmi->ddc_bus = GMBUS_PORT_DPB; |
1d843f9d | 1544 | intel_encoder->hpd_pin = HPD_PORT_B; |
08d644ad DV |
1545 | break; |
1546 | case PORT_C: | |
7ceae0a5 | 1547 | intel_hdmi->ddc_bus = GMBUS_PORT_DPC; |
1d843f9d | 1548 | intel_encoder->hpd_pin = HPD_PORT_C; |
08d644ad DV |
1549 | break; |
1550 | case PORT_D: | |
c0c35329 VS |
1551 | if (IS_CHERRYVIEW(dev)) |
1552 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV; | |
1553 | else | |
1554 | intel_hdmi->ddc_bus = GMBUS_PORT_DPD; | |
1d843f9d | 1555 | intel_encoder->hpd_pin = HPD_PORT_D; |
08d644ad DV |
1556 | break; |
1557 | case PORT_A: | |
1d843f9d | 1558 | intel_encoder->hpd_pin = HPD_PORT_A; |
08d644ad DV |
1559 | /* Internal port only for eDP. */ |
1560 | default: | |
6e4c1677 | 1561 | BUG(); |
f8aed700 | 1562 | } |
7d57382e | 1563 | |
7637bfdb | 1564 | if (IS_VALLEYVIEW(dev)) { |
90b107c8 | 1565 | intel_hdmi->write_infoframe = vlv_write_infoframe; |
687f4d06 | 1566 | intel_hdmi->set_infoframes = vlv_set_infoframes; |
b98856a8 | 1567 | } else if (IS_G4X(dev)) { |
7637bfdb JB |
1568 | intel_hdmi->write_infoframe = g4x_write_infoframe; |
1569 | intel_hdmi->set_infoframes = g4x_set_infoframes; | |
22b8bf17 | 1570 | } else if (HAS_DDI(dev)) { |
8c5f5f7c | 1571 | intel_hdmi->write_infoframe = hsw_write_infoframe; |
687f4d06 | 1572 | intel_hdmi->set_infoframes = hsw_set_infoframes; |
fdf1250a PZ |
1573 | } else if (HAS_PCH_IBX(dev)) { |
1574 | intel_hdmi->write_infoframe = ibx_write_infoframe; | |
687f4d06 | 1575 | intel_hdmi->set_infoframes = ibx_set_infoframes; |
fdf1250a PZ |
1576 | } else { |
1577 | intel_hdmi->write_infoframe = cpt_write_infoframe; | |
687f4d06 | 1578 | intel_hdmi->set_infoframes = cpt_set_infoframes; |
64a8fc01 | 1579 | } |
45187ace | 1580 | |
affa9354 | 1581 | if (HAS_DDI(dev)) |
bcbc889b PZ |
1582 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
1583 | else | |
1584 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 1585 | intel_connector->unregister = intel_connector_unregister; |
b9cb234c PZ |
1586 | |
1587 | intel_hdmi_add_properties(intel_hdmi, connector); | |
1588 | ||
1589 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
34ea3d38 | 1590 | drm_connector_register(connector); |
b9cb234c PZ |
1591 | |
1592 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written | |
1593 | * 0xd. Failure to do so will result in spurious interrupts being | |
1594 | * generated on the port when a cable is not attached. | |
1595 | */ | |
1596 | if (IS_G4X(dev) && !IS_GM45(dev)) { | |
1597 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); | |
1598 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); | |
1599 | } | |
1600 | } | |
1601 | ||
b242b7f7 | 1602 | void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port) |
b9cb234c PZ |
1603 | { |
1604 | struct intel_digital_port *intel_dig_port; | |
1605 | struct intel_encoder *intel_encoder; | |
b9cb234c PZ |
1606 | struct intel_connector *intel_connector; |
1607 | ||
b14c5679 | 1608 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
b9cb234c PZ |
1609 | if (!intel_dig_port) |
1610 | return; | |
1611 | ||
b14c5679 | 1612 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
b9cb234c PZ |
1613 | if (!intel_connector) { |
1614 | kfree(intel_dig_port); | |
1615 | return; | |
1616 | } | |
1617 | ||
1618 | intel_encoder = &intel_dig_port->base; | |
b9cb234c PZ |
1619 | |
1620 | drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs, | |
1621 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1622 | |
5bfe2ac0 | 1623 | intel_encoder->compute_config = intel_hdmi_compute_config; |
00c09d70 PZ |
1624 | intel_encoder->disable = intel_disable_hdmi; |
1625 | intel_encoder->get_hw_state = intel_hdmi_get_hw_state; | |
045ac3b5 | 1626 | intel_encoder->get_config = intel_hdmi_get_config; |
e4a1d846 | 1627 | if (IS_CHERRYVIEW(dev)) { |
9197c88b | 1628 | intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable; |
e4a1d846 CML |
1629 | intel_encoder->pre_enable = chv_hdmi_pre_enable; |
1630 | intel_encoder->enable = vlv_enable_hdmi; | |
580d3811 | 1631 | intel_encoder->post_disable = chv_hdmi_post_disable; |
e4a1d846 | 1632 | } else if (IS_VALLEYVIEW(dev)) { |
9514ac6e CML |
1633 | intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable; |
1634 | intel_encoder->pre_enable = vlv_hdmi_pre_enable; | |
b76cf76b | 1635 | intel_encoder->enable = vlv_enable_hdmi; |
9514ac6e | 1636 | intel_encoder->post_disable = vlv_hdmi_post_disable; |
b76cf76b | 1637 | } else { |
13732ba7 | 1638 | intel_encoder->pre_enable = intel_hdmi_pre_enable; |
b76cf76b | 1639 | intel_encoder->enable = intel_enable_hdmi; |
89b667f8 | 1640 | } |
5ab432ef | 1641 | |
b9cb234c | 1642 | intel_encoder->type = INTEL_OUTPUT_HDMI; |
882ec384 VS |
1643 | if (IS_CHERRYVIEW(dev)) { |
1644 | if (port == PORT_D) | |
1645 | intel_encoder->crtc_mask = 1 << 2; | |
1646 | else | |
1647 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
1648 | } else { | |
1649 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
1650 | } | |
301ea74a | 1651 | intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG; |
c6f1495d VS |
1652 | /* |
1653 | * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems | |
1654 | * to work on real hardware. And since g4x can send infoframes to | |
1655 | * only one port anyway, nothing is lost by allowing it. | |
1656 | */ | |
1657 | if (IS_G4X(dev)) | |
1658 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | |
7d57382e | 1659 | |
174edf1f | 1660 | intel_dig_port->port = port; |
b242b7f7 | 1661 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
b9cb234c | 1662 | intel_dig_port->dp.output_reg = 0; |
55b7d6e8 | 1663 | |
b9cb234c | 1664 | intel_hdmi_init_connector(intel_dig_port, intel_connector); |
7d57382e | 1665 | } |