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drm/i915/kbl: Add WaDisableGamClockGating
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7 34/**
18afd443
JN		 35 * DOC: RC6
36 *
dc39fff7
BW		 37 * RC6 is a special power stage which allows the GPU to enter an very
38 * low-voltage mode when idle, using down to 0V while at this stage. This
39 * stage is entered automatically when the GPU is idle when RC6 support is
40 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
41 *
42 * There are different RC6 modes available in Intel GPU, which differentiate
43 * among each other with the latency required to enter and leave RC6 and
44 * voltage consumed by the GPU in different states.
45 *
46 * The combination of the following flags define which states GPU is allowed
47 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
48 * RC6pp is deepest RC6. Their support by hardware varies according to the
49 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
50 * which brings the most power savings; deeper states save more power, but
51 * require higher latency to switch to and wake up.
52 */
53#define INTEL_RC6_ENABLE (1<<0)
54#define INTEL_RC6p_ENABLE (1<<1)
55#define INTEL_RC6pp_ENABLE (1<<2)
56
11b28341 57static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 58{
32608ca2
ID		 59 struct drm_i915_private *dev_priv = dev->dev_private;
60
11b28341 61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
da0a0aca
DV		 62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
11b28341
MK		 65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
67}
68
69static void bxt_init_clock_gating(struct drm_device *dev)
70{
71 struct drm_i915_private *dev_priv = dev->dev_private;
72
73 gen9_init_clock_gating(dev);
74
a7546159
NH		 75 /* WaDisableSDEUnitClockGating:bxt */
76 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
78
32608ca2
ID		 79 /*
80 * FIXME:
868434c5 81 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 82 */
32608ca2 83 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 84 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 85
86 /*
87 * Wa: Backlight PWM may stop in the asserted state, causing backlight
88 * to stay fully on.
89 */
90 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
91 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
92 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 93}
94
c921aba8
DV		 95static void i915_pineview_get_mem_freq(struct drm_device *dev)
96{
50227e1c 97 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 98 u32 tmp;
99
100 tmp = I915_READ(CLKCFG);
101
102 switch (tmp & CLKCFG_FSB_MASK) {
103 case CLKCFG_FSB_533:
104 dev_priv->fsb_freq = 533; /* 133*4 */
105 break;
106 case CLKCFG_FSB_800:
107 dev_priv->fsb_freq = 800; /* 200*4 */
108 break;
109 case CLKCFG_FSB_667:
110 dev_priv->fsb_freq = 667; /* 167*4 */
111 break;
112 case CLKCFG_FSB_400:
113 dev_priv->fsb_freq = 400; /* 100*4 */
114 break;
115 }
116
117 switch (tmp & CLKCFG_MEM_MASK) {
118 case CLKCFG_MEM_533:
119 dev_priv->mem_freq = 533;
120 break;
121 case CLKCFG_MEM_667:
122 dev_priv->mem_freq = 667;
123 break;
124 case CLKCFG_MEM_800:
125 dev_priv->mem_freq = 800;
126 break;
127 }
128
129 /* detect pineview DDR3 setting */
130 tmp = I915_READ(CSHRDDR3CTL);
131 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
132}
133
134static void i915_ironlake_get_mem_freq(struct drm_device *dev)
135{
50227e1c 136 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 137 u16 ddrpll, csipll;
138
139 ddrpll = I915_READ16(DDRMPLL1);
140 csipll = I915_READ16(CSIPLL0);
141
142 switch (ddrpll & 0xff) {
143 case 0xc:
144 dev_priv->mem_freq = 800;
145 break;
146 case 0x10:
147 dev_priv->mem_freq = 1066;
148 break;
149 case 0x14:
150 dev_priv->mem_freq = 1333;
151 break;
152 case 0x18:
153 dev_priv->mem_freq = 1600;
154 break;
155 default:
156 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
157 ddrpll & 0xff);
158 dev_priv->mem_freq = 0;
159 break;
160 }
161
20e4d407 162 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 163
164 switch (csipll & 0x3ff) {
165 case 0x00c:
166 dev_priv->fsb_freq = 3200;
167 break;
168 case 0x00e:
169 dev_priv->fsb_freq = 3733;
170 break;
171 case 0x010:
172 dev_priv->fsb_freq = 4266;
173 break;
174 case 0x012:
175 dev_priv->fsb_freq = 4800;
176 break;
177 case 0x014:
178 dev_priv->fsb_freq = 5333;
179 break;
180 case 0x016:
181 dev_priv->fsb_freq = 5866;
182 break;
183 case 0x018:
184 dev_priv->fsb_freq = 6400;
185 break;
186 default:
187 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
188 csipll & 0x3ff);
189 dev_priv->fsb_freq = 0;
190 break;
191 }
192
193 if (dev_priv->fsb_freq == 3200) {
20e4d407 194 dev_priv->ips.c_m = 0;
c921aba8 195 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 196 dev_priv->ips.c_m = 1;
c921aba8 197 } else {
20e4d407 198 dev_priv->ips.c_m = 2;
c921aba8
DV		 199 }
200}
201
b445e3b0
ED		 202static const struct cxsr_latency cxsr_latency_table[] = {
203 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
204 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
205 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
206 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
207 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
208
209 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
210 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
211 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
212 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
213 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
214
215 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
216 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
217 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
218 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
219 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
220
221 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
222 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
223 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
224 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
225 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
226
227 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
228 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
229 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
230 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
231 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
232
233 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
234 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
235 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
236 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
237 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
238};
239
63c62275 240static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 241 int is_ddr3,
242 int fsb,
243 int mem)
244{
245 const struct cxsr_latency *latency;
246 int i;
247
248 if (fsb == 0 || mem == 0)
249 return NULL;
250
251 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
252 latency = &cxsr_latency_table[i];
253 if (is_desktop == latency->is_desktop &&
254 is_ddr3 == latency->is_ddr3 &&
255 fsb == latency->fsb_freq && mem == latency->mem_freq)
256 return latency;
257 }
258
259 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
260
261 return NULL;
262}
263
fc1ac8de
VS		 264static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
265{
266 u32 val;
267
268 mutex_lock(&dev_priv->rps.hw_lock);
269
270 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
271 if (enable)
272 val &= ~FORCE_DDR_HIGH_FREQ;
273 else
274 val |= FORCE_DDR_HIGH_FREQ;
275 val &= ~FORCE_DDR_LOW_FREQ;
276 val |= FORCE_DDR_FREQ_REQ_ACK;
277 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
278
279 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
280 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
281 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
282
283 mutex_unlock(&dev_priv->rps.hw_lock);
284}
285
cfb41411
VS		 286static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
287{
288 u32 val;
289
290 mutex_lock(&dev_priv->rps.hw_lock);
291
292 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
293 if (enable)
294 val |= DSP_MAXFIFO_PM5_ENABLE;
295 else
296 val &= ~DSP_MAXFIFO_PM5_ENABLE;
297 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
298
299 mutex_unlock(&dev_priv->rps.hw_lock);
300}
301
f4998963
VS		 302#define FW_WM(value, plane) \
303 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
304
5209b1f4 305void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 306{
5209b1f4
ID		 307 struct drm_device *dev = dev_priv->dev;
308 u32 val;
b445e3b0 309
666a4537 310 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 311 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 312 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 313 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 314 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
315 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 316 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 317 } else if (IS_PINEVIEW(dev)) {
318 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
319 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
320 I915_WRITE(DSPFW3, val);
a7a6c498 321 POSTING_READ(DSPFW3);
5209b1f4
ID		 322 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
323 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
324 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
325 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 326 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 327 } else if (IS_I915GM(dev)) {
328 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
329 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
330 I915_WRITE(INSTPM, val);
a7a6c498 331 POSTING_READ(INSTPM);
5209b1f4
ID		 332 } else {
333 return;
334 }
b445e3b0 335
5209b1f4
ID		 336 DRM_DEBUG_KMS("memory self-refresh is %s\n",
337 enable ? "enabled" : "disabled");
b445e3b0
ED		 338}
339
fc1ac8de 340
b445e3b0
ED		 341/*
342 * Latency for FIFO fetches is dependent on several factors:
343 * - memory configuration (speed, channels)
344 * - chipset
345 * - current MCH state
346 * It can be fairly high in some situations, so here we assume a fairly
347 * pessimal value. It's a tradeoff between extra memory fetches (if we
348 * set this value too high, the FIFO will fetch frequently to stay full)
349 * and power consumption (set it too low to save power and we might see
350 * FIFO underruns and display "flicker").
351 *
352 * A value of 5us seems to be a good balance; safe for very low end
353 * platforms but not overly aggressive on lower latency configs.
354 */
5aef6003 355static const int pessimal_latency_ns = 5000;
b445e3b0 356
b5004720
VS		 357#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
358 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
359
360static int vlv_get_fifo_size(struct drm_device *dev,
361 enum pipe pipe, int plane)
362{
363 struct drm_i915_private *dev_priv = dev->dev_private;
364 int sprite0_start, sprite1_start, size;
365
366 switch (pipe) {
367 uint32_t dsparb, dsparb2, dsparb3;
368 case PIPE_A:
369 dsparb = I915_READ(DSPARB);
370 dsparb2 = I915_READ(DSPARB2);
371 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
372 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
373 break;
374 case PIPE_B:
375 dsparb = I915_READ(DSPARB);
376 dsparb2 = I915_READ(DSPARB2);
377 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
378 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
379 break;
380 case PIPE_C:
381 dsparb2 = I915_READ(DSPARB2);
382 dsparb3 = I915_READ(DSPARB3);
383 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
384 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
385 break;
386 default:
387 return 0;
388 }
389
390 switch (plane) {
391 case 0:
392 size = sprite0_start;
393 break;
394 case 1:
395 size = sprite1_start - sprite0_start;
396 break;
397 case 2:
398 size = 512 - 1 - sprite1_start;
399 break;
400 default:
401 return 0;
402 }
403
404 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
405 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
406 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
407 size);
408
409 return size;
410}
411
1fa61106 412static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 413{
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t dsparb = I915_READ(DSPARB);
416 int size;
417
418 size = dsparb & 0x7f;
419 if (plane)
420 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
421
422 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
423 plane ? "B" : "A", size);
424
425 return size;
426}
427
feb56b93 428static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 429{
430 struct drm_i915_private *dev_priv = dev->dev_private;
431 uint32_t dsparb = I915_READ(DSPARB);
432 int size;
433
434 size = dsparb & 0x1ff;
435 if (plane)
436 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
437 size >>= 1; /* Convert to cachelines */
438
439 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
440 plane ? "B" : "A", size);
441
442 return size;
443}
444
1fa61106 445static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 uint32_t dsparb = I915_READ(DSPARB);
449 int size;
450
451 size = dsparb & 0x7f;
452 size >>= 2; /* Convert to cachelines */
453
454 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
455 plane ? "B" : "A",
456 size);
457
458 return size;
459}
460
b445e3b0
ED		 461/* Pineview has different values for various configs */
462static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 463 .fifo_size = PINEVIEW_DISPLAY_FIFO,
464 .max_wm = PINEVIEW_MAX_WM,
465 .default_wm = PINEVIEW_DFT_WM,
466 .guard_size = PINEVIEW_GUARD_WM,
467 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 468};
469static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 470 .fifo_size = PINEVIEW_DISPLAY_FIFO,
471 .max_wm = PINEVIEW_MAX_WM,
472 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
473 .guard_size = PINEVIEW_GUARD_WM,
474 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 475};
476static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 477 .fifo_size = PINEVIEW_CURSOR_FIFO,
478 .max_wm = PINEVIEW_CURSOR_MAX_WM,
479 .default_wm = PINEVIEW_CURSOR_DFT_WM,
480 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
481 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 482};
483static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 484 .fifo_size = PINEVIEW_CURSOR_FIFO,
485 .max_wm = PINEVIEW_CURSOR_MAX_WM,
486 .default_wm = PINEVIEW_CURSOR_DFT_WM,
487 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 489};
490static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 491 .fifo_size = G4X_FIFO_SIZE,
492 .max_wm = G4X_MAX_WM,
493 .default_wm = G4X_MAX_WM,
494 .guard_size = 2,
495 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 496};
497static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 498 .fifo_size = I965_CURSOR_FIFO,
499 .max_wm = I965_CURSOR_MAX_WM,
500 .default_wm = I965_CURSOR_DFT_WM,
501 .guard_size = 2,
502 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 503};
b445e3b0 504static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 505 .fifo_size = I965_CURSOR_FIFO,
506 .max_wm = I965_CURSOR_MAX_WM,
507 .default_wm = I965_CURSOR_DFT_WM,
508 .guard_size = 2,
509 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 510};
511static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 512 .fifo_size = I945_FIFO_SIZE,
513 .max_wm = I915_MAX_WM,
514 .default_wm = 1,
515 .guard_size = 2,
516 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 517};
518static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 519 .fifo_size = I915_FIFO_SIZE,
520 .max_wm = I915_MAX_WM,
521 .default_wm = 1,
522 .guard_size = 2,
523 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 524};
9d539105 525static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 526 .fifo_size = I855GM_FIFO_SIZE,
527 .max_wm = I915_MAX_WM,
528 .default_wm = 1,
529 .guard_size = 2,
530 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 531};
9d539105
VS		 532static const struct intel_watermark_params i830_bc_wm_info = {
533 .fifo_size = I855GM_FIFO_SIZE,
534 .max_wm = I915_MAX_WM/2,
535 .default_wm = 1,
536 .guard_size = 2,
537 .cacheline_size = I830_FIFO_LINE_SIZE,
538};
feb56b93 539static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 540 .fifo_size = I830_FIFO_SIZE,
541 .max_wm = I915_MAX_WM,
542 .default_wm = 1,
543 .guard_size = 2,
544 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 545};
546
b445e3b0
ED		 547/**
548 * intel_calculate_wm - calculate watermark level
549 * @clock_in_khz: pixel clock
550 * @wm: chip FIFO params
ac484963 551 * @cpp: bytes per pixel
b445e3b0
ED		 552 * @latency_ns: memory latency for the platform
553 *
554 * Calculate the watermark level (the level at which the display plane will
555 * start fetching from memory again). Each chip has a different display
556 * FIFO size and allocation, so the caller needs to figure that out and pass
557 * in the correct intel_watermark_params structure.
558 *
559 * As the pixel clock runs, the FIFO will be drained at a rate that depends
560 * on the pixel size. When it reaches the watermark level, it'll start
561 * fetching FIFO line sized based chunks from memory until the FIFO fills
562 * past the watermark point. If the FIFO drains completely, a FIFO underrun
563 * will occur, and a display engine hang could result.
564 */
565static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
566 const struct intel_watermark_params *wm,
ac484963 567 int fifo_size, int cpp,
b445e3b0
ED		 568 unsigned long latency_ns)
569{
570 long entries_required, wm_size;
571
572 /*
573 * Note: we need to make sure we don't overflow for various clock &
574 * latency values.
575 * clocks go from a few thousand to several hundred thousand.
576 * latency is usually a few thousand
577 */
ac484963 578 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 579 1000;
580 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
581
582 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
583
584 wm_size = fifo_size - (entries_required + wm->guard_size);
585
586 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
587
588 /* Don't promote wm_size to unsigned... */
589 if (wm_size > (long)wm->max_wm)
590 wm_size = wm->max_wm;
591 if (wm_size <= 0)
592 wm_size = wm->default_wm;
d6feb196
VS		 593
594 /*
595 * Bspec seems to indicate that the value shouldn't be lower than
596 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
597 * Lets go for 8 which is the burst size since certain platforms
598 * already use a hardcoded 8 (which is what the spec says should be
599 * done).
600 */
601 if (wm_size <= 8)
602 wm_size = 8;
603
b445e3b0
ED		 604 return wm_size;
605}
606
607static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
608{
609 struct drm_crtc *crtc, *enabled = NULL;
610
70e1e0ec 611 for_each_crtc(dev, crtc) {
3490ea5d 612 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 613 if (enabled)
614 return NULL;
615 enabled = crtc;
616 }
617 }
618
619 return enabled;
620}
621
46ba614c 622static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 623{
46ba614c 624 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 625 struct drm_i915_private *dev_priv = dev->dev_private;
626 struct drm_crtc *crtc;
627 const struct cxsr_latency *latency;
628 u32 reg;
629 unsigned long wm;
630
631 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
632 dev_priv->fsb_freq, dev_priv->mem_freq);
633 if (!latency) {
634 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 635 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 636 return;
637 }
638
639 crtc = single_enabled_crtc(dev);
640 if (crtc) {
7c5f93b0 641 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 642 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 643 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 644
645 /* Display SR */
646 wm = intel_calculate_wm(clock, &pineview_display_wm,
647 pineview_display_wm.fifo_size,
ac484963 648 cpp, latency->display_sr);
b445e3b0
ED		 649 reg = I915_READ(DSPFW1);
650 reg &= ~DSPFW_SR_MASK;
f4998963 651 reg |= FW_WM(wm, SR);
b445e3b0
ED		 652 I915_WRITE(DSPFW1, reg);
653 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
654
655 /* cursor SR */
656 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
657 pineview_display_wm.fifo_size,
ac484963 658 cpp, latency->cursor_sr);
b445e3b0
ED		 659 reg = I915_READ(DSPFW3);
660 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 661 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 662 I915_WRITE(DSPFW3, reg);
663
664 /* Display HPLL off SR */
665 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
666 pineview_display_hplloff_wm.fifo_size,
ac484963 667 cpp, latency->display_hpll_disable);
b445e3b0
ED		 668 reg = I915_READ(DSPFW3);
669 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 670 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 671 I915_WRITE(DSPFW3, reg);
672
673 /* cursor HPLL off SR */
674 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
675 pineview_display_hplloff_wm.fifo_size,
ac484963 676 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 677 reg = I915_READ(DSPFW3);
678 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 679 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 680 I915_WRITE(DSPFW3, reg);
681 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
682
5209b1f4 683 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 684 } else {
5209b1f4 685 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 686 }
687}
688
689static bool g4x_compute_wm0(struct drm_device *dev,
690 int plane,
691 const struct intel_watermark_params *display,
692 int display_latency_ns,
693 const struct intel_watermark_params *cursor,
694 int cursor_latency_ns,
695 int *plane_wm,
696 int *cursor_wm)
697{
698 struct drm_crtc *crtc;
4fe8590a 699 const struct drm_display_mode *adjusted_mode;
ac484963 700 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 701 int line_time_us, line_count;
702 int entries, tlb_miss;
703
704 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 705 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 706 *cursor_wm = cursor->guard_size;
707 *plane_wm = display->guard_size;
708 return false;
709 }
710
6e3c9717 711 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 712 clock = adjusted_mode->crtc_clock;
fec8cba3 713 htotal = adjusted_mode->crtc_htotal;
6e3c9717 714 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 715 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 716
717 /* Use the small buffer method to calculate plane watermark */
ac484963 718 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 719 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
720 if (tlb_miss > 0)
721 entries += tlb_miss;
722 entries = DIV_ROUND_UP(entries, display->cacheline_size);
723 *plane_wm = entries + display->guard_size;
724 if (*plane_wm > (int)display->max_wm)
725 *plane_wm = display->max_wm;
726
727 /* Use the large buffer method to calculate cursor watermark */
922044c9 728 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 729 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 730 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 731 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
732 if (tlb_miss > 0)
733 entries += tlb_miss;
734 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
735 *cursor_wm = entries + cursor->guard_size;
736 if (*cursor_wm > (int)cursor->max_wm)
737 *cursor_wm = (int)cursor->max_wm;
738
739 return true;
740}
741
742/*
743 * Check the wm result.
744 *
745 * If any calculated watermark values is larger than the maximum value that
746 * can be programmed into the associated watermark register, that watermark
747 * must be disabled.
748 */
749static bool g4x_check_srwm(struct drm_device *dev,
750 int display_wm, int cursor_wm,
751 const struct intel_watermark_params *display,
752 const struct intel_watermark_params *cursor)
753{
754 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
755 display_wm, cursor_wm);
756
757 if (display_wm > display->max_wm) {
758 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
759 display_wm, display->max_wm);
760 return false;
761 }
762
763 if (cursor_wm > cursor->max_wm) {
764 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
765 cursor_wm, cursor->max_wm);
766 return false;
767 }
768
769 if (!(display_wm || cursor_wm)) {
770 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
771 return false;
772 }
773
774 return true;
775}
776
777static bool g4x_compute_srwm(struct drm_device *dev,
778 int plane,
779 int latency_ns,
780 const struct intel_watermark_params *display,
781 const struct intel_watermark_params *cursor,
782 int *display_wm, int *cursor_wm)
783{
784 struct drm_crtc *crtc;
4fe8590a 785 const struct drm_display_mode *adjusted_mode;
ac484963 786 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 787 unsigned long line_time_us;
788 int line_count, line_size;
789 int small, large;
790 int entries;
791
792 if (!latency_ns) {
793 *display_wm = *cursor_wm = 0;
794 return false;
795 }
796
797 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 798 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 799 clock = adjusted_mode->crtc_clock;
fec8cba3 800 htotal = adjusted_mode->crtc_htotal;
6e3c9717 801 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 802 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 803
922044c9 804 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 805 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 806 line_size = hdisplay * cpp;
b445e3b0
ED		 807
808 /* Use the minimum of the small and large buffer method for primary */
ac484963 809 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 810 large = line_count * line_size;
811
812 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
813 *display_wm = entries + display->guard_size;
814
815 /* calculate the self-refresh watermark for display cursor */
ac484963 816 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 817 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
818 *cursor_wm = entries + cursor->guard_size;
819
820 return g4x_check_srwm(dev,
821 *display_wm, *cursor_wm,
822 display, cursor);
823}
824
15665979
VS		 825#define FW_WM_VLV(value, plane) \
826 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
827
0018fda1
VS		 828static void vlv_write_wm_values(struct intel_crtc *crtc,
829 const struct vlv_wm_values *wm)
830{
831 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
832 enum pipe pipe = crtc->pipe;
833
834 I915_WRITE(VLV_DDL(pipe),
835 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
836 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
837 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
838 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
839
ae80152d 840 I915_WRITE(DSPFW1,
15665979
VS		 841 FW_WM(wm->sr.plane, SR) |
842 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
843 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
844 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 845 I915_WRITE(DSPFW2,
15665979
VS		 846 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
847 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
848 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 849 I915_WRITE(DSPFW3,
15665979 850 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 851
852 if (IS_CHERRYVIEW(dev_priv)) {
853 I915_WRITE(DSPFW7_CHV,
15665979
VS		 854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
855 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 856 I915_WRITE(DSPFW8_CHV,
15665979
VS		 857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
858 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 859 I915_WRITE(DSPFW9_CHV,
15665979
VS		 860 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
861 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 862 I915_WRITE(DSPHOWM,
15665979
VS		 863 FW_WM(wm->sr.plane >> 9, SR_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
865 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
866 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
868 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
869 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
871 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
872 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 873 } else {
874 I915_WRITE(DSPFW7,
15665979
VS		 875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 877 I915_WRITE(DSPHOWM,
15665979
VS		 878 FW_WM(wm->sr.plane >> 9, SR_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
880 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
881 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
883 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
884 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 885 }
886
2cb389b7
VS		 887 /* zero (unused) WM1 watermarks */
888 I915_WRITE(DSPFW4, 0);
889 I915_WRITE(DSPFW5, 0);
890 I915_WRITE(DSPFW6, 0);
891 I915_WRITE(DSPHOWM1, 0);
892
ae80152d 893 POSTING_READ(DSPFW1);
0018fda1
VS		 894}
895
15665979
VS		 896#undef FW_WM_VLV
897
6eb1a681
VS		 898enum vlv_wm_level {
899 VLV_WM_LEVEL_PM2,
900 VLV_WM_LEVEL_PM5,
901 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 902};
903
262cd2e1
VS		 904/* latency must be in 0.1us units. */
905static unsigned int vlv_wm_method2(unsigned int pixel_rate,
906 unsigned int pipe_htotal,
907 unsigned int horiz_pixels,
ac484963 908 unsigned int cpp,
262cd2e1
VS		 909 unsigned int latency)
910{
911 unsigned int ret;
912
913 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 914 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 915 ret = DIV_ROUND_UP(ret, 64);
916
917 return ret;
918}
919
920static void vlv_setup_wm_latency(struct drm_device *dev)
921{
922 struct drm_i915_private *dev_priv = dev->dev_private;
923
924 /* all latencies in usec */
925 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
926
58590c14
VS		 927 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
928
262cd2e1
VS		 929 if (IS_CHERRYVIEW(dev_priv)) {
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
931 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 932
933 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 934 }
935}
936
937static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
938 struct intel_crtc *crtc,
939 const struct intel_plane_state *state,
940 int level)
941{
942 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 943 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 944
945 if (dev_priv->wm.pri_latency[level] == 0)
946 return USHRT_MAX;
947
948 if (!state->visible)
949 return 0;
950
ac484963 951 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 952 clock = crtc->config->base.adjusted_mode.crtc_clock;
953 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
954 width = crtc->config->pipe_src_w;
955 if (WARN_ON(htotal == 0))
956 htotal = 1;
957
958 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
959 /*
960 * FIXME the formula gives values that are
961 * too big for the cursor FIFO, and hence we
962 * would never be able to use cursors. For
963 * now just hardcode the watermark.
964 */
965 wm = 63;
966 } else {
ac484963 967 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 968 dev_priv->wm.pri_latency[level] * 10);
969 }
970
971 return min_t(int, wm, USHRT_MAX);
972}
973
54f1b6e1
VS		 974static void vlv_compute_fifo(struct intel_crtc *crtc)
975{
976 struct drm_device *dev = crtc->base.dev;
977 struct vlv_wm_state *wm_state = &crtc->wm_state;
978 struct intel_plane *plane;
979 unsigned int total_rate = 0;
980 const int fifo_size = 512 - 1;
981 int fifo_extra, fifo_left = fifo_size;
982
983 for_each_intel_plane_on_crtc(dev, crtc, plane) {
984 struct intel_plane_state *state =
985 to_intel_plane_state(plane->base.state);
986
987 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
988 continue;
989
990 if (state->visible) {
991 wm_state->num_active_planes++;
992 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
993 }
994 }
995
996 for_each_intel_plane_on_crtc(dev, crtc, plane) {
997 struct intel_plane_state *state =
998 to_intel_plane_state(plane->base.state);
999 unsigned int rate;
1000
1001 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1002 plane->wm.fifo_size = 63;
1003 continue;
1004 }
1005
1006 if (!state->visible) {
1007 plane->wm.fifo_size = 0;
1008 continue;
1009 }
1010
1011 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1012 plane->wm.fifo_size = fifo_size * rate / total_rate;
1013 fifo_left -= plane->wm.fifo_size;
1014 }
1015
1016 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1017
1018 /* spread the remainder evenly */
1019 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1020 int plane_extra;
1021
1022 if (fifo_left == 0)
1023 break;
1024
1025 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1026 continue;
1027
1028 /* give it all to the first plane if none are active */
1029 if (plane->wm.fifo_size == 0 &&
1030 wm_state->num_active_planes)
1031 continue;
1032
1033 plane_extra = min(fifo_extra, fifo_left);
1034 plane->wm.fifo_size += plane_extra;
1035 fifo_left -= plane_extra;
1036 }
1037
1038 WARN_ON(fifo_left != 0);
1039}
1040
262cd2e1
VS		 1041static void vlv_invert_wms(struct intel_crtc *crtc)
1042{
1043 struct vlv_wm_state *wm_state = &crtc->wm_state;
1044 int level;
1045
1046 for (level = 0; level < wm_state->num_levels; level++) {
1047 struct drm_device *dev = crtc->base.dev;
1048 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1049 struct intel_plane *plane;
1050
1051 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1052 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1053
1054 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1055 switch (plane->base.type) {
1056 int sprite;
1057 case DRM_PLANE_TYPE_CURSOR:
1058 wm_state->wm[level].cursor = plane->wm.fifo_size -
1059 wm_state->wm[level].cursor;
1060 break;
1061 case DRM_PLANE_TYPE_PRIMARY:
1062 wm_state->wm[level].primary = plane->wm.fifo_size -
1063 wm_state->wm[level].primary;
1064 break;
1065 case DRM_PLANE_TYPE_OVERLAY:
1066 sprite = plane->plane;
1067 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1068 wm_state->wm[level].sprite[sprite];
1069 break;
1070 }
1071 }
1072 }
1073}
1074
26e1fe4f 1075static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1076{
1077 struct drm_device *dev = crtc->base.dev;
1078 struct vlv_wm_state *wm_state = &crtc->wm_state;
1079 struct intel_plane *plane;
1080 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1081 int level;
1082
1083 memset(wm_state, 0, sizeof(*wm_state));
1084
852eb00d 1085 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1086 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1087
1088 wm_state->num_active_planes = 0;
262cd2e1 1089
54f1b6e1 1090 vlv_compute_fifo(crtc);
262cd2e1
VS		 1091
1092 if (wm_state->num_active_planes != 1)
1093 wm_state->cxsr = false;
1094
1095 if (wm_state->cxsr) {
1096 for (level = 0; level < wm_state->num_levels; level++) {
1097 wm_state->sr[level].plane = sr_fifo_size;
1098 wm_state->sr[level].cursor = 63;
1099 }
1100 }
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 struct intel_plane_state *state =
1104 to_intel_plane_state(plane->base.state);
1105
1106 if (!state->visible)
1107 continue;
1108
1109 /* normal watermarks */
1110 for (level = 0; level < wm_state->num_levels; level++) {
1111 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1112 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1113
1114 /* hack */
1115 if (WARN_ON(level == 0 && wm > max_wm))
1116 wm = max_wm;
1117
1118 if (wm > plane->wm.fifo_size)
1119 break;
1120
1121 switch (plane->base.type) {
1122 int sprite;
1123 case DRM_PLANE_TYPE_CURSOR:
1124 wm_state->wm[level].cursor = wm;
1125 break;
1126 case DRM_PLANE_TYPE_PRIMARY:
1127 wm_state->wm[level].primary = wm;
1128 break;
1129 case DRM_PLANE_TYPE_OVERLAY:
1130 sprite = plane->plane;
1131 wm_state->wm[level].sprite[sprite] = wm;
1132 break;
1133 }
1134 }
1135
1136 wm_state->num_levels = level;
1137
1138 if (!wm_state->cxsr)
1139 continue;
1140
1141 /* maxfifo watermarks */
1142 switch (plane->base.type) {
1143 int sprite, level;
1144 case DRM_PLANE_TYPE_CURSOR:
1145 for (level = 0; level < wm_state->num_levels; level++)
1146 wm_state->sr[level].cursor =
5a37ed0a 1147 wm_state->wm[level].cursor;
262cd2e1
VS		 1148 break;
1149 case DRM_PLANE_TYPE_PRIMARY:
1150 for (level = 0; level < wm_state->num_levels; level++)
1151 wm_state->sr[level].plane =
1152 min(wm_state->sr[level].plane,
1153 wm_state->wm[level].primary);
1154 break;
1155 case DRM_PLANE_TYPE_OVERLAY:
1156 sprite = plane->plane;
1157 for (level = 0; level < wm_state->num_levels; level++)
1158 wm_state->sr[level].plane =
1159 min(wm_state->sr[level].plane,
1160 wm_state->wm[level].sprite[sprite]);
1161 break;
1162 }
1163 }
1164
1165 /* clear any (partially) filled invalid levels */
58590c14 1166 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1167 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1168 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1169 }
1170
1171 vlv_invert_wms(crtc);
1172}
1173
54f1b6e1
VS		 1174#define VLV_FIFO(plane, value) \
1175 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1176
1177static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1178{
1179 struct drm_device *dev = crtc->base.dev;
1180 struct drm_i915_private *dev_priv = to_i915(dev);
1181 struct intel_plane *plane;
1182 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1183
1184 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1185 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1186 WARN_ON(plane->wm.fifo_size != 63);
1187 continue;
1188 }
1189
1190 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1191 sprite0_start = plane->wm.fifo_size;
1192 else if (plane->plane == 0)
1193 sprite1_start = sprite0_start + plane->wm.fifo_size;
1194 else
1195 fifo_size = sprite1_start + plane->wm.fifo_size;
1196 }
1197
1198 WARN_ON(fifo_size != 512 - 1);
1199
1200 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1201 pipe_name(crtc->pipe), sprite0_start,
1202 sprite1_start, fifo_size);
1203
1204 switch (crtc->pipe) {
1205 uint32_t dsparb, dsparb2, dsparb3;
1206 case PIPE_A:
1207 dsparb = I915_READ(DSPARB);
1208 dsparb2 = I915_READ(DSPARB2);
1209
1210 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1211 VLV_FIFO(SPRITEB, 0xff));
1212 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1213 VLV_FIFO(SPRITEB, sprite1_start));
1214
1215 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1216 VLV_FIFO(SPRITEB_HI, 0x1));
1217 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1218 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1219
1220 I915_WRITE(DSPARB, dsparb);
1221 I915_WRITE(DSPARB2, dsparb2);
1222 break;
1223 case PIPE_B:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1228 VLV_FIFO(SPRITED, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1230 VLV_FIFO(SPRITED, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1233 VLV_FIFO(SPRITED_HI, 0xff));
1234 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_C:
1241 dsparb3 = I915_READ(DSPARB3);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1245 VLV_FIFO(SPRITEF, 0xff));
1246 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1247 VLV_FIFO(SPRITEF, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1250 VLV_FIFO(SPRITEF_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB3, dsparb3);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 default:
1258 break;
1259 }
1260}
1261
1262#undef VLV_FIFO
1263
262cd2e1
VS		 1264static void vlv_merge_wm(struct drm_device *dev,
1265 struct vlv_wm_values *wm)
1266{
1267 struct intel_crtc *crtc;
1268 int num_active_crtcs = 0;
1269
58590c14 1270 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1271 wm->cxsr = true;
1272
1273 for_each_intel_crtc(dev, crtc) {
1274 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1275
1276 if (!crtc->active)
1277 continue;
1278
1279 if (!wm_state->cxsr)
1280 wm->cxsr = false;
1281
1282 num_active_crtcs++;
1283 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1284 }
1285
1286 if (num_active_crtcs != 1)
1287 wm->cxsr = false;
1288
6f9c784b
VS		 1289 if (num_active_crtcs > 1)
1290 wm->level = VLV_WM_LEVEL_PM2;
1291
262cd2e1
VS		 1292 for_each_intel_crtc(dev, crtc) {
1293 struct vlv_wm_state *wm_state = &crtc->wm_state;
1294 enum pipe pipe = crtc->pipe;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 wm->pipe[pipe] = wm_state->wm[wm->level];
1300 if (wm->cxsr)
1301 wm->sr = wm_state->sr[wm->level];
1302
1303 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1306 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1307 }
1308}
1309
1310static void vlv_update_wm(struct drm_crtc *crtc)
1311{
1312 struct drm_device *dev = crtc->dev;
1313 struct drm_i915_private *dev_priv = dev->dev_private;
1314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1315 enum pipe pipe = intel_crtc->pipe;
1316 struct vlv_wm_values wm = {};
1317
26e1fe4f 1318 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1319 vlv_merge_wm(dev, &wm);
1320
54f1b6e1
VS		 1321 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1322 /* FIXME should be part of crtc atomic commit */
1323 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1324 return;
54f1b6e1 1325 }
262cd2e1
VS		 1326
1327 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1328 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1329 chv_set_memory_dvfs(dev_priv, false);
1330
1331 if (wm.level < VLV_WM_LEVEL_PM5 &&
1332 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1333 chv_set_memory_pm5(dev_priv, false);
1334
852eb00d 1335 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1336 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1337
54f1b6e1
VS		 1338 /* FIXME should be part of crtc atomic commit */
1339 vlv_pipe_set_fifo_size(intel_crtc);
1340
262cd2e1
VS		 1341 vlv_write_wm_values(intel_crtc, &wm);
1342
1343 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1344 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1345 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1346 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1347 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1348
852eb00d 1349 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1350 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1351
1352 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1353 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1354 chv_set_memory_pm5(dev_priv, true);
1355
1356 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1357 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1358 chv_set_memory_dvfs(dev_priv, true);
1359
1360 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1361}
1362
ae80152d
VS		 1363#define single_plane_enabled(mask) is_power_of_2(mask)
1364
46ba614c 1365static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1366{
46ba614c 1367 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1368 static const int sr_latency_ns = 12000;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1371 int plane_sr, cursor_sr;
1372 unsigned int enabled = 0;
9858425c 1373 bool cxsr_enabled;
b445e3b0 1374
51cea1f4 1375 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1376 &g4x_wm_info, pessimal_latency_ns,
1377 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1378 &planea_wm, &cursora_wm))
51cea1f4 1379 enabled |= 1 << PIPE_A;
b445e3b0 1380
51cea1f4 1381 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1382 &g4x_wm_info, pessimal_latency_ns,
1383 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1384 &planeb_wm, &cursorb_wm))
51cea1f4 1385 enabled |= 1 << PIPE_B;
b445e3b0 1386
b445e3b0
ED		 1387 if (single_plane_enabled(enabled) &&
1388 g4x_compute_srwm(dev, ffs(enabled) - 1,
1389 sr_latency_ns,
1390 &g4x_wm_info,
1391 &g4x_cursor_wm_info,
52bd02d8 1392 &plane_sr, &cursor_sr)) {
9858425c 1393 cxsr_enabled = true;
52bd02d8 1394 } else {
9858425c 1395 cxsr_enabled = false;
5209b1f4 1396 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1397 plane_sr = cursor_sr = 0;
1398 }
b445e3b0 1399
a5043453
VS		 1400 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1401 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1402 planea_wm, cursora_wm,
1403 planeb_wm, cursorb_wm,
1404 plane_sr, cursor_sr);
1405
1406 I915_WRITE(DSPFW1,
f4998963
VS		 1407 FW_WM(plane_sr, SR) |
1408 FW_WM(cursorb_wm, CURSORB) |
1409 FW_WM(planeb_wm, PLANEB) |
1410 FW_WM(planea_wm, PLANEA));
b445e3b0 1411 I915_WRITE(DSPFW2,
8c919b28 1412 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1413 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1414 /* HPLL off in SR has some issues on G4x... disable it */
1415 I915_WRITE(DSPFW3,
8c919b28 1416 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1417 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1418
1419 if (cxsr_enabled)
1420 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1421}
1422
46ba614c 1423static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1424{
46ba614c 1425 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1426 struct drm_i915_private *dev_priv = dev->dev_private;
1427 struct drm_crtc *crtc;
1428 int srwm = 1;
1429 int cursor_sr = 16;
9858425c 1430 bool cxsr_enabled;
b445e3b0
ED		 1431
1432 /* Calc sr entries for one plane configs */
1433 crtc = single_enabled_crtc(dev);
1434 if (crtc) {
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns = 12000;
124abe07 1437 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1438 int clock = adjusted_mode->crtc_clock;
fec8cba3 1439 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1440 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1441 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1442 unsigned long line_time_us;
1443 int entries;
1444
922044c9 1445 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1446
1447 /* Use ns/us then divide to preserve precision */
1448 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1449 cpp * hdisplay;
b445e3b0
ED		 1450 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1451 srwm = I965_FIFO_SIZE - entries;
1452 if (srwm < 0)
1453 srwm = 1;
1454 srwm &= 0x1ff;
1455 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1456 entries, srwm);
1457
1458 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1459 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1460 entries = DIV_ROUND_UP(entries,
1461 i965_cursor_wm_info.cacheline_size);
1462 cursor_sr = i965_cursor_wm_info.fifo_size -
1463 (entries + i965_cursor_wm_info.guard_size);
1464
1465 if (cursor_sr > i965_cursor_wm_info.max_wm)
1466 cursor_sr = i965_cursor_wm_info.max_wm;
1467
1468 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1469 "cursor %d\n", srwm, cursor_sr);
1470
9858425c 1471 cxsr_enabled = true;
b445e3b0 1472 } else {
9858425c 1473 cxsr_enabled = false;
b445e3b0 1474 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1475 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1476 }
1477
1478 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1479 srwm);
1480
1481 /* 965 has limitations... */
f4998963
VS		 1482 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1483 FW_WM(8, CURSORB) |
1484 FW_WM(8, PLANEB) |
1485 FW_WM(8, PLANEA));
1486 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1487 FW_WM(8, PLANEC_OLD));
b445e3b0 1488 /* update cursor SR watermark */
f4998963 1489 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1490
1491 if (cxsr_enabled)
1492 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1493}
1494
f4998963
VS		 1495#undef FW_WM
1496
46ba614c 1497static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1498{
46ba614c 1499 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1500 struct drm_i915_private *dev_priv = dev->dev_private;
1501 const struct intel_watermark_params *wm_info;
1502 uint32_t fwater_lo;
1503 uint32_t fwater_hi;
1504 int cwm, srwm = 1;
1505 int fifo_size;
1506 int planea_wm, planeb_wm;
1507 struct drm_crtc *crtc, *enabled = NULL;
1508
1509 if (IS_I945GM(dev))
1510 wm_info = &i945_wm_info;
1511 else if (!IS_GEN2(dev))
1512 wm_info = &i915_wm_info;
1513 else
9d539105 1514 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1515
1516 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1517 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1518 if (intel_crtc_active(crtc)) {
241bfc38 1519 const struct drm_display_mode *adjusted_mode;
ac484963 1520 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1521 if (IS_GEN2(dev))
1522 cpp = 4;
1523
6e3c9717 1524 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1525 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1526 wm_info, fifo_size, cpp,
5aef6003 1527 pessimal_latency_ns);
b445e3b0 1528 enabled = crtc;
9d539105 1529 } else {
b445e3b0 1530 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1531 if (planea_wm > (long)wm_info->max_wm)
1532 planea_wm = wm_info->max_wm;
1533 }
1534
1535 if (IS_GEN2(dev))
1536 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1539 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1540 if (intel_crtc_active(crtc)) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0
ED		 1550 if (enabled == NULL)
1551 enabled = crtc;
1552 else
1553 enabled = NULL;
9d539105 1554 } else {
b445e3b0 1555 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1556 if (planeb_wm > (long)wm_info->max_wm)
1557 planeb_wm = wm_info->max_wm;
1558 }
b445e3b0
ED		 1559
1560 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1561
2ab1bc9d 1562 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1563 struct drm_i915_gem_object *obj;
2ab1bc9d 1564
59bea882 1565 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1566
1567 /* self-refresh seems busted with untiled */
2ff8fde1 1568 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1569 enabled = NULL;
1570 }
1571
b445e3b0
ED		 1572 /*
1573 * Overlay gets an aggressive default since video jitter is bad.
1574 */
1575 cwm = 2;
1576
1577 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1578 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1579
1580 /* Calc sr entries for one plane configs */
1581 if (HAS_FW_BLC(dev) && enabled) {
1582 /* self-refresh has much higher latency */
1583 static const int sr_latency_ns = 6000;
124abe07 1584 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1585 int clock = adjusted_mode->crtc_clock;
fec8cba3 1586 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1587 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1588 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1589 unsigned long line_time_us;
1590 int entries;
1591
922044c9 1592 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1593
1594 /* Use ns/us then divide to preserve precision */
1595 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1596 cpp * hdisplay;
b445e3b0
ED		 1597 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1598 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1599 srwm = wm_info->fifo_size - entries;
1600 if (srwm < 0)
1601 srwm = 1;
1602
1603 if (IS_I945G(dev) || IS_I945GM(dev))
1604 I915_WRITE(FW_BLC_SELF,
1605 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1606 else if (IS_I915GM(dev))
1607 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1608 }
1609
1610 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1611 planea_wm, planeb_wm, cwm, srwm);
1612
1613 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1614 fwater_hi = (cwm & 0x1f);
1615
1616 /* Set request length to 8 cachelines per fetch */
1617 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1618 fwater_hi = fwater_hi | (1 << 8);
1619
1620 I915_WRITE(FW_BLC, fwater_lo);
1621 I915_WRITE(FW_BLC2, fwater_hi);
1622
5209b1f4
ID		 1623 if (enabled)
1624 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1625}
1626
feb56b93 1627static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1628{
46ba614c 1629 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1630 struct drm_i915_private *dev_priv = dev->dev_private;
1631 struct drm_crtc *crtc;
241bfc38 1632 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1633 uint32_t fwater_lo;
1634 int planea_wm;
1635
1636 crtc = single_enabled_crtc(dev);
1637 if (crtc == NULL)
1638 return;
1639
6e3c9717 1640 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1641 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1642 &i845_wm_info,
b445e3b0 1643 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1644 4, pessimal_latency_ns);
b445e3b0
ED		 1645 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1646 fwater_lo |= (3<<8) | planea_wm;
1647
1648 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1649
1650 I915_WRITE(FW_BLC, fwater_lo);
1651}
1652
8cfb3407 1653uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1654{
fd4daa9c 1655 uint32_t pixel_rate;
801bcfff 1656
8cfb3407 1657 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1658
1659 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1660 * adjust the pixel_rate here. */
1661
8cfb3407 1662 if (pipe_config->pch_pfit.enabled) {
801bcfff 1663 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1664 uint32_t pfit_size = pipe_config->pch_pfit.size;
1665
1666 pipe_w = pipe_config->pipe_src_w;
1667 pipe_h = pipe_config->pipe_src_h;
801bcfff 1668
801bcfff
PZ		 1669 pfit_w = (pfit_size >> 16) & 0xFFFF;
1670 pfit_h = pfit_size & 0xFFFF;
1671 if (pipe_w < pfit_w)
1672 pipe_w = pfit_w;
1673 if (pipe_h < pfit_h)
1674 pipe_h = pfit_h;
1675
15126882
MR		 1676 if (WARN_ON(!pfit_w || !pfit_h))
1677 return pixel_rate;
1678
801bcfff
PZ		 1679 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1680 pfit_w * pfit_h);
1681 }
1682
1683 return pixel_rate;
1684}
1685
37126462 1686/* latency must be in 0.1us units. */
ac484963 1687static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1688{
1689 uint64_t ret;
1690
3312ba65
VS		 1691 if (WARN(latency == 0, "Latency value missing\n"))
1692 return UINT_MAX;
1693
ac484963 1694 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1695 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1696
1697 return ret;
1698}
1699
37126462 1700/* latency must be in 0.1us units. */
23297044 1701static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1702 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1703 uint32_t latency)
1704{
1705 uint32_t ret;
1706
3312ba65
VS		 1707 if (WARN(latency == 0, "Latency value missing\n"))
1708 return UINT_MAX;
15126882
MR		 1709 if (WARN_ON(!pipe_htotal))
1710 return UINT_MAX;
3312ba65 1711
801bcfff 1712 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1713 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1714 ret = DIV_ROUND_UP(ret, 64) + 2;
1715 return ret;
1716}
1717
23297044 1718static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1719 uint8_t cpp)
cca32e9a 1720{
15126882
MR		 1721 /*
1722 * Neither of these should be possible since this function shouldn't be
1723 * called if the CRTC is off or the plane is invisible. But let's be
1724 * extra paranoid to avoid a potential divide-by-zero if we screw up
1725 * elsewhere in the driver.
1726 */
ac484963 1727 if (WARN_ON(!cpp))
15126882
MR		 1728 return 0;
1729 if (WARN_ON(!horiz_pixels))
1730 return 0;
1731
ac484963 1732 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1733}
1734
820c1980 1735struct ilk_wm_maximums {
cca32e9a
PZ		 1736 uint16_t pri;
1737 uint16_t spr;
1738 uint16_t cur;
1739 uint16_t fbc;
1740};
1741
37126462
VS		 1742/*
1743 * For both WM_PIPE and WM_LP.
1744 * mem_value must be in 0.1us units.
1745 */
7221fc33 1746static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1747 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1748 uint32_t mem_value,
1749 bool is_lp)
801bcfff 1750{
ac484963
VS		 1751 int cpp = pstate->base.fb ?
1752 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1753 uint32_t method1, method2;
1754
7221fc33 1755 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1756 return 0;
1757
ac484963 1758 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1759
1760 if (!is_lp)
1761 return method1;
1762
7221fc33
MR		 1763 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1764 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1765 drm_rect_width(&pstate->dst),
ac484963 1766 cpp, mem_value);
cca32e9a
PZ		 1767
1768 return min(method1, method2);
801bcfff
PZ		 1769}
1770
37126462
VS		 1771/*
1772 * For both WM_PIPE and WM_LP.
1773 * mem_value must be in 0.1us units.
1774 */
7221fc33 1775static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1776 const struct intel_plane_state *pstate,
801bcfff
PZ		 1777 uint32_t mem_value)
1778{
ac484963
VS		 1779 int cpp = pstate->base.fb ?
1780 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1781 uint32_t method1, method2;
1782
7221fc33 1783 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1784 return 0;
1785
ac484963 1786 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1787 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1788 cstate->base.adjusted_mode.crtc_htotal,
43d59eda 1789 drm_rect_width(&pstate->dst),
ac484963 1790 cpp, mem_value);
801bcfff
PZ		 1791 return min(method1, method2);
1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
b2435692
MR		 1802 /*
1803 * We treat the cursor plane as always-on for the purposes of watermark
1804 * calculation. Until we have two-stage watermark programming merged,
1805 * this is necessary to avoid flickering.
1806 */
1807 int cpp = 4;
1808 int width = pstate->visible ? pstate->base.crtc_w : 64;
43d59eda 1809
b2435692 1810 if (!cstate->base.active)
801bcfff
PZ		 1811 return 0;
1812
7221fc33
MR		 1813 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1814 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1815 width, cpp, mem_value);
801bcfff
PZ		 1816}
1817
cca32e9a 1818/* Only for WM_LP. */
7221fc33 1819static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1820 const struct intel_plane_state *pstate,
1fda9882 1821 uint32_t pri_val)
cca32e9a 1822{
ac484963
VS		 1823 int cpp = pstate->base.fb ?
1824 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1825
7221fc33 1826 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1827 return 0;
1828
ac484963 1829 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), cpp);
cca32e9a
PZ		 1830}
1831
158ae64f
VS		 1832static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1833{
416f4727
VS		 1834 if (INTEL_INFO(dev)->gen >= 8)
1835 return 3072;
1836 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1837 return 768;
1838 else
1839 return 512;
1840}
1841
4e975081
VS		 1842static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1843 int level, bool is_sprite)
1844{
1845 if (INTEL_INFO(dev)->gen >= 8)
1846 /* BDW primary/sprite plane watermarks */
1847 return level == 0 ? 255 : 2047;
1848 else if (INTEL_INFO(dev)->gen >= 7)
1849 /* IVB/HSW primary/sprite plane watermarks */
1850 return level == 0 ? 127 : 1023;
1851 else if (!is_sprite)
1852 /* ILK/SNB primary plane watermarks */
1853 return level == 0 ? 127 : 511;
1854 else
1855 /* ILK/SNB sprite plane watermarks */
1856 return level == 0 ? 63 : 255;
1857}
1858
1859static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1860 int level)
1861{
1862 if (INTEL_INFO(dev)->gen >= 7)
1863 return level == 0 ? 63 : 255;
1864 else
1865 return level == 0 ? 31 : 63;
1866}
1867
1868static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 return 31;
1872 else
1873 return 15;
1874}
1875
158ae64f
VS		 1876/* Calculate the maximum primary/sprite plane watermark */
1877static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1878 int level,
240264f4 1879 const struct intel_wm_config *config,
158ae64f
VS		 1880 enum intel_ddb_partitioning ddb_partitioning,
1881 bool is_sprite)
1882{
1883 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1884
1885 /* if sprites aren't enabled, sprites get nothing */
240264f4 1886 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1887 return 0;
1888
1889 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1890 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1891 fifo_size /= INTEL_INFO(dev)->num_pipes;
1892
1893 /*
1894 * For some reason the non self refresh
1895 * FIFO size is only half of the self
1896 * refresh FIFO size on ILK/SNB.
1897 */
1898 if (INTEL_INFO(dev)->gen <= 6)
1899 fifo_size /= 2;
1900 }
1901
240264f4 1902 if (config->sprites_enabled) {
158ae64f
VS		 1903 /* level 0 is always calculated with 1:1 split */
1904 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1905 if (is_sprite)
1906 fifo_size *= 5;
1907 fifo_size /= 6;
1908 } else {
1909 fifo_size /= 2;
1910 }
1911 }
1912
1913 /* clamp to max that the registers can hold */
4e975081 1914 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1915}
1916
1917/* Calculate the maximum cursor plane watermark */
1918static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1919 int level,
1920 const struct intel_wm_config *config)
158ae64f
VS		 1921{
1922 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1923 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1924 return 64;
1925
1926 /* otherwise just report max that registers can hold */
4e975081 1927 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1928}
1929
d34ff9c6 1930static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1931 int level,
1932 const struct intel_wm_config *config,
1933 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1934 struct ilk_wm_maximums *max)
158ae64f 1935{
240264f4
VS		 1936 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1937 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1938 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1939 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1940}
1941
a3cb4048
VS		 1942static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1943 int level,
1944 struct ilk_wm_maximums *max)
1945{
1946 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1947 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1948 max->cur = ilk_cursor_wm_reg_max(dev, level);
1949 max->fbc = ilk_fbc_wm_reg_max(dev);
1950}
1951
d9395655 1952static bool ilk_validate_wm_level(int level,
820c1980 1953 const struct ilk_wm_maximums *max,
d9395655 1954 struct intel_wm_level *result)
a9786a11
VS		 1955{
1956 bool ret;
1957
1958 /* already determined to be invalid? */
1959 if (!result->enable)
1960 return false;
1961
1962 result->enable = result->pri_val <= max->pri &&
1963 result->spr_val <= max->spr &&
1964 result->cur_val <= max->cur;
1965
1966 ret = result->enable;
1967
1968 /*
1969 * HACK until we can pre-compute everything,
1970 * and thus fail gracefully if LP0 watermarks
1971 * are exceeded...
1972 */
1973 if (level == 0 && !result->enable) {
1974 if (result->pri_val > max->pri)
1975 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1976 level, result->pri_val, max->pri);
1977 if (result->spr_val > max->spr)
1978 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1979 level, result->spr_val, max->spr);
1980 if (result->cur_val > max->cur)
1981 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1982 level, result->cur_val, max->cur);
1983
1984 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1985 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1986 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1987 result->enable = true;
1988 }
1989
a9786a11
VS		 1990 return ret;
1991}
1992
d34ff9c6 1993static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1994 const struct intel_crtc *intel_crtc,
6f5ddd17 1995 int level,
7221fc33 1996 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1997 struct intel_plane_state *pristate,
1998 struct intel_plane_state *sprstate,
1999 struct intel_plane_state *curstate,
1fd527cc 2000 struct intel_wm_level *result)
6f5ddd17
VS		 2001{
2002 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2003 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2004 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2005
2006 /* WM1+ latency values stored in 0.5us units */
2007 if (level > 0) {
2008 pri_latency *= 5;
2009 spr_latency *= 5;
2010 cur_latency *= 5;
2011 }
2012
e3bddded
ML		 2013 if (pristate) {
2014 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2015 pri_latency, level);
2016 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2017 }
2018
2019 if (sprstate)
2020 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2021
2022 if (curstate)
2023 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2024
6f5ddd17
VS		 2025 result->enable = true;
2026}
2027
801bcfff 2028static uint32_t
ee91a159
MR		 2029hsw_compute_linetime_wm(struct drm_device *dev,
2030 struct intel_crtc_state *cstate)
1f8eeabf
ED		 2031{
2032 struct drm_i915_private *dev_priv = dev->dev_private;
ee91a159
MR		 2033 const struct drm_display_mode *adjusted_mode =
2034 &cstate->base.adjusted_mode;
85a02deb 2035 u32 linetime, ips_linetime;
1f8eeabf 2036
ee91a159
MR		 2037 if (!cstate->base.active)
2038 return 0;
2039 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2040 return 0;
2041 if (WARN_ON(dev_priv->cdclk_freq == 0))
801bcfff 2042 return 0;
1011d8c4 2043
1f8eeabf
ED		 2044 /* The WM are computed with base on how long it takes to fill a single
2045 * row at the given clock rate, multiplied by 8.
2046 * */
124abe07
VS		 2047 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2048 adjusted_mode->crtc_clock);
2049 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2050 dev_priv->cdclk_freq);
1f8eeabf 2051
801bcfff
PZ		 2052 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2053 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2054}
2055
2af30a5c 2056static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2057{
2058 struct drm_i915_private *dev_priv = dev->dev_private;
2059
2af30a5c
PB		 2060 if (IS_GEN9(dev)) {
2061 uint32_t val;
4f947386 2062 int ret, i;
367294be 2063 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2064
2065 /* read the first set of memory latencies[0:3] */
2066 val = 0; /* data0 to be programmed to 0 for first set */
2067 mutex_lock(&dev_priv->rps.hw_lock);
2068 ret = sandybridge_pcode_read(dev_priv,
2069 GEN9_PCODE_READ_MEM_LATENCY,
2070 &val);
2071 mutex_unlock(&dev_priv->rps.hw_lock);
2072
2073 if (ret) {
2074 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2075 return;
2076 }
2077
2078 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2079 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2080 GEN9_MEM_LATENCY_LEVEL_MASK;
2081 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2082 GEN9_MEM_LATENCY_LEVEL_MASK;
2083 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2084 GEN9_MEM_LATENCY_LEVEL_MASK;
2085
2086 /* read the second set of memory latencies[4:7] */
2087 val = 1; /* data0 to be programmed to 1 for second set */
2088 mutex_lock(&dev_priv->rps.hw_lock);
2089 ret = sandybridge_pcode_read(dev_priv,
2090 GEN9_PCODE_READ_MEM_LATENCY,
2091 &val);
2092 mutex_unlock(&dev_priv->rps.hw_lock);
2093 if (ret) {
2094 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2095 return;
2096 }
2097
2098 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2099 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2100 GEN9_MEM_LATENCY_LEVEL_MASK;
2101 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2102 GEN9_MEM_LATENCY_LEVEL_MASK;
2103 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2104 GEN9_MEM_LATENCY_LEVEL_MASK;
2105
367294be 2106 /*
6f97235b
DL		 2107 * WaWmMemoryReadLatency:skl
2108 *
367294be
VK		 2109 * punit doesn't take into account the read latency so we need
2110 * to add 2us to the various latency levels we retrieve from
2111 * the punit.
2112 * - W0 is a bit special in that it's the only level that
2113 * can't be disabled if we want to have display working, so
2114 * we always add 2us there.
2115 * - For levels >=1, punit returns 0us latency when they are
2116 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2117 *
2118 * Additionally, if a level n (n > 1) has a 0us latency, all
2119 * levels m (m >= n) need to be disabled. We make sure to
2120 * sanitize the values out of the punit to satisfy this
2121 * requirement.
367294be
VK		 2122 */
2123 wm[0] += 2;
2124 for (level = 1; level <= max_level; level++)
2125 if (wm[level] != 0)
2126 wm[level] += 2;
4f947386
VK		 2127 else {
2128 for (i = level + 1; i <= max_level; i++)
2129 wm[i] = 0;
367294be 2130
4f947386
VK		 2131 break;
2132 }
2af30a5c 2133 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2134 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2135
2136 wm[0] = (sskpd >> 56) & 0xFF;
2137 if (wm[0] == 0)
2138 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2139 wm[1] = (sskpd >> 4) & 0xFF;
2140 wm[2] = (sskpd >> 12) & 0xFF;
2141 wm[3] = (sskpd >> 20) & 0x1FF;
2142 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2143 } else if (INTEL_INFO(dev)->gen >= 6) {
2144 uint32_t sskpd = I915_READ(MCH_SSKPD);
2145
2146 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2147 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2148 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2149 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2150 } else if (INTEL_INFO(dev)->gen >= 5) {
2151 uint32_t mltr = I915_READ(MLTR_ILK);
2152
2153 /* ILK primary LP0 latency is 700 ns */
2154 wm[0] = 7;
2155 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2156 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2157 }
2158}
2159
53615a5e
VS		 2160static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2161{
2162 /* ILK sprite LP0 latency is 1300 ns */
2163 if (INTEL_INFO(dev)->gen == 5)
2164 wm[0] = 13;
2165}
2166
2167static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2168{
2169 /* ILK cursor LP0 latency is 1300 ns */
2170 if (INTEL_INFO(dev)->gen == 5)
2171 wm[0] = 13;
2172
2173 /* WaDoubleCursorLP3Latency:ivb */
2174 if (IS_IVYBRIDGE(dev))
2175 wm[3] *= 2;
2176}
2177
546c81fd 2178int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2179{
26ec971e 2180 /* how many WM levels are we expecting */
b6e742f6 2181 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2182 return 7;
2183 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2184 return 4;
26ec971e 2185 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2186 return 3;
26ec971e 2187 else
ad0d6dc4
VS		 2188 return 2;
2189}
7526ed79 2190
ad0d6dc4
VS		 2191static void intel_print_wm_latency(struct drm_device *dev,
2192 const char *name,
2af30a5c 2193 const uint16_t wm[8])
ad0d6dc4
VS		 2194{
2195 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2196
2197 for (level = 0; level <= max_level; level++) {
2198 unsigned int latency = wm[level];
2199
2200 if (latency == 0) {
2201 DRM_ERROR("%s WM%d latency not provided\n",
2202 name, level);
2203 continue;
2204 }
2205
2af30a5c
PB		 2206 /*
2207 * - latencies are in us on gen9.
2208 * - before then, WM1+ latency values are in 0.5us units
2209 */
2210 if (IS_GEN9(dev))
2211 latency *= 10;
2212 else if (level > 0)
26ec971e
VS		 2213 latency *= 5;
2214
2215 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2216 name, level, wm[level],
2217 latency / 10, latency % 10);
2218 }
2219}
2220
e95a2f75
VS		 2221static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2222 uint16_t wm[5], uint16_t min)
2223{
2224 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2225
2226 if (wm[0] >= min)
2227 return false;
2228
2229 wm[0] = max(wm[0], min);
2230 for (level = 1; level <= max_level; level++)
2231 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2232
2233 return true;
2234}
2235
2236static void snb_wm_latency_quirk(struct drm_device *dev)
2237{
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 bool changed;
2240
2241 /*
2242 * The BIOS provided WM memory latency values are often
2243 * inadequate for high resolution displays. Adjust them.
2244 */
2245 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2246 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2247 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2248
2249 if (!changed)
2250 return;
2251
2252 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2253 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2254 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2255 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2256}
2257
fa50ad61 2258static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2259{
2260 struct drm_i915_private *dev_priv = dev->dev_private;
2261
2262 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2263
2264 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2265 sizeof(dev_priv->wm.pri_latency));
2266 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2267 sizeof(dev_priv->wm.pri_latency));
2268
2269 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2270 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2271
2272 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2273 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2274 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2275
2276 if (IS_GEN6(dev))
2277 snb_wm_latency_quirk(dev);
53615a5e
VS		 2278}
2279
2af30a5c
PB		 2280static void skl_setup_wm_latency(struct drm_device *dev)
2281{
2282 struct drm_i915_private *dev_priv = dev->dev_private;
2283
2284 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2285 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2286}
2287
ed4a6a7c
MR		 2288static bool ilk_validate_pipe_wm(struct drm_device *dev,
2289 struct intel_pipe_wm *pipe_wm)
2290{
2291 /* LP0 watermark maximums depend on this pipe alone */
2292 const struct intel_wm_config config = {
2293 .num_pipes_active = 1,
2294 .sprites_enabled = pipe_wm->sprites_enabled,
2295 .sprites_scaled = pipe_wm->sprites_scaled,
2296 };
2297 struct ilk_wm_maximums max;
2298
2299 /* LP0 watermarks always use 1/2 DDB partitioning */
2300 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2301
2302 /* At least LP0 must be valid */
2303 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2304 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2305 return false;
2306 }
2307
2308 return true;
2309}
2310
0b2ae6d7 2311/* Compute new watermarks for the pipe */
e3bddded 2312static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2313{
e3bddded
ML		 2314 struct drm_atomic_state *state = cstate->base.state;
2315 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2316 struct intel_pipe_wm *pipe_wm;
e3bddded 2317 struct drm_device *dev = state->dev;
d34ff9c6 2318 const struct drm_i915_private *dev_priv = dev->dev_private;
43d59eda 2319 struct intel_plane *intel_plane;
86c8bbbe 2320 struct intel_plane_state *pristate = NULL;
43d59eda 2321 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2322 struct intel_plane_state *curstate = NULL;
d81f04c5 2323 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2324 struct ilk_wm_maximums max;
0b2ae6d7 2325
86c8bbbe
MR		 2326 pipe_wm = &cstate->wm.optimal.ilk;
2327
43d59eda 2328 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2329 struct intel_plane_state *ps;
2330
2331 ps = intel_atomic_get_existing_plane_state(state,
2332 intel_plane);
2333 if (!ps)
2334 continue;
86c8bbbe
MR		 2335
2336 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2337 pristate = ps;
86c8bbbe 2338 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2339 sprstate = ps;
86c8bbbe 2340 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2341 curstate = ps;
43d59eda
MR		 2342 }
2343
bf220452 2344 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded
ML		 2345 if (sprstate) {
2346 pipe_wm->sprites_enabled = sprstate->visible;
2347 pipe_wm->sprites_scaled = sprstate->visible &&
2348 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2349 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2350 }
2351
d81f04c5 2352 usable_level = max_level;
bf220452 2353
7b39a0b7 2354 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2355 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2356 usable_level = 1;
7b39a0b7
VS		 2357
2358 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2359 if (pipe_wm->sprites_scaled)
d81f04c5 2360 usable_level = 0;
7b39a0b7 2361
86c8bbbe 2362 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2363 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2364
2365 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2366 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2367
a42a5719 2368 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ee91a159 2369 pipe_wm->linetime = hsw_compute_linetime_wm(dev, cstate);
0b2ae6d7 2370
ed4a6a7c 2371 if (!ilk_validate_pipe_wm(dev, pipe_wm))
bf220452 2372 return -EINVAL;
a3cb4048
VS		 2373
2374 ilk_compute_wm_reg_maximums(dev, 1, &max);
2375
2376 for (level = 1; level <= max_level; level++) {
71f0a626 2377 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2378
86c8bbbe 2379 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2380 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2381
2382 /*
2383 * Disable any watermark level that exceeds the
2384 * register maximums since such watermarks are
2385 * always invalid.
2386 */
71f0a626
ML		 2387 if (level > usable_level)
2388 continue;
a3cb4048 2389
71f0a626
ML		 2390 if (ilk_validate_wm_level(level, &max, wm))
2391 pipe_wm->wm[level] = *wm;
2392 else
d81f04c5 2393 usable_level = level;
a3cb4048
VS		 2394 }
2395
86c8bbbe 2396 return 0;
0b2ae6d7
VS		 2397}
2398
ed4a6a7c
MR		 2399/*
2400 * Build a set of 'intermediate' watermark values that satisfy both the old
2401 * state and the new state. These can be programmed to the hardware
2402 * immediately.
2403 */
2404static int ilk_compute_intermediate_wm(struct drm_device *dev,
2405 struct intel_crtc *intel_crtc,
2406 struct intel_crtc_state *newstate)
2407{
2408 struct intel_pipe_wm *a = &newstate->wm.intermediate;
2409 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2410 int level, max_level = ilk_wm_max_level(dev);
2411
2412 /*
2413 * Start with the final, target watermarks, then combine with the
2414 * currently active watermarks to get values that are safe both before
2415 * and after the vblank.
2416 */
2417 *a = newstate->wm.optimal.ilk;
2418 a->pipe_enabled |= b->pipe_enabled;
2419 a->sprites_enabled |= b->sprites_enabled;
2420 a->sprites_scaled |= b->sprites_scaled;
2421
2422 for (level = 0; level <= max_level; level++) {
2423 struct intel_wm_level *a_wm = &a->wm[level];
2424 const struct intel_wm_level *b_wm = &b->wm[level];
2425
2426 a_wm->enable &= b_wm->enable;
2427 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2428 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2429 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2430 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2431 }
2432
2433 /*
2434 * We need to make sure that these merged watermark values are
2435 * actually a valid configuration themselves. If they're not,
2436 * there's no safe way to transition from the old state to
2437 * the new state, so we need to fail the atomic transaction.
2438 */
2439 if (!ilk_validate_pipe_wm(dev, a))
2440 return -EINVAL;
2441
2442 /*
2443 * If our intermediate WM are identical to the final WM, then we can
2444 * omit the post-vblank programming; only update if it's different.
2445 */
2446 if (memcmp(a, &newstate->wm.optimal.ilk, sizeof(*a)) == 0)
2447 newstate->wm.need_postvbl_update = false;
2448
2449 return 0;
2450}
2451
0b2ae6d7
VS		 2452/*
2453 * Merge the watermarks from all active pipes for a specific level.
2454 */
2455static void ilk_merge_wm_level(struct drm_device *dev,
2456 int level,
2457 struct intel_wm_level *ret_wm)
2458{
2459 const struct intel_crtc *intel_crtc;
2460
d52fea5b
VS		 2461 ret_wm->enable = true;
2462
d3fcc808 2463 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2464 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2465 const struct intel_wm_level *wm = &active->wm[level];
2466
2467 if (!active->pipe_enabled)
2468 continue;
0b2ae6d7 2469
d52fea5b
VS		 2470 /*
2471 * The watermark values may have been used in the past,
2472 * so we must maintain them in the registers for some
2473 * time even if the level is now disabled.
2474 */
0b2ae6d7 2475 if (!wm->enable)
d52fea5b 2476 ret_wm->enable = false;
0b2ae6d7
VS		 2477
2478 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2479 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2480 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2481 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2482 }
0b2ae6d7
VS		 2483}
2484
2485/*
2486 * Merge all low power watermarks for all active pipes.
2487 */
2488static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2489 const struct intel_wm_config *config,
820c1980 2490 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2491 struct intel_pipe_wm *merged)
2492{
7733b49b 2493 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2494 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2495 int last_enabled_level = max_level;
0b2ae6d7 2496
0ba22e26
VS		 2497 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2498 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2499 config->num_pipes_active > 1)
1204d5ba 2500 last_enabled_level = 0;
0ba22e26 2501
6c8b6c28
VS		 2502 /* ILK: FBC WM must be disabled always */
2503 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2504
2505 /* merge each WM1+ level */
2506 for (level = 1; level <= max_level; level++) {
2507 struct intel_wm_level *wm = &merged->wm[level];
2508
2509 ilk_merge_wm_level(dev, level, wm);
2510
d52fea5b
VS		 2511 if (level > last_enabled_level)
2512 wm->enable = false;
2513 else if (!ilk_validate_wm_level(level, max, wm))
2514 /* make sure all following levels get disabled */
2515 last_enabled_level = level - 1;
0b2ae6d7
VS		 2516
2517 /*
2518 * The spec says it is preferred to disable
2519 * FBC WMs instead of disabling a WM level.
2520 */
2521 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2522 if (wm->enable)
2523 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2524 wm->fbc_val = 0;
2525 }
2526 }
6c8b6c28
VS		 2527
2528 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2529 /*
2530 * FIXME this is racy. FBC might get enabled later.
2531 * What we should check here is whether FBC can be
2532 * enabled sometime later.
2533 */
7733b49b 2534 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2535 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2536 for (level = 2; level <= max_level; level++) {
2537 struct intel_wm_level *wm = &merged->wm[level];
2538
2539 wm->enable = false;
2540 }
2541 }
0b2ae6d7
VS		 2542}
2543
b380ca3c
VS		 2544static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2545{
2546 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2547 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2548}
2549
a68d68ee
VS		 2550/* The value we need to program into the WM_LPx latency field */
2551static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2552{
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2554
a42a5719 2555 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2556 return 2 * level;
2557 else
2558 return dev_priv->wm.pri_latency[level];
2559}
2560
820c1980 2561static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2562 const struct intel_pipe_wm *merged,
609cedef 2563 enum intel_ddb_partitioning partitioning,
820c1980 2564 struct ilk_wm_values *results)
801bcfff 2565{
0b2ae6d7
VS		 2566 struct intel_crtc *intel_crtc;
2567 int level, wm_lp;
cca32e9a 2568
0362c781 2569 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2570 results->partitioning = partitioning;
cca32e9a 2571
0b2ae6d7 2572 /* LP1+ register values */
cca32e9a 2573 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2574 const struct intel_wm_level *r;
801bcfff 2575
b380ca3c 2576 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2577
0362c781 2578 r = &merged->wm[level];
cca32e9a 2579
d52fea5b
VS		 2580 /*
2581 * Maintain the watermark values even if the level is
2582 * disabled. Doing otherwise could cause underruns.
2583 */
2584 results->wm_lp[wm_lp - 1] =
a68d68ee 2585 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2586 (r->pri_val << WM1_LP_SR_SHIFT) |
2587 r->cur_val;
2588
d52fea5b
VS		 2589 if (r->enable)
2590 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2591
416f4727
VS		 2592 if (INTEL_INFO(dev)->gen >= 8)
2593 results->wm_lp[wm_lp - 1] |=
2594 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2595 else
2596 results->wm_lp[wm_lp - 1] |=
2597 r->fbc_val << WM1_LP_FBC_SHIFT;
2598
d52fea5b
VS		 2599 /*
2600 * Always set WM1S_LP_EN when spr_val != 0, even if the
2601 * level is disabled. Doing otherwise could cause underruns.
2602 */
6cef2b8a
VS		 2603 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2604 WARN_ON(wm_lp != 1);
2605 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2606 } else
2607 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2608 }
801bcfff 2609
0b2ae6d7 2610 /* LP0 register values */
d3fcc808 2611 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2612 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2613 const struct intel_wm_level *r =
2614 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2615
2616 if (WARN_ON(!r->enable))
2617 continue;
2618
ed4a6a7c 2619 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2620
0b2ae6d7
VS		 2621 results->wm_pipe[pipe] =
2622 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2623 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2624 r->cur_val;
801bcfff
PZ		 2625 }
2626}
2627
861f3389
PZ		 2628/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2629 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2630static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2631 struct intel_pipe_wm *r1,
2632 struct intel_pipe_wm *r2)
861f3389 2633{
198a1e9b
VS		 2634 int level, max_level = ilk_wm_max_level(dev);
2635 int level1 = 0, level2 = 0;
861f3389 2636
198a1e9b
VS		 2637 for (level = 1; level <= max_level; level++) {
2638 if (r1->wm[level].enable)
2639 level1 = level;
2640 if (r2->wm[level].enable)
2641 level2 = level;
861f3389
PZ		 2642 }
2643
198a1e9b
VS		 2644 if (level1 == level2) {
2645 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2646 return r2;
2647 else
2648 return r1;
198a1e9b 2649 } else if (level1 > level2) {
861f3389
PZ		 2650 return r1;
2651 } else {
2652 return r2;
2653 }
2654}
2655
49a687c4
VS		 2656/* dirty bits used to track which watermarks need changes */
2657#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2658#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2659#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2660#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2661#define WM_DIRTY_FBC (1 << 24)
2662#define WM_DIRTY_DDB (1 << 25)
2663
055e393f 2664static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2665 const struct ilk_wm_values *old,
2666 const struct ilk_wm_values *new)
49a687c4
VS		 2667{
2668 unsigned int dirty = 0;
2669 enum pipe pipe;
2670 int wm_lp;
2671
055e393f 2672 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2673 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2674 dirty |= WM_DIRTY_LINETIME(pipe);
2675 /* Must disable LP1+ watermarks too */
2676 dirty |= WM_DIRTY_LP_ALL;
2677 }
2678
2679 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2680 dirty |= WM_DIRTY_PIPE(pipe);
2681 /* Must disable LP1+ watermarks too */
2682 dirty |= WM_DIRTY_LP_ALL;
2683 }
2684 }
2685
2686 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2687 dirty |= WM_DIRTY_FBC;
2688 /* Must disable LP1+ watermarks too */
2689 dirty |= WM_DIRTY_LP_ALL;
2690 }
2691
2692 if (old->partitioning != new->partitioning) {
2693 dirty |= WM_DIRTY_DDB;
2694 /* Must disable LP1+ watermarks too */
2695 dirty |= WM_DIRTY_LP_ALL;
2696 }
2697
2698 /* LP1+ watermarks already deemed dirty, no need to continue */
2699 if (dirty & WM_DIRTY_LP_ALL)
2700 return dirty;
2701
2702 /* Find the lowest numbered LP1+ watermark in need of an update... */
2703 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2704 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2705 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2706 break;
2707 }
2708
2709 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2710 for (; wm_lp <= 3; wm_lp++)
2711 dirty |= WM_DIRTY_LP(wm_lp);
2712
2713 return dirty;
2714}
2715
8553c18e
VS		 2716static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2717 unsigned int dirty)
801bcfff 2718{
820c1980 2719 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2720 bool changed = false;
801bcfff 2721
facd619b
VS		 2722 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2723 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2724 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2725 changed = true;
facd619b
VS		 2726 }
2727 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2728 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2729 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2730 changed = true;
facd619b
VS		 2731 }
2732 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2733 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2734 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2735 changed = true;
facd619b 2736 }
801bcfff 2737
facd619b
VS		 2738 /*
2739 * Don't touch WM1S_LP_EN here.
2740 * Doing so could cause underruns.
2741 */
6cef2b8a 2742
8553c18e
VS		 2743 return changed;
2744}
2745
2746/*
2747 * The spec says we shouldn't write when we don't need, because every write
2748 * causes WMs to be re-evaluated, expending some power.
2749 */
820c1980
ID		 2750static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2751 struct ilk_wm_values *results)
8553c18e
VS		 2752{
2753 struct drm_device *dev = dev_priv->dev;
820c1980 2754 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2755 unsigned int dirty;
2756 uint32_t val;
2757
055e393f 2758 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2759 if (!dirty)
2760 return;
2761
2762 _ilk_disable_lp_wm(dev_priv, dirty);
2763
49a687c4 2764 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2765 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2766 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2767 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2768 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2769 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2770
49a687c4 2771 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2772 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2773 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2774 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2775 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2776 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2777
49a687c4 2778 if (dirty & WM_DIRTY_DDB) {
a42a5719 2779 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2780 val = I915_READ(WM_MISC);
2781 if (results->partitioning == INTEL_DDB_PART_1_2)
2782 val &= ~WM_MISC_DATA_PARTITION_5_6;
2783 else
2784 val |= WM_MISC_DATA_PARTITION_5_6;
2785 I915_WRITE(WM_MISC, val);
2786 } else {
2787 val = I915_READ(DISP_ARB_CTL2);
2788 if (results->partitioning == INTEL_DDB_PART_1_2)
2789 val &= ~DISP_DATA_PARTITION_5_6;
2790 else
2791 val |= DISP_DATA_PARTITION_5_6;
2792 I915_WRITE(DISP_ARB_CTL2, val);
2793 }
1011d8c4
PZ		 2794 }
2795
49a687c4 2796 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2797 val = I915_READ(DISP_ARB_CTL);
2798 if (results->enable_fbc_wm)
2799 val &= ~DISP_FBC_WM_DIS;
2800 else
2801 val |= DISP_FBC_WM_DIS;
2802 I915_WRITE(DISP_ARB_CTL, val);
2803 }
2804
954911eb
ID		 2805 if (dirty & WM_DIRTY_LP(1) &&
2806 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2807 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2808
2809 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2810 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2811 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2812 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2813 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2814 }
801bcfff 2815
facd619b 2816 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2817 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2818 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2819 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2820 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2821 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2822
2823 dev_priv->wm.hw = *results;
801bcfff
PZ		 2824}
2825
ed4a6a7c 2826bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e
VS		 2827{
2828 struct drm_i915_private *dev_priv = dev->dev_private;
2829
2830 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2831}
2832
b9cec075
DL		 2833/*
2834 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2835 * different active planes.
2836 */
2837
2838#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2839#define BXT_DDB_SIZE 512
b9cec075 2840
024c9045
MR		 2841/*
2842 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2843 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2844 * other universal planes are in indices 1..n. Note that this may leave unused
2845 * indices between the top "sprite" plane and the cursor.
2846 */
2847static int
2848skl_wm_plane_id(const struct intel_plane *plane)
2849{
2850 switch (plane->base.type) {
2851 case DRM_PLANE_TYPE_PRIMARY:
2852 return 0;
2853 case DRM_PLANE_TYPE_CURSOR:
2854 return PLANE_CURSOR;
2855 case DRM_PLANE_TYPE_OVERLAY:
2856 return plane->plane + 1;
2857 default:
2858 MISSING_CASE(plane->base.type);
2859 return plane->plane;
2860 }
2861}
2862
b9cec075
DL		 2863static void
2864skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2865 const struct intel_crtc_state *cstate,
b9cec075 2866 const struct intel_wm_config *config,
b9cec075
DL		 2867 struct skl_ddb_entry *alloc /* out */)
2868{
024c9045 2869 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2870 struct drm_crtc *crtc;
2871 unsigned int pipe_size, ddb_size;
2872 int nth_active_pipe;
2873
024c9045 2874 if (!cstate->base.active) {
b9cec075
DL		 2875 alloc->start = 0;
2876 alloc->end = 0;
2877 return;
2878 }
2879
43d735a6
DL		 2880 if (IS_BROXTON(dev))
2881 ddb_size = BXT_DDB_SIZE;
2882 else
2883 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2884
2885 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2886
2887 nth_active_pipe = 0;
2888 for_each_crtc(dev, crtc) {
3ef00284 2889 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2890 continue;
2891
2892 if (crtc == for_crtc)
2893 break;
2894
2895 nth_active_pipe++;
2896 }
2897
2898 pipe_size = ddb_size / config->num_pipes_active;
2899 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2900 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2901}
2902
2903static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2904{
2905 if (config->num_pipes_active == 1)
2906 return 32;
2907
2908 return 8;
2909}
2910
a269c583
DL		 2911static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2912{
2913 entry->start = reg & 0x3ff;
2914 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2915 if (entry->end)
2916 entry->end += 1;
a269c583
DL		 2917}
2918
08db6652
DL		 2919void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2920 struct skl_ddb_allocation *ddb /* out */)
a269c583 2921{
a269c583
DL		 2922 enum pipe pipe;
2923 int plane;
2924 u32 val;
2925
b10f1b20
ML		 2926 memset(ddb, 0, sizeof(*ddb));
2927
a269c583 2928 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 2929 enum intel_display_power_domain power_domain;
2930
2931 power_domain = POWER_DOMAIN_PIPE(pipe);
2932 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 2933 continue;
2934
dd740780 2935 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2936 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2937 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2938 val);
2939 }
2940
2941 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2942 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2943 val);
4d800030
ID		 2944
2945 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 2946 }
2947}
2948
b9cec075 2949static unsigned int
024c9045
MR		 2950skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2951 const struct drm_plane_state *pstate,
2952 int y)
b9cec075 2953{
9aec6a08 2954 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 2955 struct drm_framebuffer *fb = pstate->fb;
9aec6a08
KM		 2956 uint32_t width = 0, height = 0;
2957
2958 width = drm_rect_width(&intel_pstate->src) >> 16;
2959 height = drm_rect_height(&intel_pstate->src) >> 16;
2960
2961 if (intel_rotation_90_or_270(pstate->rotation))
2962 swap(width, height);
2cd601c6
CK		 2963
2964 /* for planar format */
024c9045 2965 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2966 if (y) /* y-plane data rate */
9aec6a08 2967 return width * height *
024c9045 2968 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2969 else /* uv-plane data rate */
9aec6a08 2970 return (width / 2) * (height / 2) *
024c9045 2971 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2972 }
2973
2974 /* for packed formats */
9aec6a08 2975 return width * height * drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2976}
2977
2978/*
2979 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2980 * a 8192x4096@32bpp framebuffer:
2981 * 3 * 4096 * 8192 * 4 < 2^32
2982 */
2983static unsigned int
024c9045 2984skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2985{
024c9045
MR		 2986 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2987 struct drm_device *dev = intel_crtc->base.dev;
2988 const struct intel_plane *intel_plane;
b9cec075 2989 unsigned int total_data_rate = 0;
b9cec075 2990
024c9045
MR		 2991 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2992 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2993
024c9045 2994 if (pstate->fb == NULL)
b9cec075
DL		 2995 continue;
2996
024c9045
MR		 2997 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2998 continue;
2999
3000 /* packed/uv */
3001 total_data_rate += skl_plane_relative_data_rate(cstate,
3002 pstate,
3003 0);
3004
3005 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
3006 /* y-plane */
3007 total_data_rate += skl_plane_relative_data_rate(cstate,
3008 pstate,
3009 1);
b9cec075
DL		 3010 }
3011
3012 return total_data_rate;
3013}
3014
3015static void
024c9045 3016skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3017 struct skl_ddb_allocation *ddb /* out */)
3018{
024c9045 3019 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 3020 struct drm_device *dev = crtc->dev;
aa363136
MR		 3021 struct drm_i915_private *dev_priv = to_i915(dev);
3022 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 3023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3024 struct intel_plane *intel_plane;
b9cec075 3025 enum pipe pipe = intel_crtc->pipe;
34bb56af 3026 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3027 uint16_t alloc_size, start, cursor_blocks;
80958155 3028 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 3029 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 3030 unsigned int total_data_rate;
b9cec075 3031
024c9045 3032 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 3033 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3034 if (alloc_size == 0) {
3035 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 3036 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
3037 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 3038 return;
3039 }
3040
3041 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 3042 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3043 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3044
3045 alloc_size -= cursor_blocks;
34bb56af 3046 alloc->end -= cursor_blocks;
b9cec075 3047
80958155 3048 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 3049 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3050 struct drm_plane *plane = &intel_plane->base;
3051 struct drm_framebuffer *fb = plane->state->fb;
3052 int id = skl_wm_plane_id(intel_plane);
80958155 3053
9aec6a08 3054 if (!to_intel_plane_state(plane->state)->visible)
024c9045 3055 continue;
9aec6a08 3056
024c9045 3057 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 3058 continue;
3059
024c9045
MR		 3060 minimum[id] = 8;
3061 alloc_size -= minimum[id];
3062 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
3063 alloc_size -= y_minimum[id];
80958155
DL		 3064 }
3065
b9cec075 3066 /*
80958155
DL		 3067 * 2. Distribute the remaining space in proportion to the amount of
3068 * data each plane needs to fetch from memory.
b9cec075
DL		 3069 *
3070 * FIXME: we may not allocate every single block here.
3071 */
024c9045 3072 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 3073
34bb56af 3074 start = alloc->start;
024c9045
MR		 3075 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3076 struct drm_plane *plane = &intel_plane->base;
3077 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 3078 unsigned int data_rate, y_data_rate;
3079 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3080 int id = skl_wm_plane_id(intel_plane);
b9cec075 3081
9aec6a08 3082 if (!to_intel_plane_state(pstate)->visible)
024c9045
MR		 3083 continue;
3084 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 3085 continue;
3086
024c9045 3087 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 3088
3089 /*
2cd601c6 3090 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3091 * promote the expression to 64 bits to avoid overflowing, the
3092 * result is < available as data_rate / total_data_rate < 1
3093 */
024c9045 3094 plane_blocks = minimum[id];
80958155
DL		 3095 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3096 total_data_rate);
b9cec075 3097
024c9045
MR		 3098 ddb->plane[pipe][id].start = start;
3099 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 3100
3101 start += plane_blocks;
2cd601c6
CK		 3102
3103 /*
3104 * allocation for y_plane part of planar format:
3105 */
024c9045
MR		 3106 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
3107 y_data_rate = skl_plane_relative_data_rate(cstate,
3108 pstate,
3109 1);
3110 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3111 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3112 total_data_rate);
3113
024c9045
MR		 3114 ddb->y_plane[pipe][id].start = start;
3115 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3116
3117 start += y_plane_blocks;
3118 }
3119
b9cec075
DL		 3120 }
3121
3122}
3123
5cec258b 3124static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3125{
3126 /* TODO: Take into account the scalers once we support them */
2d112de7 3127 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3128}
3129
3130/*
3131 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3132 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3133 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3134 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3135*/
ac484963 3136static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3137{
3138 uint32_t wm_intermediate_val, ret;
3139
3140 if (latency == 0)
3141 return UINT_MAX;
3142
ac484963 3143 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3144 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3145
3146 return ret;
3147}
3148
3149static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 3150 uint32_t horiz_pixels, uint8_t cpp,
0fda6568 3151 uint64_t tiling, uint32_t latency)
2d41c0b5 3152{
d4c2aa60
TU		 3153 uint32_t ret;
3154 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3155 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3156
3157 if (latency == 0)
3158 return UINT_MAX;
3159
ac484963 3160 plane_bytes_per_line = horiz_pixels * cpp;
0fda6568
TU		 3161
3162 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3163 tiling == I915_FORMAT_MOD_Yf_TILED) {
3164 plane_bytes_per_line *= 4;
3165 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3166 plane_blocks_per_line /= 4;
3167 } else {
3168 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3169 }
3170
2d41c0b5
PB		 3171 wm_intermediate_val = latency * pixel_rate;
3172 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3173 plane_blocks_per_line;
2d41c0b5
PB		 3174
3175 return ret;
3176}
3177
2d41c0b5
PB		 3178static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3179 const struct intel_crtc *intel_crtc)
3180{
3181 struct drm_device *dev = intel_crtc->base.dev;
3182 struct drm_i915_private *dev_priv = dev->dev_private;
3183 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3184
e6d90023
KM		 3185 /*
3186 * If ddb allocation of pipes changed, it may require recalculation of
3187 * watermarks
3188 */
3189 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3190 return true;
3191
3192 return false;
3193}
3194
d4c2aa60 3195static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3196 struct intel_crtc_state *cstate,
3197 struct intel_plane *intel_plane,
afb024aa 3198 uint16_t ddb_allocation,
d4c2aa60 3199 int level,
afb024aa
DL		 3200 uint16_t *out_blocks, /* out */
3201 uint8_t *out_lines /* out */)
2d41c0b5 3202{
024c9045
MR		 3203 struct drm_plane *plane = &intel_plane->base;
3204 struct drm_framebuffer *fb = plane->state->fb;
9aec6a08
KM		 3205 struct intel_plane_state *intel_pstate =
3206 to_intel_plane_state(plane->state);
d4c2aa60
TU		 3207 uint32_t latency = dev_priv->wm.skl_latency[level];
3208 uint32_t method1, method2;
3209 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3210 uint32_t res_blocks, res_lines;
3211 uint32_t selected_result;
ac484963 3212 uint8_t cpp;
9aec6a08 3213 uint32_t width = 0, height = 0;
2d41c0b5 3214
9aec6a08 3215 if (latency == 0 || !cstate->base.active || !intel_pstate->visible)
2d41c0b5
PB		 3216 return false;
3217
9aec6a08
KM		 3218 width = drm_rect_width(&intel_pstate->src) >> 16;
3219 height = drm_rect_height(&intel_pstate->src) >> 16;
3220
3221 if (intel_rotation_90_or_270(plane->state->rotation))
3222 swap(width, height);
3223
ac484963 3224 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
024c9045 3225 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
ac484963 3226 cpp, latency);
024c9045
MR		 3227 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3228 cstate->base.adjusted_mode.crtc_htotal,
9aec6a08
KM		 3229 width,
3230 cpp,
3231 fb->modifier[0],
d4c2aa60 3232 latency);
2d41c0b5 3233
9aec6a08 3234 plane_bytes_per_line = width * cpp;
d4c2aa60 3235 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3236
024c9045
MR		 3237 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3238 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3239 uint32_t min_scanlines = 4;
3240 uint32_t y_tile_minimum;
024c9045 3241 if (intel_rotation_90_or_270(plane->state->rotation)) {
ac484963 3242 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
024c9045
MR		 3243 drm_format_plane_cpp(fb->pixel_format, 1) :
3244 drm_format_plane_cpp(fb->pixel_format, 0);
3245
ac484963 3246 switch (cpp) {
1fc0a8f7
TU		 3247 case 1:
3248 min_scanlines = 16;
3249 break;
3250 case 2:
3251 min_scanlines = 8;
3252 break;
3253 case 8:
3254 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3255 }
1fc0a8f7
TU		 3256 }
3257 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3258 selected_result = max(method2, y_tile_minimum);
3259 } else {
3260 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3261 selected_result = min(method1, method2);
3262 else
3263 selected_result = method1;
3264 }
2d41c0b5 3265
d4c2aa60
TU		 3266 res_blocks = selected_result + 1;
3267 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3268
0fda6568 3269 if (level >= 1 && level <= 7) {
024c9045
MR		 3270 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3271 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3272 res_lines += 4;
3273 else
3274 res_blocks++;
3275 }
e6d66171 3276
d4c2aa60 3277 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3278 return false;
3279
3280 *out_blocks = res_blocks;
3281 *out_lines = res_lines;
2d41c0b5
PB		 3282
3283 return true;
3284}
3285
3286static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3287 struct skl_ddb_allocation *ddb,
024c9045 3288 struct intel_crtc_state *cstate,
2d41c0b5 3289 int level,
2d41c0b5
PB		 3290 struct skl_wm_level *result)
3291{
024c9045
MR		 3292 struct drm_device *dev = dev_priv->dev;
3293 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3294 struct intel_plane *intel_plane;
2d41c0b5 3295 uint16_t ddb_blocks;
024c9045
MR		 3296 enum pipe pipe = intel_crtc->pipe;
3297
3298 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3299 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3300
2d41c0b5
PB		 3301 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3302
d4c2aa60 3303 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3304 cstate,
3305 intel_plane,
2d41c0b5 3306 ddb_blocks,
d4c2aa60 3307 level,
2d41c0b5
PB		 3308 &result->plane_res_b[i],
3309 &result->plane_res_l[i]);
3310 }
2d41c0b5
PB		 3311}
3312
407b50f3 3313static uint32_t
024c9045 3314skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3315{
024c9045 3316 if (!cstate->base.active)
407b50f3
DL		 3317 return 0;
3318
024c9045 3319 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3320 return 0;
407b50f3 3321
024c9045
MR		 3322 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3323 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3324}
3325
024c9045 3326static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3327 struct skl_wm_level *trans_wm /* out */)
407b50f3 3328{
024c9045 3329 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3331 struct intel_plane *intel_plane;
9414f563 3332
024c9045 3333 if (!cstate->base.active)
407b50f3 3334 return;
9414f563
DL		 3335
3336 /* Until we know more, just disable transition WMs */
024c9045
MR		 3337 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3338 int i = skl_wm_plane_id(intel_plane);
3339
9414f563 3340 trans_wm->plane_en[i] = false;
024c9045 3341 }
407b50f3
DL		 3342}
3343
024c9045 3344static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3345 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3346 struct skl_pipe_wm *pipe_wm)
3347{
024c9045 3348 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3349 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3350 int level, max_level = ilk_wm_max_level(dev);
3351
3352 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3353 skl_compute_wm_level(dev_priv, ddb, cstate,
3354 level, &pipe_wm->wm[level]);
2d41c0b5 3355 }
024c9045 3356 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3357
024c9045 3358 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3359}
3360
3361static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3362 struct skl_pipe_wm *p_wm,
3363 struct skl_wm_values *r,
3364 struct intel_crtc *intel_crtc)
3365{
3366 int level, max_level = ilk_wm_max_level(dev);
3367 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3368 uint32_t temp;
3369 int i;
2d41c0b5
PB		 3370
3371 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3372 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3373 temp = 0;
2d41c0b5
PB		 3374
3375 temp |= p_wm->wm[level].plane_res_l[i] <<
3376 PLANE_WM_LINES_SHIFT;
3377 temp |= p_wm->wm[level].plane_res_b[i];
3378 if (p_wm->wm[level].plane_en[i])
3379 temp |= PLANE_WM_EN;
3380
3381 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3382 }
3383
3384 temp = 0;
2d41c0b5 3385
4969d33e
MR		 3386 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3387 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3388
4969d33e 3389 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3390 temp |= PLANE_WM_EN;
3391
4969d33e 3392 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3393
3394 }
3395
9414f563
DL		 3396 /* transition WMs */
3397 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3398 temp = 0;
3399 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3400 temp |= p_wm->trans_wm.plane_res_b[i];
3401 if (p_wm->trans_wm.plane_en[i])
3402 temp |= PLANE_WM_EN;
3403
3404 r->plane_trans[pipe][i] = temp;
3405 }
3406
3407 temp = 0;
4969d33e
MR		 3408 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3409 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3410 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3411 temp |= PLANE_WM_EN;
3412
4969d33e 3413 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3414
2d41c0b5
PB		 3415 r->wm_linetime[pipe] = p_wm->linetime;
3416}
3417
f0f59a00
VS		 3418static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3419 i915_reg_t reg,
16160e3d
DL		 3420 const struct skl_ddb_entry *entry)
3421{
3422 if (entry->end)
3423 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3424 else
3425 I915_WRITE(reg, 0);
3426}
3427
2d41c0b5
PB		 3428static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3429 const struct skl_wm_values *new)
3430{
3431 struct drm_device *dev = dev_priv->dev;
3432 struct intel_crtc *crtc;
3433
19c8054c 3434 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3435 int i, level, max_level = ilk_wm_max_level(dev);
3436 enum pipe pipe = crtc->pipe;
3437
5d374d96
DL		 3438 if (!new->dirty[pipe])
3439 continue;
8211bd5b 3440
5d374d96 3441 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3442
5d374d96
DL		 3443 for (level = 0; level <= max_level; level++) {
3444 for (i = 0; i < intel_num_planes(crtc); i++)
3445 I915_WRITE(PLANE_WM(pipe, i, level),
3446 new->plane[pipe][i][level]);
3447 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3448 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3449 }
5d374d96
DL		 3450 for (i = 0; i < intel_num_planes(crtc); i++)
3451 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3452 new->plane_trans[pipe][i]);
4969d33e
MR		 3453 I915_WRITE(CUR_WM_TRANS(pipe),
3454 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3455
2cd601c6 3456 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3457 skl_ddb_entry_write(dev_priv,
3458 PLANE_BUF_CFG(pipe, i),
3459 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3460 skl_ddb_entry_write(dev_priv,
3461 PLANE_NV12_BUF_CFG(pipe, i),
3462 &new->ddb.y_plane[pipe][i]);
3463 }
5d374d96
DL		 3464
3465 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3466 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3467 }
2d41c0b5
PB		 3468}
3469
0e8fb7ba
DL		 3470/*
3471 * When setting up a new DDB allocation arrangement, we need to correctly
3472 * sequence the times at which the new allocations for the pipes are taken into
3473 * account or we'll have pipes fetching from space previously allocated to
3474 * another pipe.
3475 *
3476 * Roughly the sequence looks like:
3477 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3478 * overlapping with a previous light-up pipe (another way to put it is:
3479 * pipes with their new allocation strickly included into their old ones).
3480 * 2. re-allocate the other pipes that get their allocation reduced
3481 * 3. allocate the pipes having their allocation increased
3482 *
3483 * Steps 1. and 2. are here to take care of the following case:
3484 * - Initially DDB looks like this:
3485 * | B | C |
3486 * - enable pipe A.
3487 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3488 * allocation
3489 * | A | B | C |
3490 *
3491 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3492 */
3493
d21b795c
DL		 3494static void
3495skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3496{
0e8fb7ba
DL		 3497 int plane;
3498
d21b795c
DL		 3499 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3500
dd740780 3501 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3502 I915_WRITE(PLANE_SURF(pipe, plane),
3503 I915_READ(PLANE_SURF(pipe, plane)));
3504 }
3505 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3506}
3507
3508static bool
3509skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3510 const struct skl_ddb_allocation *new,
3511 enum pipe pipe)
3512{
3513 uint16_t old_size, new_size;
3514
3515 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3516 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3517
3518 return old_size != new_size &&
3519 new->pipe[pipe].start >= old->pipe[pipe].start &&
3520 new->pipe[pipe].end <= old->pipe[pipe].end;
3521}
3522
3523static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3524 struct skl_wm_values *new_values)
3525{
3526 struct drm_device *dev = dev_priv->dev;
3527 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3528 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3529 struct intel_crtc *crtc;
3530 enum pipe pipe;
3531
3532 new_ddb = &new_values->ddb;
3533 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3534
3535 /*
3536 * First pass: flush the pipes with the new allocation contained into
3537 * the old space.
3538 *
3539 * We'll wait for the vblank on those pipes to ensure we can safely
3540 * re-allocate the freed space without this pipe fetching from it.
3541 */
3542 for_each_intel_crtc(dev, crtc) {
3543 if (!crtc->active)
3544 continue;
3545
3546 pipe = crtc->pipe;
3547
3548 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3549 continue;
3550
d21b795c 3551 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3552 intel_wait_for_vblank(dev, pipe);
3553
3554 reallocated[pipe] = true;
3555 }
3556
3557
3558 /*
3559 * Second pass: flush the pipes that are having their allocation
3560 * reduced, but overlapping with a previous allocation.
3561 *
3562 * Here as well we need to wait for the vblank to make sure the freed
3563 * space is not used anymore.
3564 */
3565 for_each_intel_crtc(dev, crtc) {
3566 if (!crtc->active)
3567 continue;
3568
3569 pipe = crtc->pipe;
3570
3571 if (reallocated[pipe])
3572 continue;
3573
3574 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3575 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3576 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3577 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3578 reallocated[pipe] = true;
0e8fb7ba 3579 }
0e8fb7ba
DL		 3580 }
3581
3582 /*
3583 * Third pass: flush the pipes that got more space allocated.
3584 *
3585 * We don't need to actively wait for the update here, next vblank
3586 * will just get more DDB space with the correct WM values.
3587 */
3588 for_each_intel_crtc(dev, crtc) {
3589 if (!crtc->active)
3590 continue;
3591
3592 pipe = crtc->pipe;
3593
3594 /*
3595 * At this point, only the pipes more space than before are
3596 * left to re-allocate.
3597 */
3598 if (reallocated[pipe])
3599 continue;
3600
d21b795c 3601 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3602 }
3603}
3604
2d41c0b5 3605static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3606 struct skl_ddb_allocation *ddb, /* out */
3607 struct skl_pipe_wm *pipe_wm /* out */)
3608{
3609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3610 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3611
aa363136 3612 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3613 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3614
4e0963c7 3615 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3616 return false;
3617
4e0963c7 3618 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3619
2d41c0b5
PB		 3620 return true;
3621}
3622
3623static void skl_update_other_pipe_wm(struct drm_device *dev,
3624 struct drm_crtc *crtc,
2d41c0b5
PB		 3625 struct skl_wm_values *r)
3626{
3627 struct intel_crtc *intel_crtc;
3628 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3629
3630 /*
3631 * If the WM update hasn't changed the allocation for this_crtc (the
3632 * crtc we are currently computing the new WM values for), other
3633 * enabled crtcs will keep the same allocation and we don't need to
3634 * recompute anything for them.
3635 */
3636 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3637 return;
3638
3639 /*
3640 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3641 * other active pipes need new DDB allocation and WM values.
3642 */
19c8054c 3643 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3644 struct skl_pipe_wm pipe_wm = {};
3645 bool wm_changed;
3646
3647 if (this_crtc->pipe == intel_crtc->pipe)
3648 continue;
3649
3650 if (!intel_crtc->active)
3651 continue;
3652
aa363136 3653 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3654 &r->ddb, &pipe_wm);
3655
3656 /*
3657 * If we end up re-computing the other pipe WM values, it's
3658 * because it was really needed, so we expect the WM values to
3659 * be different.
3660 */
3661 WARN_ON(!wm_changed);
3662
024c9045 3663 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3664 r->dirty[intel_crtc->pipe] = true;
3665 }
3666}
3667
adda50b8
BP		 3668static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3669{
3670 watermarks->wm_linetime[pipe] = 0;
3671 memset(watermarks->plane[pipe], 0,
3672 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3673 memset(watermarks->plane_trans[pipe],
3674 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3675 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3676
3677 /* Clear ddb entries for pipe */
3678 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3679 memset(&watermarks->ddb.plane[pipe], 0,
3680 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3681 memset(&watermarks->ddb.y_plane[pipe], 0,
3682 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3683 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3684 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3685
3686}
3687
2d41c0b5
PB		 3688static void skl_update_wm(struct drm_crtc *crtc)
3689{
3690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3691 struct drm_device *dev = crtc->dev;
3692 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3693 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3694 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3695 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3696
adda50b8
BP		 3697
3698 /* Clear all dirty flags */
3699 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3700
3701 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3702
aa363136 3703 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3704 return;
3705
4e0963c7 3706 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3707 results->dirty[intel_crtc->pipe] = true;
3708
aa363136 3709 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3710 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3711 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3712
3713 /* store the new configuration */
3714 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3715}
3716
d890565c
VS		 3717static void ilk_compute_wm_config(struct drm_device *dev,
3718 struct intel_wm_config *config)
3719{
3720 struct intel_crtc *crtc;
3721
3722 /* Compute the currently _active_ config */
3723 for_each_intel_crtc(dev, crtc) {
3724 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
3725
3726 if (!wm->pipe_enabled)
3727 continue;
3728
3729 config->sprites_enabled |= wm->sprites_enabled;
3730 config->sprites_scaled |= wm->sprites_scaled;
3731 config->num_pipes_active++;
3732 }
3733}
3734
ed4a6a7c 3735static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3736{
ed4a6a7c 3737 struct drm_device *dev = dev_priv->dev;
b9d5c839 3738 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3739 struct ilk_wm_maximums max;
d890565c 3740 struct intel_wm_config config = {};
820c1980 3741 struct ilk_wm_values results = {};
77c122bc 3742 enum intel_ddb_partitioning partitioning;
261a27d1 3743
d890565c
VS		 3744 ilk_compute_wm_config(dev, &config);
3745
3746 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
3747 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3748
3749 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3750 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 3751 config.num_pipes_active == 1 && config.sprites_enabled) {
3752 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
3753 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3754
820c1980 3755 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3756 } else {
198a1e9b 3757 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3758 }
3759
198a1e9b 3760 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3761 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3762
820c1980 3763 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3764
820c1980 3765 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3766}
3767
ed4a6a7c 3768static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 3769{
ed4a6a7c
MR		 3770 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3771 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 3772
ed4a6a7c
MR		 3773 mutex_lock(&dev_priv->wm.wm_mutex);
3774 intel_crtc->wm.active.ilk = cstate->wm.intermediate;
3775 ilk_program_watermarks(dev_priv);
3776 mutex_unlock(&dev_priv->wm.wm_mutex);
3777}
bf220452 3778
ed4a6a7c
MR		 3779static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
3780{
3781 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
3782 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 3783
ed4a6a7c
MR		 3784 mutex_lock(&dev_priv->wm.wm_mutex);
3785 if (cstate->wm.need_postvbl_update) {
3786 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3787 ilk_program_watermarks(dev_priv);
3788 }
3789 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 3790}
3791
3078999f
PB		 3792static void skl_pipe_wm_active_state(uint32_t val,
3793 struct skl_pipe_wm *active,
3794 bool is_transwm,
3795 bool is_cursor,
3796 int i,
3797 int level)
3798{
3799 bool is_enabled = (val & PLANE_WM_EN) != 0;
3800
3801 if (!is_transwm) {
3802 if (!is_cursor) {
3803 active->wm[level].plane_en[i] = is_enabled;
3804 active->wm[level].plane_res_b[i] =
3805 val & PLANE_WM_BLOCKS_MASK;
3806 active->wm[level].plane_res_l[i] =
3807 (val >> PLANE_WM_LINES_SHIFT) &
3808 PLANE_WM_LINES_MASK;
3809 } else {
4969d33e
MR		 3810 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3811 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3812 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3813 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3814 (val >> PLANE_WM_LINES_SHIFT) &
3815 PLANE_WM_LINES_MASK;
3816 }
3817 } else {
3818 if (!is_cursor) {
3819 active->trans_wm.plane_en[i] = is_enabled;
3820 active->trans_wm.plane_res_b[i] =
3821 val & PLANE_WM_BLOCKS_MASK;
3822 active->trans_wm.plane_res_l[i] =
3823 (val >> PLANE_WM_LINES_SHIFT) &
3824 PLANE_WM_LINES_MASK;
3825 } else {
4969d33e
MR		 3826 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3827 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3828 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3829 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3830 (val >> PLANE_WM_LINES_SHIFT) &
3831 PLANE_WM_LINES_MASK;
3832 }
3833 }
3834}
3835
3836static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3837{
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3842 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3843 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3844 enum pipe pipe = intel_crtc->pipe;
3845 int level, i, max_level;
3846 uint32_t temp;
3847
3848 max_level = ilk_wm_max_level(dev);
3849
3850 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3851
3852 for (level = 0; level <= max_level; level++) {
3853 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3854 hw->plane[pipe][i][level] =
3855 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3856 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3857 }
3858
3859 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3860 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3861 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3862
3ef00284 3863 if (!intel_crtc->active)
3078999f
PB		 3864 return;
3865
3866 hw->dirty[pipe] = true;
3867
3868 active->linetime = hw->wm_linetime[pipe];
3869
3870 for (level = 0; level <= max_level; level++) {
3871 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3872 temp = hw->plane[pipe][i][level];
3873 skl_pipe_wm_active_state(temp, active, false,
3874 false, i, level);
3875 }
4969d33e 3876 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3877 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3878 }
3879
3880 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3881 temp = hw->plane_trans[pipe][i];
3882 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3883 }
3884
4969d33e 3885 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3886 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3887
3888 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3889}
3890
3891void skl_wm_get_hw_state(struct drm_device *dev)
3892{
a269c583
DL		 3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3895 struct drm_crtc *crtc;
3896
a269c583 3897 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3898 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3899 skl_pipe_wm_get_hw_state(crtc);
3900}
3901
243e6a44
VS		 3902static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3903{
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3906 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3908 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3909 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3910 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3911 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3912 [PIPE_A] = WM0_PIPEA_ILK,
3913 [PIPE_B] = WM0_PIPEB_ILK,
3914 [PIPE_C] = WM0_PIPEC_IVB,
3915 };
3916
3917 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3918 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3919 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3920
7045c368
VS		 3921 memset(active, 0, sizeof(*active));
3922
3ef00284 3923 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3924
3925 if (active->pipe_enabled) {
243e6a44
VS		 3926 u32 tmp = hw->wm_pipe[pipe];
3927
3928 /*
3929 * For active pipes LP0 watermark is marked as
3930 * enabled, and LP1+ watermaks as disabled since
3931 * we can't really reverse compute them in case
3932 * multiple pipes are active.
3933 */
3934 active->wm[0].enable = true;
3935 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3936 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3937 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3938 active->linetime = hw->wm_linetime[pipe];
3939 } else {
3940 int level, max_level = ilk_wm_max_level(dev);
3941
3942 /*
3943 * For inactive pipes, all watermark levels
3944 * should be marked as enabled but zeroed,
3945 * which is what we'd compute them to.
3946 */
3947 for (level = 0; level <= max_level; level++)
3948 active->wm[level].enable = true;
3949 }
4e0963c7
MR		 3950
3951 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3952}
3953
6eb1a681
VS		 3954#define _FW_WM(value, plane) \
3955 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3956#define _FW_WM_VLV(value, plane) \
3957 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3958
3959static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3960 struct vlv_wm_values *wm)
3961{
3962 enum pipe pipe;
3963 uint32_t tmp;
3964
3965 for_each_pipe(dev_priv, pipe) {
3966 tmp = I915_READ(VLV_DDL(pipe));
3967
3968 wm->ddl[pipe].primary =
3969 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3970 wm->ddl[pipe].cursor =
3971 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3972 wm->ddl[pipe].sprite[0] =
3973 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3974 wm->ddl[pipe].sprite[1] =
3975 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3976 }
3977
3978 tmp = I915_READ(DSPFW1);
3979 wm->sr.plane = _FW_WM(tmp, SR);
3980 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3981 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3982 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3983
3984 tmp = I915_READ(DSPFW2);
3985 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3986 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3987 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3988
3989 tmp = I915_READ(DSPFW3);
3990 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3991
3992 if (IS_CHERRYVIEW(dev_priv)) {
3993 tmp = I915_READ(DSPFW7_CHV);
3994 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3995 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3996
3997 tmp = I915_READ(DSPFW8_CHV);
3998 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3999 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4000
4001 tmp = I915_READ(DSPFW9_CHV);
4002 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4003 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4004
4005 tmp = I915_READ(DSPHOWM);
4006 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4007 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4008 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4009 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4010 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4011 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4012 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4013 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4014 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4015 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4016 } else {
4017 tmp = I915_READ(DSPFW7);
4018 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4019 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4020
4021 tmp = I915_READ(DSPHOWM);
4022 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4023 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4024 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4025 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4026 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4027 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4028 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4029 }
4030}
4031
4032#undef _FW_WM
4033#undef _FW_WM_VLV
4034
4035void vlv_wm_get_hw_state(struct drm_device *dev)
4036{
4037 struct drm_i915_private *dev_priv = to_i915(dev);
4038 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4039 struct intel_plane *plane;
4040 enum pipe pipe;
4041 u32 val;
4042
4043 vlv_read_wm_values(dev_priv, wm);
4044
4045 for_each_intel_plane(dev, plane) {
4046 switch (plane->base.type) {
4047 int sprite;
4048 case DRM_PLANE_TYPE_CURSOR:
4049 plane->wm.fifo_size = 63;
4050 break;
4051 case DRM_PLANE_TYPE_PRIMARY:
4052 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4053 break;
4054 case DRM_PLANE_TYPE_OVERLAY:
4055 sprite = plane->plane;
4056 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4057 break;
4058 }
4059 }
4060
4061 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4062 wm->level = VLV_WM_LEVEL_PM2;
4063
4064 if (IS_CHERRYVIEW(dev_priv)) {
4065 mutex_lock(&dev_priv->rps.hw_lock);
4066
4067 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4068 if (val & DSP_MAXFIFO_PM5_ENABLE)
4069 wm->level = VLV_WM_LEVEL_PM5;
4070
58590c14
VS		 4071 /*
4072 * If DDR DVFS is disabled in the BIOS, Punit
4073 * will never ack the request. So if that happens
4074 * assume we don't have to enable/disable DDR DVFS
4075 * dynamically. To test that just set the REQ_ACK
4076 * bit to poke the Punit, but don't change the
4077 * HIGH/LOW bits so that we don't actually change
4078 * the current state.
4079 */
6eb1a681 4080 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4081 val |= FORCE_DDR_FREQ_REQ_ACK;
4082 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4083
4084 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4085 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4086 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4087 "assuming DDR DVFS is disabled\n");
4088 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4089 } else {
4090 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4091 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4092 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4093 }
6eb1a681
VS		 4094
4095 mutex_unlock(&dev_priv->rps.hw_lock);
4096 }
4097
4098 for_each_pipe(dev_priv, pipe)
4099 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4100 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4101 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4102
4103 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4104 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4105}
4106
243e6a44
VS		 4107void ilk_wm_get_hw_state(struct drm_device *dev)
4108{
4109 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4110 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4111 struct drm_crtc *crtc;
4112
70e1e0ec 4113 for_each_crtc(dev, crtc)
243e6a44
VS		 4114 ilk_pipe_wm_get_hw_state(crtc);
4115
4116 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4117 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4118 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4119
4120 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4121 if (INTEL_INFO(dev)->gen >= 7) {
4122 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4123 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4124 }
243e6a44 4125
a42a5719 4126 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4127 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4128 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4129 else if (IS_IVYBRIDGE(dev))
4130 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4131 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4132
4133 hw->enable_fbc_wm =
4134 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4135}
4136
b445e3b0
ED		 4137/**
4138 * intel_update_watermarks - update FIFO watermark values based on current modes
4139 *
4140 * Calculate watermark values for the various WM regs based on current mode
4141 * and plane configuration.
4142 *
4143 * There are several cases to deal with here:
4144 * - normal (i.e. non-self-refresh)
4145 * - self-refresh (SR) mode
4146 * - lines are large relative to FIFO size (buffer can hold up to 2)
4147 * - lines are small relative to FIFO size (buffer can hold more than 2
4148 * lines), so need to account for TLB latency
4149 *
4150 * The normal calculation is:
4151 * watermark = dotclock * bytes per pixel * latency
4152 * where latency is platform & configuration dependent (we assume pessimal
4153 * values here).
4154 *
4155 * The SR calculation is:
4156 * watermark = (trunc(latency/line time)+1) * surface width *
4157 * bytes per pixel
4158 * where
4159 * line time = htotal / dotclock
4160 * surface width = hdisplay for normal plane and 64 for cursor
4161 * and latency is assumed to be high, as above.
4162 *
4163 * The final value programmed to the register should always be rounded up,
4164 * and include an extra 2 entries to account for clock crossings.
4165 *
4166 * We don't use the sprite, so we can ignore that. And on Crestline we have
4167 * to set the non-SR watermarks to 8.
4168 */
46ba614c 4169void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4170{
46ba614c 4171 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4172
4173 if (dev_priv->display.update_wm)
46ba614c 4174 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4175}
4176
e2828914 4177/*
9270388e 4178 * Lock protecting IPS related data structures
9270388e
DV		 4179 */
4180DEFINE_SPINLOCK(mchdev_lock);
4181
4182/* Global for IPS driver to get at the current i915 device. Protected by
4183 * mchdev_lock. */
4184static struct drm_i915_private *i915_mch_dev;
4185
2b4e57bd
ED		 4186bool ironlake_set_drps(struct drm_device *dev, u8 val)
4187{
4188 struct drm_i915_private *dev_priv = dev->dev_private;
4189 u16 rgvswctl;
4190
9270388e
DV		 4191 assert_spin_locked(&mchdev_lock);
4192
2b4e57bd
ED		 4193 rgvswctl = I915_READ16(MEMSWCTL);
4194 if (rgvswctl & MEMCTL_CMD_STS) {
4195 DRM_DEBUG("gpu busy, RCS change rejected\n");
4196 return false; /* still busy with another command */
4197 }
4198
4199 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4200 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4201 I915_WRITE16(MEMSWCTL, rgvswctl);
4202 POSTING_READ16(MEMSWCTL);
4203
4204 rgvswctl |= MEMCTL_CMD_STS;
4205 I915_WRITE16(MEMSWCTL, rgvswctl);
4206
4207 return true;
4208}
4209
8090c6b9 4210static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4211{
4212 struct drm_i915_private *dev_priv = dev->dev_private;
84f1b20f 4213 u32 rgvmodectl;
2b4e57bd
ED		 4214 u8 fmax, fmin, fstart, vstart;
4215
9270388e
DV		 4216 spin_lock_irq(&mchdev_lock);
4217
84f1b20f
TU		 4218 rgvmodectl = I915_READ(MEMMODECTL);
4219
2b4e57bd
ED		 4220 /* Enable temp reporting */
4221 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4222 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4223
4224 /* 100ms RC evaluation intervals */
4225 I915_WRITE(RCUPEI, 100000);
4226 I915_WRITE(RCDNEI, 100000);
4227
4228 /* Set max/min thresholds to 90ms and 80ms respectively */
4229 I915_WRITE(RCBMAXAVG, 90000);
4230 I915_WRITE(RCBMINAVG, 80000);
4231
4232 I915_WRITE(MEMIHYST, 1);
4233
4234 /* Set up min, max, and cur for interrupt handling */
4235 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4236 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4237 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4238 MEMMODE_FSTART_SHIFT;
4239
616847e7 4240 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4241 PXVFREQ_PX_SHIFT;
4242
20e4d407
DV		 4243 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4244 dev_priv->ips.fstart = fstart;
2b4e57bd 4245
20e4d407
DV		 4246 dev_priv->ips.max_delay = fstart;
4247 dev_priv->ips.min_delay = fmin;
4248 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4249
4250 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4251 fmax, fmin, fstart);
4252
4253 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4254
4255 /*
4256 * Interrupts will be enabled in ironlake_irq_postinstall
4257 */
4258
4259 I915_WRITE(VIDSTART, vstart);
4260 POSTING_READ(VIDSTART);
4261
4262 rgvmodectl |= MEMMODE_SWMODE_EN;
4263 I915_WRITE(MEMMODECTL, rgvmodectl);
4264
9270388e 4265 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4266 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4267 mdelay(1);
2b4e57bd
ED		 4268
4269 ironlake_set_drps(dev, fstart);
4270
7d81c3e0
VS		 4271 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4272 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4273 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4274 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4275 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4276
4277 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4278}
4279
8090c6b9 4280static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4281{
4282 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4283 u16 rgvswctl;
4284
4285 spin_lock_irq(&mchdev_lock);
4286
4287 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4288
4289 /* Ack interrupts, disable EFC interrupt */
4290 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4291 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4292 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4293 I915_WRITE(DEIIR, DE_PCU_EVENT);
4294 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4295
4296 /* Go back to the starting frequency */
20e4d407 4297 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4298 mdelay(1);
2b4e57bd
ED		 4299 rgvswctl |= MEMCTL_CMD_STS;
4300 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4301 mdelay(1);
2b4e57bd 4302
9270388e 4303 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4304}
4305
acbe9475
DV		 4306/* There's a funny hw issue where the hw returns all 0 when reading from
4307 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4308 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4309 * all limits and the gpu stuck at whatever frequency it is at atm).
4310 */
74ef1173 4311static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4312{
7b9e0ae6 4313 u32 limits;
2b4e57bd 4314
20b46e59
DV		 4315 /* Only set the down limit when we've reached the lowest level to avoid
4316 * getting more interrupts, otherwise leave this clear. This prevents a
4317 * race in the hw when coming out of rc6: There's a tiny window where
4318 * the hw runs at the minimal clock before selecting the desired
4319 * frequency, if the down threshold expires in that window we will not
4320 * receive a down interrupt. */
2d1fe073 4321 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4322 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4323 if (val <= dev_priv->rps.min_freq_softlimit)
4324 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4325 } else {
4326 limits = dev_priv->rps.max_freq_softlimit << 24;
4327 if (val <= dev_priv->rps.min_freq_softlimit)
4328 limits |= dev_priv->rps.min_freq_softlimit << 16;
4329 }
20b46e59
DV		 4330
4331 return limits;
4332}
4333
dd75fdc8
CW		 4334static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4335{
4336 int new_power;
8a586437
AG		 4337 u32 threshold_up = 0, threshold_down = 0; /* in % */
4338 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4339
4340 new_power = dev_priv->rps.power;
4341 switch (dev_priv->rps.power) {
4342 case LOW_POWER:
b39fb297 4343 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4344 new_power = BETWEEN;
4345 break;
4346
4347 case BETWEEN:
b39fb297 4348 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4349 new_power = LOW_POWER;
b39fb297 4350 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4351 new_power = HIGH_POWER;
4352 break;
4353
4354 case HIGH_POWER:
b39fb297 4355 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4356 new_power = BETWEEN;
4357 break;
4358 }
4359 /* Max/min bins are special */
aed242ff 4360 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4361 new_power = LOW_POWER;
aed242ff 4362 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4363 new_power = HIGH_POWER;
4364 if (new_power == dev_priv->rps.power)
4365 return;
4366
4367 /* Note the units here are not exactly 1us, but 1280ns. */
4368 switch (new_power) {
4369 case LOW_POWER:
4370 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4371 ei_up = 16000;
4372 threshold_up = 95;
dd75fdc8
CW		 4373
4374 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4375 ei_down = 32000;
4376 threshold_down = 85;
dd75fdc8
CW		 4377 break;
4378
4379 case BETWEEN:
4380 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4381 ei_up = 13000;
4382 threshold_up = 90;
dd75fdc8
CW		 4383
4384 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4385 ei_down = 32000;
4386 threshold_down = 75;
dd75fdc8
CW		 4387 break;
4388
4389 case HIGH_POWER:
4390 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4391 ei_up = 10000;
4392 threshold_up = 85;
dd75fdc8
CW		 4393
4394 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4395 ei_down = 32000;
4396 threshold_down = 60;
dd75fdc8
CW		 4397 break;
4398 }
4399
8a586437
AG		 4400 I915_WRITE(GEN6_RP_UP_EI,
4401 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4402 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4403 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4404
4405 I915_WRITE(GEN6_RP_DOWN_EI,
4406 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4407 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4408 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4409
4410 I915_WRITE(GEN6_RP_CONTROL,
4411 GEN6_RP_MEDIA_TURBO |
4412 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4413 GEN6_RP_MEDIA_IS_GFX |
4414 GEN6_RP_ENABLE |
4415 GEN6_RP_UP_BUSY_AVG |
4416 GEN6_RP_DOWN_IDLE_AVG);
4417
dd75fdc8 4418 dev_priv->rps.power = new_power;
8fb55197
CW		 4419 dev_priv->rps.up_threshold = threshold_up;
4420 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4421 dev_priv->rps.last_adj = 0;
4422}
4423
2876ce73
CW		 4424static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4425{
4426 u32 mask = 0;
4427
4428 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4429 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4430 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4431 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4432
7b3c29f6
CW		 4433 mask &= dev_priv->pm_rps_events;
4434
59d02a1f 4435 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4436}
4437
b8a5ff8d
JM		 4438/* gen6_set_rps is called to update the frequency request, but should also be
4439 * called when the range (min_delay and max_delay) is modified so that we can
4440 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4441static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4442{
4443 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4444
23eafea6 4445 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4446 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4447 return;
4448
4fc688ce 4449 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4450 WARN_ON(val > dev_priv->rps.max_freq);
4451 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4452
eb64cad1
CW		 4453 /* min/max delay may still have been modified so be sure to
4454 * write the limits value.
4455 */
4456 if (val != dev_priv->rps.cur_freq) {
4457 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4458
5704195c
AG		 4459 if (IS_GEN9(dev))
4460 I915_WRITE(GEN6_RPNSWREQ,
4461 GEN9_FREQUENCY(val));
4462 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4463 I915_WRITE(GEN6_RPNSWREQ,
4464 HSW_FREQUENCY(val));
4465 else
4466 I915_WRITE(GEN6_RPNSWREQ,
4467 GEN6_FREQUENCY(val) |
4468 GEN6_OFFSET(0) |
4469 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4470 }
7b9e0ae6 4471
7b9e0ae6
CW		 4472 /* Make sure we continue to get interrupts
4473 * until we hit the minimum or maximum frequencies.
4474 */
74ef1173 4475 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4476 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4477
d5570a72
BW		 4478 POSTING_READ(GEN6_RPNSWREQ);
4479
b39fb297 4480 dev_priv->rps.cur_freq = val;
0f94592e 4481 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4482}
4483
ffe02b40
VS		 4484static void valleyview_set_rps(struct drm_device *dev, u8 val)
4485{
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487
4488 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4489 WARN_ON(val > dev_priv->rps.max_freq);
4490 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4491
4492 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4493 "Odd GPU freq value\n"))
4494 val &= ~1;
4495
cd25dd5b
D		 4496 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4497
8fb55197 4498 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4499 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4500 if (!IS_CHERRYVIEW(dev_priv))
4501 gen6_set_rps_thresholds(dev_priv, val);
4502 }
ffe02b40 4503
ffe02b40
VS		 4504 dev_priv->rps.cur_freq = val;
4505 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4506}
4507
a7f6e231 4508/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4509 *
4510 * * If Gfx is Idle, then
a7f6e231
D		 4511 * 1. Forcewake Media well.
4512 * 2. Request idle freq.
4513 * 3. Release Forcewake of Media well.
76c3552f
D		 4514*/
4515static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4516{
aed242ff 4517 u32 val = dev_priv->rps.idle_freq;
5549d25f 4518
aed242ff 4519 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4520 return;
4521
a7f6e231
D		 4522 /* Wake up the media well, as that takes a lot less
4523 * power than the Render well. */
4524 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4525 valleyview_set_rps(dev_priv->dev, val);
4526 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4527}
4528
43cf3bf0
CW		 4529void gen6_rps_busy(struct drm_i915_private *dev_priv)
4530{
4531 mutex_lock(&dev_priv->rps.hw_lock);
4532 if (dev_priv->rps.enabled) {
4533 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4534 gen6_rps_reset_ei(dev_priv);
4535 I915_WRITE(GEN6_PMINTRMSK,
4536 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4537 }
4538 mutex_unlock(&dev_priv->rps.hw_lock);
4539}
4540
b29c19b6
CW		 4541void gen6_rps_idle(struct drm_i915_private *dev_priv)
4542{
691bb717
DL		 4543 struct drm_device *dev = dev_priv->dev;
4544
b29c19b6 4545 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4546 if (dev_priv->rps.enabled) {
666a4537 4547 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4548 vlv_set_rps_idle(dev_priv);
7526ed79 4549 else
aed242ff 4550 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4551 dev_priv->rps.last_adj = 0;
43cf3bf0 4552 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4553 }
8d3afd7d 4554 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4555
8d3afd7d 4556 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4557 while (!list_empty(&dev_priv->rps.clients))
4558 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4559 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4560}
4561
1854d5ca 4562void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4563 struct intel_rps_client *rps,
4564 unsigned long submitted)
b29c19b6 4565{
8d3afd7d
CW		 4566 /* This is intentionally racy! We peek at the state here, then
4567 * validate inside the RPS worker.
4568 */
4569 if (!(dev_priv->mm.busy &&
4570 dev_priv->rps.enabled &&
4571 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4572 return;
43cf3bf0 4573
e61b9958
CW		 4574 /* Force a RPS boost (and don't count it against the client) if
4575 * the GPU is severely congested.
4576 */
d0bc54f2 4577 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4578 rps = NULL;
4579
8d3afd7d
CW		 4580 spin_lock(&dev_priv->rps.client_lock);
4581 if (rps == NULL || list_empty(&rps->link)) {
4582 spin_lock_irq(&dev_priv->irq_lock);
4583 if (dev_priv->rps.interrupts_enabled) {
4584 dev_priv->rps.client_boost = true;
4585 queue_work(dev_priv->wq, &dev_priv->rps.work);
4586 }
4587 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4588
2e1b8730
CW		 4589 if (rps != NULL) {
4590 list_add(&rps->link, &dev_priv->rps.clients);
4591 rps->boosts++;
1854d5ca
CW		 4592 } else
4593 dev_priv->rps.boosts++;
c0951f0c 4594 }
8d3afd7d 4595 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4596}
4597
ffe02b40 4598void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4599{
666a4537 4600 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4601 valleyview_set_rps(dev, val);
4602 else
4603 gen6_set_rps(dev, val);
0a073b84
JB		 4604}
4605
2030d684 4606static void gen9_disable_rc6(struct drm_device *dev)
20e49366
ZW		 4607{
4608 struct drm_i915_private *dev_priv = dev->dev_private;
4609
4610 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4611 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4612}
4613
2030d684
AG		 4614static void gen9_disable_rps(struct drm_device *dev)
4615{
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617
4618 I915_WRITE(GEN6_RP_CONTROL, 0);
4619}
4620
44fc7d5c 4621static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4622{
4623 struct drm_i915_private *dev_priv = dev->dev_private;
4624
4625 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4626 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 4627 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 4628}
4629
38807746
D		 4630static void cherryview_disable_rps(struct drm_device *dev)
4631{
4632 struct drm_i915_private *dev_priv = dev->dev_private;
4633
4634 I915_WRITE(GEN6_RC_CONTROL, 0);
4635}
4636
44fc7d5c
DV		 4637static void valleyview_disable_rps(struct drm_device *dev)
4638{
4639 struct drm_i915_private *dev_priv = dev->dev_private;
4640
98a2e5f9
D		 4641 /* we're doing forcewake before Disabling RC6,
4642 * This what the BIOS expects when going into suspend */
59bad947 4643 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4644
44fc7d5c 4645 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4646
59bad947 4647 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4648}
4649
dc39fff7
BW		 4650static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4651{
666a4537 4652 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4653 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4654 mode = GEN6_RC_CTL_RC6_ENABLE;
4655 else
4656 mode = 0;
4657 }
58abf1da
RV		 4658 if (HAS_RC6p(dev))
4659 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
87ad3212
JN		 4660 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
4661 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
4662 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 4663
4664 else
4665 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
87ad3212 4666 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 4667}
4668
274008e8
SAK		 4669static bool bxt_check_bios_rc6_setup(const struct drm_device *dev)
4670{
72e96d64
JL		 4671 struct drm_i915_private *dev_priv = to_i915(dev);
4672 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 4673 bool enable_rc6 = true;
4674 unsigned long rc6_ctx_base;
4675
4676 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
4677 DRM_DEBUG_KMS("RC6 Base location not set properly.\n");
4678 enable_rc6 = false;
4679 }
4680
4681 /*
4682 * The exact context size is not known for BXT, so assume a page size
4683 * for this check.
4684 */
4685 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 4686 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
4687 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
4688 ggtt->stolen_reserved_size))) {
274008e8
SAK		 4689 DRM_DEBUG_KMS("RC6 Base address not as expected.\n");
4690 enable_rc6 = false;
4691 }
4692
4693 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
4694 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
4695 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
4696 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
4697 DRM_DEBUG_KMS("Engine Idle wait time not set properly.\n");
4698 enable_rc6 = false;
4699 }
4700
4701 if (!(I915_READ(GEN6_RC_CONTROL) & (GEN6_RC_CTL_RC6_ENABLE |
4702 GEN6_RC_CTL_HW_ENABLE)) &&
4703 ((I915_READ(GEN6_RC_CONTROL) & GEN6_RC_CTL_HW_ENABLE) ||
4704 !(I915_READ(GEN6_RC_STATE) & RC6_STATE))) {
4705 DRM_DEBUG_KMS("HW/SW RC6 is not enabled by BIOS.\n");
4706 enable_rc6 = false;
4707 }
4708
4709 return enable_rc6;
4710}
4711
4712int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4713{
e7d66d89
DV		 4714 /* No RC6 before Ironlake and code is gone for ilk. */
4715 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4716 return 0;
4717
274008e8
SAK		 4718 if (!enable_rc6)
4719 return 0;
4720
4721 if (IS_BROXTON(dev) && !bxt_check_bios_rc6_setup(dev)) {
4722 DRM_INFO("RC6 disabled by BIOS\n");
4723 return 0;
4724 }
4725
456470eb 4726 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4727 if (enable_rc6 >= 0) {
4728 int mask;
4729
58abf1da 4730 if (HAS_RC6p(dev))
e6069ca8
ID		 4731 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4732 INTEL_RC6pp_ENABLE;
4733 else
4734 mask = INTEL_RC6_ENABLE;
4735
4736 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4737 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4738 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4739
4740 return enable_rc6 & mask;
4741 }
2b4e57bd 4742
8bade1ad 4743 if (IS_IVYBRIDGE(dev))
cca84a1f 4744 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4745
4746 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4747}
4748
e6069ca8
ID		 4749int intel_enable_rc6(const struct drm_device *dev)
4750{
4751 return i915.enable_rc6;
4752}
4753
93ee2920 4754static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4755{
93ee2920
TR		 4756 struct drm_i915_private *dev_priv = dev->dev_private;
4757 uint32_t rp_state_cap;
4758 u32 ddcc_status = 0;
4759 int ret;
4760
3280e8b0
BW		 4761 /* All of these values are in units of 50MHz */
4762 dev_priv->rps.cur_freq = 0;
93ee2920 4763 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4764 if (IS_BROXTON(dev)) {
4765 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4766 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4767 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4768 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4769 } else {
4770 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4771 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4772 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4773 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4774 }
4775
3280e8b0
BW		 4776 /* hw_max = RP0 until we check for overclocking */
4777 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4778
93ee2920 4779 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4780 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4781 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4782 ret = sandybridge_pcode_read(dev_priv,
4783 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4784 &ddcc_status);
4785 if (0 == ret)
4786 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4787 clamp_t(u8,
4788 ((ddcc_status >> 8) & 0xff),
4789 dev_priv->rps.min_freq,
4790 dev_priv->rps.max_freq);
93ee2920
TR		 4791 }
4792
ef11bdb3 4793 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4794 /* Store the frequency values in 16.66 MHZ units, which is
4795 the natural hardware unit for SKL */
4796 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4797 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4798 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4799 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4800 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4801 }
4802
aed242ff
CW		 4803 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4804
3280e8b0
BW		 4805 /* Preserve min/max settings in case of re-init */
4806 if (dev_priv->rps.max_freq_softlimit == 0)
4807 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4808
93ee2920
TR		 4809 if (dev_priv->rps.min_freq_softlimit == 0) {
4810 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4811 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4812 max_t(int, dev_priv->rps.efficient_freq,
4813 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4814 else
4815 dev_priv->rps.min_freq_softlimit =
4816 dev_priv->rps.min_freq;
4817 }
3280e8b0
BW		 4818}
4819
b6fef0ef 4820/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4821static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4822{
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4824
4825 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4826
ba1c554c
DL		 4827 gen6_init_rps_frequencies(dev);
4828
23eafea6 4829 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4830 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
2030d684
AG		 4831 /*
4832 * BIOS could leave the Hw Turbo enabled, so need to explicitly
4833 * clear out the Control register just to avoid inconsitency
4834 * with debugfs interface, which will show Turbo as enabled
4835 * only and that is not expected by the User after adding the
4836 * WaGsvDisableTurbo. Apart from this there is no problem even
4837 * if the Turbo is left enabled in the Control register, as the
4838 * Up/Down interrupts would remain masked.
4839 */
4840 gen9_disable_rps(dev);
23eafea6
SAK		 4841 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4842 return;
4843 }
4844
0beb059a
AG		 4845 /* Program defaults and thresholds for RPS*/
4846 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4847 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4848
4849 /* 1 second timeout*/
4850 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4851 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4852
b6fef0ef 4853 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4854
0beb059a
AG		 4855 /* Leaning on the below call to gen6_set_rps to program/setup the
4856 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4857 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4858 dev_priv->rps.power = HIGH_POWER; /* force a reset */
5fd9f523 4859 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
b6fef0ef
JB		 4860
4861 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4862}
4863
4864static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4865{
4866 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 4867 struct intel_engine_cs *engine;
20e49366 4868 uint32_t rc6_mask = 0;
20e49366
ZW		 4869
4870 /* 1a: Software RC state - RC0 */
4871 I915_WRITE(GEN6_RC_STATE, 0);
4872
4873 /* 1b: Get forcewake during program sequence. Although the driver
4874 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4875 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4876
4877 /* 2a: Disable RC states. */
4878 I915_WRITE(GEN6_RC_CONTROL, 0);
4879
4880 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4881
4882 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4883 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4884 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4885 else
4886 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4887 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4888 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 4889 for_each_engine(engine, dev_priv)
e2f80391 4890 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7
SAK		 4891
4892 if (HAS_GUC_UCODE(dev))
4893 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4894
20e49366 4895 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4896
38c23527
ZW		 4897 /* 2c: Program Coarse Power Gating Policies. */
4898 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4899 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4900
20e49366
ZW		 4901 /* 3a: Enable RC6 */
4902 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4903 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 4904 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
3e7732a0 4905 /* WaRsUseTimeoutMode */
e87a005d 4906 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4907 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4908 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4909 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4910 GEN7_RC_CTL_TO_MODE |
4911 rc6_mask);
3e7732a0
SAK		 4912 } else {
4913 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4914 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4915 GEN6_RC_CTL_EI_MODE(1) |
4916 rc6_mask);
3e7732a0 4917 }
20e49366 4918
cb07bae0
SK		 4919 /*
4920 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4921 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4922 */
06e668ac 4923 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4924 I915_WRITE(GEN9_PG_ENABLE, 0);
4925 else
4926 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4927 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4928
59bad947 4929 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4930
4931}
4932
6edee7f3
BW		 4933static void gen8_enable_rps(struct drm_device *dev)
4934{
4935 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 4936 struct intel_engine_cs *engine;
93ee2920 4937 uint32_t rc6_mask = 0;
6edee7f3
BW		 4938
4939 /* 1a: Software RC state - RC0 */
4940 I915_WRITE(GEN6_RC_STATE, 0);
4941
4942 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4943 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4944 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4945
4946 /* 2a: Disable RC states. */
4947 I915_WRITE(GEN6_RC_CONTROL, 0);
4948
93ee2920
TR		 4949 /* Initialize rps frequencies */
4950 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4951
4952 /* 2b: Program RC6 thresholds.*/
4953 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4954 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4955 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
b4ac5afc 4956 for_each_engine(engine, dev_priv)
e2f80391 4957 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 4958 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4959 if (IS_BROADWELL(dev))
4960 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4961 else
4962 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4963
4964 /* 3: Enable RC6 */
4965 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4966 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4967 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4968 if (IS_BROADWELL(dev))
4969 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4970 GEN7_RC_CTL_TO_MODE |
4971 rc6_mask);
4972 else
4973 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4974 GEN6_RC_CTL_EI_MODE(1) |
4975 rc6_mask);
6edee7f3
BW		 4976
4977 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4978 I915_WRITE(GEN6_RPNSWREQ,
4979 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4980 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4981 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4982 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4983 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4984
4985 /* Docs recommend 900MHz, and 300 MHz respectively */
4986 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4987 dev_priv->rps.max_freq_softlimit << 24 |
4988 dev_priv->rps.min_freq_softlimit << 16);
4989
4990 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4991 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4992 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4993 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4994
4995 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4996
4997 /* 5: Enable RPS */
7526ed79
DV		 4998 I915_WRITE(GEN6_RP_CONTROL,
4999 GEN6_RP_MEDIA_TURBO |
5000 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5001 GEN6_RP_MEDIA_IS_GFX |
5002 GEN6_RP_ENABLE |
5003 GEN6_RP_UP_BUSY_AVG |
5004 GEN6_RP_DOWN_IDLE_AVG);
5005
5006 /* 6: Ring frequency + overclocking (our driver does this later */
5007
c7f3153a 5008 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5009 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 5010
59bad947 5011 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5012}
5013
79f5b2c7 5014static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 5015{
79f5b2c7 5016 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 5017 struct intel_engine_cs *engine;
d060c169 5018 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 5019 u32 gtfifodbg;
2b4e57bd 5020 int rc6_mode;
b4ac5afc 5021 int ret;
2b4e57bd 5022
4fc688ce 5023 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5024
2b4e57bd
ED		 5025 /* Here begins a magic sequence of register writes to enable
5026 * auto-downclocking.
5027 *
5028 * Perhaps there might be some value in exposing these to
5029 * userspace...
5030 */
5031 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5032
5033 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5034 gtfifodbg = I915_READ(GTFIFODBG);
5035 if (gtfifodbg) {
2b4e57bd
ED		 5036 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5037 I915_WRITE(GTFIFODBG, gtfifodbg);
5038 }
5039
59bad947 5040 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 5041
93ee2920
TR		 5042 /* Initialize rps frequencies */
5043 gen6_init_rps_frequencies(dev);
dd0a1aa1 5044
2b4e57bd
ED		 5045 /* disable the counters and set deterministic thresholds */
5046 I915_WRITE(GEN6_RC_CONTROL, 0);
5047
5048 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5049 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5050 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5051 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5052 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5053
b4ac5afc 5054 for_each_engine(engine, dev_priv)
e2f80391 5055 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5056
5057 I915_WRITE(GEN6_RC_SLEEP, 0);
5058 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 5059 if (IS_IVYBRIDGE(dev))
351aa566
SM		 5060 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5061 else
5062 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5063 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5064 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5065
5a7dc92a 5066 /* Check if we are enabling RC6 */
2b4e57bd
ED		 5067 rc6_mode = intel_enable_rc6(dev_priv->dev);
5068 if (rc6_mode & INTEL_RC6_ENABLE)
5069 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5070
5a7dc92a
ED		 5071 /* We don't use those on Haswell */
5072 if (!IS_HASWELL(dev)) {
5073 if (rc6_mode & INTEL_RC6p_ENABLE)
5074 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5075
5a7dc92a
ED		 5076 if (rc6_mode & INTEL_RC6pp_ENABLE)
5077 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5078 }
2b4e57bd 5079
dc39fff7 5080 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 5081
5082 I915_WRITE(GEN6_RC_CONTROL,
5083 rc6_mask |
5084 GEN6_RC_CTL_EI_MODE(1) |
5085 GEN6_RC_CTL_HW_ENABLE);
5086
dd75fdc8
CW		 5087 /* Power down if completely idle for over 50ms */
5088 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5089 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5090
42c0526c 5091 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5092 if (ret)
42c0526c 5093 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 5094
5095 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
5096 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
5097 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5098 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5099 (pcu_mbox & 0xff) * 50);
b39fb297 5100 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5101 }
5102
dd75fdc8 5103 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5104 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5105
31643d54
BW		 5106 rc6vids = 0;
5107 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5108 if (IS_GEN6(dev) && ret) {
5109 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5110 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5111 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5112 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5113 rc6vids &= 0xffff00;
5114 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5115 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5116 if (ret)
5117 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5118 }
5119
59bad947 5120 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5121}
5122
c2bc2fc5 5123static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5124{
79f5b2c7 5125 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5126 int min_freq = 15;
3ebecd07
CW		 5127 unsigned int gpu_freq;
5128 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5129 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5130 int scaling_factor = 180;
eda79642 5131 struct cpufreq_policy *policy;
2b4e57bd 5132
4fc688ce 5133 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5134
eda79642
BW		 5135 policy = cpufreq_cpu_get(0);
5136 if (policy) {
5137 max_ia_freq = policy->cpuinfo.max_freq;
5138 cpufreq_cpu_put(policy);
5139 } else {
5140 /*
5141 * Default to measured freq if none found, PCU will ensure we
5142 * don't go over
5143 */
2b4e57bd 5144 max_ia_freq = tsc_khz;
eda79642 5145 }
2b4e57bd
ED		 5146
5147 /* Convert from kHz to MHz */
5148 max_ia_freq /= 1000;
5149
153b4b95 5150 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5151 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5152 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5153
ef11bdb3 5154 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5155 /* Convert GT frequency to 50 HZ units */
5156 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5157 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5158 } else {
5159 min_gpu_freq = dev_priv->rps.min_freq;
5160 max_gpu_freq = dev_priv->rps.max_freq;
5161 }
5162
2b4e57bd
ED		 5163 /*
5164 * For each potential GPU frequency, load a ring frequency we'd like
5165 * to use for memory access. We do this by specifying the IA frequency
5166 * the PCU should use as a reference to determine the ring frequency.
5167 */
4c8c7743
AG		 5168 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5169 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5170 unsigned int ia_freq = 0, ring_freq = 0;
5171
ef11bdb3 5172 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 5173 /*
5174 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5175 * No floor required for ring frequency on SKL.
5176 */
5177 ring_freq = gpu_freq;
5178 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5179 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5180 ring_freq = max(min_ring_freq, gpu_freq);
5181 } else if (IS_HASWELL(dev)) {
f6aca45c 5182 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5183 ring_freq = max(min_ring_freq, ring_freq);
5184 /* leave ia_freq as the default, chosen by cpufreq */
5185 } else {
5186 /* On older processors, there is no separate ring
5187 * clock domain, so in order to boost the bandwidth
5188 * of the ring, we need to upclock the CPU (ia_freq).
5189 *
5190 * For GPU frequencies less than 750MHz,
5191 * just use the lowest ring freq.
5192 */
5193 if (gpu_freq < min_freq)
5194 ia_freq = 800;
5195 else
5196 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5197 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5198 }
2b4e57bd 5199
42c0526c
BW		 5200 sandybridge_pcode_write(dev_priv,
5201 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5202 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5203 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5204 gpu_freq);
2b4e57bd 5205 }
2b4e57bd
ED		 5206}
5207
c2bc2fc5
ID		 5208void gen6_update_ring_freq(struct drm_device *dev)
5209{
5210 struct drm_i915_private *dev_priv = dev->dev_private;
5211
97d3308a 5212 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5213 return;
5214
5215 mutex_lock(&dev_priv->rps.hw_lock);
5216 __gen6_update_ring_freq(dev);
5217 mutex_unlock(&dev_priv->rps.hw_lock);
5218}
5219
03af2045 5220static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5221{
095acd5f 5222 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5223 u32 val, rp0;
5224
5b5929cb 5225 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5226
5b5929cb
JN		 5227 switch (INTEL_INFO(dev)->eu_total) {
5228 case 8:
5229 /* (2 * 4) config */
5230 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5231 break;
5232 case 12:
5233 /* (2 * 6) config */
5234 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5235 break;
5236 case 16:
5237 /* (2 * 8) config */
5238 default:
5239 /* Setting (2 * 8) Min RP0 for any other combination */
5240 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5241 break;
095acd5f 5242 }
5b5929cb
JN		 5243
5244 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5245
2b6b3a09
D		 5246 return rp0;
5247}
5248
5249static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5250{
5251 u32 val, rpe;
5252
5253 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5254 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5255
5256 return rpe;
5257}
5258
7707df4a
D		 5259static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5260{
5261 u32 val, rp1;
5262
5b5929cb
JN		 5263 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5264 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5265
7707df4a
D		 5266 return rp1;
5267}
5268
f8f2b001
D		 5269static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5270{
5271 u32 val, rp1;
5272
5273 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5274
5275 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5276
5277 return rp1;
5278}
5279
03af2045 5280static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5281{
5282 u32 val, rp0;
5283
64936258 5284 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5285
5286 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5287 /* Clamp to max */
5288 rp0 = min_t(u32, rp0, 0xea);
5289
5290 return rp0;
5291}
5292
5293static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5294{
5295 u32 val, rpe;
5296
64936258 5297 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5298 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5299 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5300 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5301
5302 return rpe;
5303}
5304
03af2045 5305static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5306{
36146035
ID		 5307 u32 val;
5308
5309 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5310 /*
5311 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5312 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5313 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5314 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5315 * to make sure it matches what Punit accepts.
5316 */
5317 return max_t(u32, val, 0xc0);
0a073b84
JB		 5318}
5319
ae48434c
ID		 5320/* Check that the pctx buffer wasn't move under us. */
5321static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5322{
5323 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5324
5325 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5326 dev_priv->vlv_pctx->stolen->start);
5327}
5328
38807746
D		 5329
5330/* Check that the pcbr address is not empty. */
5331static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5332{
5333 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5334
5335 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5336}
5337
5338static void cherryview_setup_pctx(struct drm_device *dev)
5339{
72e96d64 5340 struct drm_i915_private *dev_priv = to_i915(dev);
62106b4f 5341 struct i915_ggtt *ggtt = &dev_priv->ggtt;
38807746 5342 unsigned long pctx_paddr, paddr;
38807746
D		 5343 u32 pcbr;
5344 int pctx_size = 32*1024;
5345
38807746
D		 5346 pcbr = I915_READ(VLV_PCBR);
5347 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5348 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5349 paddr = (dev_priv->mm.stolen_base +
62106b4f 5350 (ggtt->stolen_size - pctx_size));
38807746
D		 5351
5352 pctx_paddr = (paddr & (~4095));
5353 I915_WRITE(VLV_PCBR, pctx_paddr);
5354 }
ce611ef8
VS		 5355
5356 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5357}
5358
c9cddffc
JB		 5359static void valleyview_setup_pctx(struct drm_device *dev)
5360{
5361 struct drm_i915_private *dev_priv = dev->dev_private;
5362 struct drm_i915_gem_object *pctx;
5363 unsigned long pctx_paddr;
5364 u32 pcbr;
5365 int pctx_size = 24*1024;
5366
ee504898 5367 mutex_lock(&dev->struct_mutex);
17b0c1f7 5368
c9cddffc
JB		 5369 pcbr = I915_READ(VLV_PCBR);
5370 if (pcbr) {
5371 /* BIOS set it up already, grab the pre-alloc'd space */
5372 int pcbr_offset;
5373
5374 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5375 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5376 pcbr_offset,
190d6cd5 5377 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5378 pctx_size);
5379 goto out;
5380 }
5381
ce611ef8
VS		 5382 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5383
c9cddffc
JB		 5384 /*
5385 * From the Gunit register HAS:
5386 * The Gfx driver is expected to program this register and ensure
5387 * proper allocation within Gfx stolen memory. For example, this
5388 * register should be programmed such than the PCBR range does not
5389 * overlap with other ranges, such as the frame buffer, protected
5390 * memory, or any other relevant ranges.
5391 */
5392 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5393 if (!pctx) {
5394 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5395 goto out;
c9cddffc
JB		 5396 }
5397
5398 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5399 I915_WRITE(VLV_PCBR, pctx_paddr);
5400
5401out:
ce611ef8 5402 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc 5403 dev_priv->vlv_pctx = pctx;
ee504898 5404 mutex_unlock(&dev->struct_mutex);
c9cddffc
JB		 5405}
5406
ae48434c
ID		 5407static void valleyview_cleanup_pctx(struct drm_device *dev)
5408{
5409 struct drm_i915_private *dev_priv = dev->dev_private;
5410
5411 if (WARN_ON(!dev_priv->vlv_pctx))
5412 return;
5413
ee504898 5414 drm_gem_object_unreference_unlocked(&dev_priv->vlv_pctx->base);
ae48434c
ID		 5415 dev_priv->vlv_pctx = NULL;
5416}
5417
c30fec65
VS		 5418static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5419{
5420 dev_priv->rps.gpll_ref_freq =
5421 vlv_get_cck_clock(dev_priv, "GPLL ref",
5422 CCK_GPLL_CLOCK_CONTROL,
5423 dev_priv->czclk_freq);
5424
5425 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5426 dev_priv->rps.gpll_ref_freq);
5427}
5428
4e80519e
ID		 5429static void valleyview_init_gt_powersave(struct drm_device *dev)
5430{
5431 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5432 u32 val;
4e80519e
ID		 5433
5434 valleyview_setup_pctx(dev);
5435
c30fec65
VS		 5436 vlv_init_gpll_ref_freq(dev_priv);
5437
4e80519e
ID		 5438 mutex_lock(&dev_priv->rps.hw_lock);
5439
2bb25c17
VS		 5440 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5441 switch ((val >> 6) & 3) {
5442 case 0:
5443 case 1:
5444 dev_priv->mem_freq = 800;
5445 break;
5446 case 2:
5447 dev_priv->mem_freq = 1066;
5448 break;
5449 case 3:
5450 dev_priv->mem_freq = 1333;
5451 break;
5452 }
80b83b62 5453 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5454
4e80519e
ID		 5455 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5456 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5457 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5458 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5459 dev_priv->rps.max_freq);
5460
5461 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5462 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5463 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5464 dev_priv->rps.efficient_freq);
5465
f8f2b001
D		 5466 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5467 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5468 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5469 dev_priv->rps.rp1_freq);
5470
4e80519e
ID		 5471 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5472 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5473 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5474 dev_priv->rps.min_freq);
5475
aed242ff
CW		 5476 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5477
4e80519e
ID		 5478 /* Preserve min/max settings in case of re-init */
5479 if (dev_priv->rps.max_freq_softlimit == 0)
5480 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5481
5482 if (dev_priv->rps.min_freq_softlimit == 0)
5483 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5484
5485 mutex_unlock(&dev_priv->rps.hw_lock);
5486}
5487
38807746
D		 5488static void cherryview_init_gt_powersave(struct drm_device *dev)
5489{
2b6b3a09 5490 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5491 u32 val;
2b6b3a09 5492
38807746 5493 cherryview_setup_pctx(dev);
2b6b3a09 5494
c30fec65
VS		 5495 vlv_init_gpll_ref_freq(dev_priv);
5496
2b6b3a09
D		 5497 mutex_lock(&dev_priv->rps.hw_lock);
5498
a580516d 5499 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5500 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5501 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5502
2bb25c17 5503 switch ((val >> 2) & 0x7) {
2bb25c17 5504 case 3:
2bb25c17
VS		 5505 dev_priv->mem_freq = 2000;
5506 break;
bfa7df01 5507 default:
2bb25c17
VS		 5508 dev_priv->mem_freq = 1600;
5509 break;
5510 }
80b83b62 5511 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5512
2b6b3a09
D		 5513 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5514 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5515 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5516 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5517 dev_priv->rps.max_freq);
5518
5519 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5520 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5521 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5522 dev_priv->rps.efficient_freq);
5523
7707df4a
D		 5524 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5525 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5526 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5527 dev_priv->rps.rp1_freq);
5528
5b7c91b7
D		 5529 /* PUnit validated range is only [RPe, RP0] */
5530 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5531 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5532 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5533 dev_priv->rps.min_freq);
5534
1c14762d
VS		 5535 WARN_ONCE((dev_priv->rps.max_freq |
5536 dev_priv->rps.efficient_freq |
5537 dev_priv->rps.rp1_freq |
5538 dev_priv->rps.min_freq) & 1,
5539 "Odd GPU freq values\n");
5540
aed242ff
CW		 5541 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5542
2b6b3a09
D		 5543 /* Preserve min/max settings in case of re-init */
5544 if (dev_priv->rps.max_freq_softlimit == 0)
5545 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5546
5547 if (dev_priv->rps.min_freq_softlimit == 0)
5548 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5549
5550 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5551}
5552
4e80519e
ID		 5553static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5554{
5555 valleyview_cleanup_pctx(dev);
5556}
5557
38807746
D		 5558static void cherryview_enable_rps(struct drm_device *dev)
5559{
5560 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 5561 struct intel_engine_cs *engine;
2b6b3a09 5562 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5563
5564 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5565
297b32ec
VS		 5566 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
5567 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 5568 if (gtfifodbg) {
5569 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5570 gtfifodbg);
5571 I915_WRITE(GTFIFODBG, gtfifodbg);
5572 }
5573
5574 cherryview_check_pctx(dev_priv);
5575
5576 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5577 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5578 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5579
160614a2
VS		 5580 /* Disable RC states. */
5581 I915_WRITE(GEN6_RC_CONTROL, 0);
5582
38807746
D		 5583 /* 2a: Program RC6 thresholds.*/
5584 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5585 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5586 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5587
b4ac5afc 5588 for_each_engine(engine, dev_priv)
e2f80391 5589 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 5590 I915_WRITE(GEN6_RC_SLEEP, 0);
5591
f4f71c7d
D		 5592 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5593 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5594
5595 /* allows RC6 residency counter to work */
5596 I915_WRITE(VLV_COUNTER_CONTROL,
5597 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5598 VLV_MEDIA_RC6_COUNT_EN |
5599 VLV_RENDER_RC6_COUNT_EN));
5600
5601 /* For now we assume BIOS is allocating and populating the PCBR */
5602 pcbr = I915_READ(VLV_PCBR);
5603
38807746
D		 5604 /* 3: Enable RC6 */
5605 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5606 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5607 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5608
5609 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5610
2b6b3a09 5611 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5612 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5613 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5614 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5615 I915_WRITE(GEN6_RP_UP_EI, 66000);
5616 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5617
5618 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5619
5620 /* 5: Enable RPS */
5621 I915_WRITE(GEN6_RP_CONTROL,
5622 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5623 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5624 GEN6_RP_ENABLE |
5625 GEN6_RP_UP_BUSY_AVG |
5626 GEN6_RP_DOWN_IDLE_AVG);
5627
3ef62342
D		 5628 /* Setting Fixed Bias */
5629 val = VLV_OVERRIDE_EN |
5630 VLV_SOC_TDP_EN |
5631 CHV_BIAS_CPU_50_SOC_50;
5632 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5633
2b6b3a09
D		 5634 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5635
8d40c3ae
VS		 5636 /* RPS code assumes GPLL is used */
5637 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5638
742f491d 5639 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5640 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5641
5642 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5643 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5644 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5645 dev_priv->rps.cur_freq);
5646
5647 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5648 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5649 dev_priv->rps.idle_freq);
2b6b3a09 5650
5fd9f523 5651 valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b6b3a09 5652
59bad947 5653 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5654}
5655
0a073b84
JB		 5656static void valleyview_enable_rps(struct drm_device *dev)
5657{
5658 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 5659 struct intel_engine_cs *engine;
2a5913a8 5660 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5661
5662 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5663
ae48434c
ID		 5664 valleyview_check_pctx(dev_priv);
5665
297b32ec
VS		 5666 gtfifodbg = I915_READ(GTFIFODBG);
5667 if (gtfifodbg) {
f7d85c1e
JB		 5668 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5669 gtfifodbg);
0a073b84
JB		 5670 I915_WRITE(GTFIFODBG, gtfifodbg);
5671 }
5672
c8d9a590 5673 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5674 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5675
160614a2
VS		 5676 /* Disable RC states. */
5677 I915_WRITE(GEN6_RC_CONTROL, 0);
5678
cad725fe 5679 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5680 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5681 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5682 I915_WRITE(GEN6_RP_UP_EI, 66000);
5683 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5684
5685 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5686
5687 I915_WRITE(GEN6_RP_CONTROL,
5688 GEN6_RP_MEDIA_TURBO |
5689 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5690 GEN6_RP_MEDIA_IS_GFX |
5691 GEN6_RP_ENABLE |
5692 GEN6_RP_UP_BUSY_AVG |
5693 GEN6_RP_DOWN_IDLE_CONT);
5694
5695 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5696 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5697 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5698
b4ac5afc 5699 for_each_engine(engine, dev_priv)
e2f80391 5700 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 5701
2f0aa304 5702 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5703
5704 /* allows RC6 residency counter to work */
49798eb2 5705 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5706 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5707 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5708 VLV_MEDIA_RC6_COUNT_EN |
5709 VLV_RENDER_RC6_COUNT_EN));
31685c25 5710
a2b23fe0 5711 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5712 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5713
5714 intel_print_rc6_info(dev, rc6_mode);
5715
a2b23fe0 5716 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5717
3ef62342
D		 5718 /* Setting Fixed Bias */
5719 val = VLV_OVERRIDE_EN |
5720 VLV_SOC_TDP_EN |
5721 VLV_BIAS_CPU_125_SOC_875;
5722 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5723
64936258 5724 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5725
8d40c3ae
VS		 5726 /* RPS code assumes GPLL is used */
5727 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5728
742f491d 5729 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5730 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5731
b39fb297 5732 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5733 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5734 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5735 dev_priv->rps.cur_freq);
0a073b84 5736
73008b98 5737 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5fd9f523
VS		 5738 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
5739 dev_priv->rps.idle_freq);
0a073b84 5740
5fd9f523 5741 valleyview_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
0a073b84 5742
59bad947 5743 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5744}
5745
dde18883
ED		 5746static unsigned long intel_pxfreq(u32 vidfreq)
5747{
5748 unsigned long freq;
5749 int div = (vidfreq & 0x3f0000) >> 16;
5750 int post = (vidfreq & 0x3000) >> 12;
5751 int pre = (vidfreq & 0x7);
5752
5753 if (!pre)
5754 return 0;
5755
5756 freq = ((div * 133333) / ((1<<post) * pre));
5757
5758 return freq;
5759}
5760
eb48eb00
DV		 5761static const struct cparams {
5762 u16 i;
5763 u16 t;
5764 u16 m;
5765 u16 c;
5766} cparams[] = {
5767 { 1, 1333, 301, 28664 },
5768 { 1, 1066, 294, 24460 },
5769 { 1, 800, 294, 25192 },
5770 { 0, 1333, 276, 27605 },
5771 { 0, 1066, 276, 27605 },
5772 { 0, 800, 231, 23784 },
5773};
5774
f531dcb2 5775static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5776{
5777 u64 total_count, diff, ret;
5778 u32 count1, count2, count3, m = 0, c = 0;
5779 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5780 int i;
5781
02d71956
DV		 5782 assert_spin_locked(&mchdev_lock);
5783
20e4d407 5784 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5785
5786 /* Prevent division-by-zero if we are asking too fast.
5787 * Also, we don't get interesting results if we are polling
5788 * faster than once in 10ms, so just return the saved value
5789 * in such cases.
5790 */
5791 if (diff1 <= 10)
20e4d407 5792 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5793
5794 count1 = I915_READ(DMIEC);
5795 count2 = I915_READ(DDREC);
5796 count3 = I915_READ(CSIEC);
5797
5798 total_count = count1 + count2 + count3;
5799
5800 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5801 if (total_count < dev_priv->ips.last_count1) {
5802 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5803 diff += total_count;
5804 } else {
20e4d407 5805 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5806 }
5807
5808 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5809 if (cparams[i].i == dev_priv->ips.c_m &&
5810 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5811 m = cparams[i].m;
5812 c = cparams[i].c;
5813 break;
5814 }
5815 }
5816
5817 diff = div_u64(diff, diff1);
5818 ret = ((m * diff) + c);
5819 ret = div_u64(ret, 10);
5820
20e4d407
DV		 5821 dev_priv->ips.last_count1 = total_count;
5822 dev_priv->ips.last_time1 = now;
eb48eb00 5823
20e4d407 5824 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5825
5826 return ret;
5827}
5828
f531dcb2
CW		 5829unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5830{
3d13ef2e 5831 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5832 unsigned long val;
5833
3d13ef2e 5834 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5835 return 0;
5836
5837 spin_lock_irq(&mchdev_lock);
5838
5839 val = __i915_chipset_val(dev_priv);
5840
5841 spin_unlock_irq(&mchdev_lock);
5842
5843 return val;
5844}
5845
eb48eb00
DV		 5846unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5847{
5848 unsigned long m, x, b;
5849 u32 tsfs;
5850
5851 tsfs = I915_READ(TSFS);
5852
5853 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5854 x = I915_READ8(TR1);
5855
5856 b = tsfs & TSFS_INTR_MASK;
5857
5858 return ((m * x) / 127) - b;
5859}
5860
d972d6ee
MK		 5861static int _pxvid_to_vd(u8 pxvid)
5862{
5863 if (pxvid == 0)
5864 return 0;
5865
5866 if (pxvid >= 8 && pxvid < 31)
5867 pxvid = 31;
5868
5869 return (pxvid + 2) * 125;
5870}
5871
5872static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5873{
3d13ef2e 5874 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5875 const int vd = _pxvid_to_vd(pxvid);
5876 const int vm = vd - 1125;
5877
3d13ef2e 5878 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5879 return vm > 0 ? vm : 0;
5880
5881 return vd;
eb48eb00
DV		 5882}
5883
02d71956 5884static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5885{
5ed0bdf2 5886 u64 now, diff, diffms;
eb48eb00
DV		 5887 u32 count;
5888
02d71956 5889 assert_spin_locked(&mchdev_lock);
eb48eb00 5890
5ed0bdf2
TG		 5891 now = ktime_get_raw_ns();
5892 diffms = now - dev_priv->ips.last_time2;
5893 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5894
5895 /* Don't divide by 0 */
eb48eb00
DV		 5896 if (!diffms)
5897 return;
5898
5899 count = I915_READ(GFXEC);
5900
20e4d407
DV		 5901 if (count < dev_priv->ips.last_count2) {
5902 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5903 diff += count;
5904 } else {
20e4d407 5905 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5906 }
5907
20e4d407
DV		 5908 dev_priv->ips.last_count2 = count;
5909 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5910
5911 /* More magic constants... */
5912 diff = diff * 1181;
5913 diff = div_u64(diff, diffms * 10);
20e4d407 5914 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5915}
5916
02d71956
DV		 5917void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5918{
3d13ef2e
DL		 5919 struct drm_device *dev = dev_priv->dev;
5920
5921 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5922 return;
5923
9270388e 5924 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5925
5926 __i915_update_gfx_val(dev_priv);
5927
9270388e 5928 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5929}
5930
f531dcb2 5931static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5932{
5933 unsigned long t, corr, state1, corr2, state2;
5934 u32 pxvid, ext_v;
5935
02d71956
DV		 5936 assert_spin_locked(&mchdev_lock);
5937
616847e7 5938 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5939 pxvid = (pxvid >> 24) & 0x7f;
5940 ext_v = pvid_to_extvid(dev_priv, pxvid);
5941
5942 state1 = ext_v;
5943
5944 t = i915_mch_val(dev_priv);
5945
5946 /* Revel in the empirically derived constants */
5947
5948 /* Correction factor in 1/100000 units */
5949 if (t > 80)
5950 corr = ((t * 2349) + 135940);
5951 else if (t >= 50)
5952 corr = ((t * 964) + 29317);
5953 else /* < 50 */
5954 corr = ((t * 301) + 1004);
5955
5956 corr = corr * ((150142 * state1) / 10000 - 78642);
5957 corr /= 100000;
20e4d407 5958 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5959
5960 state2 = (corr2 * state1) / 10000;
5961 state2 /= 100; /* convert to mW */
5962
02d71956 5963 __i915_update_gfx_val(dev_priv);
eb48eb00 5964
20e4d407 5965 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5966}
5967
f531dcb2
CW		 5968unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5969{
3d13ef2e 5970 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5971 unsigned long val;
5972
3d13ef2e 5973 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5974 return 0;
5975
5976 spin_lock_irq(&mchdev_lock);
5977
5978 val = __i915_gfx_val(dev_priv);
5979
5980 spin_unlock_irq(&mchdev_lock);
5981
5982 return val;
5983}
5984
eb48eb00
DV		 5985/**
5986 * i915_read_mch_val - return value for IPS use
5987 *
5988 * Calculate and return a value for the IPS driver to use when deciding whether
5989 * we have thermal and power headroom to increase CPU or GPU power budget.
5990 */
5991unsigned long i915_read_mch_val(void)
5992{
5993 struct drm_i915_private *dev_priv;
5994 unsigned long chipset_val, graphics_val, ret = 0;
5995
9270388e 5996 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5997 if (!i915_mch_dev)
5998 goto out_unlock;
5999 dev_priv = i915_mch_dev;
6000
f531dcb2
CW		 6001 chipset_val = __i915_chipset_val(dev_priv);
6002 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6003
6004 ret = chipset_val + graphics_val;
6005
6006out_unlock:
9270388e 6007 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6008
6009 return ret;
6010}
6011EXPORT_SYMBOL_GPL(i915_read_mch_val);
6012
6013/**
6014 * i915_gpu_raise - raise GPU frequency limit
6015 *
6016 * Raise the limit; IPS indicates we have thermal headroom.
6017 */
6018bool i915_gpu_raise(void)
6019{
6020 struct drm_i915_private *dev_priv;
6021 bool ret = true;
6022
9270388e 6023 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6024 if (!i915_mch_dev) {
6025 ret = false;
6026 goto out_unlock;
6027 }
6028 dev_priv = i915_mch_dev;
6029
20e4d407
DV		 6030 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6031 dev_priv->ips.max_delay--;
eb48eb00
DV		 6032
6033out_unlock:
9270388e 6034 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6035
6036 return ret;
6037}
6038EXPORT_SYMBOL_GPL(i915_gpu_raise);
6039
6040/**
6041 * i915_gpu_lower - lower GPU frequency limit
6042 *
6043 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6044 * frequency maximum.
6045 */
6046bool i915_gpu_lower(void)
6047{
6048 struct drm_i915_private *dev_priv;
6049 bool ret = true;
6050
9270388e 6051 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6052 if (!i915_mch_dev) {
6053 ret = false;
6054 goto out_unlock;
6055 }
6056 dev_priv = i915_mch_dev;
6057
20e4d407
DV		 6058 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6059 dev_priv->ips.max_delay++;
eb48eb00
DV		 6060
6061out_unlock:
9270388e 6062 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6063
6064 return ret;
6065}
6066EXPORT_SYMBOL_GPL(i915_gpu_lower);
6067
6068/**
6069 * i915_gpu_busy - indicate GPU business to IPS
6070 *
6071 * Tell the IPS driver whether or not the GPU is busy.
6072 */
6073bool i915_gpu_busy(void)
6074{
6075 struct drm_i915_private *dev_priv;
e2f80391 6076 struct intel_engine_cs *engine;
eb48eb00
DV		 6077 bool ret = false;
6078
9270388e 6079 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6080 if (!i915_mch_dev)
6081 goto out_unlock;
6082 dev_priv = i915_mch_dev;
6083
b4ac5afc 6084 for_each_engine(engine, dev_priv)
e2f80391 6085 ret |= !list_empty(&engine->request_list);
eb48eb00
DV		 6086
6087out_unlock:
9270388e 6088 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6089
6090 return ret;
6091}
6092EXPORT_SYMBOL_GPL(i915_gpu_busy);
6093
6094/**
6095 * i915_gpu_turbo_disable - disable graphics turbo
6096 *
6097 * Disable graphics turbo by resetting the max frequency and setting the
6098 * current frequency to the default.
6099 */
6100bool i915_gpu_turbo_disable(void)
6101{
6102 struct drm_i915_private *dev_priv;
6103 bool ret = true;
6104
9270388e 6105 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6106 if (!i915_mch_dev) {
6107 ret = false;
6108 goto out_unlock;
6109 }
6110 dev_priv = i915_mch_dev;
6111
20e4d407 6112 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6113
20e4d407 6114 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6115 ret = false;
6116
6117out_unlock:
9270388e 6118 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6119
6120 return ret;
6121}
6122EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6123
6124/**
6125 * Tells the intel_ips driver that the i915 driver is now loaded, if
6126 * IPS got loaded first.
6127 *
6128 * This awkward dance is so that neither module has to depend on the
6129 * other in order for IPS to do the appropriate communication of
6130 * GPU turbo limits to i915.
6131 */
6132static void
6133ips_ping_for_i915_load(void)
6134{
6135 void (*link)(void);
6136
6137 link = symbol_get(ips_link_to_i915_driver);
6138 if (link) {
6139 link();
6140 symbol_put(ips_link_to_i915_driver);
6141 }
6142}
6143
6144void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6145{
02d71956
DV		 6146 /* We only register the i915 ips part with intel-ips once everything is
6147 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6148 spin_lock_irq(&mchdev_lock);
eb48eb00 6149 i915_mch_dev = dev_priv;
9270388e 6150 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6151
6152 ips_ping_for_i915_load();
6153}
6154
6155void intel_gpu_ips_teardown(void)
6156{
9270388e 6157 spin_lock_irq(&mchdev_lock);
eb48eb00 6158 i915_mch_dev = NULL;
9270388e 6159 spin_unlock_irq(&mchdev_lock);
eb48eb00 6160}
76c3552f 6161
8090c6b9 6162static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6163{
6164 struct drm_i915_private *dev_priv = dev->dev_private;
6165 u32 lcfuse;
6166 u8 pxw[16];
6167 int i;
6168
6169 /* Disable to program */
6170 I915_WRITE(ECR, 0);
6171 POSTING_READ(ECR);
6172
6173 /* Program energy weights for various events */
6174 I915_WRITE(SDEW, 0x15040d00);
6175 I915_WRITE(CSIEW0, 0x007f0000);
6176 I915_WRITE(CSIEW1, 0x1e220004);
6177 I915_WRITE(CSIEW2, 0x04000004);
6178
6179 for (i = 0; i < 5; i++)
616847e7 6180 I915_WRITE(PEW(i), 0);
dde18883 6181 for (i = 0; i < 3; i++)
616847e7 6182 I915_WRITE(DEW(i), 0);
dde18883
ED		 6183
6184 /* Program P-state weights to account for frequency power adjustment */
6185 for (i = 0; i < 16; i++) {
616847e7 6186 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6187 unsigned long freq = intel_pxfreq(pxvidfreq);
6188 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6189 PXVFREQ_PX_SHIFT;
6190 unsigned long val;
6191
6192 val = vid * vid;
6193 val *= (freq / 1000);
6194 val *= 255;
6195 val /= (127*127*900);
6196 if (val > 0xff)
6197 DRM_ERROR("bad pxval: %ld\n", val);
6198 pxw[i] = val;
6199 }
6200 /* Render standby states get 0 weight */
6201 pxw[14] = 0;
6202 pxw[15] = 0;
6203
6204 for (i = 0; i < 4; i++) {
6205 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6206 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6207 I915_WRITE(PXW(i), val);
dde18883
ED		 6208 }
6209
6210 /* Adjust magic regs to magic values (more experimental results) */
6211 I915_WRITE(OGW0, 0);
6212 I915_WRITE(OGW1, 0);
6213 I915_WRITE(EG0, 0x00007f00);
6214 I915_WRITE(EG1, 0x0000000e);
6215 I915_WRITE(EG2, 0x000e0000);
6216 I915_WRITE(EG3, 0x68000300);
6217 I915_WRITE(EG4, 0x42000000);
6218 I915_WRITE(EG5, 0x00140031);
6219 I915_WRITE(EG6, 0);
6220 I915_WRITE(EG7, 0);
6221
6222 for (i = 0; i < 8; i++)
616847e7 6223 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6224
6225 /* Enable PMON + select events */
6226 I915_WRITE(ECR, 0x80000019);
6227
6228 lcfuse = I915_READ(LCFUSE02);
6229
20e4d407 6230 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6231}
6232
ae48434c
ID		 6233void intel_init_gt_powersave(struct drm_device *dev)
6234{
b268c699
ID		 6235 struct drm_i915_private *dev_priv = dev->dev_private;
6236
b268c699
ID		 6237 /*
6238 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6239 * requirement.
6240 */
6241 if (!i915.enable_rc6) {
6242 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6243 intel_runtime_pm_get(dev_priv);
6244 }
e6069ca8 6245
38807746
D		 6246 if (IS_CHERRYVIEW(dev))
6247 cherryview_init_gt_powersave(dev);
6248 else if (IS_VALLEYVIEW(dev))
4e80519e 6249 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6250}
6251
6252void intel_cleanup_gt_powersave(struct drm_device *dev)
6253{
b268c699
ID		 6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255
38807746
D		 6256 if (IS_CHERRYVIEW(dev))
6257 return;
6258 else if (IS_VALLEYVIEW(dev))
4e80519e 6259 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6260
6261 if (!i915.enable_rc6)
6262 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6263}
6264
dbea3cea
ID		 6265static void gen6_suspend_rps(struct drm_device *dev)
6266{
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268
6269 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6270
4c2a8897 6271 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6272}
6273
156c7ca0
JB		 6274/**
6275 * intel_suspend_gt_powersave - suspend PM work and helper threads
6276 * @dev: drm device
6277 *
6278 * We don't want to disable RC6 or other features here, we just want
6279 * to make sure any work we've queued has finished and won't bother
6280 * us while we're suspended.
6281 */
6282void intel_suspend_gt_powersave(struct drm_device *dev)
6283{
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285
d4d70aa5
ID		 6286 if (INTEL_INFO(dev)->gen < 6)
6287 return;
6288
dbea3cea 6289 gen6_suspend_rps(dev);
b47adc17
D		 6290
6291 /* Force GPU to min freq during suspend */
6292 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6293}
6294
8090c6b9
DV		 6295void intel_disable_gt_powersave(struct drm_device *dev)
6296{
1a01ab3b
JB		 6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298
930ebb46 6299 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6300 ironlake_disable_drps(dev);
38807746 6301 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6302 intel_suspend_gt_powersave(dev);
e494837a 6303
4fc688ce 6304 mutex_lock(&dev_priv->rps.hw_lock);
2030d684
AG		 6305 if (INTEL_INFO(dev)->gen >= 9) {
6306 gen9_disable_rc6(dev);
20e49366 6307 gen9_disable_rps(dev);
2030d684 6308 } else if (IS_CHERRYVIEW(dev))
38807746
D		 6309 cherryview_disable_rps(dev);
6310 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6311 valleyview_disable_rps(dev);
6312 else
6313 gen6_disable_rps(dev);
e534770a 6314
c0951f0c 6315 dev_priv->rps.enabled = false;
4fc688ce 6316 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6317 }
8090c6b9
DV		 6318}
6319
1a01ab3b
JB		 6320static void intel_gen6_powersave_work(struct work_struct *work)
6321{
6322 struct drm_i915_private *dev_priv =
6323 container_of(work, struct drm_i915_private,
6324 rps.delayed_resume_work.work);
6325 struct drm_device *dev = dev_priv->dev;
6326
4fc688ce 6327 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6328
4c2a8897 6329 gen6_reset_rps_interrupts(dev);
3cc134e3 6330
38807746
D		 6331 if (IS_CHERRYVIEW(dev)) {
6332 cherryview_enable_rps(dev);
6333 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6334 valleyview_enable_rps(dev);
20e49366 6335 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6336 gen9_enable_rc6(dev);
20e49366 6337 gen9_enable_rps(dev);
ef11bdb3 6338 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6339 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6340 } else if (IS_BROADWELL(dev)) {
6341 gen8_enable_rps(dev);
c2bc2fc5 6342 __gen6_update_ring_freq(dev);
0a073b84
JB		 6343 } else {
6344 gen6_enable_rps(dev);
c2bc2fc5 6345 __gen6_update_ring_freq(dev);
0a073b84 6346 }
aed242ff
CW		 6347
6348 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6349 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6350
6351 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6352 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6353
c0951f0c 6354 dev_priv->rps.enabled = true;
3cc134e3 6355
4c2a8897 6356 gen6_enable_rps_interrupts(dev);
3cc134e3 6357
4fc688ce 6358 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6359
6360 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6361}
6362
8090c6b9
DV		 6363void intel_enable_gt_powersave(struct drm_device *dev)
6364{
1a01ab3b
JB		 6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366
f61018b1
YZ		 6367 /* Powersaving is controlled by the host when inside a VM */
6368 if (intel_vgpu_active(dev))
6369 return;
6370
8090c6b9
DV		 6371 if (IS_IRONLAKE_M(dev)) {
6372 ironlake_enable_drps(dev);
84f1b20f 6373 mutex_lock(&dev->struct_mutex);
8090c6b9 6374 intel_init_emon(dev);
dc1d0136 6375 mutex_unlock(&dev->struct_mutex);
38807746 6376 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6377 /*
6378 * PCU communication is slow and this doesn't need to be
6379 * done at any specific time, so do this out of our fast path
6380 * to make resume and init faster.
c6df39b5
ID		 6381 *
6382 * We depend on the HW RC6 power context save/restore
6383 * mechanism when entering D3 through runtime PM suspend. So
6384 * disable RPM until RPS/RC6 is properly setup. We can only
6385 * get here via the driver load/system resume/runtime resume
6386 * paths, so the _noresume version is enough (and in case of
6387 * runtime resume it's necessary).
1a01ab3b 6388 */
c6df39b5
ID		 6389 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6390 round_jiffies_up_relative(HZ)))
6391 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6392 }
6393}
6394
c6df39b5
ID		 6395void intel_reset_gt_powersave(struct drm_device *dev)
6396{
6397 struct drm_i915_private *dev_priv = dev->dev_private;
6398
dbea3cea
ID		 6399 if (INTEL_INFO(dev)->gen < 6)
6400 return;
6401
6402 gen6_suspend_rps(dev);
c6df39b5 6403 dev_priv->rps.enabled = false;
c6df39b5
ID		 6404}
6405
3107bd48
DV		 6406static void ibx_init_clock_gating(struct drm_device *dev)
6407{
6408 struct drm_i915_private *dev_priv = dev->dev_private;
6409
6410 /*
6411 * On Ibex Peak and Cougar Point, we need to disable clock
6412 * gating for the panel power sequencer or it will fail to
6413 * start up when no ports are active.
6414 */
6415 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6416}
6417
0e088b8f
VS		 6418static void g4x_disable_trickle_feed(struct drm_device *dev)
6419{
6420 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6421 enum pipe pipe;
0e088b8f 6422
055e393f 6423 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6424 I915_WRITE(DSPCNTR(pipe),
6425 I915_READ(DSPCNTR(pipe)) |
6426 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6427
6428 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6429 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6430 }
6431}
6432
017636cc
VS		 6433static void ilk_init_lp_watermarks(struct drm_device *dev)
6434{
6435 struct drm_i915_private *dev_priv = dev->dev_private;
6436
6437 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6438 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6439 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6440
6441 /*
6442 * Don't touch WM1S_LP_EN here.
6443 * Doing so could cause underruns.
6444 */
6445}
6446
1fa61106 6447static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6448{
6449 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6450 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6451
f1e8fa56
DL		 6452 /*
6453 * Required for FBC
6454 * WaFbcDisableDpfcClockGating:ilk
6455 */
4d47e4f5
DL		 6456 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6457 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6458 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6459
6460 I915_WRITE(PCH_3DCGDIS0,
6461 MARIUNIT_CLOCK_GATE_DISABLE |
6462 SVSMUNIT_CLOCK_GATE_DISABLE);
6463 I915_WRITE(PCH_3DCGDIS1,
6464 VFMUNIT_CLOCK_GATE_DISABLE);
6465
6f1d69b0
ED		 6466 /*
6467 * According to the spec the following bits should be set in
6468 * order to enable memory self-refresh
6469 * The bit 22/21 of 0x42004
6470 * The bit 5 of 0x42020
6471 * The bit 15 of 0x45000
6472 */
6473 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6474 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6475 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6476 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6477 I915_WRITE(DISP_ARB_CTL,
6478 (I915_READ(DISP_ARB_CTL) |
6479 DISP_FBC_WM_DIS));
017636cc
VS		 6480
6481 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6482
6483 /*
6484 * Based on the document from hardware guys the following bits
6485 * should be set unconditionally in order to enable FBC.
6486 * The bit 22 of 0x42000
6487 * The bit 22 of 0x42004
6488 * The bit 7,8,9 of 0x42020.
6489 */
6490 if (IS_IRONLAKE_M(dev)) {
4bb35334 6491 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6492 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6493 I915_READ(ILK_DISPLAY_CHICKEN1) |
6494 ILK_FBCQ_DIS);
6495 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6496 I915_READ(ILK_DISPLAY_CHICKEN2) |
6497 ILK_DPARB_GATE);
6f1d69b0
ED		 6498 }
6499
4d47e4f5
DL		 6500 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6501
6f1d69b0
ED		 6502 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6503 I915_READ(ILK_DISPLAY_CHICKEN2) |
6504 ILK_ELPIN_409_SELECT);
6505 I915_WRITE(_3D_CHICKEN2,
6506 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6507 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6508
ecdb4eb7 6509 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6510 I915_WRITE(CACHE_MODE_0,
6511 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6512
4e04632e
AG		 6513 /* WaDisable_RenderCache_OperationalFlush:ilk */
6514 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6515
0e088b8f 6516 g4x_disable_trickle_feed(dev);
bdad2b2f 6517
3107bd48
DV		 6518 ibx_init_clock_gating(dev);
6519}
6520
6521static void cpt_init_clock_gating(struct drm_device *dev)
6522{
6523 struct drm_i915_private *dev_priv = dev->dev_private;
6524 int pipe;
3f704fa2 6525 uint32_t val;
3107bd48
DV		 6526
6527 /*
6528 * On Ibex Peak and Cougar Point, we need to disable clock
6529 * gating for the panel power sequencer or it will fail to
6530 * start up when no ports are active.
6531 */
cd664078
JB		 6532 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6533 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6534 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6535 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6536 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6537 /* The below fixes the weird display corruption, a few pixels shifted
6538 * downward, on (only) LVDS of some HP laptops with IVY.
6539 */
055e393f 6540 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6541 val = I915_READ(TRANS_CHICKEN2(pipe));
6542 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6543 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6544 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6545 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6546 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6547 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6548 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6549 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6550 }
3107bd48 6551 /* WADP0ClockGatingDisable */
055e393f 6552 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6553 I915_WRITE(TRANS_CHICKEN1(pipe),
6554 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6555 }
6f1d69b0
ED		 6556}
6557
1d7aaa0c
DV		 6558static void gen6_check_mch_setup(struct drm_device *dev)
6559{
6560 struct drm_i915_private *dev_priv = dev->dev_private;
6561 uint32_t tmp;
6562
6563 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6564 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6565 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6566 tmp);
1d7aaa0c
DV		 6567}
6568
1fa61106 6569static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6570{
6571 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6572 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6573
231e54f6 6574 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6575
6576 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6577 I915_READ(ILK_DISPLAY_CHICKEN2) |
6578 ILK_ELPIN_409_SELECT);
6579
ecdb4eb7 6580 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6581 I915_WRITE(_3D_CHICKEN,
6582 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6583
4e04632e
AG		 6584 /* WaDisable_RenderCache_OperationalFlush:snb */
6585 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6586
8d85d272
VS		 6587 /*
6588 * BSpec recoomends 8x4 when MSAA is used,
6589 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6590 *
6591 * Note that PS/WM thread counts depend on the WIZ hashing
6592 * disable bit, which we don't touch here, but it's good
6593 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6594 */
6595 I915_WRITE(GEN6_GT_MODE,
98533251 6596 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6597
017636cc 6598 ilk_init_lp_watermarks(dev);
6f1d69b0 6599
6f1d69b0 6600 I915_WRITE(CACHE_MODE_0,
50743298 6601 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6602
6603 I915_WRITE(GEN6_UCGCTL1,
6604 I915_READ(GEN6_UCGCTL1) |
6605 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6606 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6607
6608 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6609 * gating disable must be set. Failure to set it results in
6610 * flickering pixels due to Z write ordering failures after
6611 * some amount of runtime in the Mesa "fire" demo, and Unigine
6612 * Sanctuary and Tropics, and apparently anything else with
6613 * alpha test or pixel discard.
6614 *
6615 * According to the spec, bit 11 (RCCUNIT) must also be set,
6616 * but we didn't debug actual testcases to find it out.
0f846f81 6617 *
ef59318c
VS		 6618 * WaDisableRCCUnitClockGating:snb
6619 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6620 */
6621 I915_WRITE(GEN6_UCGCTL2,
6622 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6623 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6624
5eb146dd 6625 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6626 I915_WRITE(_3D_CHICKEN3,
6627 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6628
e927ecde
VS		 6629 /*
6630 * Bspec says:
6631 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6632 * 3DSTATE_SF number of SF output attributes is more than 16."
6633 */
6634 I915_WRITE(_3D_CHICKEN3,
6635 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6636
6f1d69b0
ED		 6637 /*
6638 * According to the spec the following bits should be
6639 * set in order to enable memory self-refresh and fbc:
6640 * The bit21 and bit22 of 0x42000
6641 * The bit21 and bit22 of 0x42004
6642 * The bit5 and bit7 of 0x42020
6643 * The bit14 of 0x70180
6644 * The bit14 of 0x71180
4bb35334
DL		 6645 *
6646 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6647 */
6648 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6649 I915_READ(ILK_DISPLAY_CHICKEN1) |
6650 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6651 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6652 I915_READ(ILK_DISPLAY_CHICKEN2) |
6653 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6654 I915_WRITE(ILK_DSPCLK_GATE_D,
6655 I915_READ(ILK_DSPCLK_GATE_D) |
6656 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6657 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6658
0e088b8f 6659 g4x_disable_trickle_feed(dev);
f8f2ac9a 6660
3107bd48 6661 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6662
6663 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6664}
6665
6666static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6667{
6668 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6669
3aad9059 6670 /*
46680e0a 6671 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6672 *
6673 * This actually overrides the dispatch
6674 * mode for all thread types.
6675 */
6f1d69b0
ED		 6676 reg &= ~GEN7_FF_SCHED_MASK;
6677 reg |= GEN7_FF_TS_SCHED_HW;
6678 reg |= GEN7_FF_VS_SCHED_HW;
6679 reg |= GEN7_FF_DS_SCHED_HW;
6680
6681 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6682}
6683
17a303ec
PZ		 6684static void lpt_init_clock_gating(struct drm_device *dev)
6685{
6686 struct drm_i915_private *dev_priv = dev->dev_private;
6687
6688 /*
6689 * TODO: this bit should only be enabled when really needed, then
6690 * disabled when not needed anymore in order to save power.
6691 */
c2699524 6692 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6693 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6694 I915_READ(SOUTH_DSPCLK_GATE_D) |
6695 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6696
6697 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6698 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6699 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6700 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6701}
6702
7d708ee4
ID		 6703static void lpt_suspend_hw(struct drm_device *dev)
6704{
6705 struct drm_i915_private *dev_priv = dev->dev_private;
6706
c2699524 6707 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6708 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6709
6710 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6711 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6712 }
6713}
6714
9146f308
MK		 6715static void kabylake_init_clock_gating(struct drm_device *dev)
6716{
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718
11b28341 6719 gen9_init_clock_gating(dev);
9146f308
MK		 6720
6721 /* WaDisableSDEUnitClockGating:kbl */
6722 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6723 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6724 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
4ac41994
MK		 6725
6726 /* WaDisableGamClockGating:kbl */
6727 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
6728 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6729 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
9146f308
MK		 6730}
6731
da0a0aca
DV		 6732static void skylake_init_clock_gating(struct drm_device *dev)
6733{
11b28341 6734 gen9_init_clock_gating(dev);
da0a0aca
DV		 6735}
6736
47c2bd97 6737static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6738{
6739 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6740 enum pipe pipe;
4d487cff 6741 uint32_t misccpctl;
1020a5c2 6742
7ad0dbab 6743 ilk_init_lp_watermarks(dev);
50ed5fbd 6744
ab57fff1 6745 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6746 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6747
ab57fff1 6748 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6749 I915_WRITE(CHICKEN_PAR1_1,
6750 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6751
ab57fff1 6752 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6753 for_each_pipe(dev_priv, pipe) {
07d27e20 6754 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6755 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6756 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6757 }
63801f21 6758
ab57fff1
BW		 6759 /* WaVSRefCountFullforceMissDisable:bdw */
6760 /* WaDSRefCountFullforceMissDisable:bdw */
6761 I915_WRITE(GEN7_FF_THREAD_MODE,
6762 I915_READ(GEN7_FF_THREAD_MODE) &
6763 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6764
295e8bb7
VS		 6765 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6766 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6767
6768 /* WaDisableSDEUnitClockGating:bdw */
6769 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6770 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6771
4d487cff
VS		 6772 /*
6773 * WaProgramL3SqcReg1Default:bdw
6774 * WaTempDisableDOPClkGating:bdw
6775 */
6776 misccpctl = I915_READ(GEN7_MISCCPCTL);
6777 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6778 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
d6a862fe
ID		 6779 /*
6780 * Wait at least 100 clocks before re-enabling clock gating. See
6781 * the definition of L3SQCREG1 in BSpec.
6782 */
6783 POSTING_READ(GEN8_L3SQCREG1);
6784 udelay(1);
4d487cff
VS		 6785 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6786
6d50b065
VS		 6787 /*
6788 * WaGttCachingOffByDefault:bdw
6789 * GTT cache may not work with big pages, so if those
6790 * are ever enabled GTT cache may need to be disabled.
6791 */
6792 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6793
89d6b2b8 6794 lpt_init_clock_gating(dev);
1020a5c2
BW		 6795}
6796
cad2a2d7
ED		 6797static void haswell_init_clock_gating(struct drm_device *dev)
6798{
6799 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6800
017636cc 6801 ilk_init_lp_watermarks(dev);
cad2a2d7 6802
f3fc4884
FJ		 6803 /* L3 caching of data atomics doesn't work -- disable it. */
6804 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6805 I915_WRITE(HSW_ROW_CHICKEN3,
6806 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6807
ecdb4eb7 6808 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6809 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6810 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6811 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6812
e36ea7ff
VS		 6813 /* WaVSRefCountFullforceMissDisable:hsw */
6814 I915_WRITE(GEN7_FF_THREAD_MODE,
6815 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6816
4e04632e
AG		 6817 /* WaDisable_RenderCache_OperationalFlush:hsw */
6818 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6819
fe27c606
CW		 6820 /* enable HiZ Raw Stall Optimization */
6821 I915_WRITE(CACHE_MODE_0_GEN7,
6822 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6823
ecdb4eb7 6824 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6825 I915_WRITE(CACHE_MODE_1,
6826 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6827
a12c4967
VS		 6828 /*
6829 * BSpec recommends 8x4 when MSAA is used,
6830 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6831 *
6832 * Note that PS/WM thread counts depend on the WIZ hashing
6833 * disable bit, which we don't touch here, but it's good
6834 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6835 */
6836 I915_WRITE(GEN7_GT_MODE,
98533251 6837 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6838
94411593
KG		 6839 /* WaSampleCChickenBitEnable:hsw */
6840 I915_WRITE(HALF_SLICE_CHICKEN3,
6841 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6842
ecdb4eb7 6843 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6844 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6845
90a88643
PZ		 6846 /* WaRsPkgCStateDisplayPMReq:hsw */
6847 I915_WRITE(CHICKEN_PAR1_1,
6848 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6849
17a303ec 6850 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6851}
6852
1fa61106 6853static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6854{
6855 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6856 uint32_t snpcr;
6f1d69b0 6857
017636cc 6858 ilk_init_lp_watermarks(dev);
6f1d69b0 6859
231e54f6 6860 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6861
ecdb4eb7 6862 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6863 I915_WRITE(_3D_CHICKEN3,
6864 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6865
ecdb4eb7 6866 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6867 I915_WRITE(IVB_CHICKEN3,
6868 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6869 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6870
ecdb4eb7 6871 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6872 if (IS_IVB_GT1(dev))
6873 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6874 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6875
4e04632e
AG		 6876 /* WaDisable_RenderCache_OperationalFlush:ivb */
6877 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6878
ecdb4eb7 6879 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6880 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6881 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6882
ecdb4eb7 6883 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6884 I915_WRITE(GEN7_L3CNTLREG1,
6885 GEN7_WA_FOR_GEN7_L3_CONTROL);
6886 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6887 GEN7_WA_L3_CHICKEN_MODE);
6888 if (IS_IVB_GT1(dev))
6889 I915_WRITE(GEN7_ROW_CHICKEN2,
6890 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6891 else {
6892 /* must write both registers */
6893 I915_WRITE(GEN7_ROW_CHICKEN2,
6894 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6895 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6896 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6897 }
6f1d69b0 6898
ecdb4eb7 6899 /* WaForceL3Serialization:ivb */
61939d97
JB		 6900 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6901 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6902
1b80a19a 6903 /*
0f846f81 6904 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6905 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6906 */
6907 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6908 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6909
ecdb4eb7 6910 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6911 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6912 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6913 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6914
0e088b8f 6915 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6916
6917 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6918
22721343
CW		 6919 if (0) { /* causes HiZ corruption on ivb:gt1 */
6920 /* enable HiZ Raw Stall Optimization */
6921 I915_WRITE(CACHE_MODE_0_GEN7,
6922 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6923 }
116f2b6d 6924
ecdb4eb7 6925 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6926 I915_WRITE(CACHE_MODE_1,
6927 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6928
a607c1a4
VS		 6929 /*
6930 * BSpec recommends 8x4 when MSAA is used,
6931 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6932 *
6933 * Note that PS/WM thread counts depend on the WIZ hashing
6934 * disable bit, which we don't touch here, but it's good
6935 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6936 */
6937 I915_WRITE(GEN7_GT_MODE,
98533251 6938 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6939
20848223
BW		 6940 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6941 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6942 snpcr |= GEN6_MBC_SNPCR_MED;
6943 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6944
ab5c608b
BW		 6945 if (!HAS_PCH_NOP(dev))
6946 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6947
6948 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6949}
6950
1fa61106 6951static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6952{
6953 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6954
ecdb4eb7 6955 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6956 I915_WRITE(_3D_CHICKEN3,
6957 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6958
ecdb4eb7 6959 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6960 I915_WRITE(IVB_CHICKEN3,
6961 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6962 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6963
fad7d36e 6964 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6965 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6966 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6967 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6968 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6969
4e04632e
AG		 6970 /* WaDisable_RenderCache_OperationalFlush:vlv */
6971 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6972
ecdb4eb7 6973 /* WaForceL3Serialization:vlv */
61939d97
JB		 6974 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6975 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6976
ecdb4eb7 6977 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6978 I915_WRITE(GEN7_ROW_CHICKEN2,
6979 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6980
ecdb4eb7 6981 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6982 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6983 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6984 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6985
46680e0a
VS		 6986 gen7_setup_fixed_func_scheduler(dev_priv);
6987
3c0edaeb 6988 /*
0f846f81 6989 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6990 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6991 */
6992 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6993 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6994
c98f5062
AG		 6995 /* WaDisableL3Bank2xClockGate:vlv
6996 * Disabling L3 clock gating- MMIO 940c[25] = 1
6997 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6998 I915_WRITE(GEN7_UCGCTL4,
6999 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7000
afd58e79
VS		 7001 /*
7002 * BSpec says this must be set, even though
7003 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7004 */
6b26c86d
DV		 7005 I915_WRITE(CACHE_MODE_1,
7006 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7007
da2518f9
VS		 7008 /*
7009 * BSpec recommends 8x4 when MSAA is used,
7010 * however in practice 16x4 seems fastest.
7011 *
7012 * Note that PS/WM thread counts depend on the WIZ hashing
7013 * disable bit, which we don't touch here, but it's good
7014 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7015 */
7016 I915_WRITE(GEN7_GT_MODE,
7017 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7018
031994ee
VS		 7019 /*
7020 * WaIncreaseL3CreditsForVLVB0:vlv
7021 * This is the hardware default actually.
7022 */
7023 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7024
2d809570 7025 /*
ecdb4eb7 7026 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7027 * Disable clock gating on th GCFG unit to prevent a delay
7028 * in the reporting of vblank events.
7029 */
7a0d1eed 7030 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7031}
7032
a4565da8
VS		 7033static void cherryview_init_clock_gating(struct drm_device *dev)
7034{
7035 struct drm_i915_private *dev_priv = dev->dev_private;
7036
232ce337
VS		 7037 /* WaVSRefCountFullforceMissDisable:chv */
7038 /* WaDSRefCountFullforceMissDisable:chv */
7039 I915_WRITE(GEN7_FF_THREAD_MODE,
7040 I915_READ(GEN7_FF_THREAD_MODE) &
7041 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7042
7043 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7044 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7045 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7046
7047 /* WaDisableCSUnitClockGating:chv */
7048 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7049 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7050
7051 /* WaDisableSDEUnitClockGating:chv */
7052 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7053 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 7054
7055 /*
7056 * GTT cache may not work with big pages, so if those
7057 * are ever enabled GTT cache may need to be disabled.
7058 */
7059 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7060}
7061
1fa61106 7062static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7063{
7064 struct drm_i915_private *dev_priv = dev->dev_private;
7065 uint32_t dspclk_gate;
7066
7067 I915_WRITE(RENCLK_GATE_D1, 0);
7068 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7069 GS_UNIT_CLOCK_GATE_DISABLE |
7070 CL_UNIT_CLOCK_GATE_DISABLE);
7071 I915_WRITE(RAMCLK_GATE_D, 0);
7072 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7073 OVRUNIT_CLOCK_GATE_DISABLE |
7074 OVCUNIT_CLOCK_GATE_DISABLE;
7075 if (IS_GM45(dev))
7076 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7077 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7078
7079 /* WaDisableRenderCachePipelinedFlush */
7080 I915_WRITE(CACHE_MODE_0,
7081 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7082
4e04632e
AG		 7083 /* WaDisable_RenderCache_OperationalFlush:g4x */
7084 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7085
0e088b8f 7086 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7087}
7088
1fa61106 7089static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7090{
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092
7093 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7094 I915_WRITE(RENCLK_GATE_D2, 0);
7095 I915_WRITE(DSPCLK_GATE_D, 0);
7096 I915_WRITE(RAMCLK_GATE_D, 0);
7097 I915_WRITE16(DEUC, 0);
20f94967
VS		 7098 I915_WRITE(MI_ARB_STATE,
7099 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7100
7101 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7102 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7103}
7104
1fa61106 7105static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7106{
7107 struct drm_i915_private *dev_priv = dev->dev_private;
7108
7109 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7110 I965_RCC_CLOCK_GATE_DISABLE |
7111 I965_RCPB_CLOCK_GATE_DISABLE |
7112 I965_ISC_CLOCK_GATE_DISABLE |
7113 I965_FBC_CLOCK_GATE_DISABLE);
7114 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7115 I915_WRITE(MI_ARB_STATE,
7116 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7117
7118 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7119 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7120}
7121
1fa61106 7122static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7123{
7124 struct drm_i915_private *dev_priv = dev->dev_private;
7125 u32 dstate = I915_READ(D_STATE);
7126
7127 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7128 DSTATE_DOT_CLOCK_GATING;
7129 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7130
7131 if (IS_PINEVIEW(dev))
7132 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7133
7134 /* IIR "flip pending" means done if this bit is set */
7135 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7136
7137 /* interrupts should cause a wake up from C3 */
3299254f 7138 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7139
7140 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7141 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7142
7143 I915_WRITE(MI_ARB_STATE,
7144 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7145}
7146
1fa61106 7147static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7148{
7149 struct drm_i915_private *dev_priv = dev->dev_private;
7150
7151 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7152
7153 /* interrupts should cause a wake up from C3 */
7154 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7155 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7156
7157 I915_WRITE(MEM_MODE,
7158 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7159}
7160
1fa61106 7161static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7162{
7163 struct drm_i915_private *dev_priv = dev->dev_private;
7164
7165 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7166
7167 I915_WRITE(MEM_MODE,
7168 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7169 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7170}
7171
6f1d69b0
ED		 7172void intel_init_clock_gating(struct drm_device *dev)
7173{
7174 struct drm_i915_private *dev_priv = dev->dev_private;
7175
bb400da9 7176 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7177}
7178
7d708ee4
ID		 7179void intel_suspend_hw(struct drm_device *dev)
7180{
7181 if (HAS_PCH_LPT(dev))
7182 lpt_suspend_hw(dev);
7183}
7184
bb400da9
ID		 7185static void nop_init_clock_gating(struct drm_device *dev)
7186{
7187 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7188}
7189
7190/**
7191 * intel_init_clock_gating_hooks - setup the clock gating hooks
7192 * @dev_priv: device private
7193 *
7194 * Setup the hooks that configure which clocks of a given platform can be
7195 * gated and also apply various GT and display specific workarounds for these
7196 * platforms. Note that some GT specific workarounds are applied separately
7197 * when GPU contexts or batchbuffers start their execution.
7198 */
7199void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7200{
7201 if (IS_SKYLAKE(dev_priv))
da0a0aca 7202 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7203 else if (IS_KABYLAKE(dev_priv))
9146f308 7204 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7205 else if (IS_BROXTON(dev_priv))
7206 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7207 else if (IS_BROADWELL(dev_priv))
7208 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7209 else if (IS_CHERRYVIEW(dev_priv))
7210 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7211 else if (IS_HASWELL(dev_priv))
7212 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7213 else if (IS_IVYBRIDGE(dev_priv))
7214 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7215 else if (IS_VALLEYVIEW(dev_priv))
7216 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7217 else if (IS_GEN6(dev_priv))
7218 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7219 else if (IS_GEN5(dev_priv))
7220 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7221 else if (IS_G4X(dev_priv))
7222 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7223 else if (IS_CRESTLINE(dev_priv))
7224 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7225 else if (IS_BROADWATER(dev_priv))
7226 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7227 else if (IS_GEN3(dev_priv))
7228 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7229 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7230 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7231 else if (IS_GEN2(dev_priv))
7232 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7233 else {
7234 MISSING_CASE(INTEL_DEVID(dev_priv));
7235 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7236 }
7237}
7238
1fa61106
ED		 7239/* Set up chip specific power management-related functions */
7240void intel_init_pm(struct drm_device *dev)
7241{
7242 struct drm_i915_private *dev_priv = dev->dev_private;
7243
7ff0ebcc 7244 intel_fbc_init(dev_priv);
1fa61106 7245
c921aba8
DV		 7246 /* For cxsr */
7247 if (IS_PINEVIEW(dev))
7248 i915_pineview_get_mem_freq(dev);
7249 else if (IS_GEN5(dev))
7250 i915_ironlake_get_mem_freq(dev);
7251
1fa61106 7252 /* For FIFO watermark updates */
f5ed50cb 7253 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7254 skl_setup_wm_latency(dev);
2d41c0b5 7255 dev_priv->display.update_wm = skl_update_wm;
c83155a6 7256 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7257 ilk_setup_wm_latency(dev);
53615a5e 7258
bd602544
VS		 7259 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7260 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7261 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7262 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7263 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7264 dev_priv->display.compute_intermediate_wm =
7265 ilk_compute_intermediate_wm;
7266 dev_priv->display.initial_watermarks =
7267 ilk_initial_watermarks;
7268 dev_priv->display.optimize_watermarks =
7269 ilk_optimize_watermarks;
bd602544
VS		 7270 } else {
7271 DRM_DEBUG_KMS("Failed to read display plane latency. "
7272 "Disable CxSR\n");
7273 }
a4565da8 7274 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7275 vlv_setup_wm_latency(dev);
262cd2e1 7276 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7277 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7278 vlv_setup_wm_latency(dev);
26e1fe4f 7279 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7280 } else if (IS_PINEVIEW(dev)) {
7281 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7282 dev_priv->is_ddr3,
7283 dev_priv->fsb_freq,
7284 dev_priv->mem_freq)) {
7285 DRM_INFO("failed to find known CxSR latency "
7286 "(found ddr%s fsb freq %d, mem freq %d), "
7287 "disabling CxSR\n",
7288 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7289 dev_priv->fsb_freq, dev_priv->mem_freq);
7290 /* Disable CxSR and never update its watermark again */
5209b1f4 7291 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7292 dev_priv->display.update_wm = NULL;
7293 } else
7294 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7295 } else if (IS_G4X(dev)) {
7296 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7297 } else if (IS_GEN4(dev)) {
7298 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7299 } else if (IS_GEN3(dev)) {
7300 dev_priv->display.update_wm = i9xx_update_wm;
7301 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7302 } else if (IS_GEN2(dev)) {
7303 if (INTEL_INFO(dev)->num_pipes == 1) {
7304 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7305 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7306 } else {
7307 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7308 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7309 }
feb56b93
DV		 7310 } else {
7311 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7312 }
7313}
7314
151a49d0 7315int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7316{
4fc688ce 7317 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7318
7319 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7320 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7321 return -EAGAIN;
7322 }
7323
7324 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7325 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7326 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7327
7328 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7329 500)) {
7330 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7331 return -ETIMEDOUT;
7332 }
7333
7334 *val = I915_READ(GEN6_PCODE_DATA);
7335 I915_WRITE(GEN6_PCODE_DATA, 0);
7336
7337 return 0;
7338}
7339
151a49d0 7340int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7341{
4fc688ce 7342 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7343
7344 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7345 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7346 return -EAGAIN;
7347 }
7348
7349 I915_WRITE(GEN6_PCODE_DATA, val);
7350 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7351
7352 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7353 500)) {
7354 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7355 return -ETIMEDOUT;
7356 }
7357
7358 I915_WRITE(GEN6_PCODE_DATA, 0);
7359
7360 return 0;
7361}
a0e4e199 7362
dd06f88c
VS		 7363static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7364{
c30fec65
VS		 7365 /*
7366 * N = val - 0xb7
7367 * Slow = Fast = GPLL ref * N
7368 */
7369 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7370}
7371
b55dd647 7372static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7373{
c30fec65 7374 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7375}
7376
b55dd647 7377static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7378{
c30fec65
VS		 7379 /*
7380 * N = val / 2
7381 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7382 */
7383 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7384}
7385
b55dd647 7386static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7387{
1c14762d 7388 /* CHV needs even values */
c30fec65 7389 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7390}
7391
616bc820 7392int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7393{
2d1fe073 7394 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7395 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7396 GEN9_FREQ_SCALER);
2d1fe073 7397 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7398 return chv_gpu_freq(dev_priv, val);
2d1fe073 7399 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7400 return byt_gpu_freq(dev_priv, val);
7401 else
7402 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7403}
7404
616bc820
VS		 7405int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7406{
2d1fe073 7407 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7408 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7409 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7410 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7411 return chv_freq_opcode(dev_priv, val);
2d1fe073 7412 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7413 return byt_freq_opcode(dev_priv, val);
7414 else
500a3d2e 7415 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7416}
22b1b2f8 7417
6ad790c0
CW		 7418struct request_boost {
7419 struct work_struct work;
eed29a5b 7420 struct drm_i915_gem_request *req;
6ad790c0
CW		 7421};
7422
7423static void __intel_rps_boost_work(struct work_struct *work)
7424{
7425 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7426 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7427
e61b9958 7428 if (!i915_gem_request_completed(req, true))
4a570db5 7429 gen6_rps_boost(to_i915(req->engine->dev), NULL,
e61b9958 7430 req->emitted_jiffies);
6ad790c0 7431
e61b9958 7432 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7433 kfree(boost);
7434}
7435
7436void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7437 struct drm_i915_gem_request *req)
6ad790c0
CW		 7438{
7439 struct request_boost *boost;
7440
eed29a5b 7441 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7442 return;
7443
e61b9958
CW		 7444 if (i915_gem_request_completed(req, true))
7445 return;
7446
6ad790c0
CW		 7447 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7448 if (boost == NULL)
7449 return;
7450
eed29a5b
DV		 7451 i915_gem_request_reference(req);
7452 boost->req = req;
6ad790c0
CW		 7453
7454 INIT_WORK(&boost->work, __intel_rps_boost_work);
7455 queue_work(to_i915(dev)->wq, &boost->work);
7456}
7457
f742a552 7458void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7459{
7460 struct drm_i915_private *dev_priv = dev->dev_private;
7461
f742a552 7462 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7463 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7464
907b28c5
CW		 7465 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7466 intel_gen6_powersave_work);
1854d5ca 7467 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7468 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7469 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7470
33688d95 7471 dev_priv->pm.suspended = false;
1f814dac 7472 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7473 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7474}
Linux kernel - Deliverables
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