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drm/i915: Rename intel_engine_cs function parameters
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
a4d8a0fe 30#include <linux/log2.h>
760285e7 31#include <drm/drmP.h>
62fdfeaf 32#include "i915_drv.h"
760285e7 33#include <drm/i915_drm.h>
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
82e104cc 37int __intel_ring_space(int head, int tail, int size)
c7dca47b 38{
4f54741e
DG		 39 int space = head - tail;
40 if (space <= 0)
1cf0ba14 41 space += size;
4f54741e 42 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 43}
44
ebd0fd4b
DG		 45void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46{
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54}
55
82e104cc 56int intel_ring_space(struct intel_ringbuffer *ringbuf)
1cf0ba14 57{
ebd0fd4b
DG		 58 intel_ring_update_space(ringbuf);
59 return ringbuf->space;
1cf0ba14
CW		 60}
61
0bc40be8 62bool intel_ring_stopped(struct intel_engine_cs *engine)
09246732 63{
0bc40be8
TU		 64 struct drm_i915_private *dev_priv = engine->dev->dev_private;
65 return dev_priv->gpu_error.stop_rings & intel_ring_flag(engine);
88b4aa87 66}
09246732 67
0bc40be8 68static void __intel_ring_advance(struct intel_engine_cs *engine)
88b4aa87 69{
0bc40be8 70 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 71 ringbuf->tail &= ringbuf->size - 1;
0bc40be8 72 if (intel_ring_stopped(engine))
09246732 73 return;
0bc40be8 74 engine->write_tail(engine, ringbuf->tail);
09246732
CW		 75}
76
b72f3acb 77static int
a84c3ae1 78gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 79 u32 invalidate_domains,
80 u32 flush_domains)
81{
e2f80391 82 struct intel_engine_cs *engine = req->ring;
46f0f8d1
CW		 83 u32 cmd;
84 int ret;
85
86 cmd = MI_FLUSH;
31b14c9f 87 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 88 cmd |= MI_NO_WRITE_FLUSH;
89
90 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
91 cmd |= MI_READ_FLUSH;
92
5fb9de1a 93 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 94 if (ret)
95 return ret;
96
e2f80391
TU		 97 intel_ring_emit(engine, cmd);
98 intel_ring_emit(engine, MI_NOOP);
99 intel_ring_advance(engine);
46f0f8d1
CW		 100
101 return 0;
102}
103
104static int
a84c3ae1 105gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 106 u32 invalidate_domains,
107 u32 flush_domains)
62fdfeaf 108{
e2f80391
TU		 109 struct intel_engine_cs *engine = req->ring;
110 struct drm_device *dev = engine->dev;
6f392d54 111 u32 cmd;
b72f3acb 112 int ret;
6f392d54 113
36d527de
CW		 114 /*
115 * read/write caches:
116 *
117 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
118 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
119 * also flushed at 2d versus 3d pipeline switches.
120 *
121 * read-only caches:
122 *
123 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
124 * MI_READ_FLUSH is set, and is always flushed on 965.
125 *
126 * I915_GEM_DOMAIN_COMMAND may not exist?
127 *
128 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
129 * invalidated when MI_EXE_FLUSH is set.
130 *
131 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
132 * invalidated with every MI_FLUSH.
133 *
134 * TLBs:
135 *
136 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
137 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
138 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
139 * are flushed at any MI_FLUSH.
140 */
141
142 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 143 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 144 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 145 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
146 cmd |= MI_EXE_FLUSH;
62fdfeaf 147
36d527de
CW		 148 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
149 (IS_G4X(dev) || IS_GEN5(dev)))
150 cmd |= MI_INVALIDATE_ISP;
70eac33e 151
5fb9de1a 152 ret = intel_ring_begin(req, 2);
36d527de
CW		 153 if (ret)
154 return ret;
b72f3acb 155
e2f80391
TU		 156 intel_ring_emit(engine, cmd);
157 intel_ring_emit(engine, MI_NOOP);
158 intel_ring_advance(engine);
b72f3acb
CW		 159
160 return 0;
8187a2b7
ZN		 161}
162
8d315287
JB		 163/**
164 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
165 * implementing two workarounds on gen6. From section 1.4.7.1
166 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
167 *
168 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
169 * produced by non-pipelined state commands), software needs to first
170 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
171 * 0.
172 *
173 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
174 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
175 *
176 * And the workaround for these two requires this workaround first:
177 *
178 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
179 * BEFORE the pipe-control with a post-sync op and no write-cache
180 * flushes.
181 *
182 * And this last workaround is tricky because of the requirements on
183 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
184 * volume 2 part 1:
185 *
186 * "1 of the following must also be set:
187 * - Render Target Cache Flush Enable ([12] of DW1)
188 * - Depth Cache Flush Enable ([0] of DW1)
189 * - Stall at Pixel Scoreboard ([1] of DW1)
190 * - Depth Stall ([13] of DW1)
191 * - Post-Sync Operation ([13] of DW1)
192 * - Notify Enable ([8] of DW1)"
193 *
194 * The cache flushes require the workaround flush that triggered this
195 * one, so we can't use it. Depth stall would trigger the same.
196 * Post-sync nonzero is what triggered this second workaround, so we
197 * can't use that one either. Notify enable is IRQs, which aren't
198 * really our business. That leaves only stall at scoreboard.
199 */
200static int
f2cf1fcc 201intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 202{
e2f80391
TU		 203 struct intel_engine_cs *engine = req->ring;
204 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 205 int ret;
206
5fb9de1a 207 ret = intel_ring_begin(req, 6);
8d315287
JB		 208 if (ret)
209 return ret;
210
e2f80391
TU		 211 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
212 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
8d315287 213 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 214 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
215 intel_ring_emit(engine, 0); /* low dword */
216 intel_ring_emit(engine, 0); /* high dword */
217 intel_ring_emit(engine, MI_NOOP);
218 intel_ring_advance(engine);
8d315287 219
5fb9de1a 220 ret = intel_ring_begin(req, 6);
8d315287
JB		 221 if (ret)
222 return ret;
223
e2f80391
TU		 224 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
225 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
226 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
227 intel_ring_emit(engine, 0);
228 intel_ring_emit(engine, 0);
229 intel_ring_emit(engine, MI_NOOP);
230 intel_ring_advance(engine);
8d315287
JB		 231
232 return 0;
233}
234
235static int
a84c3ae1
JH		 236gen6_render_ring_flush(struct drm_i915_gem_request *req,
237 u32 invalidate_domains, u32 flush_domains)
8d315287 238{
e2f80391 239 struct intel_engine_cs *engine = req->ring;
8d315287 240 u32 flags = 0;
e2f80391 241 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 242 int ret;
243
b3111509 244 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 245 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 246 if (ret)
247 return ret;
248
8d315287
JB		 249 /* Just flush everything. Experiments have shown that reducing the
250 * number of bits based on the write domains has little performance
251 * impact.
252 */
7d54a904
CW		 253 if (flush_domains) {
254 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
255 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
256 /*
257 * Ensure that any following seqno writes only happen
258 * when the render cache is indeed flushed.
259 */
97f209bc 260 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 261 }
262 if (invalidate_domains) {
263 flags |= PIPE_CONTROL_TLB_INVALIDATE;
264 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
265 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
266 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
267 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
268 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
269 /*
270 * TLB invalidate requires a post-sync write.
271 */
3ac78313 272 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 273 }
8d315287 274
5fb9de1a 275 ret = intel_ring_begin(req, 4);
8d315287
JB		 276 if (ret)
277 return ret;
278
e2f80391
TU		 279 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
280 intel_ring_emit(engine, flags);
281 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
282 intel_ring_emit(engine, 0);
283 intel_ring_advance(engine);
8d315287
JB		 284
285 return 0;
286}
287
f3987631 288static int
f2cf1fcc 289gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 290{
e2f80391 291 struct intel_engine_cs *engine = req->ring;
f3987631
PZ		 292 int ret;
293
5fb9de1a 294 ret = intel_ring_begin(req, 4);
f3987631
PZ		 295 if (ret)
296 return ret;
297
e2f80391
TU		 298 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
299 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
f3987631 300 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 301 intel_ring_emit(engine, 0);
302 intel_ring_emit(engine, 0);
303 intel_ring_advance(engine);
f3987631
PZ		 304
305 return 0;
306}
307
4772eaeb 308static int
a84c3ae1 309gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 310 u32 invalidate_domains, u32 flush_domains)
311{
e2f80391 312 struct intel_engine_cs *engine = req->ring;
4772eaeb 313 u32 flags = 0;
e2f80391 314 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 315 int ret;
316
f3987631
PZ		 317 /*
318 * Ensure that any following seqno writes only happen when the render
319 * cache is indeed flushed.
320 *
321 * Workaround: 4th PIPE_CONTROL command (except the ones with only
322 * read-cache invalidate bits set) must have the CS_STALL bit set. We
323 * don't try to be clever and just set it unconditionally.
324 */
325 flags |= PIPE_CONTROL_CS_STALL;
326
4772eaeb
PZ		 327 /* Just flush everything. Experiments have shown that reducing the
328 * number of bits based on the write domains has little performance
329 * impact.
330 */
331 if (flush_domains) {
332 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
333 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 334 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 335 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4772eaeb
PZ		 336 }
337 if (invalidate_domains) {
338 flags |= PIPE_CONTROL_TLB_INVALIDATE;
339 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
340 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
341 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
342 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
343 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 344 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 345 /*
346 * TLB invalidate requires a post-sync write.
347 */
348 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 349 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 350
add284a3
CW		 351 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
352
f3987631
PZ		 353 /* Workaround: we must issue a pipe_control with CS-stall bit
354 * set before a pipe_control command that has the state cache
355 * invalidate bit set. */
f2cf1fcc 356 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 357 }
358
5fb9de1a 359 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 360 if (ret)
361 return ret;
362
e2f80391
TU		 363 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
364 intel_ring_emit(engine, flags);
365 intel_ring_emit(engine, scratch_addr);
366 intel_ring_emit(engine, 0);
367 intel_ring_advance(engine);
4772eaeb
PZ		 368
369 return 0;
370}
371
884ceace 372static int
f2cf1fcc 373gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 374 u32 flags, u32 scratch_addr)
375{
e2f80391 376 struct intel_engine_cs *engine = req->ring;
884ceace
KG		 377 int ret;
378
5fb9de1a 379 ret = intel_ring_begin(req, 6);
884ceace
KG		 380 if (ret)
381 return ret;
382
e2f80391
TU		 383 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
384 intel_ring_emit(engine, flags);
385 intel_ring_emit(engine, scratch_addr);
386 intel_ring_emit(engine, 0);
387 intel_ring_emit(engine, 0);
388 intel_ring_emit(engine, 0);
389 intel_ring_advance(engine);
884ceace
KG		 390
391 return 0;
392}
393
a5f3d68e 394static int
a84c3ae1 395gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 396 u32 invalidate_domains, u32 flush_domains)
397{
398 u32 flags = 0;
f2cf1fcc 399 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 400 int ret;
a5f3d68e
BW		 401
402 flags |= PIPE_CONTROL_CS_STALL;
403
404 if (flush_domains) {
405 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
406 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 407 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 408 flags |= PIPE_CONTROL_FLUSH_ENABLE;
a5f3d68e
BW		 409 }
410 if (invalidate_domains) {
411 flags |= PIPE_CONTROL_TLB_INVALIDATE;
412 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
413 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
414 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
415 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
416 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
417 flags |= PIPE_CONTROL_QW_WRITE;
418 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 419
420 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 421 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 422 PIPE_CONTROL_CS_STALL |
423 PIPE_CONTROL_STALL_AT_SCOREBOARD,
424 0);
425 if (ret)
426 return ret;
a5f3d68e
BW		 427 }
428
f2cf1fcc 429 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 430}
431
0bc40be8 432static void ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 433 u32 value)
d46eefa2 434{
0bc40be8
TU		 435 struct drm_i915_private *dev_priv = engine->dev->dev_private;
436 I915_WRITE_TAIL(engine, value);
d46eefa2
XH		 437}
438
0bc40be8 439u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
8187a2b7 440{
0bc40be8 441 struct drm_i915_private *dev_priv = engine->dev->dev_private;
50877445 442 u64 acthd;
8187a2b7 443
0bc40be8
TU		 444 if (INTEL_INFO(engine->dev)->gen >= 8)
445 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
446 RING_ACTHD_UDW(engine->mmio_base));
447 else if (INTEL_INFO(engine->dev)->gen >= 4)
448 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
50877445
CW		 449 else
450 acthd = I915_READ(ACTHD);
451
452 return acthd;
8187a2b7
ZN		 453}
454
0bc40be8 455static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
035dc1e0 456{
0bc40be8 457 struct drm_i915_private *dev_priv = engine->dev->dev_private;
035dc1e0
DV		 458 u32 addr;
459
460 addr = dev_priv->status_page_dmah->busaddr;
0bc40be8 461 if (INTEL_INFO(engine->dev)->gen >= 4)
035dc1e0
DV		 462 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
463 I915_WRITE(HWS_PGA, addr);
464}
465
0bc40be8 466static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
af75f269 467{
0bc40be8
TU		 468 struct drm_device *dev = engine->dev;
469 struct drm_i915_private *dev_priv = engine->dev->dev_private;
f0f59a00 470 i915_reg_t mmio;
af75f269
DL		 471
472 /* The ring status page addresses are no longer next to the rest of
473 * the ring registers as of gen7.
474 */
475 if (IS_GEN7(dev)) {
0bc40be8 476 switch (engine->id) {
af75f269
DL		 477 case RCS:
478 mmio = RENDER_HWS_PGA_GEN7;
479 break;
480 case BCS:
481 mmio = BLT_HWS_PGA_GEN7;
482 break;
483 /*
484 * VCS2 actually doesn't exist on Gen7. Only shut up
485 * gcc switch check warning
486 */
487 case VCS2:
488 case VCS:
489 mmio = BSD_HWS_PGA_GEN7;
490 break;
491 case VECS:
492 mmio = VEBOX_HWS_PGA_GEN7;
493 break;
494 }
0bc40be8
TU		 495 } else if (IS_GEN6(engine->dev)) {
496 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
af75f269
DL		 497 } else {
498 /* XXX: gen8 returns to sanity */
0bc40be8 499 mmio = RING_HWS_PGA(engine->mmio_base);
af75f269
DL		 500 }
501
0bc40be8 502 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
af75f269
DL		 503 POSTING_READ(mmio);
504
505 /*
506 * Flush the TLB for this page
507 *
508 * FIXME: These two bits have disappeared on gen8, so a question
509 * arises: do we still need this and if so how should we go about
510 * invalidating the TLB?
511 */
512 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
0bc40be8 513 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
af75f269
DL		 514
515 /* ring should be idle before issuing a sync flush*/
0bc40be8 516 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
af75f269
DL		 517
518 I915_WRITE(reg,
519 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
520 INSTPM_SYNC_FLUSH));
521 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
522 1000))
523 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
0bc40be8 524 engine->name);
af75f269
DL		 525 }
526}
527
0bc40be8 528static bool stop_ring(struct intel_engine_cs *engine)
8187a2b7 529{
0bc40be8 530 struct drm_i915_private *dev_priv = to_i915(engine->dev);
8187a2b7 531
0bc40be8
TU		 532 if (!IS_GEN2(engine->dev)) {
533 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
534 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
535 DRM_ERROR("%s : timed out trying to stop ring\n",
536 engine->name);
9bec9b13
CW		 537 /* Sometimes we observe that the idle flag is not
538 * set even though the ring is empty. So double
539 * check before giving up.
540 */
0bc40be8 541 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
9bec9b13 542 return false;
9991ae78
CW		 543 }
544 }
b7884eb4 545
0bc40be8
TU		 546 I915_WRITE_CTL(engine, 0);
547 I915_WRITE_HEAD(engine, 0);
548 engine->write_tail(engine, 0);
8187a2b7 549
0bc40be8
TU		 550 if (!IS_GEN2(engine->dev)) {
551 (void)I915_READ_CTL(engine);
552 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
9991ae78 553 }
a51435a3 554
0bc40be8 555 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
9991ae78 556}
8187a2b7 557
0bc40be8 558static int init_ring_common(struct intel_engine_cs *engine)
9991ae78 559{
0bc40be8 560 struct drm_device *dev = engine->dev;
9991ae78 561 struct drm_i915_private *dev_priv = dev->dev_private;
0bc40be8 562 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 563 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 564 int ret = 0;
565
59bad947 566 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78 567
0bc40be8 568 if (!stop_ring(engine)) {
9991ae78 569 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 570 DRM_DEBUG_KMS("%s head not reset to zero "
571 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 572 engine->name,
573 I915_READ_CTL(engine),
574 I915_READ_HEAD(engine),
575 I915_READ_TAIL(engine),
576 I915_READ_START(engine));
8187a2b7 577
0bc40be8 578 if (!stop_ring(engine)) {
6fd0d56e
CW		 579 DRM_ERROR("failed to set %s head to zero "
580 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 581 engine->name,
582 I915_READ_CTL(engine),
583 I915_READ_HEAD(engine),
584 I915_READ_TAIL(engine),
585 I915_READ_START(engine));
9991ae78
CW		 586 ret = -EIO;
587 goto out;
6fd0d56e 588 }
8187a2b7
ZN		 589 }
590
9991ae78 591 if (I915_NEED_GFX_HWS(dev))
0bc40be8 592 intel_ring_setup_status_page(engine);
9991ae78 593 else
0bc40be8 594 ring_setup_phys_status_page(engine);
9991ae78 595
ece4a17d 596 /* Enforce ordering by reading HEAD register back */
0bc40be8 597 I915_READ_HEAD(engine);
ece4a17d 598
0d8957c8
DV		 599 /* Initialize the ring. This must happen _after_ we've cleared the ring
600 * registers with the above sequence (the readback of the HEAD registers
601 * also enforces ordering), otherwise the hw might lose the new ring
602 * register values. */
0bc40be8 603 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 604
605 /* WaClearRingBufHeadRegAtInit:ctg,elk */
0bc40be8 606 if (I915_READ_HEAD(engine))
95468892 607 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
0bc40be8
TU		 608 engine->name, I915_READ_HEAD(engine));
609 I915_WRITE_HEAD(engine, 0);
610 (void)I915_READ_HEAD(engine);
95468892 611
0bc40be8 612 I915_WRITE_CTL(engine,
93b0a4e0 613 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 614 | RING_VALID);
8187a2b7 615
8187a2b7 616 /* If the head is still not zero, the ring is dead */
0bc40be8
TU		 617 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
618 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
619 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
e74cfed5 620 DRM_ERROR("%s initialization failed "
48e48a0b 621 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
0bc40be8
TU		 622 engine->name,
623 I915_READ_CTL(engine),
624 I915_READ_CTL(engine) & RING_VALID,
625 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
626 I915_READ_START(engine),
627 (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 628 ret = -EIO;
629 goto out;
8187a2b7
ZN		 630 }
631
ebd0fd4b 632 ringbuf->last_retired_head = -1;
0bc40be8
TU		 633 ringbuf->head = I915_READ_HEAD(engine);
634 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
ebd0fd4b 635 intel_ring_update_space(ringbuf);
1ec14ad3 636
0bc40be8 637 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
50f018df 638
b7884eb4 639out:
59bad947 640 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 641
642 return ret;
8187a2b7
ZN		 643}
644
9b1136d5 645void
0bc40be8 646intel_fini_pipe_control(struct intel_engine_cs *engine)
9b1136d5 647{
0bc40be8 648 struct drm_device *dev = engine->dev;
9b1136d5 649
0bc40be8 650 if (engine->scratch.obj == NULL)
9b1136d5
OM		 651 return;
652
653 if (INTEL_INFO(dev)->gen >= 5) {
0bc40be8
TU		 654 kunmap(sg_page(engine->scratch.obj->pages->sgl));
655 i915_gem_object_ggtt_unpin(engine->scratch.obj);
9b1136d5
OM		 656 }
657
0bc40be8
TU		 658 drm_gem_object_unreference(&engine->scratch.obj->base);
659 engine->scratch.obj = NULL;
9b1136d5
OM		 660}
661
662int
0bc40be8 663intel_init_pipe_control(struct intel_engine_cs *engine)
c6df541c 664{
c6df541c
CW		 665 int ret;
666
0bc40be8 667 WARN_ON(engine->scratch.obj);
c6df541c 668
0bc40be8
TU		 669 engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
670 if (engine->scratch.obj == NULL) {
c6df541c
CW		 671 DRM_ERROR("Failed to allocate seqno page\n");
672 ret = -ENOMEM;
673 goto err;
674 }
e4ffd173 675
0bc40be8
TU		 676 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
677 I915_CACHE_LLC);
a9cc726c
DV		 678 if (ret)
679 goto err_unref;
c6df541c 680
0bc40be8 681 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
c6df541c
CW		 682 if (ret)
683 goto err_unref;
684
0bc40be8
TU		 685 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
686 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
687 if (engine->scratch.cpu_page == NULL) {
56b085a0 688 ret = -ENOMEM;
c6df541c 689 goto err_unpin;
56b085a0 690 }
c6df541c 691
2b1086cc 692 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0bc40be8 693 engine->name, engine->scratch.gtt_offset);
c6df541c
CW		 694 return 0;
695
696err_unpin:
0bc40be8 697 i915_gem_object_ggtt_unpin(engine->scratch.obj);
c6df541c 698err_unref:
0bc40be8 699 drm_gem_object_unreference(&engine->scratch.obj->base);
c6df541c 700err:
c6df541c
CW		 701 return ret;
702}
703
e2be4faf 704static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 705{
7225342a 706 int ret, i;
e2f80391
TU		 707 struct intel_engine_cs *engine = req->ring;
708 struct drm_device *dev = engine->dev;
888b5995 709 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 710 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 711
02235808 712 if (w->count == 0)
7225342a 713 return 0;
888b5995 714
e2f80391 715 engine->gpu_caches_dirty = true;
4866d729 716 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 717 if (ret)
718 return ret;
888b5995 719
5fb9de1a 720 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 721 if (ret)
722 return ret;
723
e2f80391 724 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
7225342a 725 for (i = 0; i < w->count; i++) {
e2f80391
TU		 726 intel_ring_emit_reg(engine, w->reg[i].addr);
727 intel_ring_emit(engine, w->reg[i].value);
7225342a 728 }
e2f80391 729 intel_ring_emit(engine, MI_NOOP);
7225342a 730
e2f80391 731 intel_ring_advance(engine);
7225342a 732
e2f80391 733 engine->gpu_caches_dirty = true;
4866d729 734 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 735 if (ret)
736 return ret;
888b5995 737
7225342a 738 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 739
7225342a 740 return 0;
86d7f238
AS		 741}
742
8753181e 743static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 744{
745 int ret;
746
e2be4faf 747 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 748 if (ret != 0)
749 return ret;
750
be01363f 751 ret = i915_gem_render_state_init(req);
8f0e2b9d 752 if (ret)
e26e1b97 753 return ret;
8f0e2b9d 754
e26e1b97 755 return 0;
8f0e2b9d
DV		 756}
757
7225342a 758static int wa_add(struct drm_i915_private *dev_priv,
f0f59a00
VS		 759 i915_reg_t addr,
760 const u32 mask, const u32 val)
7225342a
MK		 761{
762 const u32 idx = dev_priv->workarounds.count;
763
764 if (WARN_ON(idx >= I915_MAX_WA_REGS))
765 return -ENOSPC;
766
767 dev_priv->workarounds.reg[idx].addr = addr;
768 dev_priv->workarounds.reg[idx].value = val;
769 dev_priv->workarounds.reg[idx].mask = mask;
770
771 dev_priv->workarounds.count++;
772
773 return 0;
86d7f238
AS		 774}
775
ca5a0fbd 776#define WA_REG(addr, mask, val) do { \
cf4b0de6 777 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 778 if (r) \
779 return r; \
ca5a0fbd 780 } while (0)
7225342a
MK		 781
782#define WA_SET_BIT_MASKED(addr, mask) \
26459343 783 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 784
785#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 786 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 787
98533251 788#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 789 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 790
cf4b0de6
DL		 791#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
792#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 793
cf4b0de6 794#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 795
0bc40be8
TU		 796static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
797 i915_reg_t reg)
33136b06 798{
0bc40be8 799 struct drm_i915_private *dev_priv = engine->dev->dev_private;
33136b06 800 struct i915_workarounds *wa = &dev_priv->workarounds;
0bc40be8 801 const uint32_t index = wa->hw_whitelist_count[engine->id];
33136b06
AS		 802
803 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
804 return -EINVAL;
805
0bc40be8 806 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
33136b06 807 i915_mmio_reg_offset(reg));
0bc40be8 808 wa->hw_whitelist_count[engine->id]++;
33136b06
AS		 809
810 return 0;
811}
812
0bc40be8 813static int gen8_init_workarounds(struct intel_engine_cs *engine)
e9a64ada 814{
0bc40be8 815 struct drm_device *dev = engine->dev;
68c6198b
AS		 816 struct drm_i915_private *dev_priv = dev->dev_private;
817
818 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 819
717d84d6
AS		 820 /* WaDisableAsyncFlipPerfMode:bdw,chv */
821 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
822
d0581194
AS		 823 /* WaDisablePartialInstShootdown:bdw,chv */
824 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
825 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
826
a340af58
AS		 827 /* Use Force Non-Coherent whenever executing a 3D context. This is a
828 * workaround for for a possible hang in the unlikely event a TLB
829 * invalidation occurs during a PSD flush.
830 */
831 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 832 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 833 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 834 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 835 HDC_FORCE_NON_COHERENT);
836
6def8fdd
AS		 837 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
838 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
839 * polygons in the same 8x4 pixel/sample area to be processed without
840 * stalling waiting for the earlier ones to write to Hierarchical Z
841 * buffer."
842 *
843 * This optimization is off by default for BDW and CHV; turn it on.
844 */
845 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
846
48404636
AS		 847 /* Wa4x4STCOptimizationDisable:bdw,chv */
848 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
849
7eebcde6
AS		 850 /*
851 * BSpec recommends 8x4 when MSAA is used,
852 * however in practice 16x4 seems fastest.
853 *
854 * Note that PS/WM thread counts depend on the WIZ hashing
855 * disable bit, which we don't touch here, but it's good
856 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
857 */
858 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
859 GEN6_WIZ_HASHING_MASK,
860 GEN6_WIZ_HASHING_16x4);
861
e9a64ada
AS		 862 return 0;
863}
864
0bc40be8 865static int bdw_init_workarounds(struct intel_engine_cs *engine)
86d7f238 866{
e9a64ada 867 int ret;
0bc40be8 868 struct drm_device *dev = engine->dev;
888b5995 869 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 870
0bc40be8 871 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 872 if (ret)
873 return ret;
874
101b376d 875 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 876 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 877
101b376d 878 /* WaDisableDopClockGating:bdw */
7225342a
MK		 879 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
880 DOP_CLOCK_GATING_DISABLE);
86d7f238 881
7225342a
MK		 882 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
883 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 884
7225342a 885 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 886 /* WaForceContextSaveRestoreNonCoherent:bdw */
887 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 888 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 889 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 890
86d7f238
AS		 891 return 0;
892}
893
0bc40be8 894static int chv_init_workarounds(struct intel_engine_cs *engine)
00e1e623 895{
e9a64ada 896 int ret;
0bc40be8 897 struct drm_device *dev = engine->dev;
00e1e623
VS		 898 struct drm_i915_private *dev_priv = dev->dev_private;
899
0bc40be8 900 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 901 if (ret)
902 return ret;
903
00e1e623 904 /* WaDisableThreadStallDopClockGating:chv */
d0581194 905 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 906
d60de81d
KG		 907 /* Improve HiZ throughput on CHV. */
908 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
909
7225342a
MK		 910 return 0;
911}
912
0bc40be8 913static int gen9_init_workarounds(struct intel_engine_cs *engine)
3b106531 914{
0bc40be8 915 struct drm_device *dev = engine->dev;
ab0dfafe 916 struct drm_i915_private *dev_priv = dev->dev_private;
8ea6f892 917 uint32_t tmp;
e0f3fa09 918 int ret;
ab0dfafe 919
9c4cbf82
MK		 920 /* WaEnableLbsSlaRetryTimerDecrement:skl */
921 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
922 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
923
924 /* WaDisableKillLogic:bxt,skl */
925 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
926 ECOCHK_DIS_TLB);
927
b0e6f6d4 928 /* WaDisablePartialInstShootdown:skl,bxt */
ab0dfafe
HN		 929 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
931
a119a6e6 932 /* Syncing dependencies between camera and graphics:skl,bxt */
8424171e
NH		 933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
935
e87a005d
JN		 936 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
937 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
938 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
a86eb582
DL		 939 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
940 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 941
e87a005d
JN		 942 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
943 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
944 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
183c6dac
DL		 945 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
946 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 947 /*
948 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
949 * but we do that in per ctx batchbuffer as there is an issue
950 * with this register not getting restored on ctx restore
951 */
183c6dac
DL		 952 }
953
e87a005d
JN		 954 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
955 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
cac23df4
NH		 956 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
957 GEN9_ENABLE_YV12_BUGFIX);
cac23df4 958
5068368c 959 /* Wa4x4STCOptimizationDisable:skl,bxt */
27160c96 960 /* WaDisablePartialResolveInVc:skl,bxt */
60294683
AS		 961 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
962 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 963
16be17af 964 /* WaCcsTlbPrefetchDisable:skl,bxt */
e2db7071
DL		 965 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
966 GEN9_CCS_TLB_PREFETCH_ENABLE);
967
5a2ae95e 968 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
e87a005d
JN		 969 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
970 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
38a39a7b
BW		 971 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
972 PIXEL_MASK_CAMMING_DISABLE);
973
8ea6f892
ID		 974 /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
975 tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
e87a005d
JN		 976 if (IS_SKL_REVID(dev, SKL_REVID_F0, SKL_REVID_F0) ||
977 IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
8ea6f892
ID		 978 tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
979 WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
980
8c761609 981 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
e87a005d 982 if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
8c761609
AS		 983 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
984 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 985
6b6d5626
RB		 986 /* WaDisableSTUnitPowerOptimization:skl,bxt */
987 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
988
6ecf56ae
AS		 989 /* WaOCLCoherentLineFlush:skl,bxt */
990 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
991 GEN8_LQSC_FLUSH_COHERENT_LINES));
992
e0f3fa09 993 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt */
0bc40be8 994 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
e0f3fa09
AS		 995 if (ret)
996 return ret;
997
3669ab61 998 /* WaAllowUMDToModifyHDCChicken1:skl,bxt */
0bc40be8 999 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
3669ab61
AS		 1000 if (ret)
1001 return ret;
1002
3b106531
HN		 1003 return 0;
1004}
1005
0bc40be8 1006static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
b7668791 1007{
0bc40be8 1008 struct drm_device *dev = engine->dev;
b7668791
DL		 1009 struct drm_i915_private *dev_priv = dev->dev_private;
1010 u8 vals[3] = { 0, 0, 0 };
1011 unsigned int i;
1012
1013 for (i = 0; i < 3; i++) {
1014 u8 ss;
1015
1016 /*
1017 * Only consider slices where one, and only one, subslice has 7
1018 * EUs
1019 */
a4d8a0fe 1020 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
b7668791
DL		 1021 continue;
1022
1023 /*
1024 * subslice_7eu[i] != 0 (because of the check above) and
1025 * ss_max == 4 (maximum number of subslices possible per slice)
1026 *
1027 * -> 0 <= ss <= 3;
1028 */
1029 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1030 vals[i] = 3 - ss;
1031 }
1032
1033 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1034 return 0;
1035
1036 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1037 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1038 GEN9_IZ_HASHING_MASK(2) |
1039 GEN9_IZ_HASHING_MASK(1) |
1040 GEN9_IZ_HASHING_MASK(0),
1041 GEN9_IZ_HASHING(2, vals[2]) |
1042 GEN9_IZ_HASHING(1, vals[1]) |
1043 GEN9_IZ_HASHING(0, vals[0]));
1044
1045 return 0;
1046}
1047
0bc40be8 1048static int skl_init_workarounds(struct intel_engine_cs *engine)
8d205494 1049{
aa0011a8 1050 int ret;
0bc40be8 1051 struct drm_device *dev = engine->dev;
d0bbbc4f
DL		 1052 struct drm_i915_private *dev_priv = dev->dev_private;
1053
0bc40be8 1054 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1055 if (ret)
1056 return ret;
8d205494 1057
a78536e7
AS		 1058 /*
1059 * Actual WA is to disable percontext preemption granularity control
1060 * until D0 which is the default case so this is equivalent to
1061 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1062 */
1063 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1064 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1065 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1066 }
1067
e87a005d 1068 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
9c4cbf82
MK		 1069 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1070 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1071 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1072 }
1073
1074 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1075 * involving this register should also be added to WA batch as required.
1076 */
e87a005d 1077 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
9c4cbf82
MK		 1078 /* WaDisableLSQCROPERFforOCL:skl */
1079 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1080 GEN8_LQSC_RO_PERF_DIS);
1081
1082 /* WaEnableGapsTsvCreditFix:skl */
e87a005d 1083 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1084 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1085 GEN9_GAPS_TSV_CREDIT_DISABLE));
1086 }
1087
d0bbbc4f 1088 /* WaDisablePowerCompilerClockGating:skl */
e87a005d 1089 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1090 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1091 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1092
e238659d 1093 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) {
b62adbd1
NH		 1094 /*
1095 *Use Force Non-Coherent whenever executing a 3D context. This
1096 * is a workaround for a possible hang in the unlikely event
1097 * a TLB invalidation occurs during a PSD flush.
1098 */
1099 /* WaForceEnableNonCoherent:skl */
1100 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1101 HDC_FORCE_NON_COHERENT);
e238659d
MK		 1102
1103 /* WaDisableHDCInvalidation:skl */
1104 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
1105 BDW_DISABLE_HDC_INVALIDATION);
b62adbd1
NH		 1106 }
1107
e87a005d
JN		 1108 /* WaBarrierPerformanceFixDisable:skl */
1109 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1110 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1111 HDC_FENCE_DEST_SLM_DISABLE |
1112 HDC_BARRIER_PERFORMANCE_DISABLE);
1113
9bd9dfb4 1114 /* WaDisableSbeCacheDispatchPortSharing:skl */
e87a005d 1115 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1116 WA_SET_BIT_MASKED(
1117 GEN7_HALF_SLICE_CHICKEN1,
1118 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1119
6107497e 1120 /* WaDisableLSQCROPERFforOCL:skl */
0bc40be8 1121 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
6107497e
AS		 1122 if (ret)
1123 return ret;
1124
0bc40be8 1125 return skl_tune_iz_hashing(engine);
7225342a
MK		 1126}
1127
0bc40be8 1128static int bxt_init_workarounds(struct intel_engine_cs *engine)
cae0437f 1129{
aa0011a8 1130 int ret;
0bc40be8 1131 struct drm_device *dev = engine->dev;
dfb601e6
NH		 1132 struct drm_i915_private *dev_priv = dev->dev_private;
1133
0bc40be8 1134 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1135 if (ret)
1136 return ret;
cae0437f 1137
9c4cbf82
MK		 1138 /* WaStoreMultiplePTEenable:bxt */
1139 /* This is a requirement according to Hardware specification */
cbdc12a9 1140 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
9c4cbf82
MK		 1141 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1142
1143 /* WaSetClckGatingDisableMedia:bxt */
cbdc12a9 1144 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
9c4cbf82
MK		 1145 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1146 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1147 }
1148
dfb601e6
NH		 1149 /* WaDisableThreadStallDopClockGating:bxt */
1150 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1151 STALL_DOP_GATING_DISABLE);
1152
983b4b9d 1153 /* WaDisableSbeCacheDispatchPortSharing:bxt */
e87a005d 1154 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1155 WA_SET_BIT_MASKED(
1156 GEN7_HALF_SLICE_CHICKEN1,
1157 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1158 }
1159
2c8580e4
AS		 1160 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1161 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1162 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
a786d53a 1163 /* WaDisableLSQCROPERFforOCL:bxt */
2c8580e4 1164 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
0bc40be8 1165 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
2c8580e4
AS		 1166 if (ret)
1167 return ret;
a786d53a 1168
0bc40be8 1169 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
a786d53a
AS		 1170 if (ret)
1171 return ret;
2c8580e4
AS		 1172 }
1173
cae0437f
NH		 1174 return 0;
1175}
1176
0bc40be8 1177int init_workarounds_ring(struct intel_engine_cs *engine)
7225342a 1178{
0bc40be8 1179 struct drm_device *dev = engine->dev;
7225342a
MK		 1180 struct drm_i915_private *dev_priv = dev->dev_private;
1181
0bc40be8 1182 WARN_ON(engine->id != RCS);
7225342a
MK		 1183
1184 dev_priv->workarounds.count = 0;
33136b06 1185 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
7225342a
MK		 1186
1187 if (IS_BROADWELL(dev))
0bc40be8 1188 return bdw_init_workarounds(engine);
7225342a
MK		 1189
1190 if (IS_CHERRYVIEW(dev))
0bc40be8 1191 return chv_init_workarounds(engine);
00e1e623 1192
8d205494 1193 if (IS_SKYLAKE(dev))
0bc40be8 1194 return skl_init_workarounds(engine);
cae0437f
NH		 1195
1196 if (IS_BROXTON(dev))
0bc40be8 1197 return bxt_init_workarounds(engine);
3b106531 1198
00e1e623
VS		 1199 return 0;
1200}
1201
0bc40be8 1202static int init_render_ring(struct intel_engine_cs *engine)
8187a2b7 1203{
0bc40be8 1204 struct drm_device *dev = engine->dev;
1ec14ad3 1205 struct drm_i915_private *dev_priv = dev->dev_private;
0bc40be8 1206 int ret = init_ring_common(engine);
9c33baa6
KZ		 1207 if (ret)
1208 return ret;
a69ffdbf 1209
61a563a2
AG		 1210 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1211 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1212 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1213
1214 /* We need to disable the AsyncFlip performance optimisations in order
1215 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1216 * programmed to '1' on all products.
8693a824 1217 *
2441f877 1218 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1219 */
2441f877 1220 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1221 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1222
f05bb0c7 1223 /* Required for the hardware to program scanline values for waiting */
01fa0302 1224 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1225 if (INTEL_INFO(dev)->gen == 6)
1226 I915_WRITE(GFX_MODE,
aa83e30d 1227 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1228
01fa0302 1229 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1230 if (IS_GEN7(dev))
1231 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1232 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1233 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1234
5e13a0c5 1235 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1236 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1237 * "If this bit is set, STCunit will have LRA as replacement
1238 * policy. [...] This bit must be reset. LRA replacement
1239 * policy is not supported."
1240 */
1241 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1242 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1243 }
1244
9cc83020 1245 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1246 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1247
040d2baa 1248 if (HAS_L3_DPF(dev))
0bc40be8 1249 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
15b9f80e 1250
0bc40be8 1251 return init_workarounds_ring(engine);
8187a2b7
ZN		 1252}
1253
0bc40be8 1254static void render_ring_cleanup(struct intel_engine_cs *engine)
c6df541c 1255{
0bc40be8 1256 struct drm_device *dev = engine->dev;
3e78998a
BW		 1257 struct drm_i915_private *dev_priv = dev->dev_private;
1258
1259 if (dev_priv->semaphore_obj) {
1260 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1261 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1262 dev_priv->semaphore_obj = NULL;
1263 }
b45305fc 1264
0bc40be8 1265 intel_fini_pipe_control(engine);
c6df541c
CW		 1266}
1267
f7169687 1268static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1269 unsigned int num_dwords)
1270{
1271#define MBOX_UPDATE_DWORDS 8
f7169687 1272 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1273 struct drm_device *dev = signaller->dev;
1274 struct drm_i915_private *dev_priv = dev->dev_private;
1275 struct intel_engine_cs *waiter;
1276 int i, ret, num_rings;
1277
1278 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1279 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1280#undef MBOX_UPDATE_DWORDS
1281
5fb9de1a 1282 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1283 if (ret)
1284 return ret;
1285
1286 for_each_ring(waiter, dev_priv, i) {
6259cead 1287 u32 seqno;
3e78998a
BW		 1288 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1289 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1290 continue;
1291
f7169687 1292 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1293 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1294 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1295 PIPE_CONTROL_QW_WRITE |
1296 PIPE_CONTROL_FLUSH_ENABLE);
1297 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1298 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1299 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1300 intel_ring_emit(signaller, 0);
1301 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1302 MI_SEMAPHORE_TARGET(waiter->id));
1303 intel_ring_emit(signaller, 0);
1304 }
1305
1306 return 0;
1307}
1308
f7169687 1309static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1310 unsigned int num_dwords)
1311{
1312#define MBOX_UPDATE_DWORDS 6
f7169687 1313 struct intel_engine_cs *signaller = signaller_req->ring;
3e78998a
BW		 1314 struct drm_device *dev = signaller->dev;
1315 struct drm_i915_private *dev_priv = dev->dev_private;
1316 struct intel_engine_cs *waiter;
1317 int i, ret, num_rings;
1318
1319 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1320 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1321#undef MBOX_UPDATE_DWORDS
1322
5fb9de1a 1323 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1324 if (ret)
1325 return ret;
1326
1327 for_each_ring(waiter, dev_priv, i) {
6259cead 1328 u32 seqno;
3e78998a
BW		 1329 u64 gtt_offset = signaller->semaphore.signal_ggtt[i];
1330 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1331 continue;
1332
f7169687 1333 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1334 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1335 MI_FLUSH_DW_OP_STOREDW);
1336 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1337 MI_FLUSH_DW_USE_GTT);
1338 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1339 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1340 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
1341 MI_SEMAPHORE_TARGET(waiter->id));
1342 intel_ring_emit(signaller, 0);
1343 }
1344
1345 return 0;
1346}
1347
f7169687 1348static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1349 unsigned int num_dwords)
1ec14ad3 1350{
f7169687 1351 struct intel_engine_cs *signaller = signaller_req->ring;
024a43e1
BW		 1352 struct drm_device *dev = signaller->dev;
1353 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1354 struct intel_engine_cs *useless;
a1444b79 1355 int i, ret, num_rings;
78325f2d 1356
a1444b79
BW		 1357#define MBOX_UPDATE_DWORDS 3
1358 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1359 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1360#undef MBOX_UPDATE_DWORDS
024a43e1 1361
5fb9de1a 1362 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1363 if (ret)
1364 return ret;
024a43e1 1365
78325f2d 1366 for_each_ring(useless, dev_priv, i) {
f0f59a00
VS		 1367 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[i];
1368
1369 if (i915_mmio_reg_valid(mbox_reg)) {
f7169687 1370 u32 seqno = i915_gem_request_get_seqno(signaller_req);
f0f59a00 1371
78325f2d 1372 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
f92a9162 1373 intel_ring_emit_reg(signaller, mbox_reg);
6259cead 1374 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1375 }
1376 }
024a43e1 1377
a1444b79
BW		 1378 /* If num_dwords was rounded, make sure the tail pointer is correct */
1379 if (num_rings % 2 == 0)
1380 intel_ring_emit(signaller, MI_NOOP);
1381
024a43e1 1382 return 0;
1ec14ad3
CW		 1383}
1384
c8c99b0f
BW		 1385/**
1386 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1387 *
1388 * @request - request to write to the ring
c8c99b0f
BW		 1389 *
1390 * Update the mailbox registers in the *other* rings with the current seqno.
1391 * This acts like a signal in the canonical semaphore.
1392 */
1ec14ad3 1393static int
ee044a88 1394gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1395{
e2f80391 1396 struct intel_engine_cs *engine = req->ring;
024a43e1 1397 int ret;
52ed2325 1398
e2f80391
TU		 1399 if (engine->semaphore.signal)
1400 ret = engine->semaphore.signal(req, 4);
707d9cf9 1401 else
5fb9de1a 1402 ret = intel_ring_begin(req, 4);
707d9cf9 1403
1ec14ad3
CW		 1404 if (ret)
1405 return ret;
1406
e2f80391
TU		 1407 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1408 intel_ring_emit(engine,
1409 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1410 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1411 intel_ring_emit(engine, MI_USER_INTERRUPT);
1412 __intel_ring_advance(engine);
1ec14ad3 1413
1ec14ad3
CW		 1414 return 0;
1415}
1416
f72b3435
MK		 1417static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1418 u32 seqno)
1419{
1420 struct drm_i915_private *dev_priv = dev->dev_private;
1421 return dev_priv->last_seqno < seqno;
1422}
1423
c8c99b0f
BW		 1424/**
1425 * intel_ring_sync - sync the waiter to the signaller on seqno
1426 *
1427 * @waiter - ring that is waiting
1428 * @signaller - ring which has, or will signal
1429 * @seqno - seqno which the waiter will block on
1430 */
5ee426ca
BW		 1431
1432static int
599d924c 1433gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1434 struct intel_engine_cs *signaller,
1435 u32 seqno)
1436{
599d924c 1437 struct intel_engine_cs *waiter = waiter_req->ring;
5ee426ca
BW		 1438 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1439 int ret;
1440
5fb9de1a 1441 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1442 if (ret)
1443 return ret;
1444
1445 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1446 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1447 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1448 MI_SEMAPHORE_SAD_GTE_SDD);
1449 intel_ring_emit(waiter, seqno);
1450 intel_ring_emit(waiter,
1451 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1452 intel_ring_emit(waiter,
1453 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1454 intel_ring_advance(waiter);
1455 return 0;
1456}
1457
c8c99b0f 1458static int
599d924c 1459gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1460 struct intel_engine_cs *signaller,
686cb5f9 1461 u32 seqno)
1ec14ad3 1462{
599d924c 1463 struct intel_engine_cs *waiter = waiter_req->ring;
c8c99b0f
BW		 1464 u32 dw1 = MI_SEMAPHORE_MBOX |
1465 MI_SEMAPHORE_COMPARE |
1466 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1467 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1468 int ret;
1ec14ad3 1469
1500f7ea
BW		 1470 /* Throughout all of the GEM code, seqno passed implies our current
1471 * seqno is >= the last seqno executed. However for hardware the
1472 * comparison is strictly greater than.
1473 */
1474 seqno -= 1;
1475
ebc348b2 1476 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1477
5fb9de1a 1478 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1479 if (ret)
1480 return ret;
1481
f72b3435
MK		 1482 /* If seqno wrap happened, omit the wait with no-ops */
1483 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1484 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1485 intel_ring_emit(waiter, seqno);
1486 intel_ring_emit(waiter, 0);
1487 intel_ring_emit(waiter, MI_NOOP);
1488 } else {
1489 intel_ring_emit(waiter, MI_NOOP);
1490 intel_ring_emit(waiter, MI_NOOP);
1491 intel_ring_emit(waiter, MI_NOOP);
1492 intel_ring_emit(waiter, MI_NOOP);
1493 }
c8c99b0f 1494 intel_ring_advance(waiter);
1ec14ad3
CW		 1495
1496 return 0;
1497}
1498
c6df541c
CW		 1499#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1500do { \
fcbc34e4
KG		 1501 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1502 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1503 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1504 intel_ring_emit(ring__, 0); \
1505 intel_ring_emit(ring__, 0); \
1506} while (0)
1507
1508static int
ee044a88 1509pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1510{
e2f80391
TU		 1511 struct intel_engine_cs *engine = req->ring;
1512 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1513 int ret;
1514
1515 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1516 * incoherent with writes to memory, i.e. completely fubar,
1517 * so we need to use PIPE_NOTIFY instead.
1518 *
1519 * However, we also need to workaround the qword write
1520 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1521 * memory before requesting an interrupt.
1522 */
5fb9de1a 1523 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1524 if (ret)
1525 return ret;
1526
e2f80391
TU		 1527 intel_ring_emit(engine,
1528 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1529 PIPE_CONTROL_WRITE_FLUSH |
1530 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
e2f80391
TU		 1531 intel_ring_emit(engine,
1532 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1533 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1534 intel_ring_emit(engine, 0);
1535 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1536 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
e2f80391 1537 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1538 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1539 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1540 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1541 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1542 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1543 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1544 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1545 PIPE_CONTROL_FLUSH(engine, scratch_addr);
a71d8d94 1546
e2f80391
TU		 1547 intel_ring_emit(engine,
1548 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1549 PIPE_CONTROL_WRITE_FLUSH |
1550 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1551 PIPE_CONTROL_NOTIFY);
e2f80391
TU		 1552 intel_ring_emit(engine,
1553 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1554 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1555 intel_ring_emit(engine, 0);
1556 __intel_ring_advance(engine);
c6df541c 1557
c6df541c
CW		 1558 return 0;
1559}
1560
4cd53c0c 1561static u32
0bc40be8 1562gen6_ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
4cd53c0c 1563{
4cd53c0c
DV		 1564 /* Workaround to force correct ordering between irq and seqno writes on
1565 * ivb (and maybe also on snb) by reading from a CS register (like
1566 * ACTHD) before reading the status page. */
50877445 1567 if (!lazy_coherency) {
0bc40be8
TU		 1568 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1569 POSTING_READ(RING_ACTHD(engine->mmio_base));
50877445
CW		 1570 }
1571
0bc40be8 1572 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
4cd53c0c
DV		 1573}
1574
8187a2b7 1575static u32
0bc40be8 1576ring_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
8187a2b7 1577{
0bc40be8 1578 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1ec14ad3
CW		 1579}
1580
b70ec5bf 1581static void
0bc40be8 1582ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1583{
0bc40be8 1584 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
b70ec5bf
MK		 1585}
1586
c6df541c 1587static u32
0bc40be8 1588pc_render_get_seqno(struct intel_engine_cs *engine, bool lazy_coherency)
c6df541c 1589{
0bc40be8 1590 return engine->scratch.cpu_page[0];
c6df541c
CW		 1591}
1592
b70ec5bf 1593static void
0bc40be8 1594pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1595{
0bc40be8 1596 engine->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1597}
1598
e48d8634 1599static bool
0bc40be8 1600gen5_ring_get_irq(struct intel_engine_cs *engine)
e48d8634 1601{
0bc40be8 1602 struct drm_device *dev = engine->dev;
4640c4ff 1603 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1604 unsigned long flags;
e48d8634 1605
7cd512f1 1606 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1607 return false;
1608
7338aefa 1609 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1610 if (engine->irq_refcount++ == 0)
1611 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1612 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1613
1614 return true;
1615}
1616
1617static void
0bc40be8 1618gen5_ring_put_irq(struct intel_engine_cs *engine)
e48d8634 1619{
0bc40be8 1620 struct drm_device *dev = engine->dev;
4640c4ff 1621 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1622 unsigned long flags;
e48d8634 1623
7338aefa 1624 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1625 if (--engine->irq_refcount == 0)
1626 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1627 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1628}
1629
b13c2b96 1630static bool
0bc40be8 1631i9xx_ring_get_irq(struct intel_engine_cs *engine)
62fdfeaf 1632{
0bc40be8 1633 struct drm_device *dev = engine->dev;
4640c4ff 1634 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1635 unsigned long flags;
62fdfeaf 1636
7cd512f1 1637 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1638 return false;
1639
7338aefa 1640 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1641 if (engine->irq_refcount++ == 0) {
1642 dev_priv->irq_mask &= ~engine->irq_enable_mask;
f637fde4
DV		 1643 I915_WRITE(IMR, dev_priv->irq_mask);
1644 POSTING_READ(IMR);
1645 }
7338aefa 1646 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1647
1648 return true;
62fdfeaf
EA		 1649}
1650
8187a2b7 1651static void
0bc40be8 1652i9xx_ring_put_irq(struct intel_engine_cs *engine)
62fdfeaf 1653{
0bc40be8 1654 struct drm_device *dev = engine->dev;
4640c4ff 1655 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1656 unsigned long flags;
62fdfeaf 1657
7338aefa 1658 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1659 if (--engine->irq_refcount == 0) {
1660 dev_priv->irq_mask |= engine->irq_enable_mask;
f637fde4
DV		 1661 I915_WRITE(IMR, dev_priv->irq_mask);
1662 POSTING_READ(IMR);
1663 }
7338aefa 1664 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1665}
1666
c2798b19 1667static bool
0bc40be8 1668i8xx_ring_get_irq(struct intel_engine_cs *engine)
c2798b19 1669{
0bc40be8 1670 struct drm_device *dev = engine->dev;
4640c4ff 1671 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1672 unsigned long flags;
c2798b19 1673
7cd512f1 1674 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1675 return false;
1676
7338aefa 1677 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1678 if (engine->irq_refcount++ == 0) {
1679 dev_priv->irq_mask &= ~engine->irq_enable_mask;
c2798b19
CW		 1680 I915_WRITE16(IMR, dev_priv->irq_mask);
1681 POSTING_READ16(IMR);
1682 }
7338aefa 1683 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1684
1685 return true;
1686}
1687
1688static void
0bc40be8 1689i8xx_ring_put_irq(struct intel_engine_cs *engine)
c2798b19 1690{
0bc40be8 1691 struct drm_device *dev = engine->dev;
4640c4ff 1692 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1693 unsigned long flags;
c2798b19 1694
7338aefa 1695 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1696 if (--engine->irq_refcount == 0) {
1697 dev_priv->irq_mask |= engine->irq_enable_mask;
c2798b19
CW		 1698 I915_WRITE16(IMR, dev_priv->irq_mask);
1699 POSTING_READ16(IMR);
1700 }
7338aefa 1701 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1702}
1703
b72f3acb 1704static int
a84c3ae1 1705bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1706 u32 invalidate_domains,
1707 u32 flush_domains)
d1b851fc 1708{
e2f80391 1709 struct intel_engine_cs *engine = req->ring;
b72f3acb
CW		 1710 int ret;
1711
5fb9de1a 1712 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1713 if (ret)
1714 return ret;
1715
e2f80391
TU		 1716 intel_ring_emit(engine, MI_FLUSH);
1717 intel_ring_emit(engine, MI_NOOP);
1718 intel_ring_advance(engine);
b72f3acb 1719 return 0;
d1b851fc
ZN		 1720}
1721
3cce469c 1722static int
ee044a88 1723i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1724{
e2f80391 1725 struct intel_engine_cs *engine = req->ring;
3cce469c
CW		 1726 int ret;
1727
5fb9de1a 1728 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1729 if (ret)
1730 return ret;
6f392d54 1731
e2f80391
TU		 1732 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1733 intel_ring_emit(engine,
1734 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1735 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1736 intel_ring_emit(engine, MI_USER_INTERRUPT);
1737 __intel_ring_advance(engine);
d1b851fc 1738
3cce469c 1739 return 0;
d1b851fc
ZN		 1740}
1741
0f46832f 1742static bool
0bc40be8 1743gen6_ring_get_irq(struct intel_engine_cs *engine)
0f46832f 1744{
0bc40be8 1745 struct drm_device *dev = engine->dev;
4640c4ff 1746 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1747 unsigned long flags;
0f46832f 1748
7cd512f1
DV		 1749 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1750 return false;
0f46832f 1751
7338aefa 1752 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1753 if (engine->irq_refcount++ == 0) {
1754 if (HAS_L3_DPF(dev) && engine->id == RCS)
1755 I915_WRITE_IMR(engine,
1756 ~(engine->irq_enable_mask |
35a85ac6 1757 GT_PARITY_ERROR(dev)));
15b9f80e 1758 else
0bc40be8
TU		 1759 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1760 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
0f46832f 1761 }
7338aefa 1762 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1763
1764 return true;
1765}
1766
1767static void
0bc40be8 1768gen6_ring_put_irq(struct intel_engine_cs *engine)
0f46832f 1769{
0bc40be8 1770 struct drm_device *dev = engine->dev;
4640c4ff 1771 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1772 unsigned long flags;
0f46832f 1773
7338aefa 1774 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1775 if (--engine->irq_refcount == 0) {
1776 if (HAS_L3_DPF(dev) && engine->id == RCS)
1777 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
15b9f80e 1778 else
0bc40be8
TU		 1779 I915_WRITE_IMR(engine, ~0);
1780 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1ec14ad3 1781 }
7338aefa 1782 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1783}
1784
a19d2933 1785static bool
0bc40be8 1786hsw_vebox_get_irq(struct intel_engine_cs *engine)
a19d2933 1787{
0bc40be8 1788 struct drm_device *dev = engine->dev;
a19d2933
BW		 1789 struct drm_i915_private *dev_priv = dev->dev_private;
1790 unsigned long flags;
1791
7cd512f1 1792 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1793 return false;
1794
59cdb63d 1795 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1796 if (engine->irq_refcount++ == 0) {
1797 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1798 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1799 }
59cdb63d 1800 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1801
1802 return true;
1803}
1804
1805static void
0bc40be8 1806hsw_vebox_put_irq(struct intel_engine_cs *engine)
a19d2933 1807{
0bc40be8 1808 struct drm_device *dev = engine->dev;
a19d2933
BW		 1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 unsigned long flags;
1811
59cdb63d 1812 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1813 if (--engine->irq_refcount == 0) {
1814 I915_WRITE_IMR(engine, ~0);
1815 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1816 }
59cdb63d 1817 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1818}
1819
abd58f01 1820static bool
0bc40be8 1821gen8_ring_get_irq(struct intel_engine_cs *engine)
abd58f01 1822{
0bc40be8 1823 struct drm_device *dev = engine->dev;
abd58f01
BW		 1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 unsigned long flags;
1826
7cd512f1 1827 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1828 return false;
1829
1830 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1831 if (engine->irq_refcount++ == 0) {
1832 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1833 I915_WRITE_IMR(engine,
1834 ~(engine->irq_enable_mask |
abd58f01
BW		 1835 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1836 } else {
0bc40be8 1837 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
abd58f01 1838 }
0bc40be8 1839 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1840 }
1841 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1842
1843 return true;
1844}
1845
1846static void
0bc40be8 1847gen8_ring_put_irq(struct intel_engine_cs *engine)
abd58f01 1848{
0bc40be8 1849 struct drm_device *dev = engine->dev;
abd58f01
BW		 1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 unsigned long flags;
1852
1853 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1854 if (--engine->irq_refcount == 0) {
1855 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1856 I915_WRITE_IMR(engine,
abd58f01
BW		 1857 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1858 } else {
0bc40be8 1859 I915_WRITE_IMR(engine, ~0);
abd58f01 1860 }
0bc40be8 1861 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1862 }
1863 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1864}
1865
d1b851fc 1866static int
53fddaf7 1867i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1868 u64 offset, u32 length,
8e004efc 1869 unsigned dispatch_flags)
d1b851fc 1870{
e2f80391 1871 struct intel_engine_cs *engine = req->ring;
e1f99ce6 1872 int ret;
78501eac 1873
5fb9de1a 1874 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1875 if (ret)
1876 return ret;
1877
e2f80391 1878 intel_ring_emit(engine,
65f56876
CW		 1879 MI_BATCH_BUFFER_START |
1880 MI_BATCH_GTT |
8e004efc
JH		 1881 (dispatch_flags & I915_DISPATCH_SECURE ?
1882 0 : MI_BATCH_NON_SECURE_I965));
e2f80391
TU		 1883 intel_ring_emit(engine, offset);
1884 intel_ring_advance(engine);
78501eac 1885
d1b851fc
ZN		 1886 return 0;
1887}
1888
b45305fc
DV		 1889/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1890#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1891#define I830_TLB_ENTRIES (2)
1892#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1893static int
53fddaf7 1894i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1895 u64 offset, u32 len,
1896 unsigned dispatch_flags)
62fdfeaf 1897{
e2f80391
TU		 1898 struct intel_engine_cs *engine = req->ring;
1899 u32 cs_offset = engine->scratch.gtt_offset;
c4e7a414 1900 int ret;
62fdfeaf 1901
5fb9de1a 1902 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1903 if (ret)
1904 return ret;
62fdfeaf 1905
c4d69da1 1906 /* Evict the invalid PTE TLBs */
e2f80391
TU		 1907 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1908 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1909 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1910 intel_ring_emit(engine, cs_offset);
1911 intel_ring_emit(engine, 0xdeadbeef);
1912 intel_ring_emit(engine, MI_NOOP);
1913 intel_ring_advance(engine);
b45305fc 1914
8e004efc 1915 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1916 if (len > I830_BATCH_LIMIT)
1917 return -ENOSPC;
1918
5fb9de1a 1919 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1920 if (ret)
1921 return ret;
c4d69da1
CW		 1922
1923 /* Blit the batch (which has now all relocs applied) to the
1924 * stable batch scratch bo area (so that the CS never
1925 * stumbles over its tlb invalidation bug) ...
1926 */
e2f80391
TU		 1927 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1928 intel_ring_emit(engine,
1929 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1930 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1931 intel_ring_emit(engine, cs_offset);
1932 intel_ring_emit(engine, 4096);
1933 intel_ring_emit(engine, offset);
1934
1935 intel_ring_emit(engine, MI_FLUSH);
1936 intel_ring_emit(engine, MI_NOOP);
1937 intel_ring_advance(engine);
b45305fc
DV		 1938
1939 /* ... and execute it. */
c4d69da1 1940 offset = cs_offset;
b45305fc 1941 }
e1f99ce6 1942
9d611c03 1943 ret = intel_ring_begin(req, 2);
c4d69da1
CW		 1944 if (ret)
1945 return ret;
1946
e2f80391
TU		 1947 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1948 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1949 0 : MI_BATCH_NON_SECURE));
1950 intel_ring_advance(engine);
c4d69da1 1951
fb3256da
DV		 1952 return 0;
1953}
1954
1955static int
53fddaf7 1956i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1957 u64 offset, u32 len,
8e004efc 1958 unsigned dispatch_flags)
fb3256da 1959{
e2f80391 1960 struct intel_engine_cs *engine = req->ring;
fb3256da
DV		 1961 int ret;
1962
5fb9de1a 1963 ret = intel_ring_begin(req, 2);
fb3256da
DV		 1964 if (ret)
1965 return ret;
1966
e2f80391
TU		 1967 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1968 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1969 0 : MI_BATCH_NON_SECURE));
1970 intel_ring_advance(engine);
62fdfeaf 1971
62fdfeaf
EA		 1972 return 0;
1973}
1974
0bc40be8 1975static void cleanup_phys_status_page(struct intel_engine_cs *engine)
7d3fdfff 1976{
0bc40be8 1977 struct drm_i915_private *dev_priv = to_i915(engine->dev);
7d3fdfff
VS		 1978
1979 if (!dev_priv->status_page_dmah)
1980 return;
1981
0bc40be8
TU		 1982 drm_pci_free(engine->dev, dev_priv->status_page_dmah);
1983 engine->status_page.page_addr = NULL;
7d3fdfff
VS		 1984}
1985
0bc40be8 1986static void cleanup_status_page(struct intel_engine_cs *engine)
62fdfeaf 1987{
05394f39 1988 struct drm_i915_gem_object *obj;
62fdfeaf 1989
0bc40be8 1990 obj = engine->status_page.obj;
8187a2b7 1991 if (obj == NULL)
62fdfeaf 1992 return;
62fdfeaf 1993
9da3da66 1994 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 1995 i915_gem_object_ggtt_unpin(obj);
05394f39 1996 drm_gem_object_unreference(&obj->base);
0bc40be8 1997 engine->status_page.obj = NULL;
62fdfeaf
EA		 1998}
1999
0bc40be8 2000static int init_status_page(struct intel_engine_cs *engine)
62fdfeaf 2001{
0bc40be8 2002 struct drm_i915_gem_object *obj = engine->status_page.obj;
62fdfeaf 2003
7d3fdfff 2004 if (obj == NULL) {
1f767e02 2005 unsigned flags;
e3efda49 2006 int ret;
e4ffd173 2007
0bc40be8 2008 obj = i915_gem_alloc_object(engine->dev, 4096);
e3efda49
CW		 2009 if (obj == NULL) {
2010 DRM_ERROR("Failed to allocate status page\n");
2011 return -ENOMEM;
2012 }
62fdfeaf 2013
e3efda49
CW		 2014 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2015 if (ret)
2016 goto err_unref;
2017
1f767e02 2018 flags = 0;
0bc40be8 2019 if (!HAS_LLC(engine->dev))
1f767e02
CW		 2020 /* On g33, we cannot place HWS above 256MiB, so
2021 * restrict its pinning to the low mappable arena.
2022 * Though this restriction is not documented for
2023 * gen4, gen5, or byt, they also behave similarly
2024 * and hang if the HWS is placed at the top of the
2025 * GTT. To generalise, it appears that all !llc
2026 * platforms have issues with us placing the HWS
2027 * above the mappable region (even though we never
2028 * actualy map it).
2029 */
2030 flags |= PIN_MAPPABLE;
2031 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 2032 if (ret) {
2033err_unref:
2034 drm_gem_object_unreference(&obj->base);
2035 return ret;
2036 }
2037
0bc40be8 2038 engine->status_page.obj = obj;
e3efda49 2039 }
62fdfeaf 2040
0bc40be8
TU		 2041 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2042 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2043 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 2044
8187a2b7 2045 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
0bc40be8 2046 engine->name, engine->status_page.gfx_addr);
62fdfeaf
EA		 2047
2048 return 0;
62fdfeaf
EA		 2049}
2050
0bc40be8 2051static int init_phys_status_page(struct intel_engine_cs *engine)
6b8294a4 2052{
0bc40be8 2053 struct drm_i915_private *dev_priv = engine->dev->dev_private;
6b8294a4
CW		 2054
2055 if (!dev_priv->status_page_dmah) {
2056 dev_priv->status_page_dmah =
0bc40be8 2057 drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
6b8294a4
CW		 2058 if (!dev_priv->status_page_dmah)
2059 return -ENOMEM;
2060 }
2061
0bc40be8
TU		 2062 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2063 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
6b8294a4
CW		 2064
2065 return 0;
2066}
2067
7ba717cf 2068void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 2069{
def0c5f6
CW		 2070 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
2071 vunmap(ringbuf->virtual_start);
2072 else
2073 iounmap(ringbuf->virtual_start);
7ba717cf 2074 ringbuf->virtual_start = NULL;
0eb973d3 2075 ringbuf->vma = NULL;
2919d291 2076 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 2077}
2078
def0c5f6
CW		 2079static u32 *vmap_obj(struct drm_i915_gem_object *obj)
2080{
2081 struct sg_page_iter sg_iter;
2082 struct page **pages;
2083 void *addr;
2084 int i;
2085
2086 pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages));
2087 if (pages == NULL)
2088 return NULL;
2089
2090 i = 0;
2091 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0)
2092 pages[i++] = sg_page_iter_page(&sg_iter);
2093
2094 addr = vmap(pages, i, 0, PAGE_KERNEL);
2095 drm_free_large(pages);
2096
2097 return addr;
2098}
2099
7ba717cf
TD		 2100int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2101 struct intel_ringbuffer *ringbuf)
2102{
2103 struct drm_i915_private *dev_priv = to_i915(dev);
2104 struct drm_i915_gem_object *obj = ringbuf->obj;
2105 int ret;
2106
def0c5f6
CW		 2107 if (HAS_LLC(dev_priv) && !obj->stolen) {
2108 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, 0);
2109 if (ret)
2110 return ret;
7ba717cf 2111
def0c5f6
CW		 2112 ret = i915_gem_object_set_to_cpu_domain(obj, true);
2113 if (ret) {
2114 i915_gem_object_ggtt_unpin(obj);
2115 return ret;
2116 }
2117
2118 ringbuf->virtual_start = vmap_obj(obj);
2119 if (ringbuf->virtual_start == NULL) {
2120 i915_gem_object_ggtt_unpin(obj);
2121 return -ENOMEM;
2122 }
2123 } else {
2124 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE);
2125 if (ret)
2126 return ret;
7ba717cf 2127
def0c5f6
CW		 2128 ret = i915_gem_object_set_to_gtt_domain(obj, true);
2129 if (ret) {
2130 i915_gem_object_ggtt_unpin(obj);
2131 return ret;
2132 }
2133
ff3dc087
DCS		 2134 /* Access through the GTT requires the device to be awake. */
2135 assert_rpm_wakelock_held(dev_priv);
2136
def0c5f6
CW		 2137 ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base +
2138 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2139 if (ringbuf->virtual_start == NULL) {
2140 i915_gem_object_ggtt_unpin(obj);
2141 return -EINVAL;
2142 }
7ba717cf
TD		 2143 }
2144
0eb973d3
TU		 2145 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
2146
7ba717cf
TD		 2147 return 0;
2148}
2149
01101fa7 2150static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2151{
2919d291
OM		 2152 drm_gem_object_unreference(&ringbuf->obj->base);
2153 ringbuf->obj = NULL;
2154}
2155
01101fa7
CW		 2156static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2157 struct intel_ringbuffer *ringbuf)
62fdfeaf 2158{
05394f39 2159 struct drm_i915_gem_object *obj;
62fdfeaf 2160
ebc052e0
CW		 2161 obj = NULL;
2162 if (!HAS_LLC(dev))
93b0a4e0 2163 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2164 if (obj == NULL)
93b0a4e0 2165 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2166 if (obj == NULL)
2167 return -ENOMEM;
8187a2b7 2168
24f3a8cf
AG		 2169 /* mark ring buffers as read-only from GPU side by default */
2170 obj->gt_ro = 1;
2171
93b0a4e0 2172 ringbuf->obj = obj;
e3efda49 2173
7ba717cf 2174 return 0;
e3efda49
CW		 2175}
2176
01101fa7
CW		 2177struct intel_ringbuffer *
2178intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2179{
2180 struct intel_ringbuffer *ring;
2181 int ret;
2182
2183 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2184 if (ring == NULL) {
2185 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2186 engine->name);
01101fa7 2187 return ERR_PTR(-ENOMEM);
608c1a52 2188 }
01101fa7
CW		 2189
2190 ring->ring = engine;
608c1a52 2191 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2192
2193 ring->size = size;
2194 /* Workaround an erratum on the i830 which causes a hang if
2195 * the TAIL pointer points to within the last 2 cachelines
2196 * of the buffer.
2197 */
2198 ring->effective_size = size;
2199 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2200 ring->effective_size -= 2 * CACHELINE_BYTES;
2201
2202 ring->last_retired_head = -1;
2203 intel_ring_update_space(ring);
2204
2205 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2206 if (ret) {
608c1a52
CW		 2207 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2208 engine->name, ret);
2209 list_del(&ring->link);
01101fa7
CW		 2210 kfree(ring);
2211 return ERR_PTR(ret);
2212 }
2213
2214 return ring;
2215}
2216
2217void
2218intel_ringbuffer_free(struct intel_ringbuffer *ring)
2219{
2220 intel_destroy_ringbuffer_obj(ring);
608c1a52 2221 list_del(&ring->link);
01101fa7
CW		 2222 kfree(ring);
2223}
2224
e3efda49 2225static int intel_init_ring_buffer(struct drm_device *dev,
0bc40be8 2226 struct intel_engine_cs *engine)
e3efda49 2227{
bfc882b4 2228 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2229 int ret;
2230
0bc40be8 2231 WARN_ON(engine->buffer);
bfc882b4 2232
0bc40be8
TU		 2233 engine->dev = dev;
2234 INIT_LIST_HEAD(&engine->active_list);
2235 INIT_LIST_HEAD(&engine->request_list);
2236 INIT_LIST_HEAD(&engine->execlist_queue);
2237 INIT_LIST_HEAD(&engine->buffers);
2238 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2239 memset(engine->semaphore.sync_seqno, 0,
2240 sizeof(engine->semaphore.sync_seqno));
e3efda49 2241
0bc40be8 2242 init_waitqueue_head(&engine->irq_queue);
e3efda49 2243
0bc40be8 2244 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
b0366a54
DG		 2245 if (IS_ERR(ringbuf)) {
2246 ret = PTR_ERR(ringbuf);
2247 goto error;
2248 }
0bc40be8 2249 engine->buffer = ringbuf;
01101fa7 2250
e3efda49 2251 if (I915_NEED_GFX_HWS(dev)) {
0bc40be8 2252 ret = init_status_page(engine);
e3efda49 2253 if (ret)
8ee14975 2254 goto error;
e3efda49 2255 } else {
0bc40be8
TU		 2256 WARN_ON(engine->id != RCS);
2257 ret = init_phys_status_page(engine);
e3efda49 2258 if (ret)
8ee14975 2259 goto error;
e3efda49
CW		 2260 }
2261
bfc882b4
DV		 2262 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2263 if (ret) {
2264 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
0bc40be8 2265 engine->name, ret);
bfc882b4
DV		 2266 intel_destroy_ringbuffer_obj(ringbuf);
2267 goto error;
e3efda49 2268 }
62fdfeaf 2269
0bc40be8 2270 ret = i915_cmd_parser_init_ring(engine);
44e895a8 2271 if (ret)
8ee14975
OM		 2272 goto error;
2273
8ee14975 2274 return 0;
351e3db2 2275
8ee14975 2276error:
0bc40be8 2277 intel_cleanup_ring_buffer(engine);
8ee14975 2278 return ret;
62fdfeaf
EA		 2279}
2280
0bc40be8 2281void intel_cleanup_ring_buffer(struct intel_engine_cs *engine)
62fdfeaf 2282{
6402c330 2283 struct drm_i915_private *dev_priv;
33626e6a 2284
0bc40be8 2285 if (!intel_ring_initialized(engine))
62fdfeaf
EA		 2286 return;
2287
0bc40be8 2288 dev_priv = to_i915(engine->dev);
6402c330 2289
0bc40be8
TU		 2290 if (engine->buffer) {
2291 intel_stop_ring_buffer(engine);
2292 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
33626e6a 2293
0bc40be8
TU		 2294 intel_unpin_ringbuffer_obj(engine->buffer);
2295 intel_ringbuffer_free(engine->buffer);
2296 engine->buffer = NULL;
b0366a54 2297 }
78501eac 2298
0bc40be8
TU		 2299 if (engine->cleanup)
2300 engine->cleanup(engine);
8d19215b 2301
0bc40be8
TU		 2302 if (I915_NEED_GFX_HWS(engine->dev)) {
2303 cleanup_status_page(engine);
7d3fdfff 2304 } else {
0bc40be8
TU		 2305 WARN_ON(engine->id != RCS);
2306 cleanup_phys_status_page(engine);
7d3fdfff 2307 }
44e895a8 2308
0bc40be8
TU		 2309 i915_cmd_parser_fini_ring(engine);
2310 i915_gem_batch_pool_fini(&engine->batch_pool);
2311 engine->dev = NULL;
62fdfeaf
EA		 2312}
2313
0bc40be8 2314static int ring_wait_for_space(struct intel_engine_cs *engine, int n)
a71d8d94 2315{
0bc40be8 2316 struct intel_ringbuffer *ringbuf = engine->buffer;
a71d8d94 2317 struct drm_i915_gem_request *request;
b4716185
CW		 2318 unsigned space;
2319 int ret;
a71d8d94 2320
ebd0fd4b
DG		 2321 if (intel_ring_space(ringbuf) >= n)
2322 return 0;
a71d8d94 2323
79bbcc29
JH		 2324 /* The whole point of reserving space is to not wait! */
2325 WARN_ON(ringbuf->reserved_in_use);
2326
0bc40be8 2327 list_for_each_entry(request, &engine->request_list, list) {
b4716185
CW		 2328 space = __intel_ring_space(request->postfix, ringbuf->tail,
2329 ringbuf->size);
2330 if (space >= n)
a71d8d94 2331 break;
a71d8d94
CW		 2332 }
2333
0bc40be8 2334 if (WARN_ON(&request->list == &engine->request_list))
a71d8d94
CW		 2335 return -ENOSPC;
2336
a4b3a571 2337 ret = i915_wait_request(request);
a71d8d94
CW		 2338 if (ret)
2339 return ret;
2340
b4716185 2341 ringbuf->space = space;
a71d8d94
CW		 2342 return 0;
2343}
2344
79bbcc29 2345static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf)
3e960501
CW		 2346{
2347 uint32_t __iomem *virt;
93b0a4e0 2348 int rem = ringbuf->size - ringbuf->tail;
3e960501 2349
93b0a4e0 2350 virt = ringbuf->virtual_start + ringbuf->tail;
3e960501
CW		 2351 rem /= 4;
2352 while (rem--)
2353 iowrite32(MI_NOOP, virt++);
2354
93b0a4e0 2355 ringbuf->tail = 0;
ebd0fd4b 2356 intel_ring_update_space(ringbuf);
3e960501
CW		 2357}
2358
0bc40be8 2359int intel_ring_idle(struct intel_engine_cs *engine)
3e960501 2360{
a4b3a571 2361 struct drm_i915_gem_request *req;
3e960501 2362
3e960501 2363 /* Wait upon the last request to be completed */
0bc40be8 2364 if (list_empty(&engine->request_list))
3e960501
CW		 2365 return 0;
2366
0bc40be8
TU		 2367 req = list_entry(engine->request_list.prev,
2368 struct drm_i915_gem_request,
2369 list);
b4716185
CW		 2370
2371 /* Make sure we do not trigger any retires */
2372 return __i915_wait_request(req,
0bc40be8
TU		 2373 atomic_read(&to_i915(engine->dev)->gpu_error.reset_counter),
2374 to_i915(engine->dev)->mm.interruptible,
b4716185 2375 NULL, NULL);
3e960501
CW		 2376}
2377
6689cb2b 2378int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2379{
6689cb2b 2380 request->ringbuf = request->ring->buffer;
9eba5d4a 2381 return 0;
9d773091
CW		 2382}
2383
ccd98fe4
JH		 2384int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2385{
2386 /*
2387 * The first call merely notes the reserve request and is common for
2388 * all back ends. The subsequent localised _begin() call actually
2389 * ensures that the reservation is available. Without the begin, if
2390 * the request creator immediately submitted the request without
2391 * adding any commands to it then there might not actually be
2392 * sufficient room for the submission commands.
2393 */
2394 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2395
2396 return intel_ring_begin(request, 0);
2397}
2398
29b1b415
JH		 2399void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2400{
ccd98fe4 2401 WARN_ON(ringbuf->reserved_size);
29b1b415
JH		 2402 WARN_ON(ringbuf->reserved_in_use);
2403
2404 ringbuf->reserved_size = size;
29b1b415
JH		 2405}
2406
2407void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2408{
2409 WARN_ON(ringbuf->reserved_in_use);
2410
2411 ringbuf->reserved_size = 0;
2412 ringbuf->reserved_in_use = false;
2413}
2414
2415void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2416{
2417 WARN_ON(ringbuf->reserved_in_use);
2418
2419 ringbuf->reserved_in_use = true;
2420 ringbuf->reserved_tail = ringbuf->tail;
2421}
2422
2423void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2424{
2425 WARN_ON(!ringbuf->reserved_in_use);
79bbcc29
JH		 2426 if (ringbuf->tail > ringbuf->reserved_tail) {
2427 WARN(ringbuf->tail > ringbuf->reserved_tail + ringbuf->reserved_size,
2428 "request reserved size too small: %d vs %d!\n",
2429 ringbuf->tail - ringbuf->reserved_tail, ringbuf->reserved_size);
2430 } else {
2431 /*
2432 * The ring was wrapped while the reserved space was in use.
2433 * That means that some unknown amount of the ring tail was
2434 * no-op filled and skipped. Thus simply adding the ring size
2435 * to the tail and doing the above space check will not work.
2436 * Rather than attempt to track how much tail was skipped,
2437 * it is much simpler to say that also skipping the sanity
2438 * check every once in a while is not a big issue.
2439 */
2440 }
29b1b415
JH		 2441
2442 ringbuf->reserved_size = 0;
2443 ringbuf->reserved_in_use = false;
2444}
2445
0bc40be8 2446static int __intel_ring_prepare(struct intel_engine_cs *engine, int bytes)
cbcc80df 2447{
0bc40be8 2448 struct intel_ringbuffer *ringbuf = engine->buffer;
79bbcc29
JH		 2449 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2450 int remain_actual = ringbuf->size - ringbuf->tail;
2451 int ret, total_bytes, wait_bytes = 0;
2452 bool need_wrap = false;
29b1b415 2453
79bbcc29
JH		 2454 if (ringbuf->reserved_in_use)
2455 total_bytes = bytes;
2456 else
2457 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2458
79bbcc29
JH		 2459 if (unlikely(bytes > remain_usable)) {
2460 /*
2461 * Not enough space for the basic request. So need to flush
2462 * out the remainder and then wait for base + reserved.
2463 */
2464 wait_bytes = remain_actual + total_bytes;
2465 need_wrap = true;
2466 } else {
2467 if (unlikely(total_bytes > remain_usable)) {
2468 /*
2469 * The base request will fit but the reserved space
2470 * falls off the end. So only need to to wait for the
2471 * reserved size after flushing out the remainder.
2472 */
2473 wait_bytes = remain_actual + ringbuf->reserved_size;
2474 need_wrap = true;
2475 } else if (total_bytes > ringbuf->space) {
2476 /* No wrapping required, just waiting. */
2477 wait_bytes = total_bytes;
29b1b415 2478 }
cbcc80df
MK		 2479 }
2480
79bbcc29 2481 if (wait_bytes) {
0bc40be8 2482 ret = ring_wait_for_space(engine, wait_bytes);
cbcc80df
MK		 2483 if (unlikely(ret))
2484 return ret;
79bbcc29
JH		 2485
2486 if (need_wrap)
2487 __wrap_ring_buffer(ringbuf);
cbcc80df
MK		 2488 }
2489
cbcc80df
MK		 2490 return 0;
2491}
2492
5fb9de1a 2493int intel_ring_begin(struct drm_i915_gem_request *req,
e1f99ce6 2494 int num_dwords)
8187a2b7 2495{
e2f80391 2496 struct intel_engine_cs *engine;
5fb9de1a 2497 struct drm_i915_private *dev_priv;
e1f99ce6 2498 int ret;
78501eac 2499
5fb9de1a 2500 WARN_ON(req == NULL);
e2f80391
TU		 2501 engine = req->ring;
2502 dev_priv = engine->dev->dev_private;
5fb9de1a 2503
33196ded
DV		 2504 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
2505 dev_priv->mm.interruptible);
de2b9985
DV		 2506 if (ret)
2507 return ret;
21dd3734 2508
e2f80391 2509 ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
304d695c
CW		 2510 if (ret)
2511 return ret;
2512
e2f80391 2513 engine->buffer->space -= num_dwords * sizeof(uint32_t);
304d695c 2514 return 0;
8187a2b7 2515}
78501eac 2516
753b1ad4 2517/* Align the ring tail to a cacheline boundary */
bba09b12 2518int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2519{
e2f80391
TU		 2520 struct intel_engine_cs *engine = req->ring;
2521 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2522 int ret;
2523
2524 if (num_dwords == 0)
2525 return 0;
2526
18393f63 2527 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2528 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2529 if (ret)
2530 return ret;
2531
2532 while (num_dwords--)
e2f80391 2533 intel_ring_emit(engine, MI_NOOP);
753b1ad4 2534
e2f80391 2535 intel_ring_advance(engine);
753b1ad4
VS		 2536
2537 return 0;
2538}
2539
0bc40be8 2540void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
498d2ac1 2541{
0bc40be8 2542 struct drm_device *dev = engine->dev;
3b2cc8ab 2543 struct drm_i915_private *dev_priv = dev->dev_private;
498d2ac1 2544
3b2cc8ab 2545 if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) {
0bc40be8
TU		 2546 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2547 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
3b2cc8ab 2548 if (HAS_VEBOX(dev))
0bc40be8 2549 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
e1f99ce6 2550 }
d97ed339 2551
0bc40be8
TU		 2552 engine->set_seqno(engine, seqno);
2553 engine->hangcheck.seqno = seqno;
8187a2b7 2554}
62fdfeaf 2555
0bc40be8 2556static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 2557 u32 value)
881f47b6 2558{
0bc40be8 2559 struct drm_i915_private *dev_priv = engine->dev->dev_private;
881f47b6
XH		 2560
2561 /* Every tail move must follow the sequence below */
12f55818
CW		 2562
2563 /* Disable notification that the ring is IDLE. The GT
2564 * will then assume that it is busy and bring it out of rc6.
2565 */
0206e353 2566 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2567 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2568
2569 /* Clear the context id. Here be magic! */
2570 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2571
12f55818 2572 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2573 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2574 GEN6_BSD_SLEEP_INDICATOR) == 0,
2575 50))
2576 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2577
12f55818 2578 /* Now that the ring is fully powered up, update the tail */
0bc40be8
TU		 2579 I915_WRITE_TAIL(engine, value);
2580 POSTING_READ(RING_TAIL(engine->mmio_base));
12f55818
CW		 2581
2582 /* Let the ring send IDLE messages to the GT again,
2583 * and so let it sleep to conserve power when idle.
2584 */
0206e353 2585 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2586 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2587}
2588
a84c3ae1 2589static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2590 u32 invalidate, u32 flush)
881f47b6 2591{
e2f80391 2592 struct intel_engine_cs *engine = req->ring;
71a77e07 2593 uint32_t cmd;
b72f3acb
CW		 2594 int ret;
2595
5fb9de1a 2596 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2597 if (ret)
2598 return ret;
2599
71a77e07 2600 cmd = MI_FLUSH_DW;
e2f80391 2601 if (INTEL_INFO(engine->dev)->gen >= 8)
075b3bba 2602 cmd += 1;
f0a1fb10
CW		 2603
2604 /* We always require a command barrier so that subsequent
2605 * commands, such as breadcrumb interrupts, are strictly ordered
2606 * wrt the contents of the write cache being flushed to memory
2607 * (and thus being coherent from the CPU).
2608 */
2609 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2610
9a289771
JB		 2611 /*
2612 * Bspec vol 1c.5 - video engine command streamer:
2613 * "If ENABLED, all TLBs will be invalidated once the flush
2614 * operation is complete. This bit is only valid when the
2615 * Post-Sync Operation field is a value of 1h or 3h."
2616 */
71a77e07 2617 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2618 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2619
e2f80391
TU		 2620 intel_ring_emit(engine, cmd);
2621 intel_ring_emit(engine,
2622 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2623 if (INTEL_INFO(engine->dev)->gen >= 8) {
2624 intel_ring_emit(engine, 0); /* upper addr */
2625 intel_ring_emit(engine, 0); /* value */
075b3bba 2626 } else {
e2f80391
TU		 2627 intel_ring_emit(engine, 0);
2628 intel_ring_emit(engine, MI_NOOP);
075b3bba 2629 }
e2f80391 2630 intel_ring_advance(engine);
b72f3acb 2631 return 0;
881f47b6
XH		 2632}
2633
1c7a0623 2634static int
53fddaf7 2635gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2636 u64 offset, u32 len,
8e004efc 2637 unsigned dispatch_flags)
1c7a0623 2638{
e2f80391
TU		 2639 struct intel_engine_cs *engine = req->ring;
2640 bool ppgtt = USES_PPGTT(engine->dev) &&
8e004efc 2641 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2642 int ret;
2643
5fb9de1a 2644 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2645 if (ret)
2646 return ret;
2647
2648 /* FIXME(BDW): Address space and security selectors. */
e2f80391 2649 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
919032ec
AJ		 2650 (dispatch_flags & I915_DISPATCH_RS ?
2651 MI_BATCH_RESOURCE_STREAMER : 0));
e2f80391
TU		 2652 intel_ring_emit(engine, lower_32_bits(offset));
2653 intel_ring_emit(engine, upper_32_bits(offset));
2654 intel_ring_emit(engine, MI_NOOP);
2655 intel_ring_advance(engine);
1c7a0623
BW		 2656
2657 return 0;
2658}
2659
d7d4eedd 2660static int
53fddaf7 2661hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2662 u64 offset, u32 len,
2663 unsigned dispatch_flags)
d7d4eedd 2664{
e2f80391 2665 struct intel_engine_cs *engine = req->ring;
d7d4eedd
CW		 2666 int ret;
2667
5fb9de1a 2668 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2669 if (ret)
2670 return ret;
2671
e2f80391 2672 intel_ring_emit(engine,
77072258 2673 MI_BATCH_BUFFER_START |
8e004efc 2674 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2675 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2676 (dispatch_flags & I915_DISPATCH_RS ?
2677 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd 2678 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2679 intel_ring_emit(engine, offset);
2680 intel_ring_advance(engine);
d7d4eedd
CW		 2681
2682 return 0;
2683}
2684
881f47b6 2685static int
53fddaf7 2686gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2687 u64 offset, u32 len,
8e004efc 2688 unsigned dispatch_flags)
881f47b6 2689{
e2f80391 2690 struct intel_engine_cs *engine = req->ring;
0206e353 2691 int ret;
ab6f8e32 2692
5fb9de1a 2693 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2694 if (ret)
2695 return ret;
e1f99ce6 2696
e2f80391 2697 intel_ring_emit(engine,
d7d4eedd 2698 MI_BATCH_BUFFER_START |
8e004efc
JH		 2699 (dispatch_flags & I915_DISPATCH_SECURE ?
2700 0 : MI_BATCH_NON_SECURE_I965));
0206e353 2701 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2702 intel_ring_emit(engine, offset);
2703 intel_ring_advance(engine);
ab6f8e32 2704
0206e353 2705 return 0;
881f47b6
XH		 2706}
2707
549f7365
CW		 2708/* Blitter support (SandyBridge+) */
2709
a84c3ae1 2710static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2711 u32 invalidate, u32 flush)
8d19215b 2712{
e2f80391
TU		 2713 struct intel_engine_cs *engine = req->ring;
2714 struct drm_device *dev = engine->dev;
71a77e07 2715 uint32_t cmd;
b72f3acb
CW		 2716 int ret;
2717
5fb9de1a 2718 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2719 if (ret)
2720 return ret;
2721
71a77e07 2722 cmd = MI_FLUSH_DW;
dbef0f15 2723 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2724 cmd += 1;
f0a1fb10
CW		 2725
2726 /* We always require a command barrier so that subsequent
2727 * commands, such as breadcrumb interrupts, are strictly ordered
2728 * wrt the contents of the write cache being flushed to memory
2729 * (and thus being coherent from the CPU).
2730 */
2731 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2732
9a289771
JB		 2733 /*
2734 * Bspec vol 1c.3 - blitter engine command streamer:
2735 * "If ENABLED, all TLBs will be invalidated once the flush
2736 * operation is complete. This bit is only valid when the
2737 * Post-Sync Operation field is a value of 1h or 3h."
2738 */
71a77e07 2739 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2740 cmd |= MI_INVALIDATE_TLB;
e2f80391
TU		 2741 intel_ring_emit(engine, cmd);
2742 intel_ring_emit(engine,
2743 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2744 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391
TU		 2745 intel_ring_emit(engine, 0); /* upper addr */
2746 intel_ring_emit(engine, 0); /* value */
075b3bba 2747 } else {
e2f80391
TU		 2748 intel_ring_emit(engine, 0);
2749 intel_ring_emit(engine, MI_NOOP);
075b3bba 2750 }
e2f80391 2751 intel_ring_advance(engine);
fd3da6c9 2752
b72f3acb 2753 return 0;
8d19215b
ZN		 2754}
2755
5c1143bb
XH		 2756int intel_init_render_ring_buffer(struct drm_device *dev)
2757{
4640c4ff 2758 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2759 struct intel_engine_cs *engine = &dev_priv->ring[RCS];
3e78998a
BW		 2760 struct drm_i915_gem_object *obj;
2761 int ret;
5c1143bb 2762
e2f80391
TU		 2763 engine->name = "render ring";
2764 engine->id = RCS;
2765 engine->exec_id = I915_EXEC_RENDER;
2766 engine->mmio_base = RENDER_RING_BASE;
59465b5f 2767
707d9cf9 2768 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2769 if (i915_semaphore_is_enabled(dev)) {
2770 obj = i915_gem_alloc_object(dev, 4096);
2771 if (obj == NULL) {
2772 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2773 i915.semaphores = 0;
2774 } else {
2775 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2776 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2777 if (ret != 0) {
2778 drm_gem_object_unreference(&obj->base);
2779 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2780 i915.semaphores = 0;
2781 } else
2782 dev_priv->semaphore_obj = obj;
2783 }
2784 }
7225342a 2785
e2f80391
TU		 2786 engine->init_context = intel_rcs_ctx_init;
2787 engine->add_request = gen6_add_request;
2788 engine->flush = gen8_render_ring_flush;
2789 engine->irq_get = gen8_ring_get_irq;
2790 engine->irq_put = gen8_ring_put_irq;
2791 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2792 engine->get_seqno = gen6_ring_get_seqno;
2793 engine->set_seqno = ring_set_seqno;
707d9cf9 2794 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2795 WARN_ON(!dev_priv->semaphore_obj);
e2f80391
TU		 2796 engine->semaphore.sync_to = gen8_ring_sync;
2797 engine->semaphore.signal = gen8_rcs_signal;
2798 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9
BW		 2799 }
2800 } else if (INTEL_INFO(dev)->gen >= 6) {
e2f80391
TU		 2801 engine->init_context = intel_rcs_ctx_init;
2802 engine->add_request = gen6_add_request;
2803 engine->flush = gen7_render_ring_flush;
6c6cf5aa 2804 if (INTEL_INFO(dev)->gen == 6)
e2f80391
TU		 2805 engine->flush = gen6_render_ring_flush;
2806 engine->irq_get = gen6_ring_get_irq;
2807 engine->irq_put = gen6_ring_put_irq;
2808 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2809 engine->get_seqno = gen6_ring_get_seqno;
2810 engine->set_seqno = ring_set_seqno;
707d9cf9 2811 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 2812 engine->semaphore.sync_to = gen6_ring_sync;
2813 engine->semaphore.signal = gen6_signal;
707d9cf9
BW		 2814 /*
2815 * The current semaphore is only applied on pre-gen8
2816 * platform. And there is no VCS2 ring on the pre-gen8
2817 * platform. So the semaphore between RCS and VCS2 is
2818 * initialized as INVALID. Gen8 will initialize the
2819 * sema between VCS2 and RCS later.
2820 */
e2f80391
TU		 2821 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2822 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2823 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2824 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2825 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2826 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2827 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2828 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2829 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2830 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2831 }
c6df541c 2832 } else if (IS_GEN5(dev)) {
e2f80391
TU		 2833 engine->add_request = pc_render_add_request;
2834 engine->flush = gen4_render_ring_flush;
2835 engine->get_seqno = pc_render_get_seqno;
2836 engine->set_seqno = pc_render_set_seqno;
2837 engine->irq_get = gen5_ring_get_irq;
2838 engine->irq_put = gen5_ring_put_irq;
2839 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
cc609d5d 2840 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2841 } else {
e2f80391 2842 engine->add_request = i9xx_add_request;
46f0f8d1 2843 if (INTEL_INFO(dev)->gen < 4)
e2f80391 2844 engine->flush = gen2_render_ring_flush;
46f0f8d1 2845 else
e2f80391
TU		 2846 engine->flush = gen4_render_ring_flush;
2847 engine->get_seqno = ring_get_seqno;
2848 engine->set_seqno = ring_set_seqno;
c2798b19 2849 if (IS_GEN2(dev)) {
e2f80391
TU		 2850 engine->irq_get = i8xx_ring_get_irq;
2851 engine->irq_put = i8xx_ring_put_irq;
c2798b19 2852 } else {
e2f80391
TU		 2853 engine->irq_get = i9xx_ring_get_irq;
2854 engine->irq_put = i9xx_ring_put_irq;
c2798b19 2855 }
e2f80391 2856 engine->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2857 }
e2f80391 2858 engine->write_tail = ring_write_tail;
707d9cf9 2859
d7d4eedd 2860 if (IS_HASWELL(dev))
e2f80391 2861 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623 2862 else if (IS_GEN8(dev))
e2f80391 2863 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2864 else if (INTEL_INFO(dev)->gen >= 6)
e2f80391 2865 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
fb3256da 2866 else if (INTEL_INFO(dev)->gen >= 4)
e2f80391 2867 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
fb3256da 2868 else if (IS_I830(dev) || IS_845G(dev))
e2f80391 2869 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
fb3256da 2870 else
e2f80391
TU		 2871 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2872 engine->init_hw = init_render_ring;
2873 engine->cleanup = render_ring_cleanup;
59465b5f 2874
b45305fc
DV		 2875 /* Workaround batchbuffer to combat CS tlb bug. */
2876 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2877 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2878 if (obj == NULL) {
2879 DRM_ERROR("Failed to allocate batch bo\n");
2880 return -ENOMEM;
2881 }
2882
be1fa129 2883 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2884 if (ret != 0) {
2885 drm_gem_object_unreference(&obj->base);
2886 DRM_ERROR("Failed to ping batch bo\n");
2887 return ret;
2888 }
2889
e2f80391
TU		 2890 engine->scratch.obj = obj;
2891 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2892 }
2893
e2f80391 2894 ret = intel_init_ring_buffer(dev, engine);
99be1dfe
DV		 2895 if (ret)
2896 return ret;
2897
2898 if (INTEL_INFO(dev)->gen >= 5) {
e2f80391 2899 ret = intel_init_pipe_control(engine);
99be1dfe
DV		 2900 if (ret)
2901 return ret;
2902 }
2903
2904 return 0;
5c1143bb
XH		 2905}
2906
2907int intel_init_bsd_ring_buffer(struct drm_device *dev)
2908{
4640c4ff 2909 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 2910 struct intel_engine_cs *engine = &dev_priv->ring[VCS];
5c1143bb 2911
e2f80391
TU		 2912 engine->name = "bsd ring";
2913 engine->id = VCS;
2914 engine->exec_id = I915_EXEC_BSD;
58fa3835 2915
e2f80391 2916 engine->write_tail = ring_write_tail;
780f18c8 2917 if (INTEL_INFO(dev)->gen >= 6) {
e2f80391 2918 engine->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2919 /* gen6 bsd needs a special wa for tail updates */
2920 if (IS_GEN6(dev))
e2f80391
TU		 2921 engine->write_tail = gen6_bsd_ring_write_tail;
2922 engine->flush = gen6_bsd_ring_flush;
2923 engine->add_request = gen6_add_request;
2924 engine->get_seqno = gen6_ring_get_seqno;
2925 engine->set_seqno = ring_set_seqno;
abd58f01 2926 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391 2927 engine->irq_enable_mask =
abd58f01 2928 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
e2f80391
TU		 2929 engine->irq_get = gen8_ring_get_irq;
2930 engine->irq_put = gen8_ring_put_irq;
2931 engine->dispatch_execbuffer =
1c7a0623 2932 gen8_ring_dispatch_execbuffer;
707d9cf9 2933 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 2934 engine->semaphore.sync_to = gen8_ring_sync;
2935 engine->semaphore.signal = gen8_xcs_signal;
2936 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2937 }
abd58f01 2938 } else {
e2f80391
TU		 2939 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2940 engine->irq_get = gen6_ring_get_irq;
2941 engine->irq_put = gen6_ring_put_irq;
2942 engine->dispatch_execbuffer =
1c7a0623 2943 gen6_ring_dispatch_execbuffer;
707d9cf9 2944 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 2945 engine->semaphore.sync_to = gen6_ring_sync;
2946 engine->semaphore.signal = gen6_signal;
2947 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2948 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2949 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2950 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2951 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2952 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2953 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2954 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2955 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2956 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2957 }
abd58f01 2958 }
58fa3835 2959 } else {
e2f80391
TU		 2960 engine->mmio_base = BSD_RING_BASE;
2961 engine->flush = bsd_ring_flush;
2962 engine->add_request = i9xx_add_request;
2963 engine->get_seqno = ring_get_seqno;
2964 engine->set_seqno = ring_set_seqno;
e48d8634 2965 if (IS_GEN5(dev)) {
e2f80391
TU		 2966 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2967 engine->irq_get = gen5_ring_get_irq;
2968 engine->irq_put = gen5_ring_put_irq;
e48d8634 2969 } else {
e2f80391
TU		 2970 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2971 engine->irq_get = i9xx_ring_get_irq;
2972 engine->irq_put = i9xx_ring_put_irq;
e48d8634 2973 }
e2f80391 2974 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2975 }
e2f80391 2976 engine->init_hw = init_ring_common;
58fa3835 2977
e2f80391 2978 return intel_init_ring_buffer(dev, engine);
5c1143bb 2979}
549f7365 2980
845f74a7 2981/**
62659920 2982 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 2983 */
2984int intel_init_bsd2_ring_buffer(struct drm_device *dev)
2985{
2986 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391
TU		 2987 struct intel_engine_cs *engine = &dev_priv->ring[VCS2];
2988
2989 engine->name = "bsd2 ring";
2990 engine->id = VCS2;
2991 engine->exec_id = I915_EXEC_BSD;
2992
2993 engine->write_tail = ring_write_tail;
2994 engine->mmio_base = GEN8_BSD2_RING_BASE;
2995 engine->flush = gen6_bsd_ring_flush;
2996 engine->add_request = gen6_add_request;
2997 engine->get_seqno = gen6_ring_get_seqno;
2998 engine->set_seqno = ring_set_seqno;
2999 engine->irq_enable_mask =
845f74a7 3000 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
e2f80391
TU		 3001 engine->irq_get = gen8_ring_get_irq;
3002 engine->irq_put = gen8_ring_put_irq;
3003 engine->dispatch_execbuffer =
845f74a7 3004 gen8_ring_dispatch_execbuffer;
3e78998a 3005 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3006 engine->semaphore.sync_to = gen8_ring_sync;
3007 engine->semaphore.signal = gen8_xcs_signal;
3008 GEN8_RING_SEMAPHORE_INIT(engine);
3e78998a 3009 }
e2f80391 3010 engine->init_hw = init_ring_common;
845f74a7 3011
e2f80391 3012 return intel_init_ring_buffer(dev, engine);
845f74a7
ZY		 3013}
3014
549f7365
CW		 3015int intel_init_blt_ring_buffer(struct drm_device *dev)
3016{
4640c4ff 3017 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391
TU		 3018 struct intel_engine_cs *engine = &dev_priv->ring[BCS];
3019
3020 engine->name = "blitter ring";
3021 engine->id = BCS;
3022 engine->exec_id = I915_EXEC_BLT;
3023
3024 engine->mmio_base = BLT_RING_BASE;
3025 engine->write_tail = ring_write_tail;
3026 engine->flush = gen6_ring_flush;
3027 engine->add_request = gen6_add_request;
3028 engine->get_seqno = gen6_ring_get_seqno;
3029 engine->set_seqno = ring_set_seqno;
abd58f01 3030 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391 3031 engine->irq_enable_mask =
abd58f01 3032 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
e2f80391
TU		 3033 engine->irq_get = gen8_ring_get_irq;
3034 engine->irq_put = gen8_ring_put_irq;
3035 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 3036 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3037 engine->semaphore.sync_to = gen8_ring_sync;
3038 engine->semaphore.signal = gen8_xcs_signal;
3039 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3040 }
abd58f01 3041 } else {
e2f80391
TU		 3042 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3043 engine->irq_get = gen6_ring_get_irq;
3044 engine->irq_put = gen6_ring_put_irq;
3045 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9 3046 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3047 engine->semaphore.signal = gen6_signal;
3048 engine->semaphore.sync_to = gen6_ring_sync;
707d9cf9
BW		 3049 /*
3050 * The current semaphore is only applied on pre-gen8
3051 * platform. And there is no VCS2 ring on the pre-gen8
3052 * platform. So the semaphore between BCS and VCS2 is
3053 * initialized as INVALID. Gen8 will initialize the
3054 * sema between BCS and VCS2 later.
3055 */
e2f80391
TU		 3056 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3057 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3058 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3059 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3060 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3061 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3062 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3063 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3064 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3065 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3066 }
abd58f01 3067 }
e2f80391 3068 engine->init_hw = init_ring_common;
549f7365 3069
e2f80391 3070 return intel_init_ring_buffer(dev, engine);
549f7365 3071}
a7b9761d 3072
9a8a2213
BW		 3073int intel_init_vebox_ring_buffer(struct drm_device *dev)
3074{
4640c4ff 3075 struct drm_i915_private *dev_priv = dev->dev_private;
e2f80391 3076 struct intel_engine_cs *engine = &dev_priv->ring[VECS];
9a8a2213 3077
e2f80391
TU		 3078 engine->name = "video enhancement ring";
3079 engine->id = VECS;
3080 engine->exec_id = I915_EXEC_VEBOX;
9a8a2213 3081
e2f80391
TU		 3082 engine->mmio_base = VEBOX_RING_BASE;
3083 engine->write_tail = ring_write_tail;
3084 engine->flush = gen6_ring_flush;
3085 engine->add_request = gen6_add_request;
3086 engine->get_seqno = gen6_ring_get_seqno;
3087 engine->set_seqno = ring_set_seqno;
abd58f01
BW		 3088
3089 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391 3090 engine->irq_enable_mask =
40c499f9 3091 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
e2f80391
TU		 3092 engine->irq_get = gen8_ring_get_irq;
3093 engine->irq_put = gen8_ring_put_irq;
3094 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 3095 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3096 engine->semaphore.sync_to = gen8_ring_sync;
3097 engine->semaphore.signal = gen8_xcs_signal;
3098 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3099 }
abd58f01 3100 } else {
e2f80391
TU		 3101 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3102 engine->irq_get = hsw_vebox_get_irq;
3103 engine->irq_put = hsw_vebox_put_irq;
3104 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9 3105 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3106 engine->semaphore.sync_to = gen6_ring_sync;
3107 engine->semaphore.signal = gen6_signal;
3108 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3109 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3110 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3111 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3112 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3113 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3114 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3115 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3116 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3117 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3118 }
abd58f01 3119 }
e2f80391 3120 engine->init_hw = init_ring_common;
9a8a2213 3121
e2f80391 3122 return intel_init_ring_buffer(dev, engine);
9a8a2213
BW		 3123}
3124
a7b9761d 3125int
4866d729 3126intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3127{
e2f80391 3128 struct intel_engine_cs *engine = req->ring;
a7b9761d
CW		 3129 int ret;
3130
e2f80391 3131 if (!engine->gpu_caches_dirty)
a7b9761d
CW		 3132 return 0;
3133
e2f80391 3134 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3135 if (ret)
3136 return ret;
3137
a84c3ae1 3138 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d 3139
e2f80391 3140 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3141 return 0;
3142}
3143
3144int
2f20055d 3145intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3146{
e2f80391 3147 struct intel_engine_cs *engine = req->ring;
a7b9761d
CW		 3148 uint32_t flush_domains;
3149 int ret;
3150
3151 flush_domains = 0;
e2f80391 3152 if (engine->gpu_caches_dirty)
a7b9761d
CW		 3153 flush_domains = I915_GEM_GPU_DOMAINS;
3154
e2f80391 3155 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3156 if (ret)
3157 return ret;
3158
a84c3ae1 3159 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d 3160
e2f80391 3161 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3162 return 0;
3163}
e3efda49
CW		 3164
3165void
0bc40be8 3166intel_stop_ring_buffer(struct intel_engine_cs *engine)
e3efda49
CW		 3167{
3168 int ret;
3169
0bc40be8 3170 if (!intel_ring_initialized(engine))
e3efda49
CW		 3171 return;
3172
0bc40be8
TU		 3173 ret = intel_ring_idle(engine);
3174 if (ret && !i915_reset_in_progress(&to_i915(engine->dev)->gpu_error))
e3efda49 3175 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
0bc40be8 3176 engine->name, ret);
e3efda49 3177
0bc40be8 3178 stop_ring(engine);
e3efda49 3179}
Linux kernel - Deliverables
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