[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c

/*
 * Copyright © 2008-2010 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Eric Anholt <eric@anholt.net>
 *    Zou Nan hai <nanhai.zou@intel.com>
 *    Xiang Hai hao<haihao.xiang@intel.com>
 *
 */

#include "drmP.h"
#include "drm.h"
#include "i915_drm.h"
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"

void
i915_gem_flush(struct drm_device *dev,
	       uint32_t invalidate_domains,
	       uint32_t flush_domains)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t cmd;
	RING_LOCALS;

#if WATCH_EXEC
	DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
		  invalidate_domains, flush_domains);
#endif
	trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
				     invalidate_domains, flush_domains);

	if (flush_domains & I915_GEM_DOMAIN_CPU)
		drm_agp_chipset_flush(dev);

	if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
		/*
		 * read/write caches:
		 *
		 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
		 * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
		 * also flushed at 2d versus 3d pipeline switches.
		 *
		 * read-only caches:
		 *
		 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
		 * MI_READ_FLUSH is set, and is always flushed on 965.
		 *
		 * I915_GEM_DOMAIN_COMMAND may not exist?
		 *
		 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
		 * invalidated when MI_EXE_FLUSH is set.
		 *
		 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
		 * invalidated with every MI_FLUSH.
		 *
		 * TLBs:
		 *
		 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
		 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
		 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
		 * are flushed at any MI_FLUSH.
		 */

		cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
		if ((invalidate_domains|flush_domains) &
		    I915_GEM_DOMAIN_RENDER)
			cmd &= ~MI_NO_WRITE_FLUSH;
		if (!IS_I965G(dev)) {
			/*
			 * On the 965, the sampler cache always gets flushed
			 * and this bit is reserved.
			 */
			if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
				cmd |= MI_READ_FLUSH;
		}
		if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
			cmd |= MI_EXE_FLUSH;

#if WATCH_EXEC
		DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
#endif
		BEGIN_LP_RING(2);
		OUT_RING(cmd);
		OUT_RING(MI_NOOP);
		ADVANCE_LP_RING();
	}

}
#define PIPE_CONTROL_FLUSH(addr)					\
	OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |		\
		 PIPE_CONTROL_DEPTH_STALL);				\
	OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT);			\
	OUT_RING(0);							\
	OUT_RING(0);							\

/**
 * Creates a new sequence number, emitting a write of it to the status page
 * plus an interrupt, which will trigger i915_user_interrupt_handler.
 *
 * Must be called with struct_lock held.
 *
 * Returned sequence numbers are nonzero on success.
 */
uint32_t
i915_ring_add_request(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	uint32_t seqno;
	RING_LOCALS;

	/* Grab the seqno we're going to make this request be, and bump the
	 * next (skipping 0 so it can be the reserved no-seqno value).
	 */
	seqno = dev_priv->mm.next_gem_seqno;
	dev_priv->mm.next_gem_seqno++;
	if (dev_priv->mm.next_gem_seqno == 0)
		dev_priv->mm.next_gem_seqno++;

	if (HAS_PIPE_CONTROL(dev)) {
		u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;

		/*
		 * Workaround qword write incoherence by flushing the
		 * PIPE_NOTIFY buffers out to memory before requesting
		 * an interrupt.
		 */
		BEGIN_LP_RING(32);
		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
		OUT_RING(seqno);
		OUT_RING(0);
		PIPE_CONTROL_FLUSH(scratch_addr);
		scratch_addr += 128; /* write to separate cachelines */
		PIPE_CONTROL_FLUSH(scratch_addr);
		scratch_addr += 128;
		PIPE_CONTROL_FLUSH(scratch_addr);
		scratch_addr += 128;
		PIPE_CONTROL_FLUSH(scratch_addr);
		scratch_addr += 128;
		PIPE_CONTROL_FLUSH(scratch_addr);
		scratch_addr += 128;
		PIPE_CONTROL_FLUSH(scratch_addr);
		OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
			 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
			 PIPE_CONTROL_NOTIFY);
		OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
		OUT_RING(seqno);
		OUT_RING(0);
		ADVANCE_LP_RING();
	} else {
		BEGIN_LP_RING(4);
		OUT_RING(MI_STORE_DWORD_INDEX);
		OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
		OUT_RING(seqno);

		OUT_RING(MI_USER_INTERRUPT);
		ADVANCE_LP_RING();
	}
	return seqno;
}

void i915_user_irq_get(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
		if (HAS_PCH_SPLIT(dev))
			ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
		else
			i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
	}
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
}

void i915_user_irq_put(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
	unsigned long irqflags;

	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
	if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
		if (HAS_PCH_SPLIT(dev))
			ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
		else
			i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
	}
	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
}

/** Dispatch a batchbuffer to the ring
 */
int
i915_dispatch_gem_execbuffer(struct drm_device *dev,
			      struct drm_i915_gem_execbuffer2 *exec,
			      struct drm_clip_rect *cliprects,
			      uint64_t exec_offset)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int nbox = exec->num_cliprects;
	int i = 0, count;
	uint32_t exec_start, exec_len;
	RING_LOCALS;

	exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
	exec_len = (uint32_t) exec->batch_len;

	trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);

	count = nbox ? nbox : 1;

	for (i = 0; i < count; i++) {
		if (i < nbox) {
			int ret = i915_emit_box(dev, cliprects, i,
						exec->DR1, exec->DR4);
			if (ret)
				return ret;
		}

		if (IS_I830(dev) || IS_845G(dev)) {
			BEGIN_LP_RING(4);
			OUT_RING(MI_BATCH_BUFFER);
			OUT_RING(exec_start | MI_BATCH_NON_SECURE);
			OUT_RING(exec_start + exec_len - 4);
			OUT_RING(0);
			ADVANCE_LP_RING();
		} else {
			BEGIN_LP_RING(2);
			if (IS_I965G(dev)) {
				OUT_RING(MI_BATCH_BUFFER_START |
					 (2 << 6) |
					 MI_BATCH_NON_SECURE_I965);
				OUT_RING(exec_start);
			} else {
				OUT_RING(MI_BATCH_BUFFER_START |
					 (2 << 6));
				OUT_RING(exec_start | MI_BATCH_NON_SECURE);
			}
			ADVANCE_LP_RING();
		}
	}

	/* XXX breadcrumb */
	return 0;
}

static void
i915_gem_cleanup_hws(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;

	if (dev_priv->hws_obj == NULL)
		return;

	obj = dev_priv->hws_obj;
	obj_priv = to_intel_bo(obj);

	kunmap(obj_priv->pages[0]);
	i915_gem_object_unpin(obj);
	drm_gem_object_unreference(obj);
	dev_priv->hws_obj = NULL;

	memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
	dev_priv->hw_status_page = NULL;

	if (HAS_PIPE_CONTROL(dev))
		i915_gem_cleanup_pipe_control(dev);

	/* Write high address into HWS_PGA when disabling. */
	I915_WRITE(HWS_PGA, 0x1ffff000);
}

static int
i915_gem_init_hws(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	int ret;

	/* If we need a physical address for the status page, it's already
	 * initialized at driver load time.
	 */
	if (!I915_NEED_GFX_HWS(dev))
		return 0;

	obj = i915_gem_alloc_object(dev, 4096);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate status page\n");
		ret = -ENOMEM;
		goto err;
	}
	obj_priv = to_intel_bo(obj);
	obj_priv->agp_type = AGP_USER_CACHED_MEMORY;

	ret = i915_gem_object_pin(obj, 4096);
	if (ret != 0) {
		drm_gem_object_unreference(obj);
		goto err_unref;
	}

	dev_priv->status_gfx_addr = obj_priv->gtt_offset;

	dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
	if (dev_priv->hw_status_page == NULL) {
		DRM_ERROR("Failed to map status page.\n");
		memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
		ret = -EINVAL;
		goto err_unpin;
	}

	if (HAS_PIPE_CONTROL(dev)) {
		ret = i915_gem_init_pipe_control(dev);
		if (ret)
			goto err_unpin;
	}

	dev_priv->hws_obj = obj;
	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
	if (IS_GEN6(dev)) {
		I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
		I915_READ(HWS_PGA_GEN6); /* posting read */
	} else {
		I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
		I915_READ(HWS_PGA); /* posting read */
	}
	DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);

	return 0;

err_unpin:
	i915_gem_object_unpin(obj);
err_unref:
	drm_gem_object_unreference(obj);
err:
	return 0;
}

int
i915_gem_init_ringbuffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	struct drm_gem_object *obj;
	struct drm_i915_gem_object *obj_priv;
	drm_i915_ring_buffer_t *ring = &dev_priv->ring;
	int ret;
	u32 head;

	ret = i915_gem_init_hws(dev);
	if (ret != 0)
		return ret;

	obj = i915_gem_alloc_object(dev, 128 * 1024);
	if (obj == NULL) {
		DRM_ERROR("Failed to allocate ringbuffer\n");
		i915_gem_cleanup_hws(dev);
		return -ENOMEM;
	}
	obj_priv = to_intel_bo(obj);

	ret = i915_gem_object_pin(obj, 4096);
	if (ret != 0) {
		drm_gem_object_unreference(obj);
		i915_gem_cleanup_hws(dev);
		return ret;
	}

	/* Set up the kernel mapping for the ring. */
	ring->Size = obj->size;

	ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
	ring->map.size = obj->size;
	ring->map.type = 0;
	ring->map.flags = 0;
	ring->map.mtrr = 0;

	drm_core_ioremap_wc(&ring->map, dev);
	if (ring->map.handle == NULL) {
		DRM_ERROR("Failed to map ringbuffer.\n");
		memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
		i915_gem_object_unpin(obj);
		drm_gem_object_unreference(obj);
		i915_gem_cleanup_hws(dev);
		return -EINVAL;
	}
	ring->ring_obj = obj;
	ring->virtual_start = ring->map.handle;

	/* Stop the ring if it's running. */
	I915_WRITE(PRB0_CTL, 0);
	I915_WRITE(PRB0_TAIL, 0);
	I915_WRITE(PRB0_HEAD, 0);

	/* Initialize the ring. */
	I915_WRITE(PRB0_START, obj_priv->gtt_offset);
	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;

	/* G45 ring initialization fails to reset head to zero */
	if (head != 0) {
		DRM_ERROR("Ring head not reset to zero "
			  "ctl %08x head %08x tail %08x start %08x\n",
			  I915_READ(PRB0_CTL),
			  I915_READ(PRB0_HEAD),
			  I915_READ(PRB0_TAIL),
			  I915_READ(PRB0_START));
		I915_WRITE(PRB0_HEAD, 0);

		DRM_ERROR("Ring head forced to zero "
			  "ctl %08x head %08x tail %08x start %08x\n",
			  I915_READ(PRB0_CTL),
			  I915_READ(PRB0_HEAD),
			  I915_READ(PRB0_TAIL),
			  I915_READ(PRB0_START));
	}

	I915_WRITE(PRB0_CTL,
		   ((obj->size - 4096) & RING_NR_PAGES) |
		   RING_NO_REPORT |
		   RING_VALID);

	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;

	/* If the head is still not zero, the ring is dead */
	if (head != 0) {
		DRM_ERROR("Ring initialization failed "
			  "ctl %08x head %08x tail %08x start %08x\n",
			  I915_READ(PRB0_CTL),
			  I915_READ(PRB0_HEAD),
			  I915_READ(PRB0_TAIL),
			  I915_READ(PRB0_START));
		return -EIO;
	}

	/* Update our cache of the ring state */
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_kernel_lost_context(dev);
	else {
		ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
		ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
		ring->space = ring->head - (ring->tail + 8);
		if (ring->space < 0)
			ring->space += ring->Size;
	}

	if (IS_I9XX(dev) && !IS_GEN3(dev)) {
		I915_WRITE(MI_MODE,
			   (VS_TIMER_DISPATCH) << 16 | VS_TIMER_DISPATCH);
	}

	return 0;
}

void
i915_gem_cleanup_ringbuffer(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;

	if (dev_priv->ring.ring_obj == NULL)
		return;

	drm_core_ioremapfree(&dev_priv->ring.map, dev);

	i915_gem_object_unpin(dev_priv->ring.ring_obj);
	drm_gem_object_unreference(dev_priv->ring.ring_obj);
	dev_priv->ring.ring_obj = NULL;
	memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));

	i915_gem_cleanup_hws(dev);
}

/* As a ringbuffer is only allowed to wrap between instructions, fill
 * the tail with NOOPs.
 */
int i915_wrap_ring(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	volatile unsigned int *virt;
	int rem;

	rem = dev_priv->ring.Size - dev_priv->ring.tail;
	if (dev_priv->ring.space < rem) {
		int ret = i915_wait_ring(dev, rem, __func__);
		if (ret)
			return ret;
	}
	dev_priv->ring.space -= rem;

	virt = (unsigned int *)
		(dev_priv->ring.virtual_start + dev_priv->ring.tail);
	rem /= 4;
	while (rem--)
		*virt++ = MI_NOOP;

	dev_priv->ring.tail = 0;

	return 0;
}

int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
	u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
	u32 last_acthd = I915_READ(acthd_reg);
	u32 acthd;
	u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
	int i;

	trace_i915_ring_wait_begin (dev);

	for (i = 0; i < 100000; i++) {
		ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
		acthd = I915_READ(acthd_reg);
		ring->space = ring->head - (ring->tail + 8);
		if (ring->space < 0)
			ring->space += ring->Size;
		if (ring->space >= n) {
			trace_i915_ring_wait_end (dev);
			return 0;
		}

		if (dev->primary->master) {
			struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
			if (master_priv->sarea_priv)
				master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
		}


		if (ring->head != last_head)
			i = 0;
		if (acthd != last_acthd)
			i = 0;

		last_head = ring->head;
		last_acthd = acthd;
		msleep_interruptible(10);

	}

	trace_i915_ring_wait_end (dev);
	return -EBUSY;
}
Commit	Line	Data
62fdfeaf EA	1	/*
	2	* Copyright © 2008-2010 Intel Corporation
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	20	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	21	* IN THE SOFTWARE.
	22	*
	23	* Authors:
	24	* Eric Anholt <eric@anholt.net>
	25	* Zou Nan hai <nanhai.zou@intel.com>
	26	* Xiang Hai hao<haihao.xiang@intel.com>
	27	*
	28	*/
	29
	30	#include "drmP.h"
	31	#include "drm.h"
	32	#include "i915_drm.h"
	33	#include "i915_drv.h"
	34	#include "i915_trace.h"
	35	#include "intel_drv.h"
	36
	37	void
	38	i915_gem_flush(struct drm_device *dev,
	39	uint32_t invalidate_domains,
	40	uint32_t flush_domains)
	41	{
	42	drm_i915_private_t *dev_priv = dev->dev_private;
	43	uint32_t cmd;
	44	RING_LOCALS;
	45
	46	#if WATCH_EXEC
	47	DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
	48	invalidate_domains, flush_domains);
	49	#endif
	50	trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
	51	invalidate_domains, flush_domains);
	52
	53	if (flush_domains & I915_GEM_DOMAIN_CPU)
	54	drm_agp_chipset_flush(dev);
	55
	56	if ((invalidate_domains \| flush_domains) & I915_GEM_GPU_DOMAINS) {
	57	/*
	58	* read/write caches:
	59	*
	60	* I915_GEM_DOMAIN_RENDER is always invalidated, but is
	61	* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
	62	* also flushed at 2d versus 3d pipeline switches.
	63	*
	64	* read-only caches:
65	*
66	* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
67	* MI_READ_FLUSH is set, and is always flushed on 965.
68	*
69	* I915_GEM_DOMAIN_COMMAND may not exist?
70	*
71	* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
72	* invalidated when MI_EXE_FLUSH is set.
73	*
74	* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
75	* invalidated with every MI_FLUSH.
76	*
77	* TLBs:
78	*
79	* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
80	* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
81	* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
82	* are flushed at any MI_FLUSH.
83	*/
84
85	cmd = MI_FLUSH \| MI_NO_WRITE_FLUSH;
86	if ((invalidate_domains\|flush_domains) &
87	I915_GEM_DOMAIN_RENDER)
88	cmd &= ~MI_NO_WRITE_FLUSH;
89	if (!IS_I965G(dev)) {
90	/*
91	* On the 965, the sampler cache always gets flushed
92	* and this bit is reserved.
93	*/
94	if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
95	cmd \|= MI_READ_FLUSH;
96	}
97	if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
98	cmd \|= MI_EXE_FLUSH;
99
100	#if WATCH_EXEC
101	DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
102	#endif
103	BEGIN_LP_RING(2);
104	OUT_RING(cmd);
105	OUT_RING(MI_NOOP);
106	ADVANCE_LP_RING();
107	}
108
109	}
110	#define PIPE_CONTROL_FLUSH(addr) \
111	OUT_RING(GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \| \
112	PIPE_CONTROL_DEPTH_STALL); \
113	OUT_RING(addr \| PIPE_CONTROL_GLOBAL_GTT); \
114	OUT_RING(0); \
115	OUT_RING(0); \
116
117	/**
118	* Creates a new sequence number, emitting a write of it to the status page
119	* plus an interrupt, which will trigger i915_user_interrupt_handler.
120	*
121	* Must be called with struct_lock held.
122	*
123	* Returned sequence numbers are nonzero on success.
124	*/
125	uint32_t
126	i915_ring_add_request(struct drm_device *dev)
127	{
128	drm_i915_private_t *dev_priv = dev->dev_private;
129	uint32_t seqno;
130	RING_LOCALS;
131
132	/* Grab the seqno we're going to make this request be, and bump the
133	* next (skipping 0 so it can be the reserved no-seqno value).
134	*/
135	seqno = dev_priv->mm.next_gem_seqno;
136	dev_priv->mm.next_gem_seqno++;
137	if (dev_priv->mm.next_gem_seqno == 0)
138	dev_priv->mm.next_gem_seqno++;
139
140	if (HAS_PIPE_CONTROL(dev)) {
141	u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
142
143	/*
144	* Workaround qword write incoherence by flushing the
145	* PIPE_NOTIFY buffers out to memory before requesting
146	* an interrupt.
147	*/
148	BEGIN_LP_RING(32);
149	OUT_RING(GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \|
150	PIPE_CONTROL_WC_FLUSH \| PIPE_CONTROL_TC_FLUSH);
151	OUT_RING(dev_priv->seqno_gfx_addr \| PIPE_CONTROL_GLOBAL_GTT);
152	OUT_RING(seqno);
153	OUT_RING(0);
154	PIPE_CONTROL_FLUSH(scratch_addr);
155	scratch_addr += 128; /* write to separate cachelines */
156	PIPE_CONTROL_FLUSH(scratch_addr);
157	scratch_addr += 128;
158	PIPE_CONTROL_FLUSH(scratch_addr);
159	scratch_addr += 128;
160	PIPE_CONTROL_FLUSH(scratch_addr);
161	scratch_addr += 128;
162	PIPE_CONTROL_FLUSH(scratch_addr);
163	scratch_addr += 128;
164	PIPE_CONTROL_FLUSH(scratch_addr);
165	OUT_RING(GFX_OP_PIPE_CONTROL \| PIPE_CONTROL_QW_WRITE \|
166	PIPE_CONTROL_WC_FLUSH \| PIPE_CONTROL_TC_FLUSH \|
167	PIPE_CONTROL_NOTIFY);
168	OUT_RING(dev_priv->seqno_gfx_addr \| PIPE_CONTROL_GLOBAL_GTT);
169	OUT_RING(seqno);
170	OUT_RING(0);
171	ADVANCE_LP_RING();
172	} else {
173	BEGIN_LP_RING(4);
174	OUT_RING(MI_STORE_DWORD_INDEX);
175	OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
176	OUT_RING(seqno);
177
178	OUT_RING(MI_USER_INTERRUPT);
179	ADVANCE_LP_RING();
180	}
181	return seqno;
182	}
183
184	void i915_user_irq_get(struct drm_device *dev)
185	{
186	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
187	unsigned long irqflags;
188
189	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
190	if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
191	if (HAS_PCH_SPLIT(dev))
192	ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
193	else
194	i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
195	}
196	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
197	}
198
199	void i915_user_irq_put(struct drm_device *dev)
200	{
201	drm_i915_private_t dev_priv = (drm_i915_private_t ) dev->dev_private;
202	unsigned long irqflags;
203
204	spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
205	BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
206	if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
207	if (HAS_PCH_SPLIT(dev))
208	ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
209	else
210	i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
211	}
212	spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
213	}
214
215	/** Dispatch a batchbuffer to the ring
216	*/
217	int
218	i915_dispatch_gem_execbuffer(struct drm_device *dev,
219	struct drm_i915_gem_execbuffer2 *exec,
220	struct drm_clip_rect *cliprects,
221	uint64_t exec_offset)
222	{
223	drm_i915_private_t *dev_priv = dev->dev_private;
224	int nbox = exec->num_cliprects;
225	int i = 0, count;
226	uint32_t exec_start, exec_len;
227	RING_LOCALS;
228
229	exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
230	exec_len = (uint32_t) exec->batch_len;
231
232	trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1);
233
234	count = nbox ? nbox : 1;
235
236	for (i = 0; i < count; i++) {
237	if (i < nbox) {
238	int ret = i915_emit_box(dev, cliprects, i,
239	exec->DR1, exec->DR4);
240	if (ret)
241	return ret;
242	}
243
244	if (IS_I830(dev) \|\| IS_845G(dev)) {
245	BEGIN_LP_RING(4);
246	OUT_RING(MI_BATCH_BUFFER);
247	OUT_RING(exec_start \| MI_BATCH_NON_SECURE);
248	OUT_RING(exec_start + exec_len - 4);
249	OUT_RING(0);
250	ADVANCE_LP_RING();
251	} else {
252	BEGIN_LP_RING(2);
253	if (IS_I965G(dev)) {
254	OUT_RING(MI_BATCH_BUFFER_START \|
255	(2 << 6) \|
256	MI_BATCH_NON_SECURE_I965);
257	OUT_RING(exec_start);
258	} else {
259	OUT_RING(MI_BATCH_BUFFER_START \|
260	(2 << 6));
261	OUT_RING(exec_start \| MI_BATCH_NON_SECURE);
262	}
263	ADVANCE_LP_RING();
264	}
265	}
266
267	/* XXX breadcrumb */
268	return 0;
269	}
270
271	static void
272	i915_gem_cleanup_hws(struct drm_device *dev)
273	{
274	drm_i915_private_t *dev_priv = dev->dev_private;
275	struct drm_gem_object *obj;
276	struct drm_i915_gem_object *obj_priv;
277
278	if (dev_priv->hws_obj == NULL)
279	return;
280
281	obj = dev_priv->hws_obj;
282	obj_priv = to_intel_bo(obj);
283
284	kunmap(obj_priv->pages[0]);
285	i915_gem_object_unpin(obj);
286	drm_gem_object_unreference(obj);
287	dev_priv->hws_obj = NULL;
288
289	memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
290	dev_priv->hw_status_page = NULL;
291
292	if (HAS_PIPE_CONTROL(dev))
293	i915_gem_cleanup_pipe_control(dev);
294
295	/* Write high address into HWS_PGA when disabling. */
296	I915_WRITE(HWS_PGA, 0x1ffff000);
297	}
298
299	static int
300	i915_gem_init_hws(struct drm_device *dev)
301	{
302	drm_i915_private_t *dev_priv = dev->dev_private;
303	struct drm_gem_object *obj;
304	struct drm_i915_gem_object *obj_priv;
305	int ret;
306
307	/* If we need a physical address for the status page, it's already
308	* initialized at driver load time.
309	*/
310	if (!I915_NEED_GFX_HWS(dev))
311	return 0;
312
313	obj = i915_gem_alloc_object(dev, 4096);
314	if (obj == NULL) {
315	DRM_ERROR("Failed to allocate status page\n");
316	ret = -ENOMEM;
317	goto err;
318	}
319	obj_priv = to_intel_bo(obj);
320	obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
321
322	ret = i915_gem_object_pin(obj, 4096);
323	if (ret != 0) {
324	drm_gem_object_unreference(obj);
325	goto err_unref;
326	}
327
328	dev_priv->status_gfx_addr = obj_priv->gtt_offset;
329
330	dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
331	if (dev_priv->hw_status_page == NULL) {
332	DRM_ERROR("Failed to map status page.\n");
333	memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
334	ret = -EINVAL;
335	goto err_unpin;
336	}
337
338	if (HAS_PIPE_CONTROL(dev)) {
339	ret = i915_gem_init_pipe_control(dev);
340	if (ret)
341	goto err_unpin;
342	}
343
344	dev_priv->hws_obj = obj;
345	memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
346	if (IS_GEN6(dev)) {
347	I915_WRITE(HWS_PGA_GEN6, dev_priv->status_gfx_addr);
348	I915_READ(HWS_PGA_GEN6); /* posting read */
349	} else {
350	I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
351	I915_READ(HWS_PGA); /* posting read */
352	}
353	DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
354
355	return 0;
356
357	err_unpin:
358	i915_gem_object_unpin(obj);
359	err_unref:
360	drm_gem_object_unreference(obj);
361	err:
362	return 0;
363	}
364
365	int
366	i915_gem_init_ringbuffer(struct drm_device *dev)
367	{
368	drm_i915_private_t *dev_priv = dev->dev_private;
369	struct drm_gem_object *obj;
370	struct drm_i915_gem_object *obj_priv;
371	drm_i915_ring_buffer_t *ring = &dev_priv->ring;
372	int ret;
373	u32 head;
374
375	ret = i915_gem_init_hws(dev);
376	if (ret != 0)
377	return ret;
378
379	obj = i915_gem_alloc_object(dev, 128 * 1024);
380	if (obj == NULL) {
381	DRM_ERROR("Failed to allocate ringbuffer\n");
382	i915_gem_cleanup_hws(dev);
383	return -ENOMEM;
384	}
385	obj_priv = to_intel_bo(obj);
386
387	ret = i915_gem_object_pin(obj, 4096);
388	if (ret != 0) {
389	drm_gem_object_unreference(obj);
390	i915_gem_cleanup_hws(dev);
391	return ret;
392	}
393
394	/* Set up the kernel mapping for the ring. */
395	ring->Size = obj->size;
396
397	ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
398	ring->map.size = obj->size;
399	ring->map.type = 0;
400	ring->map.flags = 0;
401	ring->map.mtrr = 0;
402
403	drm_core_ioremap_wc(&ring->map, dev);
404	if (ring->map.handle == NULL) {
405	DRM_ERROR("Failed to map ringbuffer.\n");
406	memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
407	i915_gem_object_unpin(obj);
408	drm_gem_object_unreference(obj);
409	i915_gem_cleanup_hws(dev);
410	return -EINVAL;
411	}
412	ring->ring_obj = obj;
413	ring->virtual_start = ring->map.handle;
414
415	/* Stop the ring if it's running. */
416	I915_WRITE(PRB0_CTL, 0);
417	I915_WRITE(PRB0_TAIL, 0);
418	I915_WRITE(PRB0_HEAD, 0);
419
420	/* Initialize the ring. */
421	I915_WRITE(PRB0_START, obj_priv->gtt_offset);
422	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
423
424	/* G45 ring initialization fails to reset head to zero */
425	if (head != 0) {
426	DRM_ERROR("Ring head not reset to zero "
427	"ctl %08x head %08x tail %08x start %08x\n",
428	I915_READ(PRB0_CTL),
429	I915_READ(PRB0_HEAD),
430	I915_READ(PRB0_TAIL),
431	I915_READ(PRB0_START));
432	I915_WRITE(PRB0_HEAD, 0);
433
434	DRM_ERROR("Ring head forced to zero "
435	"ctl %08x head %08x tail %08x start %08x\n",
436	I915_READ(PRB0_CTL),
437	I915_READ(PRB0_HEAD),
438	I915_READ(PRB0_TAIL),
439	I915_READ(PRB0_START));
440	}
441
442	I915_WRITE(PRB0_CTL,
443	((obj->size - 4096) & RING_NR_PAGES) \|
444	RING_NO_REPORT \|
445	RING_VALID);
446
447	head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
448
449	/* If the head is still not zero, the ring is dead */
450	if (head != 0) {
451	DRM_ERROR("Ring initialization failed "
452	"ctl %08x head %08x tail %08x start %08x\n",
453	I915_READ(PRB0_CTL),
454	I915_READ(PRB0_HEAD),
455	I915_READ(PRB0_TAIL),
456	I915_READ(PRB0_START));
457	return -EIO;
458	}
459
460	/* Update our cache of the ring state */
461	if (!drm_core_check_feature(dev, DRIVER_MODESET))
462	i915_kernel_lost_context(dev);
463	else {
464	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
465	ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
466	ring->space = ring->head - (ring->tail + 8);
467	if (ring->space < 0)
468	ring->space += ring->Size;
469	}
470
471	if (IS_I9XX(dev) && !IS_GEN3(dev)) {
472	I915_WRITE(MI_MODE,
473	(VS_TIMER_DISPATCH) << 16 \| VS_TIMER_DISPATCH);
474	}
475
476	return 0;
477	}
478
479	void
480	i915_gem_cleanup_ringbuffer(struct drm_device *dev)
481	{
482	drm_i915_private_t *dev_priv = dev->dev_private;
483
484	if (dev_priv->ring.ring_obj == NULL)
485	return;
486
487	drm_core_ioremapfree(&dev_priv->ring.map, dev);
488
489	i915_gem_object_unpin(dev_priv->ring.ring_obj);
490	drm_gem_object_unreference(dev_priv->ring.ring_obj);
491	dev_priv->ring.ring_obj = NULL;
492	memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
493
494	i915_gem_cleanup_hws(dev);
495	}
496
497	/* As a ringbuffer is only allowed to wrap between instructions, fill
498	* the tail with NOOPs.
499	*/
500	int i915_wrap_ring(struct drm_device *dev)
501	{
502	drm_i915_private_t *dev_priv = dev->dev_private;
503	volatile unsigned int *virt;
504	int rem;
505
506	rem = dev_priv->ring.Size - dev_priv->ring.tail;
507	if (dev_priv->ring.space < rem) {
508	int ret = i915_wait_ring(dev, rem, __func__);
509	if (ret)
510	return ret;
511	}
512	dev_priv->ring.space -= rem;
513
514	virt = (unsigned int *)
515	(dev_priv->ring.virtual_start + dev_priv->ring.tail);
516	rem /= 4;
517	while (rem--)
518	*virt++ = MI_NOOP;
519
520	dev_priv->ring.tail = 0;
521
522	return 0;
523	}
524
525	int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
526	{
527	drm_i915_private_t *dev_priv = dev->dev_private;
528	drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
529	u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
530	u32 last_acthd = I915_READ(acthd_reg);
531	u32 acthd;
532	u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
533	int i;
534
535	trace_i915_ring_wait_begin (dev);
536
537	for (i = 0; i < 100000; i++) {
538	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
539	acthd = I915_READ(acthd_reg);
540	ring->space = ring->head - (ring->tail + 8);
541	if (ring->space < 0)
542	ring->space += ring->Size;
543	if (ring->space >= n) {
544	trace_i915_ring_wait_end (dev);
545	return 0;
546	}
547
548	if (dev->primary->master) {
549	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
550	if (master_priv->sarea_priv)
551	master_priv->sarea_priv->perf_boxes \|= I915_BOX_WAIT;
552	}
553
554
555	if (ring->head != last_head)
556	i = 0;
557	if (acthd != last_acthd)
558	i = 0;
559
560	last_head = ring->head;
561	last_acthd = acthd;
562	msleep_interruptible(10);
563
564	}
565
566	trace_i915_ring_wait_end (dev);
567	return -EBUSY;
568	}