Commit | Line | Data |
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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 | 51 | static void |
78501eac | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
53 | u32 invalidate_domains, |
54 | u32 flush_domains) | |
62fdfeaf | 55 | { |
78501eac | 56 | struct drm_device *dev = ring->dev; |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
112 | #if WATCH_EXEC | |
113 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
114 | #endif | |
78501eac CW |
115 | intel_ring_begin(ring, 2); |
116 | intel_ring_emit(ring, cmd); | |
117 | intel_ring_emit(ring, MI_NOOP); | |
118 | intel_ring_advance(ring); | |
62fdfeaf | 119 | } |
8187a2b7 ZN |
120 | } |
121 | ||
78501eac | 122 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 123 | u32 value) |
d46eefa2 | 124 | { |
78501eac | 125 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 126 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
127 | } |
128 | ||
78501eac | 129 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 130 | { |
78501eac CW |
131 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
132 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 133 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
134 | |
135 | return I915_READ(acthd_reg); | |
136 | } | |
137 | ||
78501eac | 138 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 139 | { |
78501eac CW |
140 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
141 | struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object); | |
8187a2b7 | 142 | u32 head; |
8187a2b7 ZN |
143 | |
144 | /* Stop the ring if it's running. */ | |
7f2ab699 | 145 | I915_WRITE_CTL(ring, 0); |
570ef608 | 146 | I915_WRITE_HEAD(ring, 0); |
78501eac | 147 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
148 | |
149 | /* Initialize the ring. */ | |
6c0e1c55 | 150 | I915_WRITE_START(ring, obj_priv->gtt_offset); |
570ef608 | 151 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
152 | |
153 | /* G45 ring initialization fails to reset head to zero */ | |
154 | if (head != 0) { | |
155 | DRM_ERROR("%s head not reset to zero " | |
156 | "ctl %08x head %08x tail %08x start %08x\n", | |
157 | ring->name, | |
7f2ab699 | 158 | I915_READ_CTL(ring), |
570ef608 | 159 | I915_READ_HEAD(ring), |
870e86dd | 160 | I915_READ_TAIL(ring), |
6c0e1c55 | 161 | I915_READ_START(ring)); |
8187a2b7 | 162 | |
570ef608 | 163 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
164 | |
165 | DRM_ERROR("%s head forced to zero " | |
166 | "ctl %08x head %08x tail %08x start %08x\n", | |
167 | ring->name, | |
7f2ab699 | 168 | I915_READ_CTL(ring), |
570ef608 | 169 | I915_READ_HEAD(ring), |
870e86dd | 170 | I915_READ_TAIL(ring), |
6c0e1c55 | 171 | I915_READ_START(ring)); |
8187a2b7 ZN |
172 | } |
173 | ||
7f2ab699 | 174 | I915_WRITE_CTL(ring, |
8187a2b7 ZN |
175 | ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES) |
176 | | RING_NO_REPORT | RING_VALID); | |
177 | ||
570ef608 | 178 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
179 | /* If the head is still not zero, the ring is dead */ |
180 | if (head != 0) { | |
181 | DRM_ERROR("%s initialization failed " | |
182 | "ctl %08x head %08x tail %08x start %08x\n", | |
183 | ring->name, | |
7f2ab699 | 184 | I915_READ_CTL(ring), |
570ef608 | 185 | I915_READ_HEAD(ring), |
870e86dd | 186 | I915_READ_TAIL(ring), |
6c0e1c55 | 187 | I915_READ_START(ring)); |
8187a2b7 ZN |
188 | return -EIO; |
189 | } | |
190 | ||
78501eac CW |
191 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
192 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 193 | else { |
570ef608 | 194 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 195 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
196 | ring->space = ring->head - (ring->tail + 8); |
197 | if (ring->space < 0) | |
198 | ring->space += ring->size; | |
199 | } | |
200 | return 0; | |
201 | } | |
202 | ||
78501eac | 203 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 204 | { |
78501eac CW |
205 | struct drm_device *dev = ring->dev; |
206 | int ret = init_ring_common(ring); | |
a69ffdbf | 207 | |
a6c45cf0 | 208 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac CW |
209 | drm_i915_private_t *dev_priv = dev->dev_private; |
210 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; | |
a69ffdbf ZW |
211 | if (IS_GEN6(dev)) |
212 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
213 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 | 214 | } |
78501eac | 215 | |
8187a2b7 ZN |
216 | return ret; |
217 | } | |
218 | ||
78501eac | 219 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
8187a2b7 | 220 | do { \ |
78501eac | 221 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 222 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
78501eac CW |
223 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
224 | intel_ring_emit(ring__, 0); \ | |
225 | intel_ring_emit(ring__, 0); \ | |
8187a2b7 | 226 | } while (0) |
62fdfeaf EA |
227 | |
228 | /** | |
229 | * Creates a new sequence number, emitting a write of it to the status page | |
230 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
231 | * | |
232 | * Must be called with struct_lock held. | |
233 | * | |
234 | * Returned sequence numbers are nonzero on success. | |
235 | */ | |
8187a2b7 | 236 | static u32 |
78501eac | 237 | render_ring_add_request(struct intel_ring_buffer *ring, |
ab6f8e32 | 238 | u32 flush_domains) |
62fdfeaf | 239 | { |
78501eac | 240 | struct drm_device *dev = ring->dev; |
62fdfeaf | 241 | drm_i915_private_t *dev_priv = dev->dev_private; |
6f392d54 CW |
242 | u32 seqno; |
243 | ||
244 | seqno = i915_gem_get_seqno(dev); | |
ca76482e ZW |
245 | |
246 | if (IS_GEN6(dev)) { | |
78501eac CW |
247 | intel_ring_begin(ring, 6); |
248 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3); | |
249 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE | | |
ca76482e ZW |
250 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | |
251 | PIPE_CONTROL_NOTIFY); | |
78501eac CW |
252 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); |
253 | intel_ring_emit(ring, seqno); | |
254 | intel_ring_emit(ring, 0); | |
255 | intel_ring_emit(ring, 0); | |
256 | intel_ring_advance(ring); | |
ca76482e | 257 | } else if (HAS_PIPE_CONTROL(dev)) { |
62fdfeaf EA |
258 | u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; |
259 | ||
260 | /* | |
261 | * Workaround qword write incoherence by flushing the | |
262 | * PIPE_NOTIFY buffers out to memory before requesting | |
263 | * an interrupt. | |
264 | */ | |
78501eac CW |
265 | intel_ring_begin(ring, 32); |
266 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
62fdfeaf | 267 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
78501eac CW |
268 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); |
269 | intel_ring_emit(ring, seqno); | |
270 | intel_ring_emit(ring, 0); | |
271 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
62fdfeaf | 272 | scratch_addr += 128; /* write to separate cachelines */ |
78501eac | 273 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
62fdfeaf | 274 | scratch_addr += 128; |
78501eac | 275 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
62fdfeaf | 276 | scratch_addr += 128; |
78501eac | 277 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
62fdfeaf | 278 | scratch_addr += 128; |
78501eac | 279 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
62fdfeaf | 280 | scratch_addr += 128; |
78501eac CW |
281 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
282 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
62fdfeaf EA |
283 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
284 | PIPE_CONTROL_NOTIFY); | |
78501eac CW |
285 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); |
286 | intel_ring_emit(ring, seqno); | |
287 | intel_ring_emit(ring, 0); | |
288 | intel_ring_advance(ring); | |
62fdfeaf | 289 | } else { |
78501eac CW |
290 | intel_ring_begin(ring, 4); |
291 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
292 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
293 | intel_ring_emit(ring, seqno); | |
62fdfeaf | 294 | |
78501eac CW |
295 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
296 | intel_ring_advance(ring); | |
62fdfeaf EA |
297 | } |
298 | return seqno; | |
299 | } | |
300 | ||
8187a2b7 | 301 | static u32 |
78501eac | 302 | render_ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 303 | { |
78501eac | 304 | struct drm_device *dev = ring->dev; |
8187a2b7 ZN |
305 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
306 | if (HAS_PIPE_CONTROL(dev)) | |
307 | return ((volatile u32 *)(dev_priv->seqno_page))[0]; | |
308 | else | |
309 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
310 | } | |
311 | ||
312 | static void | |
78501eac | 313 | render_ring_get_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 314 | { |
78501eac | 315 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
316 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
317 | unsigned long irqflags; | |
318 | ||
319 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 320 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
321 | if (HAS_PCH_SPLIT(dev)) |
322 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
323 | else | |
324 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
325 | } | |
326 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
327 | } | |
328 | ||
8187a2b7 | 329 | static void |
78501eac | 330 | render_ring_put_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 331 | { |
78501eac | 332 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
333 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
334 | unsigned long irqflags; | |
335 | ||
336 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
337 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
338 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
339 | if (HAS_PCH_SPLIT(dev)) |
340 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
341 | else | |
342 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
343 | } | |
344 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
345 | } | |
346 | ||
78501eac | 347 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 348 | { |
78501eac CW |
349 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
350 | u32 mmio = IS_GEN6(ring->dev) ? | |
351 | RING_HWS_PGA_GEN6(ring->mmio_base) : | |
352 | RING_HWS_PGA(ring->mmio_base); | |
353 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
354 | POSTING_READ(mmio); | |
8187a2b7 ZN |
355 | } |
356 | ||
ab6f8e32 | 357 | static void |
78501eac CW |
358 | bsd_ring_flush(struct intel_ring_buffer *ring, |
359 | u32 invalidate_domains, | |
360 | u32 flush_domains) | |
d1b851fc | 361 | { |
78501eac CW |
362 | intel_ring_begin(ring, 2); |
363 | intel_ring_emit(ring, MI_FLUSH); | |
364 | intel_ring_emit(ring, MI_NOOP); | |
365 | intel_ring_advance(ring); | |
d1b851fc ZN |
366 | } |
367 | ||
368 | static u32 | |
78501eac | 369 | ring_add_request(struct intel_ring_buffer *ring, |
549f7365 | 370 | u32 flush_domains) |
d1b851fc ZN |
371 | { |
372 | u32 seqno; | |
6f392d54 | 373 | |
78501eac | 374 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 375 | |
78501eac CW |
376 | intel_ring_begin(ring, 4); |
377 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
378 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
379 | intel_ring_emit(ring, seqno); | |
380 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
381 | intel_ring_advance(ring); | |
d1b851fc ZN |
382 | |
383 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
384 | ||
385 | return seqno; | |
386 | } | |
387 | ||
d1b851fc | 388 | static void |
78501eac | 389 | bsd_ring_get_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
390 | { |
391 | /* do nothing */ | |
392 | } | |
393 | static void | |
78501eac | 394 | bsd_ring_put_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
395 | { |
396 | /* do nothing */ | |
397 | } | |
398 | ||
399 | static u32 | |
78501eac | 400 | ring_status_page_get_seqno(struct intel_ring_buffer *ring) |
d1b851fc ZN |
401 | { |
402 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
403 | } | |
404 | ||
405 | static int | |
78501eac CW |
406 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
407 | struct drm_i915_gem_execbuffer2 *exec, | |
408 | struct drm_clip_rect *cliprects, | |
409 | uint64_t exec_offset) | |
d1b851fc ZN |
410 | { |
411 | uint32_t exec_start; | |
78501eac | 412 | |
d1b851fc | 413 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
78501eac CW |
414 | |
415 | intel_ring_begin(ring, 2); | |
416 | intel_ring_emit(ring, | |
417 | MI_BATCH_BUFFER_START | | |
418 | (2 << 6) | | |
419 | MI_BATCH_NON_SECURE_I965); | |
420 | intel_ring_emit(ring, exec_start); | |
421 | intel_ring_advance(ring); | |
422 | ||
d1b851fc ZN |
423 | return 0; |
424 | } | |
425 | ||
8187a2b7 | 426 | static int |
78501eac CW |
427 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
428 | struct drm_i915_gem_execbuffer2 *exec, | |
429 | struct drm_clip_rect *cliprects, | |
430 | uint64_t exec_offset) | |
62fdfeaf | 431 | { |
78501eac | 432 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
433 | drm_i915_private_t *dev_priv = dev->dev_private; |
434 | int nbox = exec->num_cliprects; | |
435 | int i = 0, count; | |
436 | uint32_t exec_start, exec_len; | |
78501eac | 437 | |
62fdfeaf EA |
438 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
439 | exec_len = (uint32_t) exec->batch_len; | |
440 | ||
6f392d54 | 441 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf EA |
442 | |
443 | count = nbox ? nbox : 1; | |
444 | ||
445 | for (i = 0; i < count; i++) { | |
446 | if (i < nbox) { | |
447 | int ret = i915_emit_box(dev, cliprects, i, | |
448 | exec->DR1, exec->DR4); | |
449 | if (ret) | |
450 | return ret; | |
451 | } | |
452 | ||
453 | if (IS_I830(dev) || IS_845G(dev)) { | |
78501eac CW |
454 | intel_ring_begin(ring, 4); |
455 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
456 | intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE); | |
457 | intel_ring_emit(ring, exec_start + exec_len - 4); | |
458 | intel_ring_emit(ring, 0); | |
62fdfeaf | 459 | } else { |
78501eac | 460 | intel_ring_begin(ring, 2); |
a6c45cf0 | 461 | if (INTEL_INFO(dev)->gen >= 4) { |
78501eac | 462 | intel_ring_emit(ring, |
8187a2b7 ZN |
463 | MI_BATCH_BUFFER_START | (2 << 6) |
464 | | MI_BATCH_NON_SECURE_I965); | |
78501eac | 465 | intel_ring_emit(ring, exec_start); |
62fdfeaf | 466 | } else { |
78501eac | 467 | intel_ring_emit(ring, MI_BATCH_BUFFER_START |
8187a2b7 | 468 | | (2 << 6)); |
78501eac | 469 | intel_ring_emit(ring, exec_start | |
8187a2b7 | 470 | MI_BATCH_NON_SECURE); |
62fdfeaf | 471 | } |
62fdfeaf | 472 | } |
78501eac | 473 | intel_ring_advance(ring); |
62fdfeaf EA |
474 | } |
475 | ||
f00a3ddf | 476 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
78501eac CW |
477 | intel_ring_begin(ring, 2); |
478 | intel_ring_emit(ring, MI_FLUSH | | |
1cafd347 ZN |
479 | MI_NO_WRITE_FLUSH | |
480 | MI_INVALIDATE_ISP ); | |
78501eac CW |
481 | intel_ring_emit(ring, MI_NOOP); |
482 | intel_ring_advance(ring); | |
1cafd347 | 483 | } |
62fdfeaf | 484 | /* XXX breadcrumb */ |
1cafd347 | 485 | |
62fdfeaf EA |
486 | return 0; |
487 | } | |
488 | ||
78501eac | 489 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 490 | { |
78501eac | 491 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
62fdfeaf EA |
492 | struct drm_gem_object *obj; |
493 | struct drm_i915_gem_object *obj_priv; | |
494 | ||
8187a2b7 ZN |
495 | obj = ring->status_page.obj; |
496 | if (obj == NULL) | |
62fdfeaf | 497 | return; |
62fdfeaf EA |
498 | obj_priv = to_intel_bo(obj); |
499 | ||
500 | kunmap(obj_priv->pages[0]); | |
501 | i915_gem_object_unpin(obj); | |
502 | drm_gem_object_unreference(obj); | |
8187a2b7 | 503 | ring->status_page.obj = NULL; |
62fdfeaf EA |
504 | |
505 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
506 | } |
507 | ||
78501eac | 508 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 509 | { |
78501eac | 510 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
511 | drm_i915_private_t *dev_priv = dev->dev_private; |
512 | struct drm_gem_object *obj; | |
513 | struct drm_i915_gem_object *obj_priv; | |
514 | int ret; | |
515 | ||
62fdfeaf EA |
516 | obj = i915_gem_alloc_object(dev, 4096); |
517 | if (obj == NULL) { | |
518 | DRM_ERROR("Failed to allocate status page\n"); | |
519 | ret = -ENOMEM; | |
520 | goto err; | |
521 | } | |
522 | obj_priv = to_intel_bo(obj); | |
523 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
524 | ||
525 | ret = i915_gem_object_pin(obj, 4096); | |
526 | if (ret != 0) { | |
62fdfeaf EA |
527 | goto err_unref; |
528 | } | |
529 | ||
8187a2b7 ZN |
530 | ring->status_page.gfx_addr = obj_priv->gtt_offset; |
531 | ring->status_page.page_addr = kmap(obj_priv->pages[0]); | |
532 | if (ring->status_page.page_addr == NULL) { | |
62fdfeaf | 533 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
534 | goto err_unpin; |
535 | } | |
8187a2b7 ZN |
536 | ring->status_page.obj = obj; |
537 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 538 | |
78501eac | 539 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
540 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
541 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
542 | |
543 | return 0; | |
544 | ||
545 | err_unpin: | |
546 | i915_gem_object_unpin(obj); | |
547 | err_unref: | |
548 | drm_gem_object_unreference(obj); | |
549 | err: | |
8187a2b7 | 550 | return ret; |
62fdfeaf EA |
551 | } |
552 | ||
8187a2b7 | 553 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 554 | struct intel_ring_buffer *ring) |
62fdfeaf | 555 | { |
870e86dd | 556 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 ZN |
557 | struct drm_i915_gem_object *obj_priv; |
558 | struct drm_gem_object *obj; | |
dd785e35 CW |
559 | int ret; |
560 | ||
8187a2b7 | 561 | ring->dev = dev; |
23bc5982 CW |
562 | INIT_LIST_HEAD(&ring->active_list); |
563 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 564 | INIT_LIST_HEAD(&ring->gpu_write_list); |
62fdfeaf | 565 | |
8187a2b7 | 566 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 567 | ret = init_status_page(ring); |
8187a2b7 ZN |
568 | if (ret) |
569 | return ret; | |
570 | } | |
62fdfeaf | 571 | |
8187a2b7 | 572 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
573 | if (obj == NULL) { |
574 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 575 | ret = -ENOMEM; |
dd785e35 | 576 | goto err_hws; |
62fdfeaf | 577 | } |
62fdfeaf | 578 | |
8187a2b7 ZN |
579 | ring->gem_object = obj; |
580 | ||
a9db5c8f | 581 | ret = i915_gem_object_pin(obj, PAGE_SIZE); |
dd785e35 CW |
582 | if (ret) |
583 | goto err_unref; | |
62fdfeaf | 584 | |
8187a2b7 ZN |
585 | obj_priv = to_intel_bo(obj); |
586 | ring->map.size = ring->size; | |
62fdfeaf | 587 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
62fdfeaf EA |
588 | ring->map.type = 0; |
589 | ring->map.flags = 0; | |
590 | ring->map.mtrr = 0; | |
591 | ||
592 | drm_core_ioremap_wc(&ring->map, dev); | |
593 | if (ring->map.handle == NULL) { | |
594 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 595 | ret = -EINVAL; |
dd785e35 | 596 | goto err_unpin; |
62fdfeaf EA |
597 | } |
598 | ||
8187a2b7 | 599 | ring->virtual_start = ring->map.handle; |
78501eac | 600 | ret = ring->init(ring); |
dd785e35 CW |
601 | if (ret) |
602 | goto err_unmap; | |
62fdfeaf | 603 | |
62fdfeaf EA |
604 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
605 | i915_kernel_lost_context(dev); | |
606 | else { | |
570ef608 | 607 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 608 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
62fdfeaf EA |
609 | ring->space = ring->head - (ring->tail + 8); |
610 | if (ring->space < 0) | |
8187a2b7 | 611 | ring->space += ring->size; |
62fdfeaf | 612 | } |
8187a2b7 | 613 | return ret; |
dd785e35 CW |
614 | |
615 | err_unmap: | |
616 | drm_core_ioremapfree(&ring->map, dev); | |
617 | err_unpin: | |
618 | i915_gem_object_unpin(obj); | |
619 | err_unref: | |
620 | drm_gem_object_unreference(obj); | |
621 | ring->gem_object = NULL; | |
622 | err_hws: | |
78501eac | 623 | cleanup_status_page(ring); |
8187a2b7 | 624 | return ret; |
62fdfeaf EA |
625 | } |
626 | ||
78501eac | 627 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 628 | { |
8187a2b7 | 629 | if (ring->gem_object == NULL) |
62fdfeaf EA |
630 | return; |
631 | ||
78501eac | 632 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 633 | |
8187a2b7 ZN |
634 | i915_gem_object_unpin(ring->gem_object); |
635 | drm_gem_object_unreference(ring->gem_object); | |
636 | ring->gem_object = NULL; | |
78501eac CW |
637 | |
638 | cleanup_status_page(ring); | |
62fdfeaf EA |
639 | } |
640 | ||
78501eac | 641 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 642 | { |
8187a2b7 | 643 | unsigned int *virt; |
62fdfeaf | 644 | int rem; |
8187a2b7 | 645 | rem = ring->size - ring->tail; |
62fdfeaf | 646 | |
8187a2b7 | 647 | if (ring->space < rem) { |
78501eac | 648 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
649 | if (ret) |
650 | return ret; | |
651 | } | |
62fdfeaf | 652 | |
8187a2b7 | 653 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
654 | rem /= 8; |
655 | while (rem--) { | |
62fdfeaf | 656 | *virt++ = MI_NOOP; |
1741dd4a CW |
657 | *virt++ = MI_NOOP; |
658 | } | |
62fdfeaf | 659 | |
8187a2b7 | 660 | ring->tail = 0; |
43ed340a | 661 | ring->space = ring->head - 8; |
62fdfeaf EA |
662 | |
663 | return 0; | |
664 | } | |
665 | ||
78501eac | 666 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 667 | { |
78501eac | 668 | struct drm_device *dev = ring->dev; |
570ef608 | 669 | drm_i915_private_t *dev_priv = dev->dev_private; |
78501eac | 670 | unsigned long end; |
62fdfeaf EA |
671 | |
672 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
673 | end = jiffies + 3 * HZ; |
674 | do { | |
570ef608 | 675 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
676 | ring->space = ring->head - (ring->tail + 8); |
677 | if (ring->space < 0) | |
8187a2b7 | 678 | ring->space += ring->size; |
62fdfeaf | 679 | if (ring->space >= n) { |
78501eac | 680 | trace_i915_ring_wait_end(dev); |
62fdfeaf EA |
681 | return 0; |
682 | } | |
683 | ||
684 | if (dev->primary->master) { | |
685 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
686 | if (master_priv->sarea_priv) | |
687 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
688 | } | |
d1b851fc | 689 | |
e60a0b10 | 690 | msleep(1); |
8187a2b7 ZN |
691 | } while (!time_after(jiffies, end)); |
692 | trace_i915_ring_wait_end (dev); | |
693 | return -EBUSY; | |
694 | } | |
62fdfeaf | 695 | |
78501eac | 696 | void intel_ring_begin(struct intel_ring_buffer *ring, |
ab6f8e32 | 697 | int num_dwords) |
8187a2b7 | 698 | { |
be26a10b | 699 | int n = 4*num_dwords; |
78501eac | 700 | |
8187a2b7 | 701 | if (unlikely(ring->tail + n > ring->size)) |
78501eac CW |
702 | intel_wrap_ring_buffer(ring); |
703 | ||
8187a2b7 | 704 | if (unlikely(ring->space < n)) |
78501eac | 705 | intel_wait_ring_buffer(ring, n); |
d97ed339 CW |
706 | |
707 | ring->space -= n; | |
8187a2b7 | 708 | } |
62fdfeaf | 709 | |
78501eac | 710 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 711 | { |
d97ed339 | 712 | ring->tail &= ring->size - 1; |
78501eac | 713 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 714 | } |
62fdfeaf | 715 | |
e070868e | 716 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 717 | .name = "render ring", |
9220434a | 718 | .id = RING_RENDER, |
333e9fe9 | 719 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 720 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 721 | .init = init_render_ring, |
297b0c5b | 722 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
723 | .flush = render_ring_flush, |
724 | .add_request = render_ring_add_request, | |
f787a5f5 | 725 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
726 | .user_irq_get = render_ring_get_user_irq, |
727 | .user_irq_put = render_ring_put_user_irq, | |
78501eac | 728 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
8187a2b7 | 729 | }; |
d1b851fc ZN |
730 | |
731 | /* ring buffer for bit-stream decoder */ | |
732 | ||
e070868e | 733 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 734 | .name = "bsd ring", |
9220434a | 735 | .id = RING_BSD, |
333e9fe9 | 736 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 737 | .size = 32 * PAGE_SIZE, |
78501eac | 738 | .init = init_ring_common, |
297b0c5b | 739 | .write_tail = ring_write_tail, |
d1b851fc | 740 | .flush = bsd_ring_flush, |
549f7365 CW |
741 | .add_request = ring_add_request, |
742 | .get_seqno = ring_status_page_get_seqno, | |
d1b851fc ZN |
743 | .user_irq_get = bsd_ring_get_user_irq, |
744 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 745 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 746 | }; |
5c1143bb | 747 | |
881f47b6 | 748 | |
78501eac | 749 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 750 | u32 value) |
881f47b6 | 751 | { |
78501eac | 752 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
753 | |
754 | /* Every tail move must follow the sequence below */ | |
755 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
756 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
757 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
758 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
759 | ||
760 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
761 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
762 | 50)) | |
763 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
764 | ||
870e86dd | 765 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
766 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
767 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
768 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
769 | } | |
770 | ||
78501eac | 771 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
549f7365 CW |
772 | u32 invalidate_domains, |
773 | u32 flush_domains) | |
881f47b6 | 774 | { |
78501eac CW |
775 | intel_ring_begin(ring, 4); |
776 | intel_ring_emit(ring, MI_FLUSH_DW); | |
777 | intel_ring_emit(ring, 0); | |
778 | intel_ring_emit(ring, 0); | |
779 | intel_ring_emit(ring, 0); | |
780 | intel_ring_advance(ring); | |
881f47b6 XH |
781 | } |
782 | ||
783 | static int | |
78501eac CW |
784 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
785 | struct drm_i915_gem_execbuffer2 *exec, | |
786 | struct drm_clip_rect *cliprects, | |
787 | uint64_t exec_offset) | |
881f47b6 XH |
788 | { |
789 | uint32_t exec_start; | |
ab6f8e32 | 790 | |
881f47b6 | 791 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
ab6f8e32 | 792 | |
78501eac CW |
793 | intel_ring_begin(ring, 2); |
794 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); | |
ab6f8e32 | 795 | /* bit0-7 is the length on GEN6+ */ |
78501eac CW |
796 | intel_ring_emit(ring, exec_start); |
797 | intel_ring_advance(ring); | |
ab6f8e32 | 798 | |
881f47b6 XH |
799 | return 0; |
800 | } | |
801 | ||
802 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 803 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
804 | .name = "gen6 bsd ring", |
805 | .id = RING_BSD, | |
333e9fe9 | 806 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 807 | .size = 32 * PAGE_SIZE, |
78501eac | 808 | .init = init_ring_common, |
297b0c5b | 809 | .write_tail = gen6_bsd_ring_write_tail, |
549f7365 CW |
810 | .flush = gen6_ring_flush, |
811 | .add_request = ring_add_request, | |
812 | .get_seqno = ring_status_page_get_seqno, | |
881f47b6 XH |
813 | .user_irq_get = bsd_ring_get_user_irq, |
814 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 815 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
549f7365 CW |
816 | }; |
817 | ||
818 | /* Blitter support (SandyBridge+) */ | |
819 | ||
820 | static void | |
78501eac | 821 | blt_ring_get_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
822 | { |
823 | /* do nothing */ | |
824 | } | |
825 | static void | |
78501eac | 826 | blt_ring_put_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
827 | { |
828 | /* do nothing */ | |
829 | } | |
830 | ||
831 | static const struct intel_ring_buffer gen6_blt_ring = { | |
832 | .name = "blt ring", | |
833 | .id = RING_BLT, | |
834 | .mmio_base = BLT_RING_BASE, | |
835 | .size = 32 * PAGE_SIZE, | |
836 | .init = init_ring_common, | |
297b0c5b | 837 | .write_tail = ring_write_tail, |
549f7365 CW |
838 | .flush = gen6_ring_flush, |
839 | .add_request = ring_add_request, | |
840 | .get_seqno = ring_status_page_get_seqno, | |
841 | .user_irq_get = blt_ring_get_user_irq, | |
842 | .user_irq_put = blt_ring_put_user_irq, | |
78501eac | 843 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
881f47b6 XH |
844 | }; |
845 | ||
5c1143bb XH |
846 | int intel_init_render_ring_buffer(struct drm_device *dev) |
847 | { | |
848 | drm_i915_private_t *dev_priv = dev->dev_private; | |
849 | ||
850 | dev_priv->render_ring = render_ring; | |
851 | ||
852 | if (!I915_NEED_GFX_HWS(dev)) { | |
853 | dev_priv->render_ring.status_page.page_addr | |
854 | = dev_priv->status_page_dmah->vaddr; | |
855 | memset(dev_priv->render_ring.status_page.page_addr, | |
856 | 0, PAGE_SIZE); | |
857 | } | |
858 | ||
859 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
860 | } | |
861 | ||
862 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
863 | { | |
864 | drm_i915_private_t *dev_priv = dev->dev_private; | |
865 | ||
881f47b6 XH |
866 | if (IS_GEN6(dev)) |
867 | dev_priv->bsd_ring = gen6_bsd_ring; | |
868 | else | |
869 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
870 | |
871 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
872 | } | |
549f7365 CW |
873 | |
874 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
875 | { | |
876 | drm_i915_private_t *dev_priv = dev->dev_private; | |
877 | ||
878 | dev_priv->blt_ring = gen6_blt_ring; | |
879 | ||
880 | return intel_init_ring_buffer(dev, &dev_priv->blt_ring); | |
881 | } |