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drm/i915/kbl: Add WaEnableGapsTsvCreditFix
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
a4d8a0fe 30#include <linux/log2.h>
760285e7 31#include <drm/drmP.h>
62fdfeaf 32#include "i915_drv.h"
760285e7 33#include <drm/i915_drm.h>
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
82e104cc 37int __intel_ring_space(int head, int tail, int size)
c7dca47b 38{
4f54741e
DG		 39 int space = head - tail;
40 if (space <= 0)
1cf0ba14 41 space += size;
4f54741e 42 return space - I915_RING_FREE_SPACE;
c7dca47b
CW		 43}
44
ebd0fd4b
DG		 45void intel_ring_update_space(struct intel_ringbuffer *ringbuf)
46{
47 if (ringbuf->last_retired_head != -1) {
48 ringbuf->head = ringbuf->last_retired_head;
49 ringbuf->last_retired_head = -1;
50 }
51
52 ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR,
53 ringbuf->tail, ringbuf->size);
54}
55
117897f4 56bool intel_engine_stopped(struct intel_engine_cs *engine)
09246732 57{
0bc40be8 58 struct drm_i915_private *dev_priv = engine->dev->dev_private;
666796da 59 return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
88b4aa87 60}
09246732 61
0bc40be8 62static void __intel_ring_advance(struct intel_engine_cs *engine)
88b4aa87 63{
0bc40be8 64 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 65 ringbuf->tail &= ringbuf->size - 1;
117897f4 66 if (intel_engine_stopped(engine))
09246732 67 return;
0bc40be8 68 engine->write_tail(engine, ringbuf->tail);
09246732
CW		 69}
70
b72f3acb 71static int
a84c3ae1 72gen2_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 73 u32 invalidate_domains,
74 u32 flush_domains)
75{
4a570db5 76 struct intel_engine_cs *engine = req->engine;
46f0f8d1
CW		 77 u32 cmd;
78 int ret;
79
80 cmd = MI_FLUSH;
31b14c9f 81 if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
46f0f8d1
CW		 82 cmd |= MI_NO_WRITE_FLUSH;
83
84 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
85 cmd |= MI_READ_FLUSH;
86
5fb9de1a 87 ret = intel_ring_begin(req, 2);
46f0f8d1
CW		 88 if (ret)
89 return ret;
90
e2f80391
TU		 91 intel_ring_emit(engine, cmd);
92 intel_ring_emit(engine, MI_NOOP);
93 intel_ring_advance(engine);
46f0f8d1
CW		 94
95 return 0;
96}
97
98static int
a84c3ae1 99gen4_render_ring_flush(struct drm_i915_gem_request *req,
46f0f8d1
CW		 100 u32 invalidate_domains,
101 u32 flush_domains)
62fdfeaf 102{
4a570db5 103 struct intel_engine_cs *engine = req->engine;
e2f80391 104 struct drm_device *dev = engine->dev;
6f392d54 105 u32 cmd;
b72f3acb 106 int ret;
6f392d54 107
36d527de
CW		 108 /*
109 * read/write caches:
110 *
111 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
112 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
113 * also flushed at 2d versus 3d pipeline switches.
114 *
115 * read-only caches:
116 *
117 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
118 * MI_READ_FLUSH is set, and is always flushed on 965.
119 *
120 * I915_GEM_DOMAIN_COMMAND may not exist?
121 *
122 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
123 * invalidated when MI_EXE_FLUSH is set.
124 *
125 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
126 * invalidated with every MI_FLUSH.
127 *
128 * TLBs:
129 *
130 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
131 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
132 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
133 * are flushed at any MI_FLUSH.
134 */
135
136 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
46f0f8d1 137 if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
36d527de 138 cmd &= ~MI_NO_WRITE_FLUSH;
36d527de
CW		 139 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
140 cmd |= MI_EXE_FLUSH;
62fdfeaf 141
36d527de
CW		 142 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
143 (IS_G4X(dev) || IS_GEN5(dev)))
144 cmd |= MI_INVALIDATE_ISP;
70eac33e 145
5fb9de1a 146 ret = intel_ring_begin(req, 2);
36d527de
CW		 147 if (ret)
148 return ret;
b72f3acb 149
e2f80391
TU		 150 intel_ring_emit(engine, cmd);
151 intel_ring_emit(engine, MI_NOOP);
152 intel_ring_advance(engine);
b72f3acb
CW		 153
154 return 0;
8187a2b7
ZN		 155}
156
8d315287
JB		 157/**
158 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
159 * implementing two workarounds on gen6. From section 1.4.7.1
160 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
161 *
162 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
163 * produced by non-pipelined state commands), software needs to first
164 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
165 * 0.
166 *
167 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
168 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
169 *
170 * And the workaround for these two requires this workaround first:
171 *
172 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
173 * BEFORE the pipe-control with a post-sync op and no write-cache
174 * flushes.
175 *
176 * And this last workaround is tricky because of the requirements on
177 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
178 * volume 2 part 1:
179 *
180 * "1 of the following must also be set:
181 * - Render Target Cache Flush Enable ([12] of DW1)
182 * - Depth Cache Flush Enable ([0] of DW1)
183 * - Stall at Pixel Scoreboard ([1] of DW1)
184 * - Depth Stall ([13] of DW1)
185 * - Post-Sync Operation ([13] of DW1)
186 * - Notify Enable ([8] of DW1)"
187 *
188 * The cache flushes require the workaround flush that triggered this
189 * one, so we can't use it. Depth stall would trigger the same.
190 * Post-sync nonzero is what triggered this second workaround, so we
191 * can't use that one either. Notify enable is IRQs, which aren't
192 * really our business. That leaves only stall at scoreboard.
193 */
194static int
f2cf1fcc 195intel_emit_post_sync_nonzero_flush(struct drm_i915_gem_request *req)
8d315287 196{
4a570db5 197 struct intel_engine_cs *engine = req->engine;
e2f80391 198 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 199 int ret;
200
5fb9de1a 201 ret = intel_ring_begin(req, 6);
8d315287
JB		 202 if (ret)
203 return ret;
204
e2f80391
TU		 205 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
206 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
8d315287 207 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 208 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
209 intel_ring_emit(engine, 0); /* low dword */
210 intel_ring_emit(engine, 0); /* high dword */
211 intel_ring_emit(engine, MI_NOOP);
212 intel_ring_advance(engine);
8d315287 213
5fb9de1a 214 ret = intel_ring_begin(req, 6);
8d315287
JB		 215 if (ret)
216 return ret;
217
e2f80391
TU		 218 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(5));
219 intel_ring_emit(engine, PIPE_CONTROL_QW_WRITE);
220 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
221 intel_ring_emit(engine, 0);
222 intel_ring_emit(engine, 0);
223 intel_ring_emit(engine, MI_NOOP);
224 intel_ring_advance(engine);
8d315287
JB		 225
226 return 0;
227}
228
229static int
a84c3ae1
JH		 230gen6_render_ring_flush(struct drm_i915_gem_request *req,
231 u32 invalidate_domains, u32 flush_domains)
8d315287 232{
4a570db5 233 struct intel_engine_cs *engine = req->engine;
8d315287 234 u32 flags = 0;
e2f80391 235 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
8d315287
JB		 236 int ret;
237
b3111509 238 /* Force SNB workarounds for PIPE_CONTROL flushes */
f2cf1fcc 239 ret = intel_emit_post_sync_nonzero_flush(req);
b3111509
PZ		 240 if (ret)
241 return ret;
242
8d315287
JB		 243 /* Just flush everything. Experiments have shown that reducing the
244 * number of bits based on the write domains has little performance
245 * impact.
246 */
7d54a904
CW		 247 if (flush_domains) {
248 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
249 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
250 /*
251 * Ensure that any following seqno writes only happen
252 * when the render cache is indeed flushed.
253 */
97f209bc 254 flags |= PIPE_CONTROL_CS_STALL;
7d54a904
CW		 255 }
256 if (invalidate_domains) {
257 flags |= PIPE_CONTROL_TLB_INVALIDATE;
258 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
259 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
260 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
261 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
262 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
263 /*
264 * TLB invalidate requires a post-sync write.
265 */
3ac78313 266 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
7d54a904 267 }
8d315287 268
5fb9de1a 269 ret = intel_ring_begin(req, 4);
8d315287
JB		 270 if (ret)
271 return ret;
272
e2f80391
TU		 273 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
274 intel_ring_emit(engine, flags);
275 intel_ring_emit(engine, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
276 intel_ring_emit(engine, 0);
277 intel_ring_advance(engine);
8d315287
JB		 278
279 return 0;
280}
281
f3987631 282static int
f2cf1fcc 283gen7_render_ring_cs_stall_wa(struct drm_i915_gem_request *req)
f3987631 284{
4a570db5 285 struct intel_engine_cs *engine = req->engine;
f3987631
PZ		 286 int ret;
287
5fb9de1a 288 ret = intel_ring_begin(req, 4);
f3987631
PZ		 289 if (ret)
290 return ret;
291
e2f80391
TU		 292 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
293 intel_ring_emit(engine, PIPE_CONTROL_CS_STALL |
f3987631 294 PIPE_CONTROL_STALL_AT_SCOREBOARD);
e2f80391
TU		 295 intel_ring_emit(engine, 0);
296 intel_ring_emit(engine, 0);
297 intel_ring_advance(engine);
f3987631
PZ		 298
299 return 0;
300}
301
4772eaeb 302static int
a84c3ae1 303gen7_render_ring_flush(struct drm_i915_gem_request *req,
4772eaeb
PZ		 304 u32 invalidate_domains, u32 flush_domains)
305{
4a570db5 306 struct intel_engine_cs *engine = req->engine;
4772eaeb 307 u32 flags = 0;
e2f80391 308 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
4772eaeb
PZ		 309 int ret;
310
f3987631
PZ		 311 /*
312 * Ensure that any following seqno writes only happen when the render
313 * cache is indeed flushed.
314 *
315 * Workaround: 4th PIPE_CONTROL command (except the ones with only
316 * read-cache invalidate bits set) must have the CS_STALL bit set. We
317 * don't try to be clever and just set it unconditionally.
318 */
319 flags |= PIPE_CONTROL_CS_STALL;
320
4772eaeb
PZ		 321 /* Just flush everything. Experiments have shown that reducing the
322 * number of bits based on the write domains has little performance
323 * impact.
324 */
325 if (flush_domains) {
326 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
327 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 328 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 329 flags |= PIPE_CONTROL_FLUSH_ENABLE;
4772eaeb
PZ		 330 }
331 if (invalidate_domains) {
332 flags |= PIPE_CONTROL_TLB_INVALIDATE;
333 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
334 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
335 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
336 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
337 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
148b83d0 338 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
4772eaeb
PZ		 339 /*
340 * TLB invalidate requires a post-sync write.
341 */
342 flags |= PIPE_CONTROL_QW_WRITE;
b9e1faa7 343 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
f3987631 344
add284a3
CW		 345 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
346
f3987631
PZ		 347 /* Workaround: we must issue a pipe_control with CS-stall bit
348 * set before a pipe_control command that has the state cache
349 * invalidate bit set. */
f2cf1fcc 350 gen7_render_ring_cs_stall_wa(req);
4772eaeb
PZ		 351 }
352
5fb9de1a 353 ret = intel_ring_begin(req, 4);
4772eaeb
PZ		 354 if (ret)
355 return ret;
356
e2f80391
TU		 357 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(4));
358 intel_ring_emit(engine, flags);
359 intel_ring_emit(engine, scratch_addr);
360 intel_ring_emit(engine, 0);
361 intel_ring_advance(engine);
4772eaeb
PZ		 362
363 return 0;
364}
365
884ceace 366static int
f2cf1fcc 367gen8_emit_pipe_control(struct drm_i915_gem_request *req,
884ceace
KG		 368 u32 flags, u32 scratch_addr)
369{
4a570db5 370 struct intel_engine_cs *engine = req->engine;
884ceace
KG		 371 int ret;
372
5fb9de1a 373 ret = intel_ring_begin(req, 6);
884ceace
KG		 374 if (ret)
375 return ret;
376
e2f80391
TU		 377 intel_ring_emit(engine, GFX_OP_PIPE_CONTROL(6));
378 intel_ring_emit(engine, flags);
379 intel_ring_emit(engine, scratch_addr);
380 intel_ring_emit(engine, 0);
381 intel_ring_emit(engine, 0);
382 intel_ring_emit(engine, 0);
383 intel_ring_advance(engine);
884ceace
KG		 384
385 return 0;
386}
387
a5f3d68e 388static int
a84c3ae1 389gen8_render_ring_flush(struct drm_i915_gem_request *req,
a5f3d68e
BW		 390 u32 invalidate_domains, u32 flush_domains)
391{
392 u32 flags = 0;
4a570db5 393 u32 scratch_addr = req->engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
02c9f7e3 394 int ret;
a5f3d68e
BW		 395
396 flags |= PIPE_CONTROL_CS_STALL;
397
398 if (flush_domains) {
399 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
400 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
965fd602 401 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
40a24488 402 flags |= PIPE_CONTROL_FLUSH_ENABLE;
a5f3d68e
BW		 403 }
404 if (invalidate_domains) {
405 flags |= PIPE_CONTROL_TLB_INVALIDATE;
406 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
407 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
408 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
409 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
410 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
411 flags |= PIPE_CONTROL_QW_WRITE;
412 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
02c9f7e3
KG		 413
414 /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */
f2cf1fcc 415 ret = gen8_emit_pipe_control(req,
02c9f7e3
KG		 416 PIPE_CONTROL_CS_STALL |
417 PIPE_CONTROL_STALL_AT_SCOREBOARD,
418 0);
419 if (ret)
420 return ret;
a5f3d68e
BW		 421 }
422
f2cf1fcc 423 return gen8_emit_pipe_control(req, flags, scratch_addr);
a5f3d68e
BW		 424}
425
0bc40be8 426static void ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 427 u32 value)
d46eefa2 428{
0bc40be8
TU		 429 struct drm_i915_private *dev_priv = engine->dev->dev_private;
430 I915_WRITE_TAIL(engine, value);
d46eefa2
XH		 431}
432
0bc40be8 433u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
8187a2b7 434{
0bc40be8 435 struct drm_i915_private *dev_priv = engine->dev->dev_private;
50877445 436 u64 acthd;
8187a2b7 437
0bc40be8
TU		 438 if (INTEL_INFO(engine->dev)->gen >= 8)
439 acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
440 RING_ACTHD_UDW(engine->mmio_base));
441 else if (INTEL_INFO(engine->dev)->gen >= 4)
442 acthd = I915_READ(RING_ACTHD(engine->mmio_base));
50877445
CW		 443 else
444 acthd = I915_READ(ACTHD);
445
446 return acthd;
8187a2b7
ZN		 447}
448
0bc40be8 449static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
035dc1e0 450{
0bc40be8 451 struct drm_i915_private *dev_priv = engine->dev->dev_private;
035dc1e0
DV		 452 u32 addr;
453
454 addr = dev_priv->status_page_dmah->busaddr;
0bc40be8 455 if (INTEL_INFO(engine->dev)->gen >= 4)
035dc1e0
DV		 456 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
457 I915_WRITE(HWS_PGA, addr);
458}
459
0bc40be8 460static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
af75f269 461{
0bc40be8
TU		 462 struct drm_device *dev = engine->dev;
463 struct drm_i915_private *dev_priv = engine->dev->dev_private;
f0f59a00 464 i915_reg_t mmio;
af75f269
DL		 465
466 /* The ring status page addresses are no longer next to the rest of
467 * the ring registers as of gen7.
468 */
469 if (IS_GEN7(dev)) {
0bc40be8 470 switch (engine->id) {
af75f269
DL		 471 case RCS:
472 mmio = RENDER_HWS_PGA_GEN7;
473 break;
474 case BCS:
475 mmio = BLT_HWS_PGA_GEN7;
476 break;
477 /*
478 * VCS2 actually doesn't exist on Gen7. Only shut up
479 * gcc switch check warning
480 */
481 case VCS2:
482 case VCS:
483 mmio = BSD_HWS_PGA_GEN7;
484 break;
485 case VECS:
486 mmio = VEBOX_HWS_PGA_GEN7;
487 break;
488 }
0bc40be8
TU		 489 } else if (IS_GEN6(engine->dev)) {
490 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
af75f269
DL		 491 } else {
492 /* XXX: gen8 returns to sanity */
0bc40be8 493 mmio = RING_HWS_PGA(engine->mmio_base);
af75f269
DL		 494 }
495
0bc40be8 496 I915_WRITE(mmio, (u32)engine->status_page.gfx_addr);
af75f269
DL		 497 POSTING_READ(mmio);
498
499 /*
500 * Flush the TLB for this page
501 *
502 * FIXME: These two bits have disappeared on gen8, so a question
503 * arises: do we still need this and if so how should we go about
504 * invalidating the TLB?
505 */
506 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
0bc40be8 507 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
af75f269
DL		 508
509 /* ring should be idle before issuing a sync flush*/
0bc40be8 510 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
af75f269
DL		 511
512 I915_WRITE(reg,
513 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
514 INSTPM_SYNC_FLUSH));
515 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
516 1000))
517 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
0bc40be8 518 engine->name);
af75f269
DL		 519 }
520}
521
0bc40be8 522static bool stop_ring(struct intel_engine_cs *engine)
8187a2b7 523{
0bc40be8 524 struct drm_i915_private *dev_priv = to_i915(engine->dev);
8187a2b7 525
0bc40be8
TU		 526 if (!IS_GEN2(engine->dev)) {
527 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
528 if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
529 DRM_ERROR("%s : timed out trying to stop ring\n",
530 engine->name);
9bec9b13
CW		 531 /* Sometimes we observe that the idle flag is not
532 * set even though the ring is empty. So double
533 * check before giving up.
534 */
0bc40be8 535 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
9bec9b13 536 return false;
9991ae78
CW		 537 }
538 }
b7884eb4 539
0bc40be8
TU		 540 I915_WRITE_CTL(engine, 0);
541 I915_WRITE_HEAD(engine, 0);
542 engine->write_tail(engine, 0);
8187a2b7 543
0bc40be8
TU		 544 if (!IS_GEN2(engine->dev)) {
545 (void)I915_READ_CTL(engine);
546 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
9991ae78 547 }
a51435a3 548
0bc40be8 549 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
9991ae78 550}
8187a2b7 551
fc0768ce
TE		 552void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
553{
554 memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
555}
556
0bc40be8 557static int init_ring_common(struct intel_engine_cs *engine)
9991ae78 558{
0bc40be8 559 struct drm_device *dev = engine->dev;
9991ae78 560 struct drm_i915_private *dev_priv = dev->dev_private;
0bc40be8 561 struct intel_ringbuffer *ringbuf = engine->buffer;
93b0a4e0 562 struct drm_i915_gem_object *obj = ringbuf->obj;
9991ae78
CW		 563 int ret = 0;
564
59bad947 565 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9991ae78 566
0bc40be8 567 if (!stop_ring(engine)) {
9991ae78 568 /* G45 ring initialization often fails to reset head to zero */
6fd0d56e
CW		 569 DRM_DEBUG_KMS("%s head not reset to zero "
570 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 571 engine->name,
572 I915_READ_CTL(engine),
573 I915_READ_HEAD(engine),
574 I915_READ_TAIL(engine),
575 I915_READ_START(engine));
8187a2b7 576
0bc40be8 577 if (!stop_ring(engine)) {
6fd0d56e
CW		 578 DRM_ERROR("failed to set %s head to zero "
579 "ctl %08x head %08x tail %08x start %08x\n",
0bc40be8
TU		 580 engine->name,
581 I915_READ_CTL(engine),
582 I915_READ_HEAD(engine),
583 I915_READ_TAIL(engine),
584 I915_READ_START(engine));
9991ae78
CW		 585 ret = -EIO;
586 goto out;
6fd0d56e 587 }
8187a2b7
ZN		 588 }
589
9991ae78 590 if (I915_NEED_GFX_HWS(dev))
0bc40be8 591 intel_ring_setup_status_page(engine);
9991ae78 592 else
0bc40be8 593 ring_setup_phys_status_page(engine);
9991ae78 594
ece4a17d 595 /* Enforce ordering by reading HEAD register back */
0bc40be8 596 I915_READ_HEAD(engine);
ece4a17d 597
0d8957c8
DV		 598 /* Initialize the ring. This must happen _after_ we've cleared the ring
599 * registers with the above sequence (the readback of the HEAD registers
600 * also enforces ordering), otherwise the hw might lose the new ring
601 * register values. */
0bc40be8 602 I915_WRITE_START(engine, i915_gem_obj_ggtt_offset(obj));
95468892
CW		 603
604 /* WaClearRingBufHeadRegAtInit:ctg,elk */
0bc40be8 605 if (I915_READ_HEAD(engine))
95468892 606 DRM_DEBUG("%s initialization failed [head=%08x], fudging\n",
0bc40be8
TU		 607 engine->name, I915_READ_HEAD(engine));
608 I915_WRITE_HEAD(engine, 0);
609 (void)I915_READ_HEAD(engine);
95468892 610
0bc40be8 611 I915_WRITE_CTL(engine,
93b0a4e0 612 ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES)
5d031e5b 613 | RING_VALID);
8187a2b7 614
8187a2b7 615 /* If the head is still not zero, the ring is dead */
0bc40be8
TU		 616 if (wait_for((I915_READ_CTL(engine) & RING_VALID) != 0 &&
617 I915_READ_START(engine) == i915_gem_obj_ggtt_offset(obj) &&
618 (I915_READ_HEAD(engine) & HEAD_ADDR) == 0, 50)) {
e74cfed5 619 DRM_ERROR("%s initialization failed "
48e48a0b 620 "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n",
0bc40be8
TU		 621 engine->name,
622 I915_READ_CTL(engine),
623 I915_READ_CTL(engine) & RING_VALID,
624 I915_READ_HEAD(engine), I915_READ_TAIL(engine),
625 I915_READ_START(engine),
626 (unsigned long)i915_gem_obj_ggtt_offset(obj));
b7884eb4
DV		 627 ret = -EIO;
628 goto out;
8187a2b7
ZN		 629 }
630
ebd0fd4b 631 ringbuf->last_retired_head = -1;
0bc40be8
TU		 632 ringbuf->head = I915_READ_HEAD(engine);
633 ringbuf->tail = I915_READ_TAIL(engine) & TAIL_ADDR;
ebd0fd4b 634 intel_ring_update_space(ringbuf);
1ec14ad3 635
fc0768ce 636 intel_engine_init_hangcheck(engine);
50f018df 637
b7884eb4 638out:
59bad947 639 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b7884eb4
DV		 640
641 return ret;
8187a2b7
ZN		 642}
643
9b1136d5 644void
0bc40be8 645intel_fini_pipe_control(struct intel_engine_cs *engine)
9b1136d5 646{
0bc40be8 647 struct drm_device *dev = engine->dev;
9b1136d5 648
0bc40be8 649 if (engine->scratch.obj == NULL)
9b1136d5
OM		 650 return;
651
652 if (INTEL_INFO(dev)->gen >= 5) {
0bc40be8
TU		 653 kunmap(sg_page(engine->scratch.obj->pages->sgl));
654 i915_gem_object_ggtt_unpin(engine->scratch.obj);
9b1136d5
OM		 655 }
656
0bc40be8
TU		 657 drm_gem_object_unreference(&engine->scratch.obj->base);
658 engine->scratch.obj = NULL;
9b1136d5
OM		 659}
660
661int
0bc40be8 662intel_init_pipe_control(struct intel_engine_cs *engine)
c6df541c 663{
c6df541c
CW		 664 int ret;
665
0bc40be8 666 WARN_ON(engine->scratch.obj);
c6df541c 667
0bc40be8
TU		 668 engine->scratch.obj = i915_gem_alloc_object(engine->dev, 4096);
669 if (engine->scratch.obj == NULL) {
c6df541c
CW		 670 DRM_ERROR("Failed to allocate seqno page\n");
671 ret = -ENOMEM;
672 goto err;
673 }
e4ffd173 674
0bc40be8
TU		 675 ret = i915_gem_object_set_cache_level(engine->scratch.obj,
676 I915_CACHE_LLC);
a9cc726c
DV		 677 if (ret)
678 goto err_unref;
c6df541c 679
0bc40be8 680 ret = i915_gem_obj_ggtt_pin(engine->scratch.obj, 4096, 0);
c6df541c
CW		 681 if (ret)
682 goto err_unref;
683
0bc40be8
TU		 684 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(engine->scratch.obj);
685 engine->scratch.cpu_page = kmap(sg_page(engine->scratch.obj->pages->sgl));
686 if (engine->scratch.cpu_page == NULL) {
56b085a0 687 ret = -ENOMEM;
c6df541c 688 goto err_unpin;
56b085a0 689 }
c6df541c 690
2b1086cc 691 DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
0bc40be8 692 engine->name, engine->scratch.gtt_offset);
c6df541c
CW		 693 return 0;
694
695err_unpin:
0bc40be8 696 i915_gem_object_ggtt_unpin(engine->scratch.obj);
c6df541c 697err_unref:
0bc40be8 698 drm_gem_object_unreference(&engine->scratch.obj->base);
c6df541c 699err:
c6df541c
CW		 700 return ret;
701}
702
e2be4faf 703static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
86d7f238 704{
7225342a 705 int ret, i;
4a570db5 706 struct intel_engine_cs *engine = req->engine;
e2f80391 707 struct drm_device *dev = engine->dev;
888b5995 708 struct drm_i915_private *dev_priv = dev->dev_private;
7225342a 709 struct i915_workarounds *w = &dev_priv->workarounds;
888b5995 710
02235808 711 if (w->count == 0)
7225342a 712 return 0;
888b5995 713
e2f80391 714 engine->gpu_caches_dirty = true;
4866d729 715 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 716 if (ret)
717 return ret;
888b5995 718
5fb9de1a 719 ret = intel_ring_begin(req, (w->count * 2 + 2));
7225342a
MK		 720 if (ret)
721 return ret;
722
e2f80391 723 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(w->count));
7225342a 724 for (i = 0; i < w->count; i++) {
e2f80391
TU		 725 intel_ring_emit_reg(engine, w->reg[i].addr);
726 intel_ring_emit(engine, w->reg[i].value);
7225342a 727 }
e2f80391 728 intel_ring_emit(engine, MI_NOOP);
7225342a 729
e2f80391 730 intel_ring_advance(engine);
7225342a 731
e2f80391 732 engine->gpu_caches_dirty = true;
4866d729 733 ret = intel_ring_flush_all_caches(req);
7225342a
MK		 734 if (ret)
735 return ret;
888b5995 736
7225342a 737 DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count);
888b5995 738
7225342a 739 return 0;
86d7f238
AS		 740}
741
8753181e 742static int intel_rcs_ctx_init(struct drm_i915_gem_request *req)
8f0e2b9d
DV		 743{
744 int ret;
745
e2be4faf 746 ret = intel_ring_workarounds_emit(req);
8f0e2b9d
DV		 747 if (ret != 0)
748 return ret;
749
be01363f 750 ret = i915_gem_render_state_init(req);
8f0e2b9d 751 if (ret)
e26e1b97 752 return ret;
8f0e2b9d 753
e26e1b97 754 return 0;
8f0e2b9d
DV		 755}
756
7225342a 757static int wa_add(struct drm_i915_private *dev_priv,
f0f59a00
VS		 758 i915_reg_t addr,
759 const u32 mask, const u32 val)
7225342a
MK		 760{
761 const u32 idx = dev_priv->workarounds.count;
762
763 if (WARN_ON(idx >= I915_MAX_WA_REGS))
764 return -ENOSPC;
765
766 dev_priv->workarounds.reg[idx].addr = addr;
767 dev_priv->workarounds.reg[idx].value = val;
768 dev_priv->workarounds.reg[idx].mask = mask;
769
770 dev_priv->workarounds.count++;
771
772 return 0;
86d7f238
AS		 773}
774
ca5a0fbd 775#define WA_REG(addr, mask, val) do { \
cf4b0de6 776 const int r = wa_add(dev_priv, (addr), (mask), (val)); \
7225342a
MK		 777 if (r) \
778 return r; \
ca5a0fbd 779 } while (0)
7225342a
MK		 780
781#define WA_SET_BIT_MASKED(addr, mask) \
26459343 782 WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask))
7225342a
MK		 783
784#define WA_CLR_BIT_MASKED(addr, mask) \
26459343 785 WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask))
7225342a 786
98533251 787#define WA_SET_FIELD_MASKED(addr, mask, value) \
cf4b0de6 788 WA_REG(addr, mask, _MASKED_FIELD(mask, value))
7225342a 789
cf4b0de6
DL		 790#define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
791#define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
7225342a 792
cf4b0de6 793#define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val)
7225342a 794
0bc40be8
TU		 795static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
796 i915_reg_t reg)
33136b06 797{
0bc40be8 798 struct drm_i915_private *dev_priv = engine->dev->dev_private;
33136b06 799 struct i915_workarounds *wa = &dev_priv->workarounds;
0bc40be8 800 const uint32_t index = wa->hw_whitelist_count[engine->id];
33136b06
AS		 801
802 if (WARN_ON(index >= RING_MAX_NONPRIV_SLOTS))
803 return -EINVAL;
804
0bc40be8 805 WA_WRITE(RING_FORCE_TO_NONPRIV(engine->mmio_base, index),
33136b06 806 i915_mmio_reg_offset(reg));
0bc40be8 807 wa->hw_whitelist_count[engine->id]++;
33136b06
AS		 808
809 return 0;
810}
811
0bc40be8 812static int gen8_init_workarounds(struct intel_engine_cs *engine)
e9a64ada 813{
0bc40be8 814 struct drm_device *dev = engine->dev;
68c6198b
AS		 815 struct drm_i915_private *dev_priv = dev->dev_private;
816
817 WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
e9a64ada 818
717d84d6
AS		 819 /* WaDisableAsyncFlipPerfMode:bdw,chv */
820 WA_SET_BIT_MASKED(MI_MODE, ASYNC_FLIP_PERF_DISABLE);
821
d0581194
AS		 822 /* WaDisablePartialInstShootdown:bdw,chv */
823 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
824 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
825
a340af58
AS		 826 /* Use Force Non-Coherent whenever executing a 3D context. This is a
827 * workaround for for a possible hang in the unlikely event a TLB
828 * invalidation occurs during a PSD flush.
829 */
830 /* WaForceEnableNonCoherent:bdw,chv */
120f5d28 831 /* WaHdcDisableFetchWhenMasked:bdw,chv */
a340af58 832 WA_SET_BIT_MASKED(HDC_CHICKEN0,
120f5d28 833 HDC_DONOT_FETCH_MEM_WHEN_MASKED |
a340af58
AS		 834 HDC_FORCE_NON_COHERENT);
835
6def8fdd
AS		 836 /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0:
837 * "The Hierarchical Z RAW Stall Optimization allows non-overlapping
838 * polygons in the same 8x4 pixel/sample area to be processed without
839 * stalling waiting for the earlier ones to write to Hierarchical Z
840 * buffer."
841 *
842 * This optimization is off by default for BDW and CHV; turn it on.
843 */
844 WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE);
845
48404636
AS		 846 /* Wa4x4STCOptimizationDisable:bdw,chv */
847 WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE);
848
7eebcde6
AS		 849 /*
850 * BSpec recommends 8x4 when MSAA is used,
851 * however in practice 16x4 seems fastest.
852 *
853 * Note that PS/WM thread counts depend on the WIZ hashing
854 * disable bit, which we don't touch here, but it's good
855 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
856 */
857 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
858 GEN6_WIZ_HASHING_MASK,
859 GEN6_WIZ_HASHING_16x4);
860
e9a64ada
AS		 861 return 0;
862}
863
0bc40be8 864static int bdw_init_workarounds(struct intel_engine_cs *engine)
86d7f238 865{
e9a64ada 866 int ret;
0bc40be8 867 struct drm_device *dev = engine->dev;
888b5995 868 struct drm_i915_private *dev_priv = dev->dev_private;
86d7f238 869
0bc40be8 870 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 871 if (ret)
872 return ret;
873
101b376d 874 /* WaDisableThreadStallDopClockGating:bdw (pre-production) */
d0581194 875 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
86d7f238 876
101b376d 877 /* WaDisableDopClockGating:bdw */
7225342a
MK		 878 WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
879 DOP_CLOCK_GATING_DISABLE);
86d7f238 880
7225342a
MK		 881 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
882 GEN8_SAMPLER_POWER_BYPASS_DIS);
86d7f238 883
7225342a 884 WA_SET_BIT_MASKED(HDC_CHICKEN0,
35cb6f3b
DL		 885 /* WaForceContextSaveRestoreNonCoherent:bdw */
886 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
35cb6f3b 887 /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
7225342a 888 (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
86d7f238 889
86d7f238
AS		 890 return 0;
891}
892
0bc40be8 893static int chv_init_workarounds(struct intel_engine_cs *engine)
00e1e623 894{
e9a64ada 895 int ret;
0bc40be8 896 struct drm_device *dev = engine->dev;
00e1e623
VS		 897 struct drm_i915_private *dev_priv = dev->dev_private;
898
0bc40be8 899 ret = gen8_init_workarounds(engine);
e9a64ada
AS		 900 if (ret)
901 return ret;
902
00e1e623 903 /* WaDisableThreadStallDopClockGating:chv */
d0581194 904 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, STALL_DOP_GATING_DISABLE);
00e1e623 905
d60de81d
KG		 906 /* Improve HiZ throughput on CHV. */
907 WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X);
908
7225342a
MK		 909 return 0;
910}
911
0bc40be8 912static int gen9_init_workarounds(struct intel_engine_cs *engine)
3b106531 913{
0bc40be8 914 struct drm_device *dev = engine->dev;
ab0dfafe 915 struct drm_i915_private *dev_priv = dev->dev_private;
e0f3fa09 916 int ret;
ab0dfafe 917
68370e0a 918 /* WaEnableLbsSlaRetryTimerDecrement:skl,bxt,kbl */
9c4cbf82
MK		 919 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
920 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
921
68370e0a 922 /* WaDisableKillLogic:bxt,skl,kbl */
9c4cbf82
MK		 923 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
924 ECOCHK_DIS_TLB);
925
68370e0a
MK		 926 /* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl */
927 /* WaDisablePartialInstShootdown:skl,bxt,kbl */
ab0dfafe 928 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
950b2aae 929 FLOW_CONTROL_ENABLE |
ab0dfafe
HN		 930 PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE);
931
68370e0a 932 /* Syncing dependencies between camera and graphics:skl,bxt,kbl */
8424171e
NH		 933 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
934 GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
935
e87a005d
JN		 936 /* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
937 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
938 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
a86eb582
DL		 939 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
940 GEN9_DG_MIRROR_FIX_ENABLE);
1de4582f 941
e87a005d
JN		 942 /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
943 if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
944 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
183c6dac
DL		 945 WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
946 GEN9_RHWO_OPTIMIZATION_DISABLE);
9b01435d
AS		 947 /*
948 * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
949 * but we do that in per ctx batchbuffer as there is an issue
950 * with this register not getting restored on ctx restore
951 */
183c6dac
DL		 952 }
953
68370e0a
MK		 954 /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl */
955 /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl */
bfd8ad4e
TG		 956 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
957 GEN9_ENABLE_YV12_BUGFIX |
958 GEN9_ENABLE_GPGPU_PREEMPTION);
cac23df4 959
68370e0a
MK		 960 /* Wa4x4STCOptimizationDisable:skl,bxt,kbl */
961 /* WaDisablePartialResolveInVc:skl,bxt,kbl */
60294683
AS		 962 WA_SET_BIT_MASKED(CACHE_MODE_1, (GEN8_4x4_STC_OPTIMIZATION_DISABLE |
963 GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE));
9370cd98 964
68370e0a 965 /* WaCcsTlbPrefetchDisable:skl,bxt,kbl */
e2db7071
DL		 966 WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
967 GEN9_CCS_TLB_PREFETCH_ENABLE);
968
5a2ae95e 969 /* WaDisableMaskBasedCammingInRCC:skl,bxt */
e87a005d
JN		 970 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
971 IS_BXT_REVID(dev, 0, BXT_REVID_A1))
38a39a7b
BW		 972 WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
973 PIXEL_MASK_CAMMING_DISABLE);
974
6fd72492
MK		 975 /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl */
976 WA_SET_BIT_MASKED(HDC_CHICKEN0,
977 HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
978 HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE);
8ea6f892 979
60f452e6
MK		 980 /* WaForceEnableNonCoherent and WaDisableHDCInvalidation are
981 * both tied to WaForceContextSaveRestoreNonCoherent
982 * in some hsds for skl. We keep the tie for all gen9. The
983 * documentation is a bit hazy and so we want to get common behaviour,
984 * even though there is no clear evidence we would need both on kbl/bxt.
985 * This area has been source of system hangs so we play it safe
986 * and mimic the skl regardless of what bspec says.
987 *
988 * Use Force Non-Coherent whenever executing a 3D context. This
989 * is a workaround for a possible hang in the unlikely event
990 * a TLB invalidation occurs during a PSD flush.
991 */
992
993 /* WaForceEnableNonCoherent:skl,bxt,kbl */
994 WA_SET_BIT_MASKED(HDC_CHICKEN0,
995 HDC_FORCE_NON_COHERENT);
996
997 /* WaDisableHDCInvalidation:skl,bxt,kbl */
998 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
999 BDW_DISABLE_HDC_INVALIDATION);
1000
68370e0a
MK		 1001 /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl */
1002 if (IS_SKYLAKE(dev_priv) ||
1003 IS_KABYLAKE(dev_priv) ||
1004 IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
8c761609
AS		 1005 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
1006 GEN8_SAMPLER_POWER_BYPASS_DIS);
8c761609 1007
68370e0a 1008 /* WaDisableSTUnitPowerOptimization:skl,bxt,kbl */
6b6d5626
RB		 1009 WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN2, GEN8_ST_PO_DISABLE);
1010
68370e0a 1011 /* WaOCLCoherentLineFlush:skl,bxt,kbl */
6ecf56ae
AS		 1012 I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) |
1013 GEN8_LQSC_FLUSH_COHERENT_LINES));
1014
f98edb2b 1015 /* WaVFEStateAfterPipeControlwithMediaStateClear:skl,bxt */
1016 ret = wa_ring_whitelist_reg(engine, GEN9_CTX_PREEMPT_REG);
1017 if (ret)
1018 return ret;
1019
68370e0a 1020 /* WaEnablePreemptionGranularityControlByUMD:skl,bxt,kbl */
0bc40be8 1021 ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
e0f3fa09
AS		 1022 if (ret)
1023 return ret;
1024
68370e0a 1025 /* WaAllowUMDToModifyHDCChicken1:skl,bxt,kbl */
0bc40be8 1026 ret = wa_ring_whitelist_reg(engine, GEN8_HDC_CHICKEN1);
3669ab61
AS		 1027 if (ret)
1028 return ret;
1029
3b106531
HN		 1030 return 0;
1031}
1032
0bc40be8 1033static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
b7668791 1034{
0bc40be8 1035 struct drm_device *dev = engine->dev;
b7668791
DL		 1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037 u8 vals[3] = { 0, 0, 0 };
1038 unsigned int i;
1039
1040 for (i = 0; i < 3; i++) {
1041 u8 ss;
1042
1043 /*
1044 * Only consider slices where one, and only one, subslice has 7
1045 * EUs
1046 */
a4d8a0fe 1047 if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
b7668791
DL		 1048 continue;
1049
1050 /*
1051 * subslice_7eu[i] != 0 (because of the check above) and
1052 * ss_max == 4 (maximum number of subslices possible per slice)
1053 *
1054 * -> 0 <= ss <= 3;
1055 */
1056 ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
1057 vals[i] = 3 - ss;
1058 }
1059
1060 if (vals[0] == 0 && vals[1] == 0 && vals[2] == 0)
1061 return 0;
1062
1063 /* Tune IZ hashing. See intel_device_info_runtime_init() */
1064 WA_SET_FIELD_MASKED(GEN7_GT_MODE,
1065 GEN9_IZ_HASHING_MASK(2) |
1066 GEN9_IZ_HASHING_MASK(1) |
1067 GEN9_IZ_HASHING_MASK(0),
1068 GEN9_IZ_HASHING(2, vals[2]) |
1069 GEN9_IZ_HASHING(1, vals[1]) |
1070 GEN9_IZ_HASHING(0, vals[0]));
1071
1072 return 0;
1073}
1074
0bc40be8 1075static int skl_init_workarounds(struct intel_engine_cs *engine)
8d205494 1076{
aa0011a8 1077 int ret;
0bc40be8 1078 struct drm_device *dev = engine->dev;
d0bbbc4f
DL		 1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080
0bc40be8 1081 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1082 if (ret)
1083 return ret;
8d205494 1084
a78536e7
AS		 1085 /*
1086 * Actual WA is to disable percontext preemption granularity control
1087 * until D0 which is the default case so this is equivalent to
1088 * !WaDisablePerCtxtPreemptionGranularityControl:skl
1089 */
1090 if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
1091 I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
1092 _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
1093 }
1094
e87a005d 1095 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
9c4cbf82
MK		 1096 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
1097 I915_WRITE(FF_SLICE_CS_CHICKEN2,
1098 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
1099 }
1100
1101 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
1102 * involving this register should also be added to WA batch as required.
1103 */
e87a005d 1104 if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
9c4cbf82
MK		 1105 /* WaDisableLSQCROPERFforOCL:skl */
1106 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
1107 GEN8_LQSC_RO_PERF_DIS);
1108
1109 /* WaEnableGapsTsvCreditFix:skl */
e87a005d 1110 if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
9c4cbf82
MK		 1111 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1112 GEN9_GAPS_TSV_CREDIT_DISABLE));
1113 }
1114
d0bbbc4f 1115 /* WaDisablePowerCompilerClockGating:skl */
e87a005d 1116 if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
d0bbbc4f
DL		 1117 WA_SET_BIT_MASKED(HIZ_CHICKEN,
1118 BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
1119
e87a005d
JN		 1120 /* WaBarrierPerformanceFixDisable:skl */
1121 if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
5b6fd12a
VS		 1122 WA_SET_BIT_MASKED(HDC_CHICKEN0,
1123 HDC_FENCE_DEST_SLM_DISABLE |
1124 HDC_BARRIER_PERFORMANCE_DISABLE);
1125
9bd9dfb4 1126 /* WaDisableSbeCacheDispatchPortSharing:skl */
e87a005d 1127 if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
9bd9dfb4
MK		 1128 WA_SET_BIT_MASKED(
1129 GEN7_HALF_SLICE_CHICKEN1,
1130 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
9bd9dfb4 1131
c000456c
MK		 1132 /* WaDisableGafsUnitClkGating:skl */
1133 WA_SET_BIT(GEN7_UCGCTL4, GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE);
1134
6107497e 1135 /* WaDisableLSQCROPERFforOCL:skl */
0bc40be8 1136 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
6107497e
AS		 1137 if (ret)
1138 return ret;
1139
0bc40be8 1140 return skl_tune_iz_hashing(engine);
7225342a
MK		 1141}
1142
0bc40be8 1143static int bxt_init_workarounds(struct intel_engine_cs *engine)
cae0437f 1144{
aa0011a8 1145 int ret;
0bc40be8 1146 struct drm_device *dev = engine->dev;
dfb601e6
NH		 1147 struct drm_i915_private *dev_priv = dev->dev_private;
1148
0bc40be8 1149 ret = gen9_init_workarounds(engine);
aa0011a8
AS		 1150 if (ret)
1151 return ret;
cae0437f 1152
9c4cbf82
MK		 1153 /* WaStoreMultiplePTEenable:bxt */
1154 /* This is a requirement according to Hardware specification */
cbdc12a9 1155 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
9c4cbf82
MK		 1156 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
1157
1158 /* WaSetClckGatingDisableMedia:bxt */
cbdc12a9 1159 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
9c4cbf82
MK		 1160 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
1161 ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
1162 }
1163
dfb601e6
NH		 1164 /* WaDisableThreadStallDopClockGating:bxt */
1165 WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
1166 STALL_DOP_GATING_DISABLE);
1167
983b4b9d 1168 /* WaDisableSbeCacheDispatchPortSharing:bxt */
e87a005d 1169 if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
983b4b9d
NH		 1170 WA_SET_BIT_MASKED(
1171 GEN7_HALF_SLICE_CHICKEN1,
1172 GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
1173 }
1174
2c8580e4
AS		 1175 /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
1176 /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
1177 /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
a786d53a 1178 /* WaDisableLSQCROPERFforOCL:bxt */
2c8580e4 1179 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
0bc40be8 1180 ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
2c8580e4
AS		 1181 if (ret)
1182 return ret;
a786d53a 1183
0bc40be8 1184 ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
a786d53a
AS		 1185 if (ret)
1186 return ret;
2c8580e4
AS		 1187 }
1188
cae0437f
NH		 1189 return 0;
1190}
1191
68370e0a
MK		 1192static int kbl_init_workarounds(struct intel_engine_cs *engine)
1193{
79164509 1194 struct drm_i915_private *dev_priv = engine->dev->dev_private;
68370e0a
MK		 1195 int ret;
1196
1197 ret = gen9_init_workarounds(engine);
1198 if (ret)
1199 return ret;
1200
79164509
MK		 1201 /* WaEnableGapsTsvCreditFix:kbl */
1202 I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
1203 GEN9_GAPS_TSV_CREDIT_DISABLE));
1204
68370e0a
MK		 1205 return 0;
1206}
1207
0bc40be8 1208int init_workarounds_ring(struct intel_engine_cs *engine)
7225342a 1209{
0bc40be8 1210 struct drm_device *dev = engine->dev;
7225342a
MK		 1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212
0bc40be8 1213 WARN_ON(engine->id != RCS);
7225342a
MK		 1214
1215 dev_priv->workarounds.count = 0;
33136b06 1216 dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
7225342a
MK		 1217
1218 if (IS_BROADWELL(dev))
0bc40be8 1219 return bdw_init_workarounds(engine);
7225342a
MK		 1220
1221 if (IS_CHERRYVIEW(dev))
0bc40be8 1222 return chv_init_workarounds(engine);
00e1e623 1223
8d205494 1224 if (IS_SKYLAKE(dev))
0bc40be8 1225 return skl_init_workarounds(engine);
cae0437f
NH		 1226
1227 if (IS_BROXTON(dev))
0bc40be8 1228 return bxt_init_workarounds(engine);
3b106531 1229
68370e0a
MK		 1230 if (IS_KABYLAKE(dev_priv))
1231 return kbl_init_workarounds(engine);
1232
00e1e623
VS		 1233 return 0;
1234}
1235
0bc40be8 1236static int init_render_ring(struct intel_engine_cs *engine)
8187a2b7 1237{
0bc40be8 1238 struct drm_device *dev = engine->dev;
1ec14ad3 1239 struct drm_i915_private *dev_priv = dev->dev_private;
0bc40be8 1240 int ret = init_ring_common(engine);
9c33baa6
KZ		 1241 if (ret)
1242 return ret;
a69ffdbf 1243
61a563a2
AG		 1244 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
1245 if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
6b26c86d 1246 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
1c8c38c5
CW		 1247
1248 /* We need to disable the AsyncFlip performance optimisations in order
1249 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1250 * programmed to '1' on all products.
8693a824 1251 *
2441f877 1252 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
1c8c38c5 1253 */
2441f877 1254 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
1c8c38c5
CW		 1255 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1256
f05bb0c7 1257 /* Required for the hardware to program scanline values for waiting */
01fa0302 1258 /* WaEnableFlushTlbInvalidationMode:snb */
f05bb0c7
CW		 1259 if (INTEL_INFO(dev)->gen == 6)
1260 I915_WRITE(GFX_MODE,
aa83e30d 1261 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
f05bb0c7 1262
01fa0302 1263 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
1c8c38c5
CW		 1264 if (IS_GEN7(dev))
1265 I915_WRITE(GFX_MODE_GEN7,
01fa0302 1266 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
1c8c38c5 1267 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
78501eac 1268
5e13a0c5 1269 if (IS_GEN6(dev)) {
3a69ddd6
KG		 1270 /* From the Sandybridge PRM, volume 1 part 3, page 24:
1271 * "If this bit is set, STCunit will have LRA as replacement
1272 * policy. [...] This bit must be reset. LRA replacement
1273 * policy is not supported."
1274 */
1275 I915_WRITE(CACHE_MODE_0,
5e13a0c5 1276 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
84f9f938
BW		 1277 }
1278
9cc83020 1279 if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
6b26c86d 1280 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
84f9f938 1281
040d2baa 1282 if (HAS_L3_DPF(dev))
0bc40be8 1283 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
15b9f80e 1284
0bc40be8 1285 return init_workarounds_ring(engine);
8187a2b7
ZN		 1286}
1287
0bc40be8 1288static void render_ring_cleanup(struct intel_engine_cs *engine)
c6df541c 1289{
0bc40be8 1290 struct drm_device *dev = engine->dev;
3e78998a
BW		 1291 struct drm_i915_private *dev_priv = dev->dev_private;
1292
1293 if (dev_priv->semaphore_obj) {
1294 i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
1295 drm_gem_object_unreference(&dev_priv->semaphore_obj->base);
1296 dev_priv->semaphore_obj = NULL;
1297 }
b45305fc 1298
0bc40be8 1299 intel_fini_pipe_control(engine);
c6df541c
CW		 1300}
1301
f7169687 1302static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1303 unsigned int num_dwords)
1304{
1305#define MBOX_UPDATE_DWORDS 8
4a570db5 1306 struct intel_engine_cs *signaller = signaller_req->engine;
3e78998a
BW		 1307 struct drm_device *dev = signaller->dev;
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 struct intel_engine_cs *waiter;
c3232b18
DG		 1310 enum intel_engine_id id;
1311 int ret, num_rings;
3e78998a
BW		 1312
1313 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1314 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1315#undef MBOX_UPDATE_DWORDS
1316
5fb9de1a 1317 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1318 if (ret)
1319 return ret;
1320
c3232b18 1321 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1322 u32 seqno;
c3232b18 1323 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1324 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1325 continue;
1326
f7169687 1327 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1328 intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6));
1329 intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB |
1330 PIPE_CONTROL_QW_WRITE |
1331 PIPE_CONTROL_FLUSH_ENABLE);
1332 intel_ring_emit(signaller, lower_32_bits(gtt_offset));
1333 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1334 intel_ring_emit(signaller, seqno);
3e78998a
BW		 1335 intel_ring_emit(signaller, 0);
1336 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
83e53802 1337 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1338 intel_ring_emit(signaller, 0);
1339 }
1340
1341 return 0;
1342}
1343
f7169687 1344static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
3e78998a
BW		 1345 unsigned int num_dwords)
1346{
1347#define MBOX_UPDATE_DWORDS 6
4a570db5 1348 struct intel_engine_cs *signaller = signaller_req->engine;
3e78998a
BW		 1349 struct drm_device *dev = signaller->dev;
1350 struct drm_i915_private *dev_priv = dev->dev_private;
1351 struct intel_engine_cs *waiter;
c3232b18
DG		 1352 enum intel_engine_id id;
1353 int ret, num_rings;
3e78998a
BW		 1354
1355 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1356 num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
1357#undef MBOX_UPDATE_DWORDS
1358
5fb9de1a 1359 ret = intel_ring_begin(signaller_req, num_dwords);
3e78998a
BW		 1360 if (ret)
1361 return ret;
1362
c3232b18 1363 for_each_engine_id(waiter, dev_priv, id) {
6259cead 1364 u32 seqno;
c3232b18 1365 u64 gtt_offset = signaller->semaphore.signal_ggtt[id];
3e78998a
BW		 1366 if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID)
1367 continue;
1368
f7169687 1369 seqno = i915_gem_request_get_seqno(signaller_req);
3e78998a
BW		 1370 intel_ring_emit(signaller, (MI_FLUSH_DW + 1) |
1371 MI_FLUSH_DW_OP_STOREDW);
1372 intel_ring_emit(signaller, lower_32_bits(gtt_offset) |
1373 MI_FLUSH_DW_USE_GTT);
1374 intel_ring_emit(signaller, upper_32_bits(gtt_offset));
6259cead 1375 intel_ring_emit(signaller, seqno);
3e78998a 1376 intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL |
83e53802 1377 MI_SEMAPHORE_TARGET(waiter->hw_id));
3e78998a
BW		 1378 intel_ring_emit(signaller, 0);
1379 }
1380
1381 return 0;
1382}
1383
f7169687 1384static int gen6_signal(struct drm_i915_gem_request *signaller_req,
024a43e1 1385 unsigned int num_dwords)
1ec14ad3 1386{
4a570db5 1387 struct intel_engine_cs *signaller = signaller_req->engine;
024a43e1
BW		 1388 struct drm_device *dev = signaller->dev;
1389 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 1390 struct intel_engine_cs *useless;
c3232b18
DG		 1391 enum intel_engine_id id;
1392 int ret, num_rings;
78325f2d 1393
a1444b79
BW		 1394#define MBOX_UPDATE_DWORDS 3
1395 num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
1396 num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
1397#undef MBOX_UPDATE_DWORDS
024a43e1 1398
5fb9de1a 1399 ret = intel_ring_begin(signaller_req, num_dwords);
024a43e1
BW		 1400 if (ret)
1401 return ret;
024a43e1 1402
c3232b18
DG		 1403 for_each_engine_id(useless, dev_priv, id) {
1404 i915_reg_t mbox_reg = signaller->semaphore.mbox.signal[id];
f0f59a00
VS		 1405
1406 if (i915_mmio_reg_valid(mbox_reg)) {
f7169687 1407 u32 seqno = i915_gem_request_get_seqno(signaller_req);
f0f59a00 1408
78325f2d 1409 intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1));
f92a9162 1410 intel_ring_emit_reg(signaller, mbox_reg);
6259cead 1411 intel_ring_emit(signaller, seqno);
78325f2d
BW		 1412 }
1413 }
024a43e1 1414
a1444b79
BW		 1415 /* If num_dwords was rounded, make sure the tail pointer is correct */
1416 if (num_rings % 2 == 0)
1417 intel_ring_emit(signaller, MI_NOOP);
1418
024a43e1 1419 return 0;
1ec14ad3
CW		 1420}
1421
c8c99b0f
BW		 1422/**
1423 * gen6_add_request - Update the semaphore mailbox registers
ee044a88
JH		 1424 *
1425 * @request - request to write to the ring
c8c99b0f
BW		 1426 *
1427 * Update the mailbox registers in the *other* rings with the current seqno.
1428 * This acts like a signal in the canonical semaphore.
1429 */
1ec14ad3 1430static int
ee044a88 1431gen6_add_request(struct drm_i915_gem_request *req)
1ec14ad3 1432{
4a570db5 1433 struct intel_engine_cs *engine = req->engine;
024a43e1 1434 int ret;
52ed2325 1435
e2f80391
TU		 1436 if (engine->semaphore.signal)
1437 ret = engine->semaphore.signal(req, 4);
707d9cf9 1438 else
5fb9de1a 1439 ret = intel_ring_begin(req, 4);
707d9cf9 1440
1ec14ad3
CW		 1441 if (ret)
1442 return ret;
1443
e2f80391
TU		 1444 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1445 intel_ring_emit(engine,
1446 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1447 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1448 intel_ring_emit(engine, MI_USER_INTERRUPT);
1449 __intel_ring_advance(engine);
1ec14ad3 1450
1ec14ad3
CW		 1451 return 0;
1452}
1453
f72b3435
MK		 1454static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
1455 u32 seqno)
1456{
1457 struct drm_i915_private *dev_priv = dev->dev_private;
1458 return dev_priv->last_seqno < seqno;
1459}
1460
c8c99b0f
BW		 1461/**
1462 * intel_ring_sync - sync the waiter to the signaller on seqno
1463 *
1464 * @waiter - ring that is waiting
1465 * @signaller - ring which has, or will signal
1466 * @seqno - seqno which the waiter will block on
1467 */
5ee426ca
BW		 1468
1469static int
599d924c 1470gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
5ee426ca
BW		 1471 struct intel_engine_cs *signaller,
1472 u32 seqno)
1473{
4a570db5 1474 struct intel_engine_cs *waiter = waiter_req->engine;
5ee426ca
BW		 1475 struct drm_i915_private *dev_priv = waiter->dev->dev_private;
1476 int ret;
1477
5fb9de1a 1478 ret = intel_ring_begin(waiter_req, 4);
5ee426ca
BW		 1479 if (ret)
1480 return ret;
1481
1482 intel_ring_emit(waiter, MI_SEMAPHORE_WAIT |
1483 MI_SEMAPHORE_GLOBAL_GTT |
bae4fcd2 1484 MI_SEMAPHORE_POLL |
5ee426ca
BW		 1485 MI_SEMAPHORE_SAD_GTE_SDD);
1486 intel_ring_emit(waiter, seqno);
1487 intel_ring_emit(waiter,
1488 lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1489 intel_ring_emit(waiter,
1490 upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id)));
1491 intel_ring_advance(waiter);
1492 return 0;
1493}
1494
c8c99b0f 1495static int
599d924c 1496gen6_ring_sync(struct drm_i915_gem_request *waiter_req,
a4872ba6 1497 struct intel_engine_cs *signaller,
686cb5f9 1498 u32 seqno)
1ec14ad3 1499{
4a570db5 1500 struct intel_engine_cs *waiter = waiter_req->engine;
c8c99b0f
BW		 1501 u32 dw1 = MI_SEMAPHORE_MBOX |
1502 MI_SEMAPHORE_COMPARE |
1503 MI_SEMAPHORE_REGISTER;
ebc348b2
BW		 1504 u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id];
1505 int ret;
1ec14ad3 1506
1500f7ea
BW		 1507 /* Throughout all of the GEM code, seqno passed implies our current
1508 * seqno is >= the last seqno executed. However for hardware the
1509 * comparison is strictly greater than.
1510 */
1511 seqno -= 1;
1512
ebc348b2 1513 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
686cb5f9 1514
5fb9de1a 1515 ret = intel_ring_begin(waiter_req, 4);
1ec14ad3
CW		 1516 if (ret)
1517 return ret;
1518
f72b3435
MK		 1519 /* If seqno wrap happened, omit the wait with no-ops */
1520 if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
ebc348b2 1521 intel_ring_emit(waiter, dw1 | wait_mbox);
f72b3435
MK		 1522 intel_ring_emit(waiter, seqno);
1523 intel_ring_emit(waiter, 0);
1524 intel_ring_emit(waiter, MI_NOOP);
1525 } else {
1526 intel_ring_emit(waiter, MI_NOOP);
1527 intel_ring_emit(waiter, MI_NOOP);
1528 intel_ring_emit(waiter, MI_NOOP);
1529 intel_ring_emit(waiter, MI_NOOP);
1530 }
c8c99b0f 1531 intel_ring_advance(waiter);
1ec14ad3
CW		 1532
1533 return 0;
1534}
1535
c6df541c
CW		 1536#define PIPE_CONTROL_FLUSH(ring__, addr__) \
1537do { \
fcbc34e4
KG		 1538 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
1539 PIPE_CONTROL_DEPTH_STALL); \
c6df541c
CW		 1540 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
1541 intel_ring_emit(ring__, 0); \
1542 intel_ring_emit(ring__, 0); \
1543} while (0)
1544
1545static int
ee044a88 1546pc_render_add_request(struct drm_i915_gem_request *req)
c6df541c 1547{
4a570db5 1548 struct intel_engine_cs *engine = req->engine;
e2f80391 1549 u32 scratch_addr = engine->scratch.gtt_offset + 2 * CACHELINE_BYTES;
c6df541c
CW		 1550 int ret;
1551
1552 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
1553 * incoherent with writes to memory, i.e. completely fubar,
1554 * so we need to use PIPE_NOTIFY instead.
1555 *
1556 * However, we also need to workaround the qword write
1557 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
1558 * memory before requesting an interrupt.
1559 */
5fb9de1a 1560 ret = intel_ring_begin(req, 32);
c6df541c
CW		 1561 if (ret)
1562 return ret;
1563
e2f80391
TU		 1564 intel_ring_emit(engine,
1565 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1566 PIPE_CONTROL_WRITE_FLUSH |
1567 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
e2f80391
TU		 1568 intel_ring_emit(engine,
1569 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1570 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1571 intel_ring_emit(engine, 0);
1572 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1573 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */
e2f80391 1574 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1575 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1576 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1577 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1578 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1579 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1580 PIPE_CONTROL_FLUSH(engine, scratch_addr);
18393f63 1581 scratch_addr += 2 * CACHELINE_BYTES;
e2f80391 1582 PIPE_CONTROL_FLUSH(engine, scratch_addr);
a71d8d94 1583
e2f80391
TU		 1584 intel_ring_emit(engine,
1585 GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
9d971b37
KG		 1586 PIPE_CONTROL_WRITE_FLUSH |
1587 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
c6df541c 1588 PIPE_CONTROL_NOTIFY);
e2f80391
TU		 1589 intel_ring_emit(engine,
1590 engine->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
1591 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1592 intel_ring_emit(engine, 0);
1593 __intel_ring_advance(engine);
c6df541c 1594
c6df541c
CW		 1595 return 0;
1596}
1597
c04e0f3b
CW		 1598static void
1599gen6_seqno_barrier(struct intel_engine_cs *engine)
4cd53c0c 1600{
e32da7ad
CW		 1601 struct drm_i915_private *dev_priv = engine->dev->dev_private;
1602
4cd53c0c
DV		 1603 /* Workaround to force correct ordering between irq and seqno writes on
1604 * ivb (and maybe also on snb) by reading from a CS register (like
9b9ed309
CW		 1605 * ACTHD) before reading the status page.
1606 *
1607 * Note that this effectively stalls the read by the time it takes to
1608 * do a memory transaction, which more or less ensures that the write
1609 * from the GPU has sufficient time to invalidate the CPU cacheline.
1610 * Alternatively we could delay the interrupt from the CS ring to give
1611 * the write time to land, but that would incur a delay after every
1612 * batch i.e. much more frequent than a delay when waiting for the
1613 * interrupt (with the same net latency).
e32da7ad
CW		 1614 *
1615 * Also note that to prevent whole machine hangs on gen7, we have to
1616 * take the spinlock to guard against concurrent cacheline access.
9b9ed309 1617 */
e32da7ad 1618 spin_lock_irq(&dev_priv->uncore.lock);
c04e0f3b 1619 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
e32da7ad 1620 spin_unlock_irq(&dev_priv->uncore.lock);
4cd53c0c
DV		 1621}
1622
8187a2b7 1623static u32
c04e0f3b 1624ring_get_seqno(struct intel_engine_cs *engine)
8187a2b7 1625{
0bc40be8 1626 return intel_read_status_page(engine, I915_GEM_HWS_INDEX);
1ec14ad3
CW		 1627}
1628
b70ec5bf 1629static void
0bc40be8 1630ring_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1631{
0bc40be8 1632 intel_write_status_page(engine, I915_GEM_HWS_INDEX, seqno);
b70ec5bf
MK		 1633}
1634
c6df541c 1635static u32
c04e0f3b 1636pc_render_get_seqno(struct intel_engine_cs *engine)
c6df541c 1637{
0bc40be8 1638 return engine->scratch.cpu_page[0];
c6df541c
CW		 1639}
1640
b70ec5bf 1641static void
0bc40be8 1642pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
b70ec5bf 1643{
0bc40be8 1644 engine->scratch.cpu_page[0] = seqno;
b70ec5bf
MK		 1645}
1646
e48d8634 1647static bool
0bc40be8 1648gen5_ring_get_irq(struct intel_engine_cs *engine)
e48d8634 1649{
0bc40be8 1650 struct drm_device *dev = engine->dev;
4640c4ff 1651 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1652 unsigned long flags;
e48d8634 1653
7cd512f1 1654 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
e48d8634
DV		 1655 return false;
1656
7338aefa 1657 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1658 if (engine->irq_refcount++ == 0)
1659 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1660 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1661
1662 return true;
1663}
1664
1665static void
0bc40be8 1666gen5_ring_put_irq(struct intel_engine_cs *engine)
e48d8634 1667{
0bc40be8 1668 struct drm_device *dev = engine->dev;
4640c4ff 1669 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1670 unsigned long flags;
e48d8634 1671
7338aefa 1672 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1673 if (--engine->irq_refcount == 0)
1674 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
7338aefa 1675 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
e48d8634
DV		 1676}
1677
b13c2b96 1678static bool
0bc40be8 1679i9xx_ring_get_irq(struct intel_engine_cs *engine)
62fdfeaf 1680{
0bc40be8 1681 struct drm_device *dev = engine->dev;
4640c4ff 1682 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1683 unsigned long flags;
62fdfeaf 1684
7cd512f1 1685 if (!intel_irqs_enabled(dev_priv))
b13c2b96
CW		 1686 return false;
1687
7338aefa 1688 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1689 if (engine->irq_refcount++ == 0) {
1690 dev_priv->irq_mask &= ~engine->irq_enable_mask;
f637fde4
DV		 1691 I915_WRITE(IMR, dev_priv->irq_mask);
1692 POSTING_READ(IMR);
1693 }
7338aefa 1694 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
b13c2b96
CW		 1695
1696 return true;
62fdfeaf
EA		 1697}
1698
8187a2b7 1699static void
0bc40be8 1700i9xx_ring_put_irq(struct intel_engine_cs *engine)
62fdfeaf 1701{
0bc40be8 1702 struct drm_device *dev = engine->dev;
4640c4ff 1703 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1704 unsigned long flags;
62fdfeaf 1705
7338aefa 1706 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1707 if (--engine->irq_refcount == 0) {
1708 dev_priv->irq_mask |= engine->irq_enable_mask;
f637fde4
DV		 1709 I915_WRITE(IMR, dev_priv->irq_mask);
1710 POSTING_READ(IMR);
1711 }
7338aefa 1712 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
62fdfeaf
EA		 1713}
1714
c2798b19 1715static bool
0bc40be8 1716i8xx_ring_get_irq(struct intel_engine_cs *engine)
c2798b19 1717{
0bc40be8 1718 struct drm_device *dev = engine->dev;
4640c4ff 1719 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1720 unsigned long flags;
c2798b19 1721
7cd512f1 1722 if (!intel_irqs_enabled(dev_priv))
c2798b19
CW		 1723 return false;
1724
7338aefa 1725 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1726 if (engine->irq_refcount++ == 0) {
1727 dev_priv->irq_mask &= ~engine->irq_enable_mask;
c2798b19
CW		 1728 I915_WRITE16(IMR, dev_priv->irq_mask);
1729 POSTING_READ16(IMR);
1730 }
7338aefa 1731 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1732
1733 return true;
1734}
1735
1736static void
0bc40be8 1737i8xx_ring_put_irq(struct intel_engine_cs *engine)
c2798b19 1738{
0bc40be8 1739 struct drm_device *dev = engine->dev;
4640c4ff 1740 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1741 unsigned long flags;
c2798b19 1742
7338aefa 1743 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1744 if (--engine->irq_refcount == 0) {
1745 dev_priv->irq_mask |= engine->irq_enable_mask;
c2798b19
CW		 1746 I915_WRITE16(IMR, dev_priv->irq_mask);
1747 POSTING_READ16(IMR);
1748 }
7338aefa 1749 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
c2798b19
CW		 1750}
1751
b72f3acb 1752static int
a84c3ae1 1753bsd_ring_flush(struct drm_i915_gem_request *req,
78501eac
CW		 1754 u32 invalidate_domains,
1755 u32 flush_domains)
d1b851fc 1756{
4a570db5 1757 struct intel_engine_cs *engine = req->engine;
b72f3acb
CW		 1758 int ret;
1759
5fb9de1a 1760 ret = intel_ring_begin(req, 2);
b72f3acb
CW		 1761 if (ret)
1762 return ret;
1763
e2f80391
TU		 1764 intel_ring_emit(engine, MI_FLUSH);
1765 intel_ring_emit(engine, MI_NOOP);
1766 intel_ring_advance(engine);
b72f3acb 1767 return 0;
d1b851fc
ZN		 1768}
1769
3cce469c 1770static int
ee044a88 1771i9xx_add_request(struct drm_i915_gem_request *req)
d1b851fc 1772{
4a570db5 1773 struct intel_engine_cs *engine = req->engine;
3cce469c
CW		 1774 int ret;
1775
5fb9de1a 1776 ret = intel_ring_begin(req, 4);
3cce469c
CW		 1777 if (ret)
1778 return ret;
6f392d54 1779
e2f80391
TU		 1780 intel_ring_emit(engine, MI_STORE_DWORD_INDEX);
1781 intel_ring_emit(engine,
1782 I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1783 intel_ring_emit(engine, i915_gem_request_get_seqno(req));
1784 intel_ring_emit(engine, MI_USER_INTERRUPT);
1785 __intel_ring_advance(engine);
d1b851fc 1786
3cce469c 1787 return 0;
d1b851fc
ZN		 1788}
1789
0f46832f 1790static bool
0bc40be8 1791gen6_ring_get_irq(struct intel_engine_cs *engine)
0f46832f 1792{
0bc40be8 1793 struct drm_device *dev = engine->dev;
4640c4ff 1794 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1795 unsigned long flags;
0f46832f 1796
7cd512f1
DV		 1797 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
1798 return false;
0f46832f 1799
7338aefa 1800 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1801 if (engine->irq_refcount++ == 0) {
1802 if (HAS_L3_DPF(dev) && engine->id == RCS)
1803 I915_WRITE_IMR(engine,
1804 ~(engine->irq_enable_mask |
35a85ac6 1805 GT_PARITY_ERROR(dev)));
15b9f80e 1806 else
0bc40be8
TU		 1807 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1808 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
0f46832f 1809 }
7338aefa 1810 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
0f46832f
CW		 1811
1812 return true;
1813}
1814
1815static void
0bc40be8 1816gen6_ring_put_irq(struct intel_engine_cs *engine)
0f46832f 1817{
0bc40be8 1818 struct drm_device *dev = engine->dev;
4640c4ff 1819 struct drm_i915_private *dev_priv = dev->dev_private;
7338aefa 1820 unsigned long flags;
0f46832f 1821
7338aefa 1822 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1823 if (--engine->irq_refcount == 0) {
1824 if (HAS_L3_DPF(dev) && engine->id == RCS)
1825 I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
15b9f80e 1826 else
0bc40be8
TU		 1827 I915_WRITE_IMR(engine, ~0);
1828 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
1ec14ad3 1829 }
7338aefa 1830 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
d1b851fc
ZN		 1831}
1832
a19d2933 1833static bool
0bc40be8 1834hsw_vebox_get_irq(struct intel_engine_cs *engine)
a19d2933 1835{
0bc40be8 1836 struct drm_device *dev = engine->dev;
a19d2933
BW		 1837 struct drm_i915_private *dev_priv = dev->dev_private;
1838 unsigned long flags;
1839
7cd512f1 1840 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
a19d2933
BW		 1841 return false;
1842
59cdb63d 1843 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1844 if (engine->irq_refcount++ == 0) {
1845 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
1846 gen6_enable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1847 }
59cdb63d 1848 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1849
1850 return true;
1851}
1852
1853static void
0bc40be8 1854hsw_vebox_put_irq(struct intel_engine_cs *engine)
a19d2933 1855{
0bc40be8 1856 struct drm_device *dev = engine->dev;
a19d2933
BW		 1857 struct drm_i915_private *dev_priv = dev->dev_private;
1858 unsigned long flags;
1859
59cdb63d 1860 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1861 if (--engine->irq_refcount == 0) {
1862 I915_WRITE_IMR(engine, ~0);
1863 gen6_disable_pm_irq(dev_priv, engine->irq_enable_mask);
a19d2933 1864 }
59cdb63d 1865 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
a19d2933
BW		 1866}
1867
abd58f01 1868static bool
0bc40be8 1869gen8_ring_get_irq(struct intel_engine_cs *engine)
abd58f01 1870{
0bc40be8 1871 struct drm_device *dev = engine->dev;
abd58f01
BW		 1872 struct drm_i915_private *dev_priv = dev->dev_private;
1873 unsigned long flags;
1874
7cd512f1 1875 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
abd58f01
BW		 1876 return false;
1877
1878 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1879 if (engine->irq_refcount++ == 0) {
1880 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1881 I915_WRITE_IMR(engine,
1882 ~(engine->irq_enable_mask |
abd58f01
BW		 1883 GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1884 } else {
0bc40be8 1885 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
abd58f01 1886 }
0bc40be8 1887 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1888 }
1889 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1890
1891 return true;
1892}
1893
1894static void
0bc40be8 1895gen8_ring_put_irq(struct intel_engine_cs *engine)
abd58f01 1896{
0bc40be8 1897 struct drm_device *dev = engine->dev;
abd58f01
BW		 1898 struct drm_i915_private *dev_priv = dev->dev_private;
1899 unsigned long flags;
1900
1901 spin_lock_irqsave(&dev_priv->irq_lock, flags);
0bc40be8
TU		 1902 if (--engine->irq_refcount == 0) {
1903 if (HAS_L3_DPF(dev) && engine->id == RCS) {
1904 I915_WRITE_IMR(engine,
abd58f01
BW		 1905 ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1906 } else {
0bc40be8 1907 I915_WRITE_IMR(engine, ~0);
abd58f01 1908 }
0bc40be8 1909 POSTING_READ(RING_IMR(engine->mmio_base));
abd58f01
BW		 1910 }
1911 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1912}
1913
d1b851fc 1914static int
53fddaf7 1915i965_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 1916 u64 offset, u32 length,
8e004efc 1917 unsigned dispatch_flags)
d1b851fc 1918{
4a570db5 1919 struct intel_engine_cs *engine = req->engine;
e1f99ce6 1920 int ret;
78501eac 1921
5fb9de1a 1922 ret = intel_ring_begin(req, 2);
e1f99ce6
CW		 1923 if (ret)
1924 return ret;
1925
e2f80391 1926 intel_ring_emit(engine,
65f56876
CW		 1927 MI_BATCH_BUFFER_START |
1928 MI_BATCH_GTT |
8e004efc
JH		 1929 (dispatch_flags & I915_DISPATCH_SECURE ?
1930 0 : MI_BATCH_NON_SECURE_I965));
e2f80391
TU		 1931 intel_ring_emit(engine, offset);
1932 intel_ring_advance(engine);
78501eac 1933
d1b851fc
ZN		 1934 return 0;
1935}
1936
b45305fc
DV		 1937/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1938#define I830_BATCH_LIMIT (256*1024)
c4d69da1
CW		 1939#define I830_TLB_ENTRIES (2)
1940#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
8187a2b7 1941static int
53fddaf7 1942i830_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 1943 u64 offset, u32 len,
1944 unsigned dispatch_flags)
62fdfeaf 1945{
4a570db5 1946 struct intel_engine_cs *engine = req->engine;
e2f80391 1947 u32 cs_offset = engine->scratch.gtt_offset;
c4e7a414 1948 int ret;
62fdfeaf 1949
5fb9de1a 1950 ret = intel_ring_begin(req, 6);
c4d69da1
CW		 1951 if (ret)
1952 return ret;
62fdfeaf 1953
c4d69da1 1954 /* Evict the invalid PTE TLBs */
e2f80391
TU		 1955 intel_ring_emit(engine, COLOR_BLT_CMD | BLT_WRITE_RGBA);
1956 intel_ring_emit(engine, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096);
1957 intel_ring_emit(engine, I830_TLB_ENTRIES << 16 | 4); /* load each page */
1958 intel_ring_emit(engine, cs_offset);
1959 intel_ring_emit(engine, 0xdeadbeef);
1960 intel_ring_emit(engine, MI_NOOP);
1961 intel_ring_advance(engine);
b45305fc 1962
8e004efc 1963 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
b45305fc
DV		 1964 if (len > I830_BATCH_LIMIT)
1965 return -ENOSPC;
1966
5fb9de1a 1967 ret = intel_ring_begin(req, 6 + 2);
b45305fc
DV		 1968 if (ret)
1969 return ret;
c4d69da1
CW		 1970
1971 /* Blit the batch (which has now all relocs applied) to the
1972 * stable batch scratch bo area (so that the CS never
1973 * stumbles over its tlb invalidation bug) ...
1974 */
e2f80391
TU		 1975 intel_ring_emit(engine, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA);
1976 intel_ring_emit(engine,
1977 BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096);
1978 intel_ring_emit(engine, DIV_ROUND_UP(len, 4096) << 16 | 4096);
1979 intel_ring_emit(engine, cs_offset);
1980 intel_ring_emit(engine, 4096);
1981 intel_ring_emit(engine, offset);
1982
1983 intel_ring_emit(engine, MI_FLUSH);
1984 intel_ring_emit(engine, MI_NOOP);
1985 intel_ring_advance(engine);
b45305fc
DV		 1986
1987 /* ... and execute it. */
c4d69da1 1988 offset = cs_offset;
b45305fc 1989 }
e1f99ce6 1990
9d611c03 1991 ret = intel_ring_begin(req, 2);
c4d69da1
CW		 1992 if (ret)
1993 return ret;
1994
e2f80391
TU		 1995 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1996 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
1997 0 : MI_BATCH_NON_SECURE));
1998 intel_ring_advance(engine);
c4d69da1 1999
fb3256da
DV		 2000 return 0;
2001}
2002
2003static int
53fddaf7 2004i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2005 u64 offset, u32 len,
8e004efc 2006 unsigned dispatch_flags)
fb3256da 2007{
4a570db5 2008 struct intel_engine_cs *engine = req->engine;
fb3256da
DV		 2009 int ret;
2010
5fb9de1a 2011 ret = intel_ring_begin(req, 2);
fb3256da
DV		 2012 if (ret)
2013 return ret;
2014
e2f80391
TU		 2015 intel_ring_emit(engine, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
2016 intel_ring_emit(engine, offset | (dispatch_flags & I915_DISPATCH_SECURE ?
2017 0 : MI_BATCH_NON_SECURE));
2018 intel_ring_advance(engine);
62fdfeaf 2019
62fdfeaf
EA		 2020 return 0;
2021}
2022
0bc40be8 2023static void cleanup_phys_status_page(struct intel_engine_cs *engine)
7d3fdfff 2024{
0bc40be8 2025 struct drm_i915_private *dev_priv = to_i915(engine->dev);
7d3fdfff
VS		 2026
2027 if (!dev_priv->status_page_dmah)
2028 return;
2029
0bc40be8
TU		 2030 drm_pci_free(engine->dev, dev_priv->status_page_dmah);
2031 engine->status_page.page_addr = NULL;
7d3fdfff
VS		 2032}
2033
0bc40be8 2034static void cleanup_status_page(struct intel_engine_cs *engine)
62fdfeaf 2035{
05394f39 2036 struct drm_i915_gem_object *obj;
62fdfeaf 2037
0bc40be8 2038 obj = engine->status_page.obj;
8187a2b7 2039 if (obj == NULL)
62fdfeaf 2040 return;
62fdfeaf 2041
9da3da66 2042 kunmap(sg_page(obj->pages->sgl));
d7f46fc4 2043 i915_gem_object_ggtt_unpin(obj);
05394f39 2044 drm_gem_object_unreference(&obj->base);
0bc40be8 2045 engine->status_page.obj = NULL;
62fdfeaf
EA		 2046}
2047
0bc40be8 2048static int init_status_page(struct intel_engine_cs *engine)
62fdfeaf 2049{
0bc40be8 2050 struct drm_i915_gem_object *obj = engine->status_page.obj;
62fdfeaf 2051
7d3fdfff 2052 if (obj == NULL) {
1f767e02 2053 unsigned flags;
e3efda49 2054 int ret;
e4ffd173 2055
0bc40be8 2056 obj = i915_gem_alloc_object(engine->dev, 4096);
e3efda49
CW		 2057 if (obj == NULL) {
2058 DRM_ERROR("Failed to allocate status page\n");
2059 return -ENOMEM;
2060 }
62fdfeaf 2061
e3efda49
CW		 2062 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2063 if (ret)
2064 goto err_unref;
2065
1f767e02 2066 flags = 0;
0bc40be8 2067 if (!HAS_LLC(engine->dev))
1f767e02
CW		 2068 /* On g33, we cannot place HWS above 256MiB, so
2069 * restrict its pinning to the low mappable arena.
2070 * Though this restriction is not documented for
2071 * gen4, gen5, or byt, they also behave similarly
2072 * and hang if the HWS is placed at the top of the
2073 * GTT. To generalise, it appears that all !llc
2074 * platforms have issues with us placing the HWS
2075 * above the mappable region (even though we never
2076 * actualy map it).
2077 */
2078 flags |= PIN_MAPPABLE;
2079 ret = i915_gem_obj_ggtt_pin(obj, 4096, flags);
e3efda49
CW		 2080 if (ret) {
2081err_unref:
2082 drm_gem_object_unreference(&obj->base);
2083 return ret;
2084 }
2085
0bc40be8 2086 engine->status_page.obj = obj;
e3efda49 2087 }
62fdfeaf 2088
0bc40be8
TU		 2089 engine->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj);
2090 engine->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
2091 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 2092
8187a2b7 2093 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
0bc40be8 2094 engine->name, engine->status_page.gfx_addr);
62fdfeaf
EA		 2095
2096 return 0;
62fdfeaf
EA		 2097}
2098
0bc40be8 2099static int init_phys_status_page(struct intel_engine_cs *engine)
6b8294a4 2100{
0bc40be8 2101 struct drm_i915_private *dev_priv = engine->dev->dev_private;
6b8294a4
CW		 2102
2103 if (!dev_priv->status_page_dmah) {
2104 dev_priv->status_page_dmah =
0bc40be8 2105 drm_pci_alloc(engine->dev, PAGE_SIZE, PAGE_SIZE);
6b8294a4
CW		 2106 if (!dev_priv->status_page_dmah)
2107 return -ENOMEM;
2108 }
2109
0bc40be8
TU		 2110 engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
2111 memset(engine->status_page.page_addr, 0, PAGE_SIZE);
6b8294a4
CW		 2112
2113 return 0;
2114}
2115
7ba717cf 2116void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
2919d291 2117{
def0c5f6 2118 if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
0a798eb9 2119 i915_gem_object_unpin_map(ringbuf->obj);
def0c5f6
CW		 2120 else
2121 iounmap(ringbuf->virtual_start);
8305216f 2122 ringbuf->virtual_start = NULL;
0eb973d3 2123 ringbuf->vma = NULL;
2919d291 2124 i915_gem_object_ggtt_unpin(ringbuf->obj);
7ba717cf
TD		 2125}
2126
2127int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
2128 struct intel_ringbuffer *ringbuf)
2129{
2130 struct drm_i915_private *dev_priv = to_i915(dev);
72e96d64 2131 struct i915_ggtt *ggtt = &dev_priv->ggtt;
7ba717cf 2132 struct drm_i915_gem_object *obj = ringbuf->obj;
a687a43a
CW		 2133 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
2134 unsigned flags = PIN_OFFSET_BIAS | 4096;
8305216f 2135 void *addr;
7ba717cf
TD		 2136 int ret;
2137
def0c5f6 2138 if (HAS_LLC(dev_priv) && !obj->stolen) {
a687a43a 2139 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, flags);
def0c5f6
CW		 2140 if (ret)
2141 return ret;
7ba717cf 2142
def0c5f6 2143 ret = i915_gem_object_set_to_cpu_domain(obj, true);
d2cad535
CW		 2144 if (ret)
2145 goto err_unpin;
def0c5f6 2146
8305216f
DG		 2147 addr = i915_gem_object_pin_map(obj);
2148 if (IS_ERR(addr)) {
2149 ret = PTR_ERR(addr);
d2cad535 2150 goto err_unpin;
def0c5f6
CW		 2151 }
2152 } else {
a687a43a
CW		 2153 ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE,
2154 flags | PIN_MAPPABLE);
def0c5f6
CW		 2155 if (ret)
2156 return ret;
7ba717cf 2157
def0c5f6 2158 ret = i915_gem_object_set_to_gtt_domain(obj, true);
d2cad535
CW		 2159 if (ret)
2160 goto err_unpin;
def0c5f6 2161
ff3dc087
DCS		 2162 /* Access through the GTT requires the device to be awake. */
2163 assert_rpm_wakelock_held(dev_priv);
2164
8305216f
DG		 2165 addr = ioremap_wc(ggtt->mappable_base +
2166 i915_gem_obj_ggtt_offset(obj), ringbuf->size);
2167 if (addr == NULL) {
d2cad535
CW		 2168 ret = -ENOMEM;
2169 goto err_unpin;
def0c5f6 2170 }
7ba717cf
TD		 2171 }
2172
8305216f 2173 ringbuf->virtual_start = addr;
0eb973d3 2174 ringbuf->vma = i915_gem_obj_to_ggtt(obj);
7ba717cf 2175 return 0;
d2cad535
CW		 2176
2177err_unpin:
2178 i915_gem_object_ggtt_unpin(obj);
2179 return ret;
7ba717cf
TD		 2180}
2181
01101fa7 2182static void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
7ba717cf 2183{
2919d291
OM		 2184 drm_gem_object_unreference(&ringbuf->obj->base);
2185 ringbuf->obj = NULL;
2186}
2187
01101fa7
CW		 2188static int intel_alloc_ringbuffer_obj(struct drm_device *dev,
2189 struct intel_ringbuffer *ringbuf)
62fdfeaf 2190{
05394f39 2191 struct drm_i915_gem_object *obj;
62fdfeaf 2192
ebc052e0
CW		 2193 obj = NULL;
2194 if (!HAS_LLC(dev))
93b0a4e0 2195 obj = i915_gem_object_create_stolen(dev, ringbuf->size);
ebc052e0 2196 if (obj == NULL)
93b0a4e0 2197 obj = i915_gem_alloc_object(dev, ringbuf->size);
e3efda49
CW		 2198 if (obj == NULL)
2199 return -ENOMEM;
8187a2b7 2200
24f3a8cf
AG		 2201 /* mark ring buffers as read-only from GPU side by default */
2202 obj->gt_ro = 1;
2203
93b0a4e0 2204 ringbuf->obj = obj;
e3efda49 2205
7ba717cf 2206 return 0;
e3efda49
CW		 2207}
2208
01101fa7
CW		 2209struct intel_ringbuffer *
2210intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
2211{
2212 struct intel_ringbuffer *ring;
2213 int ret;
2214
2215 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
608c1a52
CW		 2216 if (ring == NULL) {
2217 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s\n",
2218 engine->name);
01101fa7 2219 return ERR_PTR(-ENOMEM);
608c1a52 2220 }
01101fa7 2221
4a570db5 2222 ring->engine = engine;
608c1a52 2223 list_add(&ring->link, &engine->buffers);
01101fa7
CW		 2224
2225 ring->size = size;
2226 /* Workaround an erratum on the i830 which causes a hang if
2227 * the TAIL pointer points to within the last 2 cachelines
2228 * of the buffer.
2229 */
2230 ring->effective_size = size;
2231 if (IS_I830(engine->dev) || IS_845G(engine->dev))
2232 ring->effective_size -= 2 * CACHELINE_BYTES;
2233
2234 ring->last_retired_head = -1;
2235 intel_ring_update_space(ring);
2236
2237 ret = intel_alloc_ringbuffer_obj(engine->dev, ring);
2238 if (ret) {
608c1a52
CW		 2239 DRM_DEBUG_DRIVER("Failed to allocate ringbuffer %s: %d\n",
2240 engine->name, ret);
2241 list_del(&ring->link);
01101fa7
CW		 2242 kfree(ring);
2243 return ERR_PTR(ret);
2244 }
2245
2246 return ring;
2247}
2248
2249void
2250intel_ringbuffer_free(struct intel_ringbuffer *ring)
2251{
2252 intel_destroy_ringbuffer_obj(ring);
608c1a52 2253 list_del(&ring->link);
01101fa7
CW		 2254 kfree(ring);
2255}
2256
e3efda49 2257static int intel_init_ring_buffer(struct drm_device *dev,
0bc40be8 2258 struct intel_engine_cs *engine)
e3efda49 2259{
bfc882b4 2260 struct intel_ringbuffer *ringbuf;
e3efda49
CW		 2261 int ret;
2262
0bc40be8 2263 WARN_ON(engine->buffer);
bfc882b4 2264
0bc40be8
TU		 2265 engine->dev = dev;
2266 INIT_LIST_HEAD(&engine->active_list);
2267 INIT_LIST_HEAD(&engine->request_list);
2268 INIT_LIST_HEAD(&engine->execlist_queue);
2269 INIT_LIST_HEAD(&engine->buffers);
2270 i915_gem_batch_pool_init(dev, &engine->batch_pool);
2271 memset(engine->semaphore.sync_seqno, 0,
2272 sizeof(engine->semaphore.sync_seqno));
e3efda49 2273
0bc40be8 2274 init_waitqueue_head(&engine->irq_queue);
e3efda49 2275
0bc40be8 2276 ringbuf = intel_engine_create_ringbuffer(engine, 32 * PAGE_SIZE);
b0366a54
DG		 2277 if (IS_ERR(ringbuf)) {
2278 ret = PTR_ERR(ringbuf);
2279 goto error;
2280 }
0bc40be8 2281 engine->buffer = ringbuf;
01101fa7 2282
e3efda49 2283 if (I915_NEED_GFX_HWS(dev)) {
0bc40be8 2284 ret = init_status_page(engine);
e3efda49 2285 if (ret)
8ee14975 2286 goto error;
e3efda49 2287 } else {
0bc40be8
TU		 2288 WARN_ON(engine->id != RCS);
2289 ret = init_phys_status_page(engine);
e3efda49 2290 if (ret)
8ee14975 2291 goto error;
e3efda49
CW		 2292 }
2293
bfc882b4
DV		 2294 ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf);
2295 if (ret) {
2296 DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n",
0bc40be8 2297 engine->name, ret);
bfc882b4
DV		 2298 intel_destroy_ringbuffer_obj(ringbuf);
2299 goto error;
e3efda49 2300 }
62fdfeaf 2301
0bc40be8 2302 ret = i915_cmd_parser_init_ring(engine);
44e895a8 2303 if (ret)
8ee14975
OM		 2304 goto error;
2305
8ee14975 2306 return 0;
351e3db2 2307
8ee14975 2308error:
117897f4 2309 intel_cleanup_engine(engine);
8ee14975 2310 return ret;
62fdfeaf
EA		 2311}
2312
117897f4 2313void intel_cleanup_engine(struct intel_engine_cs *engine)
62fdfeaf 2314{
6402c330 2315 struct drm_i915_private *dev_priv;
33626e6a 2316
117897f4 2317 if (!intel_engine_initialized(engine))
62fdfeaf
EA		 2318 return;
2319
0bc40be8 2320 dev_priv = to_i915(engine->dev);
6402c330 2321
0bc40be8 2322 if (engine->buffer) {
117897f4 2323 intel_stop_engine(engine);
0bc40be8 2324 WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
33626e6a 2325
0bc40be8
TU		 2326 intel_unpin_ringbuffer_obj(engine->buffer);
2327 intel_ringbuffer_free(engine->buffer);
2328 engine->buffer = NULL;
b0366a54 2329 }
78501eac 2330
0bc40be8
TU		 2331 if (engine->cleanup)
2332 engine->cleanup(engine);
8d19215b 2333
0bc40be8
TU		 2334 if (I915_NEED_GFX_HWS(engine->dev)) {
2335 cleanup_status_page(engine);
7d3fdfff 2336 } else {
0bc40be8
TU		 2337 WARN_ON(engine->id != RCS);
2338 cleanup_phys_status_page(engine);
7d3fdfff 2339 }
44e895a8 2340
0bc40be8
TU		 2341 i915_cmd_parser_fini_ring(engine);
2342 i915_gem_batch_pool_fini(&engine->batch_pool);
2343 engine->dev = NULL;
62fdfeaf
EA		 2344}
2345
666796da 2346int intel_engine_idle(struct intel_engine_cs *engine)
3e960501 2347{
a4b3a571 2348 struct drm_i915_gem_request *req;
3e960501 2349
3e960501 2350 /* Wait upon the last request to be completed */
0bc40be8 2351 if (list_empty(&engine->request_list))
3e960501
CW		 2352 return 0;
2353
0bc40be8
TU		 2354 req = list_entry(engine->request_list.prev,
2355 struct drm_i915_gem_request,
2356 list);
b4716185
CW		 2357
2358 /* Make sure we do not trigger any retires */
2359 return __i915_wait_request(req,
c19ae989 2360 req->i915->mm.interruptible,
b4716185 2361 NULL, NULL);
3e960501
CW		 2362}
2363
6689cb2b 2364int intel_ring_alloc_request_extras(struct drm_i915_gem_request *request)
9d773091 2365{
4a570db5 2366 request->ringbuf = request->engine->buffer;
9eba5d4a 2367 return 0;
9d773091
CW		 2368}
2369
ccd98fe4
JH		 2370int intel_ring_reserve_space(struct drm_i915_gem_request *request)
2371{
2372 /*
2373 * The first call merely notes the reserve request and is common for
2374 * all back ends. The subsequent localised _begin() call actually
2375 * ensures that the reservation is available. Without the begin, if
2376 * the request creator immediately submitted the request without
2377 * adding any commands to it then there might not actually be
2378 * sufficient room for the submission commands.
2379 */
2380 intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST);
2381
2382 return intel_ring_begin(request, 0);
2383}
2384
29b1b415
JH		 2385void intel_ring_reserved_space_reserve(struct intel_ringbuffer *ringbuf, int size)
2386{
92dcc67c 2387 GEM_BUG_ON(ringbuf->reserved_size);
29b1b415 2388 ringbuf->reserved_size = size;
29b1b415
JH		 2389}
2390
2391void intel_ring_reserved_space_cancel(struct intel_ringbuffer *ringbuf)
2392{
92dcc67c 2393 GEM_BUG_ON(!ringbuf->reserved_size);
29b1b415 2394 ringbuf->reserved_size = 0;
29b1b415
JH		 2395}
2396
2397void intel_ring_reserved_space_use(struct intel_ringbuffer *ringbuf)
2398{
92dcc67c
CW		 2399 GEM_BUG_ON(!ringbuf->reserved_size);
2400 ringbuf->reserved_size = 0;
29b1b415
JH		 2401}
2402
2403void intel_ring_reserved_space_end(struct intel_ringbuffer *ringbuf)
2404{
92dcc67c
CW		 2405 GEM_BUG_ON(ringbuf->reserved_size);
2406}
2407
2408static int wait_for_space(struct drm_i915_gem_request *req, int bytes)
2409{
2410 struct intel_ringbuffer *ringbuf = req->ringbuf;
2411 struct intel_engine_cs *engine = req->engine;
2412 struct drm_i915_gem_request *target;
2413
2414 intel_ring_update_space(ringbuf);
2415 if (ringbuf->space >= bytes)
2416 return 0;
2417
2418 /*
2419 * Space is reserved in the ringbuffer for finalising the request,
2420 * as that cannot be allowed to fail. During request finalisation,
2421 * reserved_space is set to 0 to stop the overallocation and the
2422 * assumption is that then we never need to wait (which has the
2423 * risk of failing with EINTR).
2424 *
2425 * See also i915_gem_request_alloc() and i915_add_request().
2426 */
2427 GEM_BUG_ON(!ringbuf->reserved_size);
2428
2429 list_for_each_entry(target, &engine->request_list, list) {
2430 unsigned space;
2431
79bbcc29 2432 /*
92dcc67c
CW		 2433 * The request queue is per-engine, so can contain requests
2434 * from multiple ringbuffers. Here, we must ignore any that
2435 * aren't from the ringbuffer we're considering.
79bbcc29 2436 */
92dcc67c
CW		 2437 if (target->ringbuf != ringbuf)
2438 continue;
2439
2440 /* Would completion of this request free enough space? */
2441 space = __intel_ring_space(target->postfix, ringbuf->tail,
2442 ringbuf->size);
2443 if (space >= bytes)
2444 break;
79bbcc29 2445 }
29b1b415 2446
92dcc67c
CW		 2447 if (WARN_ON(&target->list == &engine->request_list))
2448 return -ENOSPC;
2449
2450 return i915_wait_request(target);
29b1b415
JH		 2451}
2452
92dcc67c 2453int intel_ring_begin(struct drm_i915_gem_request *req, int num_dwords)
cbcc80df 2454{
92dcc67c 2455 struct intel_ringbuffer *ringbuf = req->ringbuf;
79bbcc29 2456 int remain_actual = ringbuf->size - ringbuf->tail;
92dcc67c
CW		 2457 int remain_usable = ringbuf->effective_size - ringbuf->tail;
2458 int bytes = num_dwords * sizeof(u32);
2459 int total_bytes, wait_bytes;
79bbcc29 2460 bool need_wrap = false;
29b1b415 2461
92dcc67c 2462 total_bytes = bytes + ringbuf->reserved_size;
29b1b415 2463
79bbcc29
JH		 2464 if (unlikely(bytes > remain_usable)) {
2465 /*
2466 * Not enough space for the basic request. So need to flush
2467 * out the remainder and then wait for base + reserved.
2468 */
2469 wait_bytes = remain_actual + total_bytes;
2470 need_wrap = true;
92dcc67c
CW		 2471 } else if (unlikely(total_bytes > remain_usable)) {
2472 /*
2473 * The base request will fit but the reserved space
2474 * falls off the end. So we don't need an immediate wrap
2475 * and only need to effectively wait for the reserved
2476 * size space from the start of ringbuffer.
2477 */
2478 wait_bytes = remain_actual + ringbuf->reserved_size;
79bbcc29 2479 } else {
92dcc67c
CW		 2480 /* No wrapping required, just waiting. */
2481 wait_bytes = total_bytes;
cbcc80df
MK		 2482 }
2483
92dcc67c
CW		 2484 if (wait_bytes > ringbuf->space) {
2485 int ret = wait_for_space(req, wait_bytes);
cbcc80df
MK		 2486 if (unlikely(ret))
2487 return ret;
79bbcc29 2488
92dcc67c 2489 intel_ring_update_space(ringbuf);
157d2c7f
CW		 2490 if (unlikely(ringbuf->space < wait_bytes))
2491 return -EAGAIN;
cbcc80df
MK		 2492 }
2493
92dcc67c
CW		 2494 if (unlikely(need_wrap)) {
2495 GEM_BUG_ON(remain_actual > ringbuf->space);
2496 GEM_BUG_ON(ringbuf->tail + remain_actual > ringbuf->size);
78501eac 2497
92dcc67c
CW		 2498 /* Fill the tail with MI_NOOP */
2499 memset(ringbuf->virtual_start + ringbuf->tail,
2500 0, remain_actual);
2501 ringbuf->tail = 0;
2502 ringbuf->space -= remain_actual;
2503 }
304d695c 2504
92dcc67c
CW		 2505 ringbuf->space -= bytes;
2506 GEM_BUG_ON(ringbuf->space < 0);
304d695c 2507 return 0;
8187a2b7 2508}
78501eac 2509
753b1ad4 2510/* Align the ring tail to a cacheline boundary */
bba09b12 2511int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
753b1ad4 2512{
4a570db5 2513 struct intel_engine_cs *engine = req->engine;
e2f80391 2514 int num_dwords = (engine->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t);
753b1ad4
VS		 2515 int ret;
2516
2517 if (num_dwords == 0)
2518 return 0;
2519
18393f63 2520 num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords;
5fb9de1a 2521 ret = intel_ring_begin(req, num_dwords);
753b1ad4
VS		 2522 if (ret)
2523 return ret;
2524
2525 while (num_dwords--)
e2f80391 2526 intel_ring_emit(engine, MI_NOOP);
753b1ad4 2527
e2f80391 2528 intel_ring_advance(engine);
753b1ad4
VS		 2529
2530 return 0;
2531}
2532
0bc40be8 2533void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
498d2ac1 2534{
d04bce48 2535 struct drm_i915_private *dev_priv = to_i915(engine->dev);
498d2ac1 2536
29dcb570
CW		 2537 /* Our semaphore implementation is strictly monotonic (i.e. we proceed
2538 * so long as the semaphore value in the register/page is greater
2539 * than the sync value), so whenever we reset the seqno,
2540 * so long as we reset the tracking semaphore value to 0, it will
2541 * always be before the next request's seqno. If we don't reset
2542 * the semaphore value, then when the seqno moves backwards all
2543 * future waits will complete instantly (causing rendering corruption).
2544 */
d04bce48 2545 if (INTEL_INFO(dev_priv)->gen == 6 || INTEL_INFO(dev_priv)->gen == 7) {
0bc40be8
TU		 2546 I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
2547 I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
d04bce48 2548 if (HAS_VEBOX(dev_priv))
0bc40be8 2549 I915_WRITE(RING_SYNC_2(engine->mmio_base), 0);
e1f99ce6 2550 }
a058d934
CW		 2551 if (dev_priv->semaphore_obj) {
2552 struct drm_i915_gem_object *obj = dev_priv->semaphore_obj;
2553 struct page *page = i915_gem_object_get_dirty_page(obj, 0);
2554 void *semaphores = kmap(page);
2555 memset(semaphores + GEN8_SEMAPHORE_OFFSET(engine->id, 0),
2556 0, I915_NUM_ENGINES * gen8_semaphore_seqno_size);
2557 kunmap(page);
2558 }
29dcb570
CW		 2559 memset(engine->semaphore.sync_seqno, 0,
2560 sizeof(engine->semaphore.sync_seqno));
d97ed339 2561
0bc40be8 2562 engine->set_seqno(engine, seqno);
01347126 2563 engine->last_submitted_seqno = seqno;
29dcb570 2564
0bc40be8 2565 engine->hangcheck.seqno = seqno;
8187a2b7 2566}
62fdfeaf 2567
0bc40be8 2568static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
297b0c5b 2569 u32 value)
881f47b6 2570{
0bc40be8 2571 struct drm_i915_private *dev_priv = engine->dev->dev_private;
881f47b6
XH		 2572
2573 /* Every tail move must follow the sequence below */
12f55818
CW		 2574
2575 /* Disable notification that the ring is IDLE. The GT
2576 * will then assume that it is busy and bring it out of rc6.
2577 */
0206e353 2578 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818
CW		 2579 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
2580
2581 /* Clear the context id. Here be magic! */
2582 I915_WRITE64(GEN6_BSD_RNCID, 0x0);
0206e353 2583
12f55818 2584 /* Wait for the ring not to be idle, i.e. for it to wake up. */
0206e353 2585 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
12f55818
CW		 2586 GEN6_BSD_SLEEP_INDICATOR) == 0,
2587 50))
2588 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
0206e353 2589
12f55818 2590 /* Now that the ring is fully powered up, update the tail */
0bc40be8
TU		 2591 I915_WRITE_TAIL(engine, value);
2592 POSTING_READ(RING_TAIL(engine->mmio_base));
12f55818
CW		 2593
2594 /* Let the ring send IDLE messages to the GT again,
2595 * and so let it sleep to conserve power when idle.
2596 */
0206e353 2597 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
12f55818 2598 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
881f47b6
XH		 2599}
2600
a84c3ae1 2601static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
ea251324 2602 u32 invalidate, u32 flush)
881f47b6 2603{
4a570db5 2604 struct intel_engine_cs *engine = req->engine;
71a77e07 2605 uint32_t cmd;
b72f3acb
CW		 2606 int ret;
2607
5fb9de1a 2608 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2609 if (ret)
2610 return ret;
2611
71a77e07 2612 cmd = MI_FLUSH_DW;
e2f80391 2613 if (INTEL_INFO(engine->dev)->gen >= 8)
075b3bba 2614 cmd += 1;
f0a1fb10
CW		 2615
2616 /* We always require a command barrier so that subsequent
2617 * commands, such as breadcrumb interrupts, are strictly ordered
2618 * wrt the contents of the write cache being flushed to memory
2619 * (and thus being coherent from the CPU).
2620 */
2621 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2622
9a289771
JB		 2623 /*
2624 * Bspec vol 1c.5 - video engine command streamer:
2625 * "If ENABLED, all TLBs will be invalidated once the flush
2626 * operation is complete. This bit is only valid when the
2627 * Post-Sync Operation field is a value of 1h or 3h."
2628 */
71a77e07 2629 if (invalidate & I915_GEM_GPU_DOMAINS)
f0a1fb10
CW		 2630 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2631
e2f80391
TU		 2632 intel_ring_emit(engine, cmd);
2633 intel_ring_emit(engine,
2634 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
2635 if (INTEL_INFO(engine->dev)->gen >= 8) {
2636 intel_ring_emit(engine, 0); /* upper addr */
2637 intel_ring_emit(engine, 0); /* value */
075b3bba 2638 } else {
e2f80391
TU		 2639 intel_ring_emit(engine, 0);
2640 intel_ring_emit(engine, MI_NOOP);
075b3bba 2641 }
e2f80391 2642 intel_ring_advance(engine);
b72f3acb 2643 return 0;
881f47b6
XH		 2644}
2645
1c7a0623 2646static int
53fddaf7 2647gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2648 u64 offset, u32 len,
8e004efc 2649 unsigned dispatch_flags)
1c7a0623 2650{
4a570db5 2651 struct intel_engine_cs *engine = req->engine;
e2f80391 2652 bool ppgtt = USES_PPGTT(engine->dev) &&
8e004efc 2653 !(dispatch_flags & I915_DISPATCH_SECURE);
1c7a0623
BW		 2654 int ret;
2655
5fb9de1a 2656 ret = intel_ring_begin(req, 4);
1c7a0623
BW		 2657 if (ret)
2658 return ret;
2659
2660 /* FIXME(BDW): Address space and security selectors. */
e2f80391 2661 intel_ring_emit(engine, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8) |
919032ec
AJ		 2662 (dispatch_flags & I915_DISPATCH_RS ?
2663 MI_BATCH_RESOURCE_STREAMER : 0));
e2f80391
TU		 2664 intel_ring_emit(engine, lower_32_bits(offset));
2665 intel_ring_emit(engine, upper_32_bits(offset));
2666 intel_ring_emit(engine, MI_NOOP);
2667 intel_ring_advance(engine);
1c7a0623
BW		 2668
2669 return 0;
2670}
2671
d7d4eedd 2672static int
53fddaf7 2673hsw_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
8e004efc
JH		 2674 u64 offset, u32 len,
2675 unsigned dispatch_flags)
d7d4eedd 2676{
4a570db5 2677 struct intel_engine_cs *engine = req->engine;
d7d4eedd
CW		 2678 int ret;
2679
5fb9de1a 2680 ret = intel_ring_begin(req, 2);
d7d4eedd
CW		 2681 if (ret)
2682 return ret;
2683
e2f80391 2684 intel_ring_emit(engine,
77072258 2685 MI_BATCH_BUFFER_START |
8e004efc 2686 (dispatch_flags & I915_DISPATCH_SECURE ?
919032ec
AJ		 2687 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2688 (dispatch_flags & I915_DISPATCH_RS ?
2689 MI_BATCH_RESOURCE_STREAMER : 0));
d7d4eedd 2690 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2691 intel_ring_emit(engine, offset);
2692 intel_ring_advance(engine);
d7d4eedd
CW		 2693
2694 return 0;
2695}
2696
881f47b6 2697static int
53fddaf7 2698gen6_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
9bcb144c 2699 u64 offset, u32 len,
8e004efc 2700 unsigned dispatch_flags)
881f47b6 2701{
4a570db5 2702 struct intel_engine_cs *engine = req->engine;
0206e353 2703 int ret;
ab6f8e32 2704
5fb9de1a 2705 ret = intel_ring_begin(req, 2);
0206e353
AJ		 2706 if (ret)
2707 return ret;
e1f99ce6 2708
e2f80391 2709 intel_ring_emit(engine,
d7d4eedd 2710 MI_BATCH_BUFFER_START |
8e004efc
JH		 2711 (dispatch_flags & I915_DISPATCH_SECURE ?
2712 0 : MI_BATCH_NON_SECURE_I965));
0206e353 2713 /* bit0-7 is the length on GEN6+ */
e2f80391
TU		 2714 intel_ring_emit(engine, offset);
2715 intel_ring_advance(engine);
ab6f8e32 2716
0206e353 2717 return 0;
881f47b6
XH		 2718}
2719
549f7365
CW		 2720/* Blitter support (SandyBridge+) */
2721
a84c3ae1 2722static int gen6_ring_flush(struct drm_i915_gem_request *req,
ea251324 2723 u32 invalidate, u32 flush)
8d19215b 2724{
4a570db5 2725 struct intel_engine_cs *engine = req->engine;
e2f80391 2726 struct drm_device *dev = engine->dev;
71a77e07 2727 uint32_t cmd;
b72f3acb
CW		 2728 int ret;
2729
5fb9de1a 2730 ret = intel_ring_begin(req, 4);
b72f3acb
CW		 2731 if (ret)
2732 return ret;
2733
71a77e07 2734 cmd = MI_FLUSH_DW;
dbef0f15 2735 if (INTEL_INFO(dev)->gen >= 8)
075b3bba 2736 cmd += 1;
f0a1fb10
CW		 2737
2738 /* We always require a command barrier so that subsequent
2739 * commands, such as breadcrumb interrupts, are strictly ordered
2740 * wrt the contents of the write cache being flushed to memory
2741 * (and thus being coherent from the CPU).
2742 */
2743 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2744
9a289771
JB		 2745 /*
2746 * Bspec vol 1c.3 - blitter engine command streamer:
2747 * "If ENABLED, all TLBs will be invalidated once the flush
2748 * operation is complete. This bit is only valid when the
2749 * Post-Sync Operation field is a value of 1h or 3h."
2750 */
71a77e07 2751 if (invalidate & I915_GEM_DOMAIN_RENDER)
f0a1fb10 2752 cmd |= MI_INVALIDATE_TLB;
e2f80391
TU		 2753 intel_ring_emit(engine, cmd);
2754 intel_ring_emit(engine,
2755 I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
dbef0f15 2756 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391
TU		 2757 intel_ring_emit(engine, 0); /* upper addr */
2758 intel_ring_emit(engine, 0); /* value */
075b3bba 2759 } else {
e2f80391
TU		 2760 intel_ring_emit(engine, 0);
2761 intel_ring_emit(engine, MI_NOOP);
075b3bba 2762 }
e2f80391 2763 intel_ring_advance(engine);
fd3da6c9 2764
b72f3acb 2765 return 0;
8d19215b
ZN		 2766}
2767
5c1143bb
XH		 2768int intel_init_render_ring_buffer(struct drm_device *dev)
2769{
4640c4ff 2770 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2771 struct intel_engine_cs *engine = &dev_priv->engine[RCS];
3e78998a
BW		 2772 struct drm_i915_gem_object *obj;
2773 int ret;
5c1143bb 2774
e2f80391
TU		 2775 engine->name = "render ring";
2776 engine->id = RCS;
2777 engine->exec_id = I915_EXEC_RENDER;
83e53802 2778 engine->hw_id = 0;
e2f80391 2779 engine->mmio_base = RENDER_RING_BASE;
59465b5f 2780
707d9cf9 2781 if (INTEL_INFO(dev)->gen >= 8) {
3e78998a
BW		 2782 if (i915_semaphore_is_enabled(dev)) {
2783 obj = i915_gem_alloc_object(dev, 4096);
2784 if (obj == NULL) {
2785 DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n");
2786 i915.semaphores = 0;
2787 } else {
2788 i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
2789 ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK);
2790 if (ret != 0) {
2791 drm_gem_object_unreference(&obj->base);
2792 DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n");
2793 i915.semaphores = 0;
2794 } else
2795 dev_priv->semaphore_obj = obj;
2796 }
2797 }
7225342a 2798
e2f80391
TU		 2799 engine->init_context = intel_rcs_ctx_init;
2800 engine->add_request = gen6_add_request;
2801 engine->flush = gen8_render_ring_flush;
2802 engine->irq_get = gen8_ring_get_irq;
2803 engine->irq_put = gen8_ring_put_irq;
2804 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b
CW		 2805 engine->irq_seqno_barrier = gen6_seqno_barrier;
2806 engine->get_seqno = ring_get_seqno;
e2f80391 2807 engine->set_seqno = ring_set_seqno;
707d9cf9 2808 if (i915_semaphore_is_enabled(dev)) {
3e78998a 2809 WARN_ON(!dev_priv->semaphore_obj);
e2f80391
TU		 2810 engine->semaphore.sync_to = gen8_ring_sync;
2811 engine->semaphore.signal = gen8_rcs_signal;
2812 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9
BW		 2813 }
2814 } else if (INTEL_INFO(dev)->gen >= 6) {
e2f80391
TU		 2815 engine->init_context = intel_rcs_ctx_init;
2816 engine->add_request = gen6_add_request;
2817 engine->flush = gen7_render_ring_flush;
6c6cf5aa 2818 if (INTEL_INFO(dev)->gen == 6)
e2f80391
TU		 2819 engine->flush = gen6_render_ring_flush;
2820 engine->irq_get = gen6_ring_get_irq;
2821 engine->irq_put = gen6_ring_put_irq;
2822 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
c04e0f3b
CW		 2823 engine->irq_seqno_barrier = gen6_seqno_barrier;
2824 engine->get_seqno = ring_get_seqno;
e2f80391 2825 engine->set_seqno = ring_set_seqno;
707d9cf9 2826 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 2827 engine->semaphore.sync_to = gen6_ring_sync;
2828 engine->semaphore.signal = gen6_signal;
707d9cf9
BW		 2829 /*
2830 * The current semaphore is only applied on pre-gen8
2831 * platform. And there is no VCS2 ring on the pre-gen8
2832 * platform. So the semaphore between RCS and VCS2 is
2833 * initialized as INVALID. Gen8 will initialize the
2834 * sema between VCS2 and RCS later.
2835 */
e2f80391
TU		 2836 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID;
2837 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV;
2838 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB;
2839 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE;
2840 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2841 engine->semaphore.mbox.signal[RCS] = GEN6_NOSYNC;
2842 engine->semaphore.mbox.signal[VCS] = GEN6_VRSYNC;
2843 engine->semaphore.mbox.signal[BCS] = GEN6_BRSYNC;
2844 engine->semaphore.mbox.signal[VECS] = GEN6_VERSYNC;
2845 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2846 }
c6df541c 2847 } else if (IS_GEN5(dev)) {
e2f80391
TU		 2848 engine->add_request = pc_render_add_request;
2849 engine->flush = gen4_render_ring_flush;
2850 engine->get_seqno = pc_render_get_seqno;
2851 engine->set_seqno = pc_render_set_seqno;
2852 engine->irq_get = gen5_ring_get_irq;
2853 engine->irq_put = gen5_ring_put_irq;
2854 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
cc609d5d 2855 GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
59465b5f 2856 } else {
e2f80391 2857 engine->add_request = i9xx_add_request;
46f0f8d1 2858 if (INTEL_INFO(dev)->gen < 4)
e2f80391 2859 engine->flush = gen2_render_ring_flush;
46f0f8d1 2860 else
e2f80391
TU		 2861 engine->flush = gen4_render_ring_flush;
2862 engine->get_seqno = ring_get_seqno;
2863 engine->set_seqno = ring_set_seqno;
c2798b19 2864 if (IS_GEN2(dev)) {
e2f80391
TU		 2865 engine->irq_get = i8xx_ring_get_irq;
2866 engine->irq_put = i8xx_ring_put_irq;
c2798b19 2867 } else {
e2f80391
TU		 2868 engine->irq_get = i9xx_ring_get_irq;
2869 engine->irq_put = i9xx_ring_put_irq;
c2798b19 2870 }
e2f80391 2871 engine->irq_enable_mask = I915_USER_INTERRUPT;
1ec14ad3 2872 }
e2f80391 2873 engine->write_tail = ring_write_tail;
707d9cf9 2874
d7d4eedd 2875 if (IS_HASWELL(dev))
e2f80391 2876 engine->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1c7a0623 2877 else if (IS_GEN8(dev))
e2f80391 2878 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
d7d4eedd 2879 else if (INTEL_INFO(dev)->gen >= 6)
e2f80391 2880 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
fb3256da 2881 else if (INTEL_INFO(dev)->gen >= 4)
e2f80391 2882 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
fb3256da 2883 else if (IS_I830(dev) || IS_845G(dev))
e2f80391 2884 engine->dispatch_execbuffer = i830_dispatch_execbuffer;
fb3256da 2885 else
e2f80391
TU		 2886 engine->dispatch_execbuffer = i915_dispatch_execbuffer;
2887 engine->init_hw = init_render_ring;
2888 engine->cleanup = render_ring_cleanup;
59465b5f 2889
b45305fc
DV		 2890 /* Workaround batchbuffer to combat CS tlb bug. */
2891 if (HAS_BROKEN_CS_TLB(dev)) {
c4d69da1 2892 obj = i915_gem_alloc_object(dev, I830_WA_SIZE);
b45305fc
DV		 2893 if (obj == NULL) {
2894 DRM_ERROR("Failed to allocate batch bo\n");
2895 return -ENOMEM;
2896 }
2897
be1fa129 2898 ret = i915_gem_obj_ggtt_pin(obj, 0, 0);
b45305fc
DV		 2899 if (ret != 0) {
2900 drm_gem_object_unreference(&obj->base);
2901 DRM_ERROR("Failed to ping batch bo\n");
2902 return ret;
2903 }
2904
e2f80391
TU		 2905 engine->scratch.obj = obj;
2906 engine->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj);
b45305fc
DV		 2907 }
2908
e2f80391 2909 ret = intel_init_ring_buffer(dev, engine);
99be1dfe
DV		 2910 if (ret)
2911 return ret;
2912
2913 if (INTEL_INFO(dev)->gen >= 5) {
e2f80391 2914 ret = intel_init_pipe_control(engine);
99be1dfe
DV		 2915 if (ret)
2916 return ret;
2917 }
2918
2919 return 0;
5c1143bb
XH		 2920}
2921
2922int intel_init_bsd_ring_buffer(struct drm_device *dev)
2923{
4640c4ff 2924 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 2925 struct intel_engine_cs *engine = &dev_priv->engine[VCS];
5c1143bb 2926
e2f80391
TU		 2927 engine->name = "bsd ring";
2928 engine->id = VCS;
2929 engine->exec_id = I915_EXEC_BSD;
83e53802 2930 engine->hw_id = 1;
58fa3835 2931
e2f80391 2932 engine->write_tail = ring_write_tail;
780f18c8 2933 if (INTEL_INFO(dev)->gen >= 6) {
e2f80391 2934 engine->mmio_base = GEN6_BSD_RING_BASE;
0fd2c201
DV		 2935 /* gen6 bsd needs a special wa for tail updates */
2936 if (IS_GEN6(dev))
e2f80391
TU		 2937 engine->write_tail = gen6_bsd_ring_write_tail;
2938 engine->flush = gen6_bsd_ring_flush;
2939 engine->add_request = gen6_add_request;
c04e0f3b
CW		 2940 engine->irq_seqno_barrier = gen6_seqno_barrier;
2941 engine->get_seqno = ring_get_seqno;
e2f80391 2942 engine->set_seqno = ring_set_seqno;
abd58f01 2943 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391 2944 engine->irq_enable_mask =
abd58f01 2945 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
e2f80391
TU		 2946 engine->irq_get = gen8_ring_get_irq;
2947 engine->irq_put = gen8_ring_put_irq;
2948 engine->dispatch_execbuffer =
1c7a0623 2949 gen8_ring_dispatch_execbuffer;
707d9cf9 2950 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 2951 engine->semaphore.sync_to = gen8_ring_sync;
2952 engine->semaphore.signal = gen8_xcs_signal;
2953 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 2954 }
abd58f01 2955 } else {
e2f80391
TU		 2956 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2957 engine->irq_get = gen6_ring_get_irq;
2958 engine->irq_put = gen6_ring_put_irq;
2959 engine->dispatch_execbuffer =
1c7a0623 2960 gen6_ring_dispatch_execbuffer;
707d9cf9 2961 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 2962 engine->semaphore.sync_to = gen6_ring_sync;
2963 engine->semaphore.signal = gen6_signal;
2964 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR;
2965 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID;
2966 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB;
2967 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE;
2968 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
2969 engine->semaphore.mbox.signal[RCS] = GEN6_RVSYNC;
2970 engine->semaphore.mbox.signal[VCS] = GEN6_NOSYNC;
2971 engine->semaphore.mbox.signal[BCS] = GEN6_BVSYNC;
2972 engine->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC;
2973 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 2974 }
abd58f01 2975 }
58fa3835 2976 } else {
e2f80391
TU		 2977 engine->mmio_base = BSD_RING_BASE;
2978 engine->flush = bsd_ring_flush;
2979 engine->add_request = i9xx_add_request;
2980 engine->get_seqno = ring_get_seqno;
2981 engine->set_seqno = ring_set_seqno;
e48d8634 2982 if (IS_GEN5(dev)) {
e2f80391
TU		 2983 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2984 engine->irq_get = gen5_ring_get_irq;
2985 engine->irq_put = gen5_ring_put_irq;
e48d8634 2986 } else {
e2f80391
TU		 2987 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2988 engine->irq_get = i9xx_ring_get_irq;
2989 engine->irq_put = i9xx_ring_put_irq;
e48d8634 2990 }
e2f80391 2991 engine->dispatch_execbuffer = i965_dispatch_execbuffer;
58fa3835 2992 }
e2f80391 2993 engine->init_hw = init_ring_common;
58fa3835 2994
e2f80391 2995 return intel_init_ring_buffer(dev, engine);
5c1143bb 2996}
549f7365 2997
845f74a7 2998/**
62659920 2999 * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3)
845f74a7
ZY		 3000 */
3001int intel_init_bsd2_ring_buffer(struct drm_device *dev)
3002{
3003 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3004 struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
e2f80391
TU		 3005
3006 engine->name = "bsd2 ring";
3007 engine->id = VCS2;
3008 engine->exec_id = I915_EXEC_BSD;
83e53802 3009 engine->hw_id = 4;
e2f80391
TU		 3010
3011 engine->write_tail = ring_write_tail;
3012 engine->mmio_base = GEN8_BSD2_RING_BASE;
3013 engine->flush = gen6_bsd_ring_flush;
3014 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3015 engine->irq_seqno_barrier = gen6_seqno_barrier;
3016 engine->get_seqno = ring_get_seqno;
e2f80391
TU		 3017 engine->set_seqno = ring_set_seqno;
3018 engine->irq_enable_mask =
845f74a7 3019 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT;
e2f80391
TU		 3020 engine->irq_get = gen8_ring_get_irq;
3021 engine->irq_put = gen8_ring_put_irq;
3022 engine->dispatch_execbuffer =
845f74a7 3023 gen8_ring_dispatch_execbuffer;
3e78998a 3024 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3025 engine->semaphore.sync_to = gen8_ring_sync;
3026 engine->semaphore.signal = gen8_xcs_signal;
3027 GEN8_RING_SEMAPHORE_INIT(engine);
3e78998a 3028 }
e2f80391 3029 engine->init_hw = init_ring_common;
845f74a7 3030
e2f80391 3031 return intel_init_ring_buffer(dev, engine);
845f74a7
ZY		 3032}
3033
549f7365
CW		 3034int intel_init_blt_ring_buffer(struct drm_device *dev)
3035{
4640c4ff 3036 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3037 struct intel_engine_cs *engine = &dev_priv->engine[BCS];
e2f80391
TU		 3038
3039 engine->name = "blitter ring";
3040 engine->id = BCS;
3041 engine->exec_id = I915_EXEC_BLT;
83e53802 3042 engine->hw_id = 2;
e2f80391
TU		 3043
3044 engine->mmio_base = BLT_RING_BASE;
3045 engine->write_tail = ring_write_tail;
3046 engine->flush = gen6_ring_flush;
3047 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3048 engine->irq_seqno_barrier = gen6_seqno_barrier;
3049 engine->get_seqno = ring_get_seqno;
e2f80391 3050 engine->set_seqno = ring_set_seqno;
abd58f01 3051 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391 3052 engine->irq_enable_mask =
abd58f01 3053 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
e2f80391
TU		 3054 engine->irq_get = gen8_ring_get_irq;
3055 engine->irq_put = gen8_ring_put_irq;
3056 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 3057 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3058 engine->semaphore.sync_to = gen8_ring_sync;
3059 engine->semaphore.signal = gen8_xcs_signal;
3060 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3061 }
abd58f01 3062 } else {
e2f80391
TU		 3063 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
3064 engine->irq_get = gen6_ring_get_irq;
3065 engine->irq_put = gen6_ring_put_irq;
3066 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9 3067 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3068 engine->semaphore.signal = gen6_signal;
3069 engine->semaphore.sync_to = gen6_ring_sync;
707d9cf9
BW		 3070 /*
3071 * The current semaphore is only applied on pre-gen8
3072 * platform. And there is no VCS2 ring on the pre-gen8
3073 * platform. So the semaphore between BCS and VCS2 is
3074 * initialized as INVALID. Gen8 will initialize the
3075 * sema between BCS and VCS2 later.
3076 */
e2f80391
TU		 3077 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR;
3078 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV;
3079 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID;
3080 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE;
3081 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3082 engine->semaphore.mbox.signal[RCS] = GEN6_RBSYNC;
3083 engine->semaphore.mbox.signal[VCS] = GEN6_VBSYNC;
3084 engine->semaphore.mbox.signal[BCS] = GEN6_NOSYNC;
3085 engine->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC;
3086 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3087 }
abd58f01 3088 }
e2f80391 3089 engine->init_hw = init_ring_common;
549f7365 3090
e2f80391 3091 return intel_init_ring_buffer(dev, engine);
549f7365 3092}
a7b9761d 3093
9a8a2213
BW		 3094int intel_init_vebox_ring_buffer(struct drm_device *dev)
3095{
4640c4ff 3096 struct drm_i915_private *dev_priv = dev->dev_private;
4a570db5 3097 struct intel_engine_cs *engine = &dev_priv->engine[VECS];
9a8a2213 3098
e2f80391
TU		 3099 engine->name = "video enhancement ring";
3100 engine->id = VECS;
3101 engine->exec_id = I915_EXEC_VEBOX;
83e53802 3102 engine->hw_id = 3;
9a8a2213 3103
e2f80391
TU		 3104 engine->mmio_base = VEBOX_RING_BASE;
3105 engine->write_tail = ring_write_tail;
3106 engine->flush = gen6_ring_flush;
3107 engine->add_request = gen6_add_request;
c04e0f3b
CW		 3108 engine->irq_seqno_barrier = gen6_seqno_barrier;
3109 engine->get_seqno = ring_get_seqno;
e2f80391 3110 engine->set_seqno = ring_set_seqno;
abd58f01
BW		 3111
3112 if (INTEL_INFO(dev)->gen >= 8) {
e2f80391 3113 engine->irq_enable_mask =
40c499f9 3114 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT;
e2f80391
TU		 3115 engine->irq_get = gen8_ring_get_irq;
3116 engine->irq_put = gen8_ring_put_irq;
3117 engine->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
707d9cf9 3118 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3119 engine->semaphore.sync_to = gen8_ring_sync;
3120 engine->semaphore.signal = gen8_xcs_signal;
3121 GEN8_RING_SEMAPHORE_INIT(engine);
707d9cf9 3122 }
abd58f01 3123 } else {
e2f80391
TU		 3124 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
3125 engine->irq_get = hsw_vebox_get_irq;
3126 engine->irq_put = hsw_vebox_put_irq;
3127 engine->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
707d9cf9 3128 if (i915_semaphore_is_enabled(dev)) {
e2f80391
TU		 3129 engine->semaphore.sync_to = gen6_ring_sync;
3130 engine->semaphore.signal = gen6_signal;
3131 engine->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER;
3132 engine->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV;
3133 engine->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB;
3134 engine->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID;
3135 engine->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID;
3136 engine->semaphore.mbox.signal[RCS] = GEN6_RVESYNC;
3137 engine->semaphore.mbox.signal[VCS] = GEN6_VVESYNC;
3138 engine->semaphore.mbox.signal[BCS] = GEN6_BVESYNC;
3139 engine->semaphore.mbox.signal[VECS] = GEN6_NOSYNC;
3140 engine->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC;
707d9cf9 3141 }
abd58f01 3142 }
e2f80391 3143 engine->init_hw = init_ring_common;
9a8a2213 3144
e2f80391 3145 return intel_init_ring_buffer(dev, engine);
9a8a2213
BW		 3146}
3147
a7b9761d 3148int
4866d729 3149intel_ring_flush_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3150{
4a570db5 3151 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3152 int ret;
3153
e2f80391 3154 if (!engine->gpu_caches_dirty)
a7b9761d
CW		 3155 return 0;
3156
e2f80391 3157 ret = engine->flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d
CW		 3158 if (ret)
3159 return ret;
3160
a84c3ae1 3161 trace_i915_gem_ring_flush(req, 0, I915_GEM_GPU_DOMAINS);
a7b9761d 3162
e2f80391 3163 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3164 return 0;
3165}
3166
3167int
2f20055d 3168intel_ring_invalidate_all_caches(struct drm_i915_gem_request *req)
a7b9761d 3169{
4a570db5 3170 struct intel_engine_cs *engine = req->engine;
a7b9761d
CW		 3171 uint32_t flush_domains;
3172 int ret;
3173
3174 flush_domains = 0;
e2f80391 3175 if (engine->gpu_caches_dirty)
a7b9761d
CW		 3176 flush_domains = I915_GEM_GPU_DOMAINS;
3177
e2f80391 3178 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d
CW		 3179 if (ret)
3180 return ret;
3181
a84c3ae1 3182 trace_i915_gem_ring_flush(req, I915_GEM_GPU_DOMAINS, flush_domains);
a7b9761d 3183
e2f80391 3184 engine->gpu_caches_dirty = false;
a7b9761d
CW		 3185 return 0;
3186}
e3efda49
CW		 3187
3188void
117897f4 3189intel_stop_engine(struct intel_engine_cs *engine)
e3efda49
CW		 3190{
3191 int ret;
3192
117897f4 3193 if (!intel_engine_initialized(engine))
e3efda49
CW		 3194 return;
3195
666796da 3196 ret = intel_engine_idle(engine);
f4457ae7 3197 if (ret)
e3efda49 3198 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
0bc40be8 3199 engine->name, ret);
e3efda49 3200
0bc40be8 3201 stop_ring(engine);
e3efda49 3202}
Linux kernel - Deliverables
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