Commit | Line | Data |
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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
6f392d54 CW |
37 | static u32 i915_gem_get_seqno(struct drm_device *dev) |
38 | { | |
39 | drm_i915_private_t *dev_priv = dev->dev_private; | |
40 | u32 seqno; | |
41 | ||
42 | seqno = dev_priv->next_seqno; | |
43 | ||
44 | /* reserve 0 for non-seqno */ | |
45 | if (++dev_priv->next_seqno == 0) | |
46 | dev_priv->next_seqno = 1; | |
47 | ||
48 | return seqno; | |
49 | } | |
50 | ||
8187a2b7 | 51 | static void |
78501eac | 52 | render_ring_flush(struct intel_ring_buffer *ring, |
ab6f8e32 CW |
53 | u32 invalidate_domains, |
54 | u32 flush_domains) | |
62fdfeaf | 55 | { |
78501eac | 56 | struct drm_device *dev = ring->dev; |
6f392d54 CW |
57 | drm_i915_private_t *dev_priv = dev->dev_private; |
58 | u32 cmd; | |
59 | ||
62fdfeaf EA |
60 | #if WATCH_EXEC |
61 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
62 | invalidate_domains, flush_domains); | |
63 | #endif | |
6f392d54 CW |
64 | |
65 | trace_i915_gem_request_flush(dev, dev_priv->next_seqno, | |
62fdfeaf EA |
66 | invalidate_domains, flush_domains); |
67 | ||
62fdfeaf EA |
68 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
69 | /* | |
70 | * read/write caches: | |
71 | * | |
72 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
73 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
74 | * also flushed at 2d versus 3d pipeline switches. | |
75 | * | |
76 | * read-only caches: | |
77 | * | |
78 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
79 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
80 | * | |
81 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
82 | * | |
83 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
84 | * invalidated when MI_EXE_FLUSH is set. | |
85 | * | |
86 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
87 | * invalidated with every MI_FLUSH. | |
88 | * | |
89 | * TLBs: | |
90 | * | |
91 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
92 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
93 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
94 | * are flushed at any MI_FLUSH. | |
95 | */ | |
96 | ||
97 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
98 | if ((invalidate_domains|flush_domains) & | |
99 | I915_GEM_DOMAIN_RENDER) | |
100 | cmd &= ~MI_NO_WRITE_FLUSH; | |
a6c45cf0 | 101 | if (INTEL_INFO(dev)->gen < 4) { |
62fdfeaf EA |
102 | /* |
103 | * On the 965, the sampler cache always gets flushed | |
104 | * and this bit is reserved. | |
105 | */ | |
106 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
107 | cmd |= MI_READ_FLUSH; | |
108 | } | |
109 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
110 | cmd |= MI_EXE_FLUSH; | |
111 | ||
112 | #if WATCH_EXEC | |
113 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
114 | #endif | |
e1f99ce6 CW |
115 | if (intel_ring_begin(ring, 2) == 0) { |
116 | intel_ring_emit(ring, cmd); | |
117 | intel_ring_emit(ring, MI_NOOP); | |
118 | intel_ring_advance(ring); | |
119 | } | |
62fdfeaf | 120 | } |
8187a2b7 ZN |
121 | } |
122 | ||
78501eac | 123 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 124 | u32 value) |
d46eefa2 | 125 | { |
78501eac | 126 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 127 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
128 | } |
129 | ||
78501eac | 130 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 131 | { |
78501eac CW |
132 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
133 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 134 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
135 | |
136 | return I915_READ(acthd_reg); | |
137 | } | |
138 | ||
78501eac | 139 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 140 | { |
78501eac CW |
141 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
142 | struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object); | |
8187a2b7 | 143 | u32 head; |
8187a2b7 ZN |
144 | |
145 | /* Stop the ring if it's running. */ | |
7f2ab699 | 146 | I915_WRITE_CTL(ring, 0); |
570ef608 | 147 | I915_WRITE_HEAD(ring, 0); |
78501eac | 148 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
149 | |
150 | /* Initialize the ring. */ | |
6c0e1c55 | 151 | I915_WRITE_START(ring, obj_priv->gtt_offset); |
570ef608 | 152 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
153 | |
154 | /* G45 ring initialization fails to reset head to zero */ | |
155 | if (head != 0) { | |
156 | DRM_ERROR("%s head not reset to zero " | |
157 | "ctl %08x head %08x tail %08x start %08x\n", | |
158 | ring->name, | |
7f2ab699 | 159 | I915_READ_CTL(ring), |
570ef608 | 160 | I915_READ_HEAD(ring), |
870e86dd | 161 | I915_READ_TAIL(ring), |
6c0e1c55 | 162 | I915_READ_START(ring)); |
8187a2b7 | 163 | |
570ef608 | 164 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 ZN |
165 | |
166 | DRM_ERROR("%s head forced to zero " | |
167 | "ctl %08x head %08x tail %08x start %08x\n", | |
168 | ring->name, | |
7f2ab699 | 169 | I915_READ_CTL(ring), |
570ef608 | 170 | I915_READ_HEAD(ring), |
870e86dd | 171 | I915_READ_TAIL(ring), |
6c0e1c55 | 172 | I915_READ_START(ring)); |
8187a2b7 ZN |
173 | } |
174 | ||
7f2ab699 | 175 | I915_WRITE_CTL(ring, |
8187a2b7 | 176 | ((ring->gem_object->size - PAGE_SIZE) & RING_NR_PAGES) |
6aa56062 | 177 | | RING_REPORT_64K | RING_VALID); |
8187a2b7 | 178 | |
8187a2b7 | 179 | /* If the head is still not zero, the ring is dead */ |
176f28eb CW |
180 | if ((I915_READ_CTL(ring) & RING_VALID) == 0 || |
181 | I915_READ_START(ring) != obj_priv->gtt_offset || | |
182 | (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) { | |
8187a2b7 ZN |
183 | DRM_ERROR("%s initialization failed " |
184 | "ctl %08x head %08x tail %08x start %08x\n", | |
185 | ring->name, | |
7f2ab699 | 186 | I915_READ_CTL(ring), |
570ef608 | 187 | I915_READ_HEAD(ring), |
870e86dd | 188 | I915_READ_TAIL(ring), |
6c0e1c55 | 189 | I915_READ_START(ring)); |
8187a2b7 ZN |
190 | return -EIO; |
191 | } | |
192 | ||
78501eac CW |
193 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
194 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 195 | else { |
570ef608 | 196 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
870e86dd | 197 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
8187a2b7 ZN |
198 | ring->space = ring->head - (ring->tail + 8); |
199 | if (ring->space < 0) | |
200 | ring->space += ring->size; | |
201 | } | |
202 | return 0; | |
203 | } | |
204 | ||
78501eac | 205 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 206 | { |
78501eac CW |
207 | struct drm_device *dev = ring->dev; |
208 | int ret = init_ring_common(ring); | |
a69ffdbf | 209 | |
a6c45cf0 | 210 | if (INTEL_INFO(dev)->gen > 3) { |
78501eac CW |
211 | drm_i915_private_t *dev_priv = dev->dev_private; |
212 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; | |
a69ffdbf ZW |
213 | if (IS_GEN6(dev)) |
214 | mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE; | |
215 | I915_WRITE(MI_MODE, mode); | |
8187a2b7 | 216 | } |
78501eac | 217 | |
8187a2b7 ZN |
218 | return ret; |
219 | } | |
220 | ||
78501eac | 221 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
8187a2b7 | 222 | do { \ |
78501eac | 223 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ |
ca76482e | 224 | PIPE_CONTROL_DEPTH_STALL | 2); \ |
78501eac CW |
225 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
226 | intel_ring_emit(ring__, 0); \ | |
227 | intel_ring_emit(ring__, 0); \ | |
8187a2b7 | 228 | } while (0) |
62fdfeaf EA |
229 | |
230 | /** | |
231 | * Creates a new sequence number, emitting a write of it to the status page | |
232 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
233 | * | |
234 | * Must be called with struct_lock held. | |
235 | * | |
236 | * Returned sequence numbers are nonzero on success. | |
237 | */ | |
3cce469c | 238 | static int |
78501eac | 239 | render_ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 240 | u32 *result) |
62fdfeaf | 241 | { |
78501eac | 242 | struct drm_device *dev = ring->dev; |
62fdfeaf | 243 | drm_i915_private_t *dev_priv = dev->dev_private; |
3cce469c CW |
244 | u32 seqno = i915_gem_get_seqno(dev); |
245 | int ret; | |
ca76482e ZW |
246 | |
247 | if (IS_GEN6(dev)) { | |
3cce469c CW |
248 | ret = intel_ring_begin(ring, 6); |
249 | if (ret) | |
250 | return ret; | |
251 | ||
252 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3); | |
253 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE | | |
254 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH | | |
255 | PIPE_CONTROL_NOTIFY); | |
256 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
257 | intel_ring_emit(ring, seqno); | |
258 | intel_ring_emit(ring, 0); | |
259 | intel_ring_emit(ring, 0); | |
ca76482e | 260 | } else if (HAS_PIPE_CONTROL(dev)) { |
62fdfeaf EA |
261 | u32 scratch_addr = dev_priv->seqno_gfx_addr + 128; |
262 | ||
263 | /* | |
264 | * Workaround qword write incoherence by flushing the | |
265 | * PIPE_NOTIFY buffers out to memory before requesting | |
266 | * an interrupt. | |
267 | */ | |
3cce469c CW |
268 | ret = intel_ring_begin(ring, 32); |
269 | if (ret) | |
270 | return ret; | |
271 | ||
272 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
273 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | |
274 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
275 | intel_ring_emit(ring, seqno); | |
276 | intel_ring_emit(ring, 0); | |
277 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
278 | scratch_addr += 128; /* write to separate cachelines */ | |
279 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
280 | scratch_addr += 128; | |
281 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
282 | scratch_addr += 128; | |
283 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
284 | scratch_addr += 128; | |
285 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
286 | scratch_addr += 128; | |
287 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
288 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | |
289 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | |
290 | PIPE_CONTROL_NOTIFY); | |
291 | intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT); | |
292 | intel_ring_emit(ring, seqno); | |
293 | intel_ring_emit(ring, 0); | |
62fdfeaf | 294 | } else { |
3cce469c CW |
295 | ret = intel_ring_begin(ring, 4); |
296 | if (ret) | |
297 | return ret; | |
62fdfeaf | 298 | |
3cce469c CW |
299 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
300 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
301 | intel_ring_emit(ring, seqno); | |
302 | ||
303 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
62fdfeaf | 304 | } |
3cce469c CW |
305 | |
306 | intel_ring_advance(ring); | |
307 | *result = seqno; | |
308 | return 0; | |
62fdfeaf EA |
309 | } |
310 | ||
8187a2b7 | 311 | static u32 |
78501eac | 312 | render_ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 313 | { |
78501eac | 314 | struct drm_device *dev = ring->dev; |
8187a2b7 ZN |
315 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
316 | if (HAS_PIPE_CONTROL(dev)) | |
317 | return ((volatile u32 *)(dev_priv->seqno_page))[0]; | |
318 | else | |
319 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
320 | } | |
321 | ||
322 | static void | |
78501eac | 323 | render_ring_get_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 324 | { |
78501eac | 325 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
326 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
327 | unsigned long irqflags; | |
328 | ||
329 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 | 330 | if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) { |
62fdfeaf EA |
331 | if (HAS_PCH_SPLIT(dev)) |
332 | ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
333 | else | |
334 | i915_enable_irq(dev_priv, I915_USER_INTERRUPT); | |
335 | } | |
336 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
337 | } | |
338 | ||
8187a2b7 | 339 | static void |
78501eac | 340 | render_ring_put_user_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 341 | { |
78501eac | 342 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
343 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
344 | unsigned long irqflags; | |
345 | ||
346 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
8187a2b7 ZN |
347 | BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0); |
348 | if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) { | |
62fdfeaf EA |
349 | if (HAS_PCH_SPLIT(dev)) |
350 | ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY); | |
351 | else | |
352 | i915_disable_irq(dev_priv, I915_USER_INTERRUPT); | |
353 | } | |
354 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); | |
355 | } | |
356 | ||
78501eac | 357 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 358 | { |
78501eac CW |
359 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
360 | u32 mmio = IS_GEN6(ring->dev) ? | |
361 | RING_HWS_PGA_GEN6(ring->mmio_base) : | |
362 | RING_HWS_PGA(ring->mmio_base); | |
363 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
364 | POSTING_READ(mmio); | |
8187a2b7 ZN |
365 | } |
366 | ||
ab6f8e32 | 367 | static void |
78501eac CW |
368 | bsd_ring_flush(struct intel_ring_buffer *ring, |
369 | u32 invalidate_domains, | |
370 | u32 flush_domains) | |
d1b851fc | 371 | { |
e1f99ce6 CW |
372 | if (intel_ring_begin(ring, 2) == 0) { |
373 | intel_ring_emit(ring, MI_FLUSH); | |
374 | intel_ring_emit(ring, MI_NOOP); | |
375 | intel_ring_advance(ring); | |
376 | } | |
d1b851fc ZN |
377 | } |
378 | ||
3cce469c | 379 | static int |
78501eac | 380 | ring_add_request(struct intel_ring_buffer *ring, |
3cce469c | 381 | u32 *result) |
d1b851fc ZN |
382 | { |
383 | u32 seqno; | |
3cce469c CW |
384 | int ret; |
385 | ||
386 | ret = intel_ring_begin(ring, 4); | |
387 | if (ret) | |
388 | return ret; | |
6f392d54 | 389 | |
78501eac | 390 | seqno = i915_gem_get_seqno(ring->dev); |
6f392d54 | 391 | |
3cce469c CW |
392 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
393 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
394 | intel_ring_emit(ring, seqno); | |
395 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
396 | intel_ring_advance(ring); | |
d1b851fc ZN |
397 | |
398 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
3cce469c CW |
399 | *result = seqno; |
400 | return 0; | |
d1b851fc ZN |
401 | } |
402 | ||
d1b851fc | 403 | static void |
78501eac | 404 | bsd_ring_get_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
405 | { |
406 | /* do nothing */ | |
407 | } | |
408 | static void | |
78501eac | 409 | bsd_ring_put_user_irq(struct intel_ring_buffer *ring) |
d1b851fc ZN |
410 | { |
411 | /* do nothing */ | |
412 | } | |
413 | ||
414 | static u32 | |
78501eac | 415 | ring_status_page_get_seqno(struct intel_ring_buffer *ring) |
d1b851fc ZN |
416 | { |
417 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
418 | } | |
419 | ||
420 | static int | |
78501eac CW |
421 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
422 | struct drm_i915_gem_execbuffer2 *exec, | |
423 | struct drm_clip_rect *cliprects, | |
424 | uint64_t exec_offset) | |
d1b851fc ZN |
425 | { |
426 | uint32_t exec_start; | |
e1f99ce6 | 427 | int ret; |
78501eac | 428 | |
d1b851fc | 429 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
78501eac | 430 | |
e1f99ce6 CW |
431 | ret = intel_ring_begin(ring, 2); |
432 | if (ret) | |
433 | return ret; | |
434 | ||
78501eac CW |
435 | intel_ring_emit(ring, |
436 | MI_BATCH_BUFFER_START | | |
437 | (2 << 6) | | |
438 | MI_BATCH_NON_SECURE_I965); | |
439 | intel_ring_emit(ring, exec_start); | |
440 | intel_ring_advance(ring); | |
441 | ||
d1b851fc ZN |
442 | return 0; |
443 | } | |
444 | ||
8187a2b7 | 445 | static int |
78501eac CW |
446 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
447 | struct drm_i915_gem_execbuffer2 *exec, | |
448 | struct drm_clip_rect *cliprects, | |
449 | uint64_t exec_offset) | |
62fdfeaf | 450 | { |
78501eac | 451 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
452 | drm_i915_private_t *dev_priv = dev->dev_private; |
453 | int nbox = exec->num_cliprects; | |
62fdfeaf | 454 | uint32_t exec_start, exec_len; |
e1f99ce6 | 455 | int i, count, ret; |
78501eac | 456 | |
62fdfeaf EA |
457 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
458 | exec_len = (uint32_t) exec->batch_len; | |
459 | ||
6f392d54 | 460 | trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1); |
62fdfeaf EA |
461 | |
462 | count = nbox ? nbox : 1; | |
62fdfeaf EA |
463 | for (i = 0; i < count; i++) { |
464 | if (i < nbox) { | |
e1f99ce6 CW |
465 | ret = i915_emit_box(dev, cliprects, i, |
466 | exec->DR1, exec->DR4); | |
62fdfeaf EA |
467 | if (ret) |
468 | return ret; | |
469 | } | |
470 | ||
471 | if (IS_I830(dev) || IS_845G(dev)) { | |
e1f99ce6 CW |
472 | ret = intel_ring_begin(ring, 4); |
473 | if (ret) | |
474 | return ret; | |
475 | ||
78501eac CW |
476 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
477 | intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE); | |
478 | intel_ring_emit(ring, exec_start + exec_len - 4); | |
479 | intel_ring_emit(ring, 0); | |
62fdfeaf | 480 | } else { |
e1f99ce6 CW |
481 | ret = intel_ring_begin(ring, 2); |
482 | if (ret) | |
483 | return ret; | |
484 | ||
a6c45cf0 | 485 | if (INTEL_INFO(dev)->gen >= 4) { |
78501eac | 486 | intel_ring_emit(ring, |
8187a2b7 ZN |
487 | MI_BATCH_BUFFER_START | (2 << 6) |
488 | | MI_BATCH_NON_SECURE_I965); | |
78501eac | 489 | intel_ring_emit(ring, exec_start); |
62fdfeaf | 490 | } else { |
78501eac | 491 | intel_ring_emit(ring, MI_BATCH_BUFFER_START |
8187a2b7 | 492 | | (2 << 6)); |
78501eac | 493 | intel_ring_emit(ring, exec_start | |
8187a2b7 | 494 | MI_BATCH_NON_SECURE); |
62fdfeaf | 495 | } |
62fdfeaf | 496 | } |
78501eac | 497 | intel_ring_advance(ring); |
62fdfeaf EA |
498 | } |
499 | ||
f00a3ddf | 500 | if (IS_G4X(dev) || IS_GEN5(dev)) { |
e1f99ce6 CW |
501 | if (intel_ring_begin(ring, 2) == 0) { |
502 | intel_ring_emit(ring, MI_FLUSH | | |
503 | MI_NO_WRITE_FLUSH | | |
504 | MI_INVALIDATE_ISP ); | |
505 | intel_ring_emit(ring, MI_NOOP); | |
506 | intel_ring_advance(ring); | |
507 | } | |
1cafd347 | 508 | } |
62fdfeaf | 509 | /* XXX breadcrumb */ |
1cafd347 | 510 | |
62fdfeaf EA |
511 | return 0; |
512 | } | |
513 | ||
78501eac | 514 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 515 | { |
78501eac | 516 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
62fdfeaf EA |
517 | struct drm_gem_object *obj; |
518 | struct drm_i915_gem_object *obj_priv; | |
519 | ||
8187a2b7 ZN |
520 | obj = ring->status_page.obj; |
521 | if (obj == NULL) | |
62fdfeaf | 522 | return; |
62fdfeaf EA |
523 | obj_priv = to_intel_bo(obj); |
524 | ||
525 | kunmap(obj_priv->pages[0]); | |
526 | i915_gem_object_unpin(obj); | |
527 | drm_gem_object_unreference(obj); | |
8187a2b7 | 528 | ring->status_page.obj = NULL; |
62fdfeaf EA |
529 | |
530 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
62fdfeaf EA |
531 | } |
532 | ||
78501eac | 533 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 534 | { |
78501eac | 535 | struct drm_device *dev = ring->dev; |
62fdfeaf EA |
536 | drm_i915_private_t *dev_priv = dev->dev_private; |
537 | struct drm_gem_object *obj; | |
538 | struct drm_i915_gem_object *obj_priv; | |
539 | int ret; | |
540 | ||
62fdfeaf EA |
541 | obj = i915_gem_alloc_object(dev, 4096); |
542 | if (obj == NULL) { | |
543 | DRM_ERROR("Failed to allocate status page\n"); | |
544 | ret = -ENOMEM; | |
545 | goto err; | |
546 | } | |
547 | obj_priv = to_intel_bo(obj); | |
548 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
549 | ||
a00b10c3 | 550 | ret = i915_gem_object_pin(obj, 4096, true, false); |
62fdfeaf | 551 | if (ret != 0) { |
62fdfeaf EA |
552 | goto err_unref; |
553 | } | |
554 | ||
8187a2b7 ZN |
555 | ring->status_page.gfx_addr = obj_priv->gtt_offset; |
556 | ring->status_page.page_addr = kmap(obj_priv->pages[0]); | |
557 | if (ring->status_page.page_addr == NULL) { | |
62fdfeaf | 558 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
62fdfeaf EA |
559 | goto err_unpin; |
560 | } | |
8187a2b7 ZN |
561 | ring->status_page.obj = obj; |
562 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 563 | |
78501eac | 564 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
565 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
566 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
567 | |
568 | return 0; | |
569 | ||
570 | err_unpin: | |
571 | i915_gem_object_unpin(obj); | |
572 | err_unref: | |
573 | drm_gem_object_unreference(obj); | |
574 | err: | |
8187a2b7 | 575 | return ret; |
62fdfeaf EA |
576 | } |
577 | ||
8187a2b7 | 578 | int intel_init_ring_buffer(struct drm_device *dev, |
ab6f8e32 | 579 | struct intel_ring_buffer *ring) |
62fdfeaf | 580 | { |
8187a2b7 ZN |
581 | struct drm_i915_gem_object *obj_priv; |
582 | struct drm_gem_object *obj; | |
dd785e35 CW |
583 | int ret; |
584 | ||
8187a2b7 | 585 | ring->dev = dev; |
23bc5982 CW |
586 | INIT_LIST_HEAD(&ring->active_list); |
587 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 588 | INIT_LIST_HEAD(&ring->gpu_write_list); |
62fdfeaf | 589 | |
8187a2b7 | 590 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 591 | ret = init_status_page(ring); |
8187a2b7 ZN |
592 | if (ret) |
593 | return ret; | |
594 | } | |
62fdfeaf | 595 | |
8187a2b7 | 596 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
597 | if (obj == NULL) { |
598 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 599 | ret = -ENOMEM; |
dd785e35 | 600 | goto err_hws; |
62fdfeaf | 601 | } |
62fdfeaf | 602 | |
8187a2b7 ZN |
603 | ring->gem_object = obj; |
604 | ||
a00b10c3 | 605 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false); |
dd785e35 CW |
606 | if (ret) |
607 | goto err_unref; | |
62fdfeaf | 608 | |
8187a2b7 ZN |
609 | obj_priv = to_intel_bo(obj); |
610 | ring->map.size = ring->size; | |
62fdfeaf | 611 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
62fdfeaf EA |
612 | ring->map.type = 0; |
613 | ring->map.flags = 0; | |
614 | ring->map.mtrr = 0; | |
615 | ||
616 | drm_core_ioremap_wc(&ring->map, dev); | |
617 | if (ring->map.handle == NULL) { | |
618 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
8187a2b7 | 619 | ret = -EINVAL; |
dd785e35 | 620 | goto err_unpin; |
62fdfeaf EA |
621 | } |
622 | ||
8187a2b7 | 623 | ring->virtual_start = ring->map.handle; |
78501eac | 624 | ret = ring->init(ring); |
dd785e35 CW |
625 | if (ret) |
626 | goto err_unmap; | |
62fdfeaf | 627 | |
c584fe47 | 628 | return 0; |
dd785e35 CW |
629 | |
630 | err_unmap: | |
631 | drm_core_ioremapfree(&ring->map, dev); | |
632 | err_unpin: | |
633 | i915_gem_object_unpin(obj); | |
634 | err_unref: | |
635 | drm_gem_object_unreference(obj); | |
636 | ring->gem_object = NULL; | |
637 | err_hws: | |
78501eac | 638 | cleanup_status_page(ring); |
8187a2b7 | 639 | return ret; |
62fdfeaf EA |
640 | } |
641 | ||
78501eac | 642 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 643 | { |
33626e6a CW |
644 | struct drm_i915_private *dev_priv; |
645 | int ret; | |
646 | ||
8187a2b7 | 647 | if (ring->gem_object == NULL) |
62fdfeaf EA |
648 | return; |
649 | ||
33626e6a CW |
650 | /* Disable the ring buffer. The ring must be idle at this point */ |
651 | dev_priv = ring->dev->dev_private; | |
652 | ret = intel_wait_ring_buffer(ring, ring->size - 8); | |
653 | I915_WRITE_CTL(ring, 0); | |
654 | ||
78501eac | 655 | drm_core_ioremapfree(&ring->map, ring->dev); |
62fdfeaf | 656 | |
8187a2b7 ZN |
657 | i915_gem_object_unpin(ring->gem_object); |
658 | drm_gem_object_unreference(ring->gem_object); | |
659 | ring->gem_object = NULL; | |
78501eac | 660 | |
8d19215b ZN |
661 | if (ring->cleanup) |
662 | ring->cleanup(ring); | |
663 | ||
78501eac | 664 | cleanup_status_page(ring); |
62fdfeaf EA |
665 | } |
666 | ||
78501eac | 667 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 668 | { |
8187a2b7 | 669 | unsigned int *virt; |
62fdfeaf | 670 | int rem; |
8187a2b7 | 671 | rem = ring->size - ring->tail; |
62fdfeaf | 672 | |
8187a2b7 | 673 | if (ring->space < rem) { |
78501eac | 674 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
675 | if (ret) |
676 | return ret; | |
677 | } | |
62fdfeaf | 678 | |
8187a2b7 | 679 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
1741dd4a CW |
680 | rem /= 8; |
681 | while (rem--) { | |
62fdfeaf | 682 | *virt++ = MI_NOOP; |
1741dd4a CW |
683 | *virt++ = MI_NOOP; |
684 | } | |
62fdfeaf | 685 | |
8187a2b7 | 686 | ring->tail = 0; |
43ed340a | 687 | ring->space = ring->head - 8; |
62fdfeaf EA |
688 | |
689 | return 0; | |
690 | } | |
691 | ||
78501eac | 692 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 693 | { |
78501eac | 694 | struct drm_device *dev = ring->dev; |
570ef608 | 695 | drm_i915_private_t *dev_priv = dev->dev_private; |
78501eac | 696 | unsigned long end; |
6aa56062 CW |
697 | u32 head; |
698 | ||
699 | head = intel_read_status_page(ring, 4); | |
700 | if (head) { | |
701 | ring->head = head & HEAD_ADDR; | |
702 | ring->space = ring->head - (ring->tail + 8); | |
703 | if (ring->space < 0) | |
704 | ring->space += ring->size; | |
705 | if (ring->space >= n) | |
706 | return 0; | |
707 | } | |
62fdfeaf EA |
708 | |
709 | trace_i915_ring_wait_begin (dev); | |
8187a2b7 ZN |
710 | end = jiffies + 3 * HZ; |
711 | do { | |
570ef608 | 712 | ring->head = I915_READ_HEAD(ring) & HEAD_ADDR; |
62fdfeaf EA |
713 | ring->space = ring->head - (ring->tail + 8); |
714 | if (ring->space < 0) | |
8187a2b7 | 715 | ring->space += ring->size; |
62fdfeaf | 716 | if (ring->space >= n) { |
78501eac | 717 | trace_i915_ring_wait_end(dev); |
62fdfeaf EA |
718 | return 0; |
719 | } | |
720 | ||
721 | if (dev->primary->master) { | |
722 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
723 | if (master_priv->sarea_priv) | |
724 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
725 | } | |
d1b851fc | 726 | |
e60a0b10 | 727 | msleep(1); |
f4e0b29b CW |
728 | if (atomic_read(&dev_priv->mm.wedged)) |
729 | return -EAGAIN; | |
8187a2b7 ZN |
730 | } while (!time_after(jiffies, end)); |
731 | trace_i915_ring_wait_end (dev); | |
732 | return -EBUSY; | |
733 | } | |
62fdfeaf | 734 | |
e1f99ce6 CW |
735 | int intel_ring_begin(struct intel_ring_buffer *ring, |
736 | int num_dwords) | |
8187a2b7 | 737 | { |
be26a10b | 738 | int n = 4*num_dwords; |
e1f99ce6 | 739 | int ret; |
78501eac | 740 | |
e1f99ce6 CW |
741 | if (unlikely(ring->tail + n > ring->size)) { |
742 | ret = intel_wrap_ring_buffer(ring); | |
743 | if (unlikely(ret)) | |
744 | return ret; | |
745 | } | |
78501eac | 746 | |
e1f99ce6 CW |
747 | if (unlikely(ring->space < n)) { |
748 | ret = intel_wait_ring_buffer(ring, n); | |
749 | if (unlikely(ret)) | |
750 | return ret; | |
751 | } | |
d97ed339 CW |
752 | |
753 | ring->space -= n; | |
e1f99ce6 | 754 | return 0; |
8187a2b7 | 755 | } |
62fdfeaf | 756 | |
78501eac | 757 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 758 | { |
d97ed339 | 759 | ring->tail &= ring->size - 1; |
78501eac | 760 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 761 | } |
62fdfeaf | 762 | |
e070868e | 763 | static const struct intel_ring_buffer render_ring = { |
8187a2b7 | 764 | .name = "render ring", |
9220434a | 765 | .id = RING_RENDER, |
333e9fe9 | 766 | .mmio_base = RENDER_RING_BASE, |
8187a2b7 | 767 | .size = 32 * PAGE_SIZE, |
8187a2b7 | 768 | .init = init_render_ring, |
297b0c5b | 769 | .write_tail = ring_write_tail, |
8187a2b7 ZN |
770 | .flush = render_ring_flush, |
771 | .add_request = render_ring_add_request, | |
f787a5f5 | 772 | .get_seqno = render_ring_get_seqno, |
8187a2b7 ZN |
773 | .user_irq_get = render_ring_get_user_irq, |
774 | .user_irq_put = render_ring_put_user_irq, | |
78501eac | 775 | .dispatch_execbuffer = render_ring_dispatch_execbuffer, |
8187a2b7 | 776 | }; |
d1b851fc ZN |
777 | |
778 | /* ring buffer for bit-stream decoder */ | |
779 | ||
e070868e | 780 | static const struct intel_ring_buffer bsd_ring = { |
d1b851fc | 781 | .name = "bsd ring", |
9220434a | 782 | .id = RING_BSD, |
333e9fe9 | 783 | .mmio_base = BSD_RING_BASE, |
d1b851fc | 784 | .size = 32 * PAGE_SIZE, |
78501eac | 785 | .init = init_ring_common, |
297b0c5b | 786 | .write_tail = ring_write_tail, |
d1b851fc | 787 | .flush = bsd_ring_flush, |
549f7365 CW |
788 | .add_request = ring_add_request, |
789 | .get_seqno = ring_status_page_get_seqno, | |
d1b851fc ZN |
790 | .user_irq_get = bsd_ring_get_user_irq, |
791 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 792 | .dispatch_execbuffer = ring_dispatch_execbuffer, |
d1b851fc | 793 | }; |
5c1143bb | 794 | |
881f47b6 | 795 | |
78501eac | 796 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 797 | u32 value) |
881f47b6 | 798 | { |
78501eac | 799 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
800 | |
801 | /* Every tail move must follow the sequence below */ | |
802 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
803 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
804 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
805 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
806 | ||
807 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
808 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
809 | 50)) | |
810 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
811 | ||
870e86dd | 812 | I915_WRITE_TAIL(ring, value); |
881f47b6 XH |
813 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
814 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
815 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
816 | } | |
817 | ||
78501eac | 818 | static void gen6_ring_flush(struct intel_ring_buffer *ring, |
549f7365 CW |
819 | u32 invalidate_domains, |
820 | u32 flush_domains) | |
881f47b6 | 821 | { |
e1f99ce6 CW |
822 | if (intel_ring_begin(ring, 4) == 0) { |
823 | intel_ring_emit(ring, MI_FLUSH_DW); | |
824 | intel_ring_emit(ring, 0); | |
825 | intel_ring_emit(ring, 0); | |
826 | intel_ring_emit(ring, 0); | |
827 | intel_ring_advance(ring); | |
828 | } | |
881f47b6 XH |
829 | } |
830 | ||
831 | static int | |
78501eac CW |
832 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
833 | struct drm_i915_gem_execbuffer2 *exec, | |
834 | struct drm_clip_rect *cliprects, | |
835 | uint64_t exec_offset) | |
881f47b6 XH |
836 | { |
837 | uint32_t exec_start; | |
e1f99ce6 | 838 | int ret; |
ab6f8e32 | 839 | |
881f47b6 | 840 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
ab6f8e32 | 841 | |
e1f99ce6 CW |
842 | ret = intel_ring_begin(ring, 2); |
843 | if (ret) | |
844 | return ret; | |
845 | ||
78501eac | 846 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
ab6f8e32 | 847 | /* bit0-7 is the length on GEN6+ */ |
78501eac CW |
848 | intel_ring_emit(ring, exec_start); |
849 | intel_ring_advance(ring); | |
ab6f8e32 | 850 | |
881f47b6 XH |
851 | return 0; |
852 | } | |
853 | ||
854 | /* ring buffer for Video Codec for Gen6+ */ | |
e070868e | 855 | static const struct intel_ring_buffer gen6_bsd_ring = { |
881f47b6 XH |
856 | .name = "gen6 bsd ring", |
857 | .id = RING_BSD, | |
333e9fe9 | 858 | .mmio_base = GEN6_BSD_RING_BASE, |
881f47b6 | 859 | .size = 32 * PAGE_SIZE, |
78501eac | 860 | .init = init_ring_common, |
297b0c5b | 861 | .write_tail = gen6_bsd_ring_write_tail, |
549f7365 CW |
862 | .flush = gen6_ring_flush, |
863 | .add_request = ring_add_request, | |
864 | .get_seqno = ring_status_page_get_seqno, | |
881f47b6 XH |
865 | .user_irq_get = bsd_ring_get_user_irq, |
866 | .user_irq_put = bsd_ring_put_user_irq, | |
78501eac | 867 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
549f7365 CW |
868 | }; |
869 | ||
870 | /* Blitter support (SandyBridge+) */ | |
871 | ||
872 | static void | |
78501eac | 873 | blt_ring_get_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
874 | { |
875 | /* do nothing */ | |
876 | } | |
877 | static void | |
78501eac | 878 | blt_ring_put_user_irq(struct intel_ring_buffer *ring) |
549f7365 CW |
879 | { |
880 | /* do nothing */ | |
881 | } | |
882 | ||
8d19215b ZN |
883 | |
884 | /* Workaround for some stepping of SNB, | |
885 | * each time when BLT engine ring tail moved, | |
886 | * the first command in the ring to be parsed | |
887 | * should be MI_BATCH_BUFFER_START | |
888 | */ | |
889 | #define NEED_BLT_WORKAROUND(dev) \ | |
890 | (IS_GEN6(dev) && (dev->pdev->revision < 8)) | |
891 | ||
892 | static inline struct drm_i915_gem_object * | |
893 | to_blt_workaround(struct intel_ring_buffer *ring) | |
894 | { | |
895 | return ring->private; | |
896 | } | |
897 | ||
898 | static int blt_ring_init(struct intel_ring_buffer *ring) | |
899 | { | |
900 | if (NEED_BLT_WORKAROUND(ring->dev)) { | |
901 | struct drm_i915_gem_object *obj; | |
27153f72 | 902 | u32 *ptr; |
8d19215b ZN |
903 | int ret; |
904 | ||
905 | obj = to_intel_bo(i915_gem_alloc_object(ring->dev, 4096)); | |
906 | if (obj == NULL) | |
907 | return -ENOMEM; | |
908 | ||
909 | ret = i915_gem_object_pin(&obj->base, 4096, true, false); | |
910 | if (ret) { | |
911 | drm_gem_object_unreference(&obj->base); | |
912 | return ret; | |
913 | } | |
914 | ||
915 | ptr = kmap(obj->pages[0]); | |
27153f72 CW |
916 | *ptr++ = MI_BATCH_BUFFER_END; |
917 | *ptr++ = MI_NOOP; | |
8d19215b ZN |
918 | kunmap(obj->pages[0]); |
919 | ||
920 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, false); | |
921 | if (ret) { | |
922 | i915_gem_object_unpin(&obj->base); | |
923 | drm_gem_object_unreference(&obj->base); | |
924 | return ret; | |
925 | } | |
926 | ||
927 | ring->private = obj; | |
928 | } | |
929 | ||
930 | return init_ring_common(ring); | |
931 | } | |
932 | ||
933 | static int blt_ring_begin(struct intel_ring_buffer *ring, | |
934 | int num_dwords) | |
935 | { | |
936 | if (ring->private) { | |
937 | int ret = intel_ring_begin(ring, num_dwords+2); | |
938 | if (ret) | |
939 | return ret; | |
940 | ||
941 | intel_ring_emit(ring, MI_BATCH_BUFFER_START); | |
942 | intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset); | |
943 | ||
944 | return 0; | |
945 | } else | |
946 | return intel_ring_begin(ring, 4); | |
947 | } | |
948 | ||
949 | static void blt_ring_flush(struct intel_ring_buffer *ring, | |
950 | u32 invalidate_domains, | |
951 | u32 flush_domains) | |
952 | { | |
953 | if (blt_ring_begin(ring, 4) == 0) { | |
954 | intel_ring_emit(ring, MI_FLUSH_DW); | |
955 | intel_ring_emit(ring, 0); | |
956 | intel_ring_emit(ring, 0); | |
957 | intel_ring_emit(ring, 0); | |
958 | intel_ring_advance(ring); | |
959 | } | |
960 | } | |
961 | ||
962 | static int | |
963 | blt_ring_add_request(struct intel_ring_buffer *ring, | |
964 | u32 *result) | |
965 | { | |
966 | u32 seqno; | |
967 | int ret; | |
968 | ||
969 | ret = blt_ring_begin(ring, 4); | |
970 | if (ret) | |
971 | return ret; | |
972 | ||
973 | seqno = i915_gem_get_seqno(ring->dev); | |
974 | ||
975 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); | |
976 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
977 | intel_ring_emit(ring, seqno); | |
978 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
979 | intel_ring_advance(ring); | |
980 | ||
981 | DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno); | |
982 | *result = seqno; | |
983 | return 0; | |
984 | } | |
985 | ||
986 | static void blt_ring_cleanup(struct intel_ring_buffer *ring) | |
987 | { | |
988 | if (!ring->private) | |
989 | return; | |
990 | ||
991 | i915_gem_object_unpin(ring->private); | |
992 | drm_gem_object_unreference(ring->private); | |
993 | ring->private = NULL; | |
994 | } | |
995 | ||
549f7365 CW |
996 | static const struct intel_ring_buffer gen6_blt_ring = { |
997 | .name = "blt ring", | |
998 | .id = RING_BLT, | |
999 | .mmio_base = BLT_RING_BASE, | |
1000 | .size = 32 * PAGE_SIZE, | |
8d19215b | 1001 | .init = blt_ring_init, |
297b0c5b | 1002 | .write_tail = ring_write_tail, |
8d19215b ZN |
1003 | .flush = blt_ring_flush, |
1004 | .add_request = blt_ring_add_request, | |
549f7365 CW |
1005 | .get_seqno = ring_status_page_get_seqno, |
1006 | .user_irq_get = blt_ring_get_user_irq, | |
1007 | .user_irq_put = blt_ring_put_user_irq, | |
78501eac | 1008 | .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, |
8d19215b | 1009 | .cleanup = blt_ring_cleanup, |
881f47b6 XH |
1010 | }; |
1011 | ||
5c1143bb XH |
1012 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1013 | { | |
1014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1015 | ||
1016 | dev_priv->render_ring = render_ring; | |
1017 | ||
1018 | if (!I915_NEED_GFX_HWS(dev)) { | |
1019 | dev_priv->render_ring.status_page.page_addr | |
1020 | = dev_priv->status_page_dmah->vaddr; | |
1021 | memset(dev_priv->render_ring.status_page.page_addr, | |
1022 | 0, PAGE_SIZE); | |
1023 | } | |
1024 | ||
1025 | return intel_init_ring_buffer(dev, &dev_priv->render_ring); | |
1026 | } | |
1027 | ||
1028 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
1029 | { | |
1030 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1031 | ||
881f47b6 XH |
1032 | if (IS_GEN6(dev)) |
1033 | dev_priv->bsd_ring = gen6_bsd_ring; | |
1034 | else | |
1035 | dev_priv->bsd_ring = bsd_ring; | |
5c1143bb XH |
1036 | |
1037 | return intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
1038 | } | |
549f7365 CW |
1039 | |
1040 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1041 | { | |
1042 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1043 | ||
1044 | dev_priv->blt_ring = gen6_blt_ring; | |
1045 | ||
1046 | return intel_init_ring_buffer(dev, &dev_priv->blt_ring); | |
1047 | } |