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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
760285e7 | 30 | #include <drm/drmP.h> |
62fdfeaf | 31 | #include "i915_drv.h" |
760285e7 | 32 | #include <drm/i915_drm.h> |
62fdfeaf | 33 | #include "i915_trace.h" |
881f47b6 | 34 | #include "intel_drv.h" |
62fdfeaf | 35 | |
48d82387 OM |
36 | bool |
37 | intel_ring_initialized(struct intel_engine_cs *ring) | |
38 | { | |
39 | struct drm_device *dev = ring->dev; | |
40 | ||
41 | if (!dev) | |
42 | return false; | |
43 | ||
44 | if (i915.enable_execlists) { | |
45 | struct intel_context *dctx = ring->default_context; | |
46 | struct intel_ringbuffer *ringbuf = dctx->engine[ring->id].ringbuf; | |
47 | ||
48 | return ringbuf->obj; | |
49 | } else | |
50 | return ring->buffer && ring->buffer->obj; | |
51 | } | |
18393f63 | 52 | |
82e104cc | 53 | int __intel_ring_space(int head, int tail, int size) |
c7dca47b | 54 | { |
4f54741e DG |
55 | int space = head - tail; |
56 | if (space <= 0) | |
1cf0ba14 | 57 | space += size; |
4f54741e | 58 | return space - I915_RING_FREE_SPACE; |
c7dca47b CW |
59 | } |
60 | ||
ebd0fd4b DG |
61 | void intel_ring_update_space(struct intel_ringbuffer *ringbuf) |
62 | { | |
63 | if (ringbuf->last_retired_head != -1) { | |
64 | ringbuf->head = ringbuf->last_retired_head; | |
65 | ringbuf->last_retired_head = -1; | |
66 | } | |
67 | ||
68 | ringbuf->space = __intel_ring_space(ringbuf->head & HEAD_ADDR, | |
69 | ringbuf->tail, ringbuf->size); | |
70 | } | |
71 | ||
82e104cc | 72 | int intel_ring_space(struct intel_ringbuffer *ringbuf) |
1cf0ba14 | 73 | { |
ebd0fd4b DG |
74 | intel_ring_update_space(ringbuf); |
75 | return ringbuf->space; | |
1cf0ba14 CW |
76 | } |
77 | ||
82e104cc | 78 | bool intel_ring_stopped(struct intel_engine_cs *ring) |
09246732 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
88b4aa87 MK |
81 | return dev_priv->gpu_error.stop_rings & intel_ring_flag(ring); |
82 | } | |
09246732 | 83 | |
a4872ba6 | 84 | void __intel_ring_advance(struct intel_engine_cs *ring) |
88b4aa87 | 85 | { |
93b0a4e0 OM |
86 | struct intel_ringbuffer *ringbuf = ring->buffer; |
87 | ringbuf->tail &= ringbuf->size - 1; | |
88b4aa87 | 88 | if (intel_ring_stopped(ring)) |
09246732 | 89 | return; |
93b0a4e0 | 90 | ring->write_tail(ring, ringbuf->tail); |
09246732 CW |
91 | } |
92 | ||
b72f3acb | 93 | static int |
a4872ba6 | 94 | gen2_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
95 | u32 invalidate_domains, |
96 | u32 flush_domains) | |
97 | { | |
98 | u32 cmd; | |
99 | int ret; | |
100 | ||
101 | cmd = MI_FLUSH; | |
31b14c9f | 102 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
103 | cmd |= MI_NO_WRITE_FLUSH; |
104 | ||
105 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
106 | cmd |= MI_READ_FLUSH; | |
107 | ||
108 | ret = intel_ring_begin(ring, 2); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
112 | intel_ring_emit(ring, cmd); | |
113 | intel_ring_emit(ring, MI_NOOP); | |
114 | intel_ring_advance(ring); | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | static int | |
a4872ba6 | 120 | gen4_render_ring_flush(struct intel_engine_cs *ring, |
46f0f8d1 CW |
121 | u32 invalidate_domains, |
122 | u32 flush_domains) | |
62fdfeaf | 123 | { |
78501eac | 124 | struct drm_device *dev = ring->dev; |
6f392d54 | 125 | u32 cmd; |
b72f3acb | 126 | int ret; |
6f392d54 | 127 | |
36d527de CW |
128 | /* |
129 | * read/write caches: | |
130 | * | |
131 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
132 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
133 | * also flushed at 2d versus 3d pipeline switches. | |
134 | * | |
135 | * read-only caches: | |
136 | * | |
137 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
138 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
139 | * | |
140 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
141 | * | |
142 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
143 | * invalidated when MI_EXE_FLUSH is set. | |
144 | * | |
145 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
146 | * invalidated with every MI_FLUSH. | |
147 | * | |
148 | * TLBs: | |
149 | * | |
150 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
151 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
152 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
153 | * are flushed at any MI_FLUSH. | |
154 | */ | |
155 | ||
156 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 157 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 158 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
159 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
160 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 161 | |
36d527de CW |
162 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
163 | (IS_G4X(dev) || IS_GEN5(dev))) | |
164 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 165 | |
36d527de CW |
166 | ret = intel_ring_begin(ring, 2); |
167 | if (ret) | |
168 | return ret; | |
b72f3acb | 169 | |
36d527de CW |
170 | intel_ring_emit(ring, cmd); |
171 | intel_ring_emit(ring, MI_NOOP); | |
172 | intel_ring_advance(ring); | |
b72f3acb CW |
173 | |
174 | return 0; | |
8187a2b7 ZN |
175 | } |
176 | ||
8d315287 JB |
177 | /** |
178 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
179 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
180 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
181 | * | |
182 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
183 | * produced by non-pipelined state commands), software needs to first | |
184 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
185 | * 0. | |
186 | * | |
187 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
188 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
189 | * | |
190 | * And the workaround for these two requires this workaround first: | |
191 | * | |
192 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
193 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
194 | * flushes. | |
195 | * | |
196 | * And this last workaround is tricky because of the requirements on | |
197 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
198 | * volume 2 part 1: | |
199 | * | |
200 | * "1 of the following must also be set: | |
201 | * - Render Target Cache Flush Enable ([12] of DW1) | |
202 | * - Depth Cache Flush Enable ([0] of DW1) | |
203 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
204 | * - Depth Stall ([13] of DW1) | |
205 | * - Post-Sync Operation ([13] of DW1) | |
206 | * - Notify Enable ([8] of DW1)" | |
207 | * | |
208 | * The cache flushes require the workaround flush that triggered this | |
209 | * one, so we can't use it. Depth stall would trigger the same. | |
210 | * Post-sync nonzero is what triggered this second workaround, so we | |
211 | * can't use that one either. Notify enable is IRQs, which aren't | |
212 | * really our business. That leaves only stall at scoreboard. | |
213 | */ | |
214 | static int | |
a4872ba6 | 215 | intel_emit_post_sync_nonzero_flush(struct intel_engine_cs *ring) |
8d315287 | 216 | { |
18393f63 | 217 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
218 | int ret; |
219 | ||
220 | ||
221 | ret = intel_ring_begin(ring, 6); | |
222 | if (ret) | |
223 | return ret; | |
224 | ||
225 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
226 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
227 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
228 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
229 | intel_ring_emit(ring, 0); /* low dword */ | |
230 | intel_ring_emit(ring, 0); /* high dword */ | |
231 | intel_ring_emit(ring, MI_NOOP); | |
232 | intel_ring_advance(ring); | |
233 | ||
234 | ret = intel_ring_begin(ring, 6); | |
235 | if (ret) | |
236 | return ret; | |
237 | ||
238 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
239 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
240 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
241 | intel_ring_emit(ring, 0); | |
242 | intel_ring_emit(ring, 0); | |
243 | intel_ring_emit(ring, MI_NOOP); | |
244 | intel_ring_advance(ring); | |
245 | ||
246 | return 0; | |
247 | } | |
248 | ||
249 | static int | |
a4872ba6 | 250 | gen6_render_ring_flush(struct intel_engine_cs *ring, |
8d315287 JB |
251 | u32 invalidate_domains, u32 flush_domains) |
252 | { | |
253 | u32 flags = 0; | |
18393f63 | 254 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
8d315287 JB |
255 | int ret; |
256 | ||
b3111509 PZ |
257 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
258 | ret = intel_emit_post_sync_nonzero_flush(ring); | |
259 | if (ret) | |
260 | return ret; | |
261 | ||
8d315287 JB |
262 | /* Just flush everything. Experiments have shown that reducing the |
263 | * number of bits based on the write domains has little performance | |
264 | * impact. | |
265 | */ | |
7d54a904 CW |
266 | if (flush_domains) { |
267 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
268 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
269 | /* | |
270 | * Ensure that any following seqno writes only happen | |
271 | * when the render cache is indeed flushed. | |
272 | */ | |
97f209bc | 273 | flags |= PIPE_CONTROL_CS_STALL; |
7d54a904 CW |
274 | } |
275 | if (invalidate_domains) { | |
276 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
277 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
278 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
279 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
280 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
281 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
282 | /* | |
283 | * TLB invalidate requires a post-sync write. | |
284 | */ | |
3ac78313 | 285 | flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; |
7d54a904 | 286 | } |
8d315287 | 287 | |
6c6cf5aa | 288 | ret = intel_ring_begin(ring, 4); |
8d315287 JB |
289 | if (ret) |
290 | return ret; | |
291 | ||
6c6cf5aa | 292 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); |
8d315287 JB |
293 | intel_ring_emit(ring, flags); |
294 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
6c6cf5aa | 295 | intel_ring_emit(ring, 0); |
8d315287 JB |
296 | intel_ring_advance(ring); |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
f3987631 | 301 | static int |
a4872ba6 | 302 | gen7_render_ring_cs_stall_wa(struct intel_engine_cs *ring) |
f3987631 PZ |
303 | { |
304 | int ret; | |
305 | ||
306 | ret = intel_ring_begin(ring, 4); | |
307 | if (ret) | |
308 | return ret; | |
309 | ||
310 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
311 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
312 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
313 | intel_ring_emit(ring, 0); | |
314 | intel_ring_emit(ring, 0); | |
315 | intel_ring_advance(ring); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
a4872ba6 | 320 | static int gen7_ring_fbc_flush(struct intel_engine_cs *ring, u32 value) |
fd3da6c9 RV |
321 | { |
322 | int ret; | |
323 | ||
324 | if (!ring->fbc_dirty) | |
325 | return 0; | |
326 | ||
37c1d94f | 327 | ret = intel_ring_begin(ring, 6); |
fd3da6c9 RV |
328 | if (ret) |
329 | return ret; | |
fd3da6c9 RV |
330 | /* WaFbcNukeOn3DBlt:ivb/hsw */ |
331 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
332 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
333 | intel_ring_emit(ring, value); | |
37c1d94f VS |
334 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT); |
335 | intel_ring_emit(ring, MSG_FBC_REND_STATE); | |
336 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
fd3da6c9 RV |
337 | intel_ring_advance(ring); |
338 | ||
339 | ring->fbc_dirty = false; | |
340 | return 0; | |
341 | } | |
342 | ||
4772eaeb | 343 | static int |
a4872ba6 | 344 | gen7_render_ring_flush(struct intel_engine_cs *ring, |
4772eaeb PZ |
345 | u32 invalidate_domains, u32 flush_domains) |
346 | { | |
347 | u32 flags = 0; | |
18393f63 | 348 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
4772eaeb PZ |
349 | int ret; |
350 | ||
f3987631 PZ |
351 | /* |
352 | * Ensure that any following seqno writes only happen when the render | |
353 | * cache is indeed flushed. | |
354 | * | |
355 | * Workaround: 4th PIPE_CONTROL command (except the ones with only | |
356 | * read-cache invalidate bits set) must have the CS_STALL bit set. We | |
357 | * don't try to be clever and just set it unconditionally. | |
358 | */ | |
359 | flags |= PIPE_CONTROL_CS_STALL; | |
360 | ||
4772eaeb PZ |
361 | /* Just flush everything. Experiments have shown that reducing the |
362 | * number of bits based on the write domains has little performance | |
363 | * impact. | |
364 | */ | |
365 | if (flush_domains) { | |
366 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
367 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
4772eaeb PZ |
368 | } |
369 | if (invalidate_domains) { | |
370 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
371 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
372 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
373 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
374 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
375 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
148b83d0 | 376 | flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR; |
4772eaeb PZ |
377 | /* |
378 | * TLB invalidate requires a post-sync write. | |
379 | */ | |
380 | flags |= PIPE_CONTROL_QW_WRITE; | |
b9e1faa7 | 381 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; |
f3987631 | 382 | |
add284a3 CW |
383 | flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD; |
384 | ||
f3987631 PZ |
385 | /* Workaround: we must issue a pipe_control with CS-stall bit |
386 | * set before a pipe_control command that has the state cache | |
387 | * invalidate bit set. */ | |
388 | gen7_render_ring_cs_stall_wa(ring); | |
4772eaeb PZ |
389 | } |
390 | ||
391 | ret = intel_ring_begin(ring, 4); | |
392 | if (ret) | |
393 | return ret; | |
394 | ||
395 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); | |
396 | intel_ring_emit(ring, flags); | |
b9e1faa7 | 397 | intel_ring_emit(ring, scratch_addr); |
4772eaeb PZ |
398 | intel_ring_emit(ring, 0); |
399 | intel_ring_advance(ring); | |
400 | ||
9688ecad | 401 | if (!invalidate_domains && flush_domains) |
fd3da6c9 RV |
402 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); |
403 | ||
4772eaeb PZ |
404 | return 0; |
405 | } | |
406 | ||
884ceace KG |
407 | static int |
408 | gen8_emit_pipe_control(struct intel_engine_cs *ring, | |
409 | u32 flags, u32 scratch_addr) | |
410 | { | |
411 | int ret; | |
412 | ||
413 | ret = intel_ring_begin(ring, 6); | |
414 | if (ret) | |
415 | return ret; | |
416 | ||
417 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); | |
418 | intel_ring_emit(ring, flags); | |
419 | intel_ring_emit(ring, scratch_addr); | |
420 | intel_ring_emit(ring, 0); | |
421 | intel_ring_emit(ring, 0); | |
422 | intel_ring_emit(ring, 0); | |
423 | intel_ring_advance(ring); | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
a5f3d68e | 428 | static int |
a4872ba6 | 429 | gen8_render_ring_flush(struct intel_engine_cs *ring, |
a5f3d68e BW |
430 | u32 invalidate_domains, u32 flush_domains) |
431 | { | |
432 | u32 flags = 0; | |
18393f63 | 433 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
02c9f7e3 | 434 | int ret; |
a5f3d68e BW |
435 | |
436 | flags |= PIPE_CONTROL_CS_STALL; | |
437 | ||
438 | if (flush_domains) { | |
439 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
440 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
441 | } | |
442 | if (invalidate_domains) { | |
443 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
444 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
445 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
446 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
447 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
448 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
449 | flags |= PIPE_CONTROL_QW_WRITE; | |
450 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
02c9f7e3 KG |
451 | |
452 | /* WaCsStallBeforeStateCacheInvalidate:bdw,chv */ | |
453 | ret = gen8_emit_pipe_control(ring, | |
454 | PIPE_CONTROL_CS_STALL | | |
455 | PIPE_CONTROL_STALL_AT_SCOREBOARD, | |
456 | 0); | |
457 | if (ret) | |
458 | return ret; | |
a5f3d68e BW |
459 | } |
460 | ||
c5ad011d RV |
461 | ret = gen8_emit_pipe_control(ring, flags, scratch_addr); |
462 | if (ret) | |
463 | return ret; | |
464 | ||
465 | if (!invalidate_domains && flush_domains) | |
466 | return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); | |
467 | ||
468 | return 0; | |
a5f3d68e BW |
469 | } |
470 | ||
a4872ba6 | 471 | static void ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 472 | u32 value) |
d46eefa2 | 473 | { |
4640c4ff | 474 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
297b0c5b | 475 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
476 | } |
477 | ||
a4872ba6 | 478 | u64 intel_ring_get_active_head(struct intel_engine_cs *ring) |
8187a2b7 | 479 | { |
4640c4ff | 480 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
50877445 | 481 | u64 acthd; |
8187a2b7 | 482 | |
50877445 CW |
483 | if (INTEL_INFO(ring->dev)->gen >= 8) |
484 | acthd = I915_READ64_2x32(RING_ACTHD(ring->mmio_base), | |
485 | RING_ACTHD_UDW(ring->mmio_base)); | |
486 | else if (INTEL_INFO(ring->dev)->gen >= 4) | |
487 | acthd = I915_READ(RING_ACTHD(ring->mmio_base)); | |
488 | else | |
489 | acthd = I915_READ(ACTHD); | |
490 | ||
491 | return acthd; | |
8187a2b7 ZN |
492 | } |
493 | ||
a4872ba6 | 494 | static void ring_setup_phys_status_page(struct intel_engine_cs *ring) |
035dc1e0 DV |
495 | { |
496 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
497 | u32 addr; | |
498 | ||
499 | addr = dev_priv->status_page_dmah->busaddr; | |
500 | if (INTEL_INFO(ring->dev)->gen >= 4) | |
501 | addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0; | |
502 | I915_WRITE(HWS_PGA, addr); | |
503 | } | |
504 | ||
af75f269 DL |
505 | static void intel_ring_setup_status_page(struct intel_engine_cs *ring) |
506 | { | |
507 | struct drm_device *dev = ring->dev; | |
508 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
509 | u32 mmio = 0; | |
510 | ||
511 | /* The ring status page addresses are no longer next to the rest of | |
512 | * the ring registers as of gen7. | |
513 | */ | |
514 | if (IS_GEN7(dev)) { | |
515 | switch (ring->id) { | |
516 | case RCS: | |
517 | mmio = RENDER_HWS_PGA_GEN7; | |
518 | break; | |
519 | case BCS: | |
520 | mmio = BLT_HWS_PGA_GEN7; | |
521 | break; | |
522 | /* | |
523 | * VCS2 actually doesn't exist on Gen7. Only shut up | |
524 | * gcc switch check warning | |
525 | */ | |
526 | case VCS2: | |
527 | case VCS: | |
528 | mmio = BSD_HWS_PGA_GEN7; | |
529 | break; | |
530 | case VECS: | |
531 | mmio = VEBOX_HWS_PGA_GEN7; | |
532 | break; | |
533 | } | |
534 | } else if (IS_GEN6(ring->dev)) { | |
535 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
536 | } else { | |
537 | /* XXX: gen8 returns to sanity */ | |
538 | mmio = RING_HWS_PGA(ring->mmio_base); | |
539 | } | |
540 | ||
541 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); | |
542 | POSTING_READ(mmio); | |
543 | ||
544 | /* | |
545 | * Flush the TLB for this page | |
546 | * | |
547 | * FIXME: These two bits have disappeared on gen8, so a question | |
548 | * arises: do we still need this and if so how should we go about | |
549 | * invalidating the TLB? | |
550 | */ | |
551 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) { | |
552 | u32 reg = RING_INSTPM(ring->mmio_base); | |
553 | ||
554 | /* ring should be idle before issuing a sync flush*/ | |
555 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
556 | ||
557 | I915_WRITE(reg, | |
558 | _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE | | |
559 | INSTPM_SYNC_FLUSH)); | |
560 | if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, | |
561 | 1000)) | |
562 | DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n", | |
563 | ring->name); | |
564 | } | |
565 | } | |
566 | ||
a4872ba6 | 567 | static bool stop_ring(struct intel_engine_cs *ring) |
8187a2b7 | 568 | { |
9991ae78 | 569 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
8187a2b7 | 570 | |
9991ae78 CW |
571 | if (!IS_GEN2(ring->dev)) { |
572 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
403bdd10 DV |
573 | if (wait_for((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { |
574 | DRM_ERROR("%s : timed out trying to stop ring\n", ring->name); | |
9bec9b13 CW |
575 | /* Sometimes we observe that the idle flag is not |
576 | * set even though the ring is empty. So double | |
577 | * check before giving up. | |
578 | */ | |
579 | if (I915_READ_HEAD(ring) != I915_READ_TAIL(ring)) | |
580 | return false; | |
9991ae78 CW |
581 | } |
582 | } | |
b7884eb4 | 583 | |
7f2ab699 | 584 | I915_WRITE_CTL(ring, 0); |
570ef608 | 585 | I915_WRITE_HEAD(ring, 0); |
78501eac | 586 | ring->write_tail(ring, 0); |
8187a2b7 | 587 | |
9991ae78 CW |
588 | if (!IS_GEN2(ring->dev)) { |
589 | (void)I915_READ_CTL(ring); | |
590 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
591 | } | |
a51435a3 | 592 | |
9991ae78 CW |
593 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
594 | } | |
8187a2b7 | 595 | |
a4872ba6 | 596 | static int init_ring_common(struct intel_engine_cs *ring) |
9991ae78 CW |
597 | { |
598 | struct drm_device *dev = ring->dev; | |
599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93b0a4e0 OM |
600 | struct intel_ringbuffer *ringbuf = ring->buffer; |
601 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
9991ae78 CW |
602 | int ret = 0; |
603 | ||
59bad947 | 604 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
9991ae78 CW |
605 | |
606 | if (!stop_ring(ring)) { | |
607 | /* G45 ring initialization often fails to reset head to zero */ | |
6fd0d56e CW |
608 | DRM_DEBUG_KMS("%s head not reset to zero " |
609 | "ctl %08x head %08x tail %08x start %08x\n", | |
610 | ring->name, | |
611 | I915_READ_CTL(ring), | |
612 | I915_READ_HEAD(ring), | |
613 | I915_READ_TAIL(ring), | |
614 | I915_READ_START(ring)); | |
8187a2b7 | 615 | |
9991ae78 | 616 | if (!stop_ring(ring)) { |
6fd0d56e CW |
617 | DRM_ERROR("failed to set %s head to zero " |
618 | "ctl %08x head %08x tail %08x start %08x\n", | |
619 | ring->name, | |
620 | I915_READ_CTL(ring), | |
621 | I915_READ_HEAD(ring), | |
622 | I915_READ_TAIL(ring), | |
623 | I915_READ_START(ring)); | |
9991ae78 CW |
624 | ret = -EIO; |
625 | goto out; | |
6fd0d56e | 626 | } |
8187a2b7 ZN |
627 | } |
628 | ||
9991ae78 CW |
629 | if (I915_NEED_GFX_HWS(dev)) |
630 | intel_ring_setup_status_page(ring); | |
631 | else | |
632 | ring_setup_phys_status_page(ring); | |
633 | ||
ece4a17d JK |
634 | /* Enforce ordering by reading HEAD register back */ |
635 | I915_READ_HEAD(ring); | |
636 | ||
0d8957c8 DV |
637 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
638 | * registers with the above sequence (the readback of the HEAD registers | |
639 | * also enforces ordering), otherwise the hw might lose the new ring | |
640 | * register values. */ | |
f343c5f6 | 641 | I915_WRITE_START(ring, i915_gem_obj_ggtt_offset(obj)); |
95468892 CW |
642 | |
643 | /* WaClearRingBufHeadRegAtInit:ctg,elk */ | |
644 | if (I915_READ_HEAD(ring)) | |
645 | DRM_DEBUG("%s initialization failed [head=%08x], fudging\n", | |
646 | ring->name, I915_READ_HEAD(ring)); | |
647 | I915_WRITE_HEAD(ring, 0); | |
648 | (void)I915_READ_HEAD(ring); | |
649 | ||
7f2ab699 | 650 | I915_WRITE_CTL(ring, |
93b0a4e0 | 651 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 652 | | RING_VALID); |
8187a2b7 | 653 | |
8187a2b7 | 654 | /* If the head is still not zero, the ring is dead */ |
f01db988 | 655 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
f343c5f6 | 656 | I915_READ_START(ring) == i915_gem_obj_ggtt_offset(obj) && |
f01db988 | 657 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
e74cfed5 | 658 | DRM_ERROR("%s initialization failed " |
48e48a0b CW |
659 | "ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx]\n", |
660 | ring->name, | |
661 | I915_READ_CTL(ring), I915_READ_CTL(ring) & RING_VALID, | |
662 | I915_READ_HEAD(ring), I915_READ_TAIL(ring), | |
663 | I915_READ_START(ring), (unsigned long)i915_gem_obj_ggtt_offset(obj)); | |
b7884eb4 DV |
664 | ret = -EIO; |
665 | goto out; | |
8187a2b7 ZN |
666 | } |
667 | ||
ebd0fd4b | 668 | ringbuf->last_retired_head = -1; |
5c6c6003 CW |
669 | ringbuf->head = I915_READ_HEAD(ring); |
670 | ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR; | |
ebd0fd4b | 671 | intel_ring_update_space(ringbuf); |
1ec14ad3 | 672 | |
50f018df CW |
673 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); |
674 | ||
b7884eb4 | 675 | out: |
59bad947 | 676 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b7884eb4 DV |
677 | |
678 | return ret; | |
8187a2b7 ZN |
679 | } |
680 | ||
9b1136d5 OM |
681 | void |
682 | intel_fini_pipe_control(struct intel_engine_cs *ring) | |
683 | { | |
684 | struct drm_device *dev = ring->dev; | |
685 | ||
686 | if (ring->scratch.obj == NULL) | |
687 | return; | |
688 | ||
689 | if (INTEL_INFO(dev)->gen >= 5) { | |
690 | kunmap(sg_page(ring->scratch.obj->pages->sgl)); | |
691 | i915_gem_object_ggtt_unpin(ring->scratch.obj); | |
692 | } | |
693 | ||
694 | drm_gem_object_unreference(&ring->scratch.obj->base); | |
695 | ring->scratch.obj = NULL; | |
696 | } | |
697 | ||
698 | int | |
699 | intel_init_pipe_control(struct intel_engine_cs *ring) | |
c6df541c | 700 | { |
c6df541c CW |
701 | int ret; |
702 | ||
bfc882b4 | 703 | WARN_ON(ring->scratch.obj); |
c6df541c | 704 | |
0d1aacac CW |
705 | ring->scratch.obj = i915_gem_alloc_object(ring->dev, 4096); |
706 | if (ring->scratch.obj == NULL) { | |
c6df541c CW |
707 | DRM_ERROR("Failed to allocate seqno page\n"); |
708 | ret = -ENOMEM; | |
709 | goto err; | |
710 | } | |
e4ffd173 | 711 | |
a9cc726c DV |
712 | ret = i915_gem_object_set_cache_level(ring->scratch.obj, I915_CACHE_LLC); |
713 | if (ret) | |
714 | goto err_unref; | |
c6df541c | 715 | |
1ec9e26d | 716 | ret = i915_gem_obj_ggtt_pin(ring->scratch.obj, 4096, 0); |
c6df541c CW |
717 | if (ret) |
718 | goto err_unref; | |
719 | ||
0d1aacac CW |
720 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(ring->scratch.obj); |
721 | ring->scratch.cpu_page = kmap(sg_page(ring->scratch.obj->pages->sgl)); | |
722 | if (ring->scratch.cpu_page == NULL) { | |
56b085a0 | 723 | ret = -ENOMEM; |
c6df541c | 724 | goto err_unpin; |
56b085a0 | 725 | } |
c6df541c | 726 | |
2b1086cc | 727 | DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n", |
0d1aacac | 728 | ring->name, ring->scratch.gtt_offset); |
c6df541c CW |
729 | return 0; |
730 | ||
731 | err_unpin: | |
d7f46fc4 | 732 | i915_gem_object_ggtt_unpin(ring->scratch.obj); |
c6df541c | 733 | err_unref: |
0d1aacac | 734 | drm_gem_object_unreference(&ring->scratch.obj->base); |
c6df541c | 735 | err: |
c6df541c CW |
736 | return ret; |
737 | } | |
738 | ||
771b9a53 MT |
739 | static int intel_ring_workarounds_emit(struct intel_engine_cs *ring, |
740 | struct intel_context *ctx) | |
86d7f238 | 741 | { |
7225342a | 742 | int ret, i; |
888b5995 AS |
743 | struct drm_device *dev = ring->dev; |
744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7225342a | 745 | struct i915_workarounds *w = &dev_priv->workarounds; |
888b5995 | 746 | |
e6c1abb7 | 747 | if (WARN_ON_ONCE(w->count == 0)) |
7225342a | 748 | return 0; |
888b5995 | 749 | |
7225342a MK |
750 | ring->gpu_caches_dirty = true; |
751 | ret = intel_ring_flush_all_caches(ring); | |
752 | if (ret) | |
753 | return ret; | |
888b5995 | 754 | |
22a916aa | 755 | ret = intel_ring_begin(ring, (w->count * 2 + 2)); |
7225342a MK |
756 | if (ret) |
757 | return ret; | |
758 | ||
22a916aa | 759 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
7225342a | 760 | for (i = 0; i < w->count; i++) { |
7225342a MK |
761 | intel_ring_emit(ring, w->reg[i].addr); |
762 | intel_ring_emit(ring, w->reg[i].value); | |
763 | } | |
22a916aa | 764 | intel_ring_emit(ring, MI_NOOP); |
7225342a MK |
765 | |
766 | intel_ring_advance(ring); | |
767 | ||
768 | ring->gpu_caches_dirty = true; | |
769 | ret = intel_ring_flush_all_caches(ring); | |
770 | if (ret) | |
771 | return ret; | |
888b5995 | 772 | |
7225342a | 773 | DRM_DEBUG_DRIVER("Number of Workarounds emitted: %d\n", w->count); |
888b5995 | 774 | |
7225342a | 775 | return 0; |
86d7f238 AS |
776 | } |
777 | ||
8f0e2b9d DV |
778 | static int intel_rcs_ctx_init(struct intel_engine_cs *ring, |
779 | struct intel_context *ctx) | |
780 | { | |
781 | int ret; | |
782 | ||
783 | ret = intel_ring_workarounds_emit(ring, ctx); | |
784 | if (ret != 0) | |
785 | return ret; | |
786 | ||
787 | ret = i915_gem_render_state_init(ring); | |
788 | if (ret) | |
789 | DRM_ERROR("init render state: %d\n", ret); | |
790 | ||
791 | return ret; | |
792 | } | |
793 | ||
7225342a | 794 | static int wa_add(struct drm_i915_private *dev_priv, |
cf4b0de6 | 795 | const u32 addr, const u32 mask, const u32 val) |
7225342a MK |
796 | { |
797 | const u32 idx = dev_priv->workarounds.count; | |
798 | ||
799 | if (WARN_ON(idx >= I915_MAX_WA_REGS)) | |
800 | return -ENOSPC; | |
801 | ||
802 | dev_priv->workarounds.reg[idx].addr = addr; | |
803 | dev_priv->workarounds.reg[idx].value = val; | |
804 | dev_priv->workarounds.reg[idx].mask = mask; | |
805 | ||
806 | dev_priv->workarounds.count++; | |
807 | ||
808 | return 0; | |
86d7f238 AS |
809 | } |
810 | ||
cf4b0de6 DL |
811 | #define WA_REG(addr, mask, val) { \ |
812 | const int r = wa_add(dev_priv, (addr), (mask), (val)); \ | |
7225342a MK |
813 | if (r) \ |
814 | return r; \ | |
815 | } | |
816 | ||
817 | #define WA_SET_BIT_MASKED(addr, mask) \ | |
26459343 | 818 | WA_REG(addr, (mask), _MASKED_BIT_ENABLE(mask)) |
7225342a MK |
819 | |
820 | #define WA_CLR_BIT_MASKED(addr, mask) \ | |
26459343 | 821 | WA_REG(addr, (mask), _MASKED_BIT_DISABLE(mask)) |
7225342a | 822 | |
98533251 | 823 | #define WA_SET_FIELD_MASKED(addr, mask, value) \ |
cf4b0de6 | 824 | WA_REG(addr, mask, _MASKED_FIELD(mask, value)) |
7225342a | 825 | |
cf4b0de6 DL |
826 | #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask)) |
827 | #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask)) | |
7225342a | 828 | |
cf4b0de6 | 829 | #define WA_WRITE(addr, val) WA_REG(addr, 0xffffffff, val) |
7225342a | 830 | |
00e1e623 | 831 | static int bdw_init_workarounds(struct intel_engine_cs *ring) |
86d7f238 | 832 | { |
888b5995 AS |
833 | struct drm_device *dev = ring->dev; |
834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
86d7f238 | 835 | |
86d7f238 | 836 | /* WaDisablePartialInstShootdown:bdw */ |
101b376d | 837 | /* WaDisableThreadStallDopClockGating:bdw (pre-production) */ |
7225342a MK |
838 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
839 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | | |
840 | STALL_DOP_GATING_DISABLE); | |
86d7f238 | 841 | |
101b376d | 842 | /* WaDisableDopClockGating:bdw */ |
7225342a MK |
843 | WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, |
844 | DOP_CLOCK_GATING_DISABLE); | |
86d7f238 | 845 | |
7225342a MK |
846 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, |
847 | GEN8_SAMPLER_POWER_BYPASS_DIS); | |
86d7f238 AS |
848 | |
849 | /* Use Force Non-Coherent whenever executing a 3D context. This is a | |
850 | * workaround for for a possible hang in the unlikely event a TLB | |
851 | * invalidation occurs during a PSD flush. | |
852 | */ | |
7225342a | 853 | WA_SET_BIT_MASKED(HDC_CHICKEN0, |
35cb6f3b | 854 | /* WaForceEnableNonCoherent:bdw */ |
7225342a | 855 | HDC_FORCE_NON_COHERENT | |
35cb6f3b DL |
856 | /* WaForceContextSaveRestoreNonCoherent:bdw */ |
857 | HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT | | |
858 | /* WaHdcDisableFetchWhenMasked:bdw */ | |
f3f32360 | 859 | HDC_DONOT_FETCH_MEM_WHEN_MASKED | |
35cb6f3b | 860 | /* WaDisableFenceDestinationToSLM:bdw (pre-prod) */ |
7225342a | 861 | (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0)); |
86d7f238 | 862 | |
2701fc43 KG |
863 | /* From the Haswell PRM, Command Reference: Registers, CACHE_MODE_0: |
864 | * "The Hierarchical Z RAW Stall Optimization allows non-overlapping | |
865 | * polygons in the same 8x4 pixel/sample area to be processed without | |
866 | * stalling waiting for the earlier ones to write to Hierarchical Z | |
867 | * buffer." | |
868 | * | |
869 | * This optimization is off by default for Broadwell; turn it on. | |
870 | */ | |
871 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
872 | ||
86d7f238 | 873 | /* Wa4x4STCOptimizationDisable:bdw */ |
7225342a MK |
874 | WA_SET_BIT_MASKED(CACHE_MODE_1, |
875 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
86d7f238 AS |
876 | |
877 | /* | |
878 | * BSpec recommends 8x4 when MSAA is used, | |
879 | * however in practice 16x4 seems fastest. | |
880 | * | |
881 | * Note that PS/WM thread counts depend on the WIZ hashing | |
882 | * disable bit, which we don't touch here, but it's good | |
883 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
884 | */ | |
98533251 DL |
885 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, |
886 | GEN6_WIZ_HASHING_MASK, | |
887 | GEN6_WIZ_HASHING_16x4); | |
888b5995 | 888 | |
86d7f238 AS |
889 | return 0; |
890 | } | |
891 | ||
00e1e623 VS |
892 | static int chv_init_workarounds(struct intel_engine_cs *ring) |
893 | { | |
00e1e623 VS |
894 | struct drm_device *dev = ring->dev; |
895 | struct drm_i915_private *dev_priv = dev->dev_private; | |
896 | ||
00e1e623 | 897 | /* WaDisablePartialInstShootdown:chv */ |
00e1e623 | 898 | /* WaDisableThreadStallDopClockGating:chv */ |
7225342a | 899 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, |
605f1433 AS |
900 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE | |
901 | STALL_DOP_GATING_DISABLE); | |
00e1e623 | 902 | |
95289009 AS |
903 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
904 | * workaround for a possible hang in the unlikely event a TLB | |
905 | * invalidation occurs during a PSD flush. | |
906 | */ | |
907 | /* WaForceEnableNonCoherent:chv */ | |
908 | /* WaHdcDisableFetchWhenMasked:chv */ | |
909 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
910 | HDC_FORCE_NON_COHERENT | | |
911 | HDC_DONOT_FETCH_MEM_WHEN_MASKED); | |
912 | ||
973a5b06 KG |
913 | /* According to the CACHE_MODE_0 default value documentation, some |
914 | * CHV platforms disable this optimization by default. Turn it on. | |
915 | */ | |
916 | WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, HIZ_RAW_STALL_OPT_DISABLE); | |
917 | ||
14bc16e3 VS |
918 | /* Wa4x4STCOptimizationDisable:chv */ |
919 | WA_SET_BIT_MASKED(CACHE_MODE_1, | |
920 | GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
921 | ||
d60de81d KG |
922 | /* Improve HiZ throughput on CHV. */ |
923 | WA_SET_BIT_MASKED(HIZ_CHICKEN, CHV_HZ_8X8_MODE_IN_1X); | |
924 | ||
e7fc2436 VS |
925 | /* |
926 | * BSpec recommends 8x4 when MSAA is used, | |
927 | * however in practice 16x4 seems fastest. | |
928 | * | |
929 | * Note that PS/WM thread counts depend on the WIZ hashing | |
930 | * disable bit, which we don't touch here, but it's good | |
931 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
932 | */ | |
933 | WA_SET_FIELD_MASKED(GEN7_GT_MODE, | |
934 | GEN6_WIZ_HASHING_MASK, | |
935 | GEN6_WIZ_HASHING_16x4); | |
936 | ||
7225342a MK |
937 | return 0; |
938 | } | |
939 | ||
3b106531 HN |
940 | static int gen9_init_workarounds(struct intel_engine_cs *ring) |
941 | { | |
ab0dfafe HN |
942 | struct drm_device *dev = ring->dev; |
943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
944 | ||
945 | /* WaDisablePartialInstShootdown:skl */ | |
946 | WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN, | |
947 | PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE); | |
948 | ||
8424171e NH |
949 | /* Syncing dependencies between camera and graphics */ |
950 | WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, | |
951 | GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC); | |
952 | ||
e90fff15 NH |
953 | if (INTEL_REVID(dev) >= SKL_REVID_A0 && |
954 | INTEL_REVID(dev) <= SKL_REVID_B0) { | |
1de4582f NH |
955 | /* |
956 | * WaDisableDgMirrorFixInHalfSliceChicken5:skl | |
957 | * This is a pre-production w/a. | |
958 | */ | |
959 | I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, | |
960 | I915_READ(GEN9_HALF_SLICE_CHICKEN5) & | |
961 | ~GEN9_DG_MIRROR_FIX_ENABLE); | |
962 | } | |
963 | ||
cac23df4 NH |
964 | if (INTEL_REVID(dev) >= SKL_REVID_C0) { |
965 | /* WaEnableYV12BugFixInHalfSliceChicken7:skl */ | |
966 | WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7, | |
967 | GEN9_ENABLE_YV12_BUGFIX); | |
968 | } | |
969 | ||
13bea49c HN |
970 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
971 | /* | |
972 | *Use Force Non-Coherent whenever executing a 3D context. This | |
973 | * is a workaround for a possible hang in the unlikely event | |
974 | * a TLB invalidation occurs during a PSD flush. | |
975 | */ | |
976 | /* WaForceEnableNonCoherent:skl */ | |
977 | WA_SET_BIT_MASKED(HDC_CHICKEN0, | |
978 | HDC_FORCE_NON_COHERENT); | |
979 | } | |
980 | ||
1840481f HN |
981 | /* Wa4x4STCOptimizationDisable:skl */ |
982 | WA_SET_BIT_MASKED(CACHE_MODE_1, GEN8_4x4_STC_OPTIMIZATION_DISABLE); | |
983 | ||
3b106531 HN |
984 | return 0; |
985 | } | |
986 | ||
8d205494 DL |
987 | static int skl_init_workarounds(struct intel_engine_cs *ring) |
988 | { | |
989 | gen9_init_workarounds(ring); | |
990 | ||
991 | return 0; | |
992 | } | |
993 | ||
771b9a53 | 994 | int init_workarounds_ring(struct intel_engine_cs *ring) |
7225342a MK |
995 | { |
996 | struct drm_device *dev = ring->dev; | |
997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
998 | ||
999 | WARN_ON(ring->id != RCS); | |
1000 | ||
1001 | dev_priv->workarounds.count = 0; | |
1002 | ||
1003 | if (IS_BROADWELL(dev)) | |
1004 | return bdw_init_workarounds(ring); | |
1005 | ||
1006 | if (IS_CHERRYVIEW(dev)) | |
1007 | return chv_init_workarounds(ring); | |
00e1e623 | 1008 | |
8d205494 DL |
1009 | if (IS_SKYLAKE(dev)) |
1010 | return skl_init_workarounds(ring); | |
1011 | else if (IS_GEN9(dev)) | |
3b106531 HN |
1012 | return gen9_init_workarounds(ring); |
1013 | ||
00e1e623 VS |
1014 | return 0; |
1015 | } | |
1016 | ||
a4872ba6 | 1017 | static int init_render_ring(struct intel_engine_cs *ring) |
8187a2b7 | 1018 | { |
78501eac | 1019 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1021 | int ret = init_ring_common(ring); |
9c33baa6 KZ |
1022 | if (ret) |
1023 | return ret; | |
a69ffdbf | 1024 | |
61a563a2 AG |
1025 | /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ |
1026 | if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) | |
6b26c86d | 1027 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
1c8c38c5 CW |
1028 | |
1029 | /* We need to disable the AsyncFlip performance optimisations in order | |
1030 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1031 | * programmed to '1' on all products. | |
8693a824 | 1032 | * |
b3f797ac | 1033 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv |
1c8c38c5 | 1034 | */ |
fbdcb068 | 1035 | if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 9) |
1c8c38c5 CW |
1036 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); |
1037 | ||
f05bb0c7 | 1038 | /* Required for the hardware to program scanline values for waiting */ |
01fa0302 | 1039 | /* WaEnableFlushTlbInvalidationMode:snb */ |
f05bb0c7 CW |
1040 | if (INTEL_INFO(dev)->gen == 6) |
1041 | I915_WRITE(GFX_MODE, | |
aa83e30d | 1042 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT)); |
f05bb0c7 | 1043 | |
01fa0302 | 1044 | /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */ |
1c8c38c5 CW |
1045 | if (IS_GEN7(dev)) |
1046 | I915_WRITE(GFX_MODE_GEN7, | |
01fa0302 | 1047 | _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) | |
1c8c38c5 | 1048 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); |
78501eac | 1049 | |
5e13a0c5 | 1050 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
1051 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
1052 | * "If this bit is set, STCunit will have LRA as replacement | |
1053 | * policy. [...] This bit must be reset. LRA replacement | |
1054 | * policy is not supported." | |
1055 | */ | |
1056 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 1057 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
84f9f938 BW |
1058 | } |
1059 | ||
6b26c86d DV |
1060 | if (INTEL_INFO(dev)->gen >= 6) |
1061 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 1062 | |
040d2baa | 1063 | if (HAS_L3_DPF(dev)) |
35a85ac6 | 1064 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e | 1065 | |
7225342a | 1066 | return init_workarounds_ring(ring); |
8187a2b7 ZN |
1067 | } |
1068 | ||
a4872ba6 | 1069 | static void render_ring_cleanup(struct intel_engine_cs *ring) |
c6df541c | 1070 | { |
b45305fc | 1071 | struct drm_device *dev = ring->dev; |
3e78998a BW |
1072 | struct drm_i915_private *dev_priv = dev->dev_private; |
1073 | ||
1074 | if (dev_priv->semaphore_obj) { | |
1075 | i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj); | |
1076 | drm_gem_object_unreference(&dev_priv->semaphore_obj->base); | |
1077 | dev_priv->semaphore_obj = NULL; | |
1078 | } | |
b45305fc | 1079 | |
9b1136d5 | 1080 | intel_fini_pipe_control(ring); |
c6df541c CW |
1081 | } |
1082 | ||
3e78998a BW |
1083 | static int gen8_rcs_signal(struct intel_engine_cs *signaller, |
1084 | unsigned int num_dwords) | |
1085 | { | |
1086 | #define MBOX_UPDATE_DWORDS 8 | |
1087 | struct drm_device *dev = signaller->dev; | |
1088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1089 | struct intel_engine_cs *waiter; | |
1090 | int i, ret, num_rings; | |
1091 | ||
1092 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1093 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1094 | #undef MBOX_UPDATE_DWORDS | |
1095 | ||
1096 | ret = intel_ring_begin(signaller, num_dwords); | |
1097 | if (ret) | |
1098 | return ret; | |
1099 | ||
1100 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 1101 | u32 seqno; |
3e78998a BW |
1102 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
1103 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
1104 | continue; | |
1105 | ||
6259cead JH |
1106 | seqno = i915_gem_request_get_seqno( |
1107 | signaller->outstanding_lazy_request); | |
3e78998a BW |
1108 | intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); |
1109 | intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1110 | PIPE_CONTROL_QW_WRITE | | |
1111 | PIPE_CONTROL_FLUSH_ENABLE); | |
1112 | intel_ring_emit(signaller, lower_32_bits(gtt_offset)); | |
1113 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1114 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1115 | intel_ring_emit(signaller, 0); |
1116 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | | |
1117 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1118 | intel_ring_emit(signaller, 0); | |
1119 | } | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
1124 | static int gen8_xcs_signal(struct intel_engine_cs *signaller, | |
1125 | unsigned int num_dwords) | |
1126 | { | |
1127 | #define MBOX_UPDATE_DWORDS 6 | |
1128 | struct drm_device *dev = signaller->dev; | |
1129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1130 | struct intel_engine_cs *waiter; | |
1131 | int i, ret, num_rings; | |
1132 | ||
1133 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1134 | num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS; | |
1135 | #undef MBOX_UPDATE_DWORDS | |
1136 | ||
1137 | ret = intel_ring_begin(signaller, num_dwords); | |
1138 | if (ret) | |
1139 | return ret; | |
1140 | ||
1141 | for_each_ring(waiter, dev_priv, i) { | |
6259cead | 1142 | u32 seqno; |
3e78998a BW |
1143 | u64 gtt_offset = signaller->semaphore.signal_ggtt[i]; |
1144 | if (gtt_offset == MI_SEMAPHORE_SYNC_INVALID) | |
1145 | continue; | |
1146 | ||
6259cead JH |
1147 | seqno = i915_gem_request_get_seqno( |
1148 | signaller->outstanding_lazy_request); | |
3e78998a BW |
1149 | intel_ring_emit(signaller, (MI_FLUSH_DW + 1) | |
1150 | MI_FLUSH_DW_OP_STOREDW); | |
1151 | intel_ring_emit(signaller, lower_32_bits(gtt_offset) | | |
1152 | MI_FLUSH_DW_USE_GTT); | |
1153 | intel_ring_emit(signaller, upper_32_bits(gtt_offset)); | |
6259cead | 1154 | intel_ring_emit(signaller, seqno); |
3e78998a BW |
1155 | intel_ring_emit(signaller, MI_SEMAPHORE_SIGNAL | |
1156 | MI_SEMAPHORE_TARGET(waiter->id)); | |
1157 | intel_ring_emit(signaller, 0); | |
1158 | } | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
a4872ba6 | 1163 | static int gen6_signal(struct intel_engine_cs *signaller, |
024a43e1 | 1164 | unsigned int num_dwords) |
1ec14ad3 | 1165 | { |
024a43e1 BW |
1166 | struct drm_device *dev = signaller->dev; |
1167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 1168 | struct intel_engine_cs *useless; |
a1444b79 | 1169 | int i, ret, num_rings; |
78325f2d | 1170 | |
a1444b79 BW |
1171 | #define MBOX_UPDATE_DWORDS 3 |
1172 | num_rings = hweight32(INTEL_INFO(dev)->ring_mask); | |
1173 | num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2); | |
1174 | #undef MBOX_UPDATE_DWORDS | |
024a43e1 BW |
1175 | |
1176 | ret = intel_ring_begin(signaller, num_dwords); | |
1177 | if (ret) | |
1178 | return ret; | |
024a43e1 | 1179 | |
78325f2d BW |
1180 | for_each_ring(useless, dev_priv, i) { |
1181 | u32 mbox_reg = signaller->semaphore.mbox.signal[i]; | |
1182 | if (mbox_reg != GEN6_NOSYNC) { | |
6259cead JH |
1183 | u32 seqno = i915_gem_request_get_seqno( |
1184 | signaller->outstanding_lazy_request); | |
78325f2d BW |
1185 | intel_ring_emit(signaller, MI_LOAD_REGISTER_IMM(1)); |
1186 | intel_ring_emit(signaller, mbox_reg); | |
6259cead | 1187 | intel_ring_emit(signaller, seqno); |
78325f2d BW |
1188 | } |
1189 | } | |
024a43e1 | 1190 | |
a1444b79 BW |
1191 | /* If num_dwords was rounded, make sure the tail pointer is correct */ |
1192 | if (num_rings % 2 == 0) | |
1193 | intel_ring_emit(signaller, MI_NOOP); | |
1194 | ||
024a43e1 | 1195 | return 0; |
1ec14ad3 CW |
1196 | } |
1197 | ||
c8c99b0f BW |
1198 | /** |
1199 | * gen6_add_request - Update the semaphore mailbox registers | |
1200 | * | |
1201 | * @ring - ring that is adding a request | |
1202 | * @seqno - return seqno stuck into the ring | |
1203 | * | |
1204 | * Update the mailbox registers in the *other* rings with the current seqno. | |
1205 | * This acts like a signal in the canonical semaphore. | |
1206 | */ | |
1ec14ad3 | 1207 | static int |
a4872ba6 | 1208 | gen6_add_request(struct intel_engine_cs *ring) |
1ec14ad3 | 1209 | { |
024a43e1 | 1210 | int ret; |
52ed2325 | 1211 | |
707d9cf9 BW |
1212 | if (ring->semaphore.signal) |
1213 | ret = ring->semaphore.signal(ring, 4); | |
1214 | else | |
1215 | ret = intel_ring_begin(ring, 4); | |
1216 | ||
1ec14ad3 CW |
1217 | if (ret) |
1218 | return ret; | |
1219 | ||
1ec14ad3 CW |
1220 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1221 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1222 | intel_ring_emit(ring, |
1223 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
1ec14ad3 | 1224 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1225 | __intel_ring_advance(ring); |
1ec14ad3 | 1226 | |
1ec14ad3 CW |
1227 | return 0; |
1228 | } | |
1229 | ||
f72b3435 MK |
1230 | static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev, |
1231 | u32 seqno) | |
1232 | { | |
1233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1234 | return dev_priv->last_seqno < seqno; | |
1235 | } | |
1236 | ||
c8c99b0f BW |
1237 | /** |
1238 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
1239 | * | |
1240 | * @waiter - ring that is waiting | |
1241 | * @signaller - ring which has, or will signal | |
1242 | * @seqno - seqno which the waiter will block on | |
1243 | */ | |
5ee426ca BW |
1244 | |
1245 | static int | |
1246 | gen8_ring_sync(struct intel_engine_cs *waiter, | |
1247 | struct intel_engine_cs *signaller, | |
1248 | u32 seqno) | |
1249 | { | |
1250 | struct drm_i915_private *dev_priv = waiter->dev->dev_private; | |
1251 | int ret; | |
1252 | ||
1253 | ret = intel_ring_begin(waiter, 4); | |
1254 | if (ret) | |
1255 | return ret; | |
1256 | ||
1257 | intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | | |
1258 | MI_SEMAPHORE_GLOBAL_GTT | | |
bae4fcd2 | 1259 | MI_SEMAPHORE_POLL | |
5ee426ca BW |
1260 | MI_SEMAPHORE_SAD_GTE_SDD); |
1261 | intel_ring_emit(waiter, seqno); | |
1262 | intel_ring_emit(waiter, | |
1263 | lower_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1264 | intel_ring_emit(waiter, | |
1265 | upper_32_bits(GEN8_WAIT_OFFSET(waiter, signaller->id))); | |
1266 | intel_ring_advance(waiter); | |
1267 | return 0; | |
1268 | } | |
1269 | ||
c8c99b0f | 1270 | static int |
a4872ba6 OM |
1271 | gen6_ring_sync(struct intel_engine_cs *waiter, |
1272 | struct intel_engine_cs *signaller, | |
686cb5f9 | 1273 | u32 seqno) |
1ec14ad3 | 1274 | { |
c8c99b0f BW |
1275 | u32 dw1 = MI_SEMAPHORE_MBOX | |
1276 | MI_SEMAPHORE_COMPARE | | |
1277 | MI_SEMAPHORE_REGISTER; | |
ebc348b2 BW |
1278 | u32 wait_mbox = signaller->semaphore.mbox.wait[waiter->id]; |
1279 | int ret; | |
1ec14ad3 | 1280 | |
1500f7ea BW |
1281 | /* Throughout all of the GEM code, seqno passed implies our current |
1282 | * seqno is >= the last seqno executed. However for hardware the | |
1283 | * comparison is strictly greater than. | |
1284 | */ | |
1285 | seqno -= 1; | |
1286 | ||
ebc348b2 | 1287 | WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID); |
686cb5f9 | 1288 | |
c8c99b0f | 1289 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
1290 | if (ret) |
1291 | return ret; | |
1292 | ||
f72b3435 MK |
1293 | /* If seqno wrap happened, omit the wait with no-ops */ |
1294 | if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) { | |
ebc348b2 | 1295 | intel_ring_emit(waiter, dw1 | wait_mbox); |
f72b3435 MK |
1296 | intel_ring_emit(waiter, seqno); |
1297 | intel_ring_emit(waiter, 0); | |
1298 | intel_ring_emit(waiter, MI_NOOP); | |
1299 | } else { | |
1300 | intel_ring_emit(waiter, MI_NOOP); | |
1301 | intel_ring_emit(waiter, MI_NOOP); | |
1302 | intel_ring_emit(waiter, MI_NOOP); | |
1303 | intel_ring_emit(waiter, MI_NOOP); | |
1304 | } | |
c8c99b0f | 1305 | intel_ring_advance(waiter); |
1ec14ad3 CW |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | ||
c6df541c CW |
1310 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
1311 | do { \ | |
fcbc34e4 KG |
1312 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
1313 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
1314 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
1315 | intel_ring_emit(ring__, 0); \ | |
1316 | intel_ring_emit(ring__, 0); \ | |
1317 | } while (0) | |
1318 | ||
1319 | static int | |
a4872ba6 | 1320 | pc_render_add_request(struct intel_engine_cs *ring) |
c6df541c | 1321 | { |
18393f63 | 1322 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; |
c6df541c CW |
1323 | int ret; |
1324 | ||
1325 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
1326 | * incoherent with writes to memory, i.e. completely fubar, | |
1327 | * so we need to use PIPE_NOTIFY instead. | |
1328 | * | |
1329 | * However, we also need to workaround the qword write | |
1330 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
1331 | * memory before requesting an interrupt. | |
1332 | */ | |
1333 | ret = intel_ring_begin(ring, 32); | |
1334 | if (ret) | |
1335 | return ret; | |
1336 | ||
fcbc34e4 | 1337 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1338 | PIPE_CONTROL_WRITE_FLUSH | |
1339 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
0d1aacac | 1340 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1341 | intel_ring_emit(ring, |
1342 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c CW |
1343 | intel_ring_emit(ring, 0); |
1344 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
18393f63 | 1345 | scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ |
c6df541c | 1346 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1347 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1348 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1349 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1350 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1351 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1352 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
18393f63 | 1353 | scratch_addr += 2 * CACHELINE_BYTES; |
c6df541c | 1354 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
a71d8d94 | 1355 | |
fcbc34e4 | 1356 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
1357 | PIPE_CONTROL_WRITE_FLUSH | |
1358 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c | 1359 | PIPE_CONTROL_NOTIFY); |
0d1aacac | 1360 | intel_ring_emit(ring, ring->scratch.gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
6259cead JH |
1361 | intel_ring_emit(ring, |
1362 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
c6df541c | 1363 | intel_ring_emit(ring, 0); |
09246732 | 1364 | __intel_ring_advance(ring); |
c6df541c | 1365 | |
c6df541c CW |
1366 | return 0; |
1367 | } | |
1368 | ||
4cd53c0c | 1369 | static u32 |
a4872ba6 | 1370 | gen6_ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
4cd53c0c | 1371 | { |
4cd53c0c DV |
1372 | /* Workaround to force correct ordering between irq and seqno writes on |
1373 | * ivb (and maybe also on snb) by reading from a CS register (like | |
1374 | * ACTHD) before reading the status page. */ | |
50877445 CW |
1375 | if (!lazy_coherency) { |
1376 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1377 | POSTING_READ(RING_ACTHD(ring->mmio_base)); | |
1378 | } | |
1379 | ||
4cd53c0c DV |
1380 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1381 | } | |
1382 | ||
8187a2b7 | 1383 | static u32 |
a4872ba6 | 1384 | ring_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
8187a2b7 | 1385 | { |
1ec14ad3 CW |
1386 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
1387 | } | |
1388 | ||
b70ec5bf | 1389 | static void |
a4872ba6 | 1390 | ring_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf MK |
1391 | { |
1392 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1393 | } | |
1394 | ||
c6df541c | 1395 | static u32 |
a4872ba6 | 1396 | pc_render_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
c6df541c | 1397 | { |
0d1aacac | 1398 | return ring->scratch.cpu_page[0]; |
c6df541c CW |
1399 | } |
1400 | ||
b70ec5bf | 1401 | static void |
a4872ba6 | 1402 | pc_render_set_seqno(struct intel_engine_cs *ring, u32 seqno) |
b70ec5bf | 1403 | { |
0d1aacac | 1404 | ring->scratch.cpu_page[0] = seqno; |
b70ec5bf MK |
1405 | } |
1406 | ||
e48d8634 | 1407 | static bool |
a4872ba6 | 1408 | gen5_ring_get_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1409 | { |
1410 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1411 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1412 | unsigned long flags; |
e48d8634 | 1413 | |
7cd512f1 | 1414 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
e48d8634 DV |
1415 | return false; |
1416 | ||
7338aefa | 1417 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1418 | if (ring->irq_refcount++ == 0) |
480c8033 | 1419 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1420 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1421 | |
1422 | return true; | |
1423 | } | |
1424 | ||
1425 | static void | |
a4872ba6 | 1426 | gen5_ring_put_irq(struct intel_engine_cs *ring) |
e48d8634 DV |
1427 | { |
1428 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1429 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1430 | unsigned long flags; |
e48d8634 | 1431 | |
7338aefa | 1432 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
43eaea13 | 1433 | if (--ring->irq_refcount == 0) |
480c8033 | 1434 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
7338aefa | 1435 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
1436 | } |
1437 | ||
b13c2b96 | 1438 | static bool |
a4872ba6 | 1439 | i9xx_ring_get_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1440 | { |
78501eac | 1441 | struct drm_device *dev = ring->dev; |
4640c4ff | 1442 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1443 | unsigned long flags; |
62fdfeaf | 1444 | |
7cd512f1 | 1445 | if (!intel_irqs_enabled(dev_priv)) |
b13c2b96 CW |
1446 | return false; |
1447 | ||
7338aefa | 1448 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1449 | if (ring->irq_refcount++ == 0) { |
f637fde4 DV |
1450 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1451 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1452 | POSTING_READ(IMR); | |
1453 | } | |
7338aefa | 1454 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
1455 | |
1456 | return true; | |
62fdfeaf EA |
1457 | } |
1458 | ||
8187a2b7 | 1459 | static void |
a4872ba6 | 1460 | i9xx_ring_put_irq(struct intel_engine_cs *ring) |
62fdfeaf | 1461 | { |
78501eac | 1462 | struct drm_device *dev = ring->dev; |
4640c4ff | 1463 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1464 | unsigned long flags; |
62fdfeaf | 1465 | |
7338aefa | 1466 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1467 | if (--ring->irq_refcount == 0) { |
f637fde4 DV |
1468 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1469 | I915_WRITE(IMR, dev_priv->irq_mask); | |
1470 | POSTING_READ(IMR); | |
1471 | } | |
7338aefa | 1472 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
1473 | } |
1474 | ||
c2798b19 | 1475 | static bool |
a4872ba6 | 1476 | i8xx_ring_get_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1477 | { |
1478 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1479 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1480 | unsigned long flags; |
c2798b19 | 1481 | |
7cd512f1 | 1482 | if (!intel_irqs_enabled(dev_priv)) |
c2798b19 CW |
1483 | return false; |
1484 | ||
7338aefa | 1485 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1486 | if (ring->irq_refcount++ == 0) { |
c2798b19 CW |
1487 | dev_priv->irq_mask &= ~ring->irq_enable_mask; |
1488 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1489 | POSTING_READ16(IMR); | |
1490 | } | |
7338aefa | 1491 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1492 | |
1493 | return true; | |
1494 | } | |
1495 | ||
1496 | static void | |
a4872ba6 | 1497 | i8xx_ring_put_irq(struct intel_engine_cs *ring) |
c2798b19 CW |
1498 | { |
1499 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1500 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1501 | unsigned long flags; |
c2798b19 | 1502 | |
7338aefa | 1503 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1504 | if (--ring->irq_refcount == 0) { |
c2798b19 CW |
1505 | dev_priv->irq_mask |= ring->irq_enable_mask; |
1506 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
1507 | POSTING_READ16(IMR); | |
1508 | } | |
7338aefa | 1509 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
1510 | } |
1511 | ||
b72f3acb | 1512 | static int |
a4872ba6 | 1513 | bsd_ring_flush(struct intel_engine_cs *ring, |
78501eac CW |
1514 | u32 invalidate_domains, |
1515 | u32 flush_domains) | |
d1b851fc | 1516 | { |
b72f3acb CW |
1517 | int ret; |
1518 | ||
b72f3acb CW |
1519 | ret = intel_ring_begin(ring, 2); |
1520 | if (ret) | |
1521 | return ret; | |
1522 | ||
1523 | intel_ring_emit(ring, MI_FLUSH); | |
1524 | intel_ring_emit(ring, MI_NOOP); | |
1525 | intel_ring_advance(ring); | |
1526 | return 0; | |
d1b851fc ZN |
1527 | } |
1528 | ||
3cce469c | 1529 | static int |
a4872ba6 | 1530 | i9xx_add_request(struct intel_engine_cs *ring) |
d1b851fc | 1531 | { |
3cce469c CW |
1532 | int ret; |
1533 | ||
1534 | ret = intel_ring_begin(ring, 4); | |
1535 | if (ret) | |
1536 | return ret; | |
6f392d54 | 1537 | |
3cce469c CW |
1538 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
1539 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
6259cead JH |
1540 | intel_ring_emit(ring, |
1541 | i915_gem_request_get_seqno(ring->outstanding_lazy_request)); | |
3cce469c | 1542 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
09246732 | 1543 | __intel_ring_advance(ring); |
d1b851fc | 1544 | |
3cce469c | 1545 | return 0; |
d1b851fc ZN |
1546 | } |
1547 | ||
0f46832f | 1548 | static bool |
a4872ba6 | 1549 | gen6_ring_get_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1550 | { |
1551 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1552 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1553 | unsigned long flags; |
0f46832f | 1554 | |
7cd512f1 DV |
1555 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
1556 | return false; | |
0f46832f | 1557 | |
7338aefa | 1558 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1559 | if (ring->irq_refcount++ == 0) { |
040d2baa | 1560 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
cc609d5d BW |
1561 | I915_WRITE_IMR(ring, |
1562 | ~(ring->irq_enable_mask | | |
35a85ac6 | 1563 | GT_PARITY_ERROR(dev))); |
15b9f80e BW |
1564 | else |
1565 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
480c8033 | 1566 | gen5_enable_gt_irq(dev_priv, ring->irq_enable_mask); |
0f46832f | 1567 | } |
7338aefa | 1568 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
1569 | |
1570 | return true; | |
1571 | } | |
1572 | ||
1573 | static void | |
a4872ba6 | 1574 | gen6_ring_put_irq(struct intel_engine_cs *ring) |
0f46832f CW |
1575 | { |
1576 | struct drm_device *dev = ring->dev; | |
4640c4ff | 1577 | struct drm_i915_private *dev_priv = dev->dev_private; |
7338aefa | 1578 | unsigned long flags; |
0f46832f | 1579 | |
7338aefa | 1580 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1581 | if (--ring->irq_refcount == 0) { |
040d2baa | 1582 | if (HAS_L3_DPF(dev) && ring->id == RCS) |
35a85ac6 | 1583 | I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); |
15b9f80e BW |
1584 | else |
1585 | I915_WRITE_IMR(ring, ~0); | |
480c8033 | 1586 | gen5_disable_gt_irq(dev_priv, ring->irq_enable_mask); |
1ec14ad3 | 1587 | } |
7338aefa | 1588 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
d1b851fc ZN |
1589 | } |
1590 | ||
a19d2933 | 1591 | static bool |
a4872ba6 | 1592 | hsw_vebox_get_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1593 | { |
1594 | struct drm_device *dev = ring->dev; | |
1595 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1596 | unsigned long flags; | |
1597 | ||
7cd512f1 | 1598 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
a19d2933 BW |
1599 | return false; |
1600 | ||
59cdb63d | 1601 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1602 | if (ring->irq_refcount++ == 0) { |
a19d2933 | 1603 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
480c8033 | 1604 | gen6_enable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1605 | } |
59cdb63d | 1606 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1607 | |
1608 | return true; | |
1609 | } | |
1610 | ||
1611 | static void | |
a4872ba6 | 1612 | hsw_vebox_put_irq(struct intel_engine_cs *ring) |
a19d2933 BW |
1613 | { |
1614 | struct drm_device *dev = ring->dev; | |
1615 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1616 | unsigned long flags; | |
1617 | ||
59cdb63d | 1618 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c7113cc3 | 1619 | if (--ring->irq_refcount == 0) { |
a19d2933 | 1620 | I915_WRITE_IMR(ring, ~0); |
480c8033 | 1621 | gen6_disable_pm_irq(dev_priv, ring->irq_enable_mask); |
a19d2933 | 1622 | } |
59cdb63d | 1623 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
a19d2933 BW |
1624 | } |
1625 | ||
abd58f01 | 1626 | static bool |
a4872ba6 | 1627 | gen8_ring_get_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1628 | { |
1629 | struct drm_device *dev = ring->dev; | |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1631 | unsigned long flags; | |
1632 | ||
7cd512f1 | 1633 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
abd58f01 BW |
1634 | return false; |
1635 | ||
1636 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1637 | if (ring->irq_refcount++ == 0) { | |
1638 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1639 | I915_WRITE_IMR(ring, | |
1640 | ~(ring->irq_enable_mask | | |
1641 | GT_RENDER_L3_PARITY_ERROR_INTERRUPT)); | |
1642 | } else { | |
1643 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
1644 | } | |
1645 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1646 | } | |
1647 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1648 | ||
1649 | return true; | |
1650 | } | |
1651 | ||
1652 | static void | |
a4872ba6 | 1653 | gen8_ring_put_irq(struct intel_engine_cs *ring) |
abd58f01 BW |
1654 | { |
1655 | struct drm_device *dev = ring->dev; | |
1656 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1657 | unsigned long flags; | |
1658 | ||
1659 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1660 | if (--ring->irq_refcount == 0) { | |
1661 | if (HAS_L3_DPF(dev) && ring->id == RCS) { | |
1662 | I915_WRITE_IMR(ring, | |
1663 | ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT); | |
1664 | } else { | |
1665 | I915_WRITE_IMR(ring, ~0); | |
1666 | } | |
1667 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1668 | } | |
1669 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1670 | } | |
1671 | ||
d1b851fc | 1672 | static int |
a4872ba6 | 1673 | i965_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1674 | u64 offset, u32 length, |
d7d4eedd | 1675 | unsigned flags) |
d1b851fc | 1676 | { |
e1f99ce6 | 1677 | int ret; |
78501eac | 1678 | |
e1f99ce6 CW |
1679 | ret = intel_ring_begin(ring, 2); |
1680 | if (ret) | |
1681 | return ret; | |
1682 | ||
78501eac | 1683 | intel_ring_emit(ring, |
65f56876 CW |
1684 | MI_BATCH_BUFFER_START | |
1685 | MI_BATCH_GTT | | |
d7d4eedd | 1686 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); |
c4e7a414 | 1687 | intel_ring_emit(ring, offset); |
78501eac CW |
1688 | intel_ring_advance(ring); |
1689 | ||
d1b851fc ZN |
1690 | return 0; |
1691 | } | |
1692 | ||
b45305fc DV |
1693 | /* Just userspace ABI convention to limit the wa batch bo to a resonable size */ |
1694 | #define I830_BATCH_LIMIT (256*1024) | |
c4d69da1 CW |
1695 | #define I830_TLB_ENTRIES (2) |
1696 | #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT) | |
8187a2b7 | 1697 | static int |
a4872ba6 | 1698 | i830_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1699 | u64 offset, u32 len, |
d7d4eedd | 1700 | unsigned flags) |
62fdfeaf | 1701 | { |
c4d69da1 | 1702 | u32 cs_offset = ring->scratch.gtt_offset; |
c4e7a414 | 1703 | int ret; |
62fdfeaf | 1704 | |
c4d69da1 CW |
1705 | ret = intel_ring_begin(ring, 6); |
1706 | if (ret) | |
1707 | return ret; | |
62fdfeaf | 1708 | |
c4d69da1 CW |
1709 | /* Evict the invalid PTE TLBs */ |
1710 | intel_ring_emit(ring, COLOR_BLT_CMD | BLT_WRITE_RGBA); | |
1711 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096); | |
1712 | intel_ring_emit(ring, I830_TLB_ENTRIES << 16 | 4); /* load each page */ | |
1713 | intel_ring_emit(ring, cs_offset); | |
1714 | intel_ring_emit(ring, 0xdeadbeef); | |
1715 | intel_ring_emit(ring, MI_NOOP); | |
1716 | intel_ring_advance(ring); | |
b45305fc | 1717 | |
c4d69da1 | 1718 | if ((flags & I915_DISPATCH_PINNED) == 0) { |
b45305fc DV |
1719 | if (len > I830_BATCH_LIMIT) |
1720 | return -ENOSPC; | |
1721 | ||
c4d69da1 | 1722 | ret = intel_ring_begin(ring, 6 + 2); |
b45305fc DV |
1723 | if (ret) |
1724 | return ret; | |
c4d69da1 CW |
1725 | |
1726 | /* Blit the batch (which has now all relocs applied) to the | |
1727 | * stable batch scratch bo area (so that the CS never | |
1728 | * stumbles over its tlb invalidation bug) ... | |
1729 | */ | |
1730 | intel_ring_emit(ring, SRC_COPY_BLT_CMD | BLT_WRITE_RGBA); | |
1731 | intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096); | |
611a7a4f | 1732 | intel_ring_emit(ring, DIV_ROUND_UP(len, 4096) << 16 | 4096); |
b45305fc | 1733 | intel_ring_emit(ring, cs_offset); |
b45305fc DV |
1734 | intel_ring_emit(ring, 4096); |
1735 | intel_ring_emit(ring, offset); | |
c4d69da1 | 1736 | |
b45305fc | 1737 | intel_ring_emit(ring, MI_FLUSH); |
c4d69da1 CW |
1738 | intel_ring_emit(ring, MI_NOOP); |
1739 | intel_ring_advance(ring); | |
b45305fc DV |
1740 | |
1741 | /* ... and execute it. */ | |
c4d69da1 | 1742 | offset = cs_offset; |
b45305fc | 1743 | } |
e1f99ce6 | 1744 | |
c4d69da1 CW |
1745 | ret = intel_ring_begin(ring, 4); |
1746 | if (ret) | |
1747 | return ret; | |
1748 | ||
1749 | intel_ring_emit(ring, MI_BATCH_BUFFER); | |
1750 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); | |
1751 | intel_ring_emit(ring, offset + len - 8); | |
1752 | intel_ring_emit(ring, MI_NOOP); | |
1753 | intel_ring_advance(ring); | |
1754 | ||
fb3256da DV |
1755 | return 0; |
1756 | } | |
1757 | ||
1758 | static int | |
a4872ba6 | 1759 | i915_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 1760 | u64 offset, u32 len, |
d7d4eedd | 1761 | unsigned flags) |
fb3256da DV |
1762 | { |
1763 | int ret; | |
1764 | ||
1765 | ret = intel_ring_begin(ring, 2); | |
1766 | if (ret) | |
1767 | return ret; | |
1768 | ||
65f56876 | 1769 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
d7d4eedd | 1770 | intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); |
c4e7a414 | 1771 | intel_ring_advance(ring); |
62fdfeaf | 1772 | |
62fdfeaf EA |
1773 | return 0; |
1774 | } | |
1775 | ||
a4872ba6 | 1776 | static void cleanup_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1777 | { |
05394f39 | 1778 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1779 | |
8187a2b7 ZN |
1780 | obj = ring->status_page.obj; |
1781 | if (obj == NULL) | |
62fdfeaf | 1782 | return; |
62fdfeaf | 1783 | |
9da3da66 | 1784 | kunmap(sg_page(obj->pages->sgl)); |
d7f46fc4 | 1785 | i915_gem_object_ggtt_unpin(obj); |
05394f39 | 1786 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 1787 | ring->status_page.obj = NULL; |
62fdfeaf EA |
1788 | } |
1789 | ||
a4872ba6 | 1790 | static int init_status_page(struct intel_engine_cs *ring) |
62fdfeaf | 1791 | { |
05394f39 | 1792 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1793 | |
e3efda49 | 1794 | if ((obj = ring->status_page.obj) == NULL) { |
1f767e02 | 1795 | unsigned flags; |
e3efda49 | 1796 | int ret; |
e4ffd173 | 1797 | |
e3efda49 CW |
1798 | obj = i915_gem_alloc_object(ring->dev, 4096); |
1799 | if (obj == NULL) { | |
1800 | DRM_ERROR("Failed to allocate status page\n"); | |
1801 | return -ENOMEM; | |
1802 | } | |
62fdfeaf | 1803 | |
e3efda49 CW |
1804 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
1805 | if (ret) | |
1806 | goto err_unref; | |
1807 | ||
1f767e02 CW |
1808 | flags = 0; |
1809 | if (!HAS_LLC(ring->dev)) | |
1810 | /* On g33, we cannot place HWS above 256MiB, so | |
1811 | * restrict its pinning to the low mappable arena. | |
1812 | * Though this restriction is not documented for | |
1813 | * gen4, gen5, or byt, they also behave similarly | |
1814 | * and hang if the HWS is placed at the top of the | |
1815 | * GTT. To generalise, it appears that all !llc | |
1816 | * platforms have issues with us placing the HWS | |
1817 | * above the mappable region (even though we never | |
1818 | * actualy map it). | |
1819 | */ | |
1820 | flags |= PIN_MAPPABLE; | |
1821 | ret = i915_gem_obj_ggtt_pin(obj, 4096, flags); | |
e3efda49 CW |
1822 | if (ret) { |
1823 | err_unref: | |
1824 | drm_gem_object_unreference(&obj->base); | |
1825 | return ret; | |
1826 | } | |
1827 | ||
1828 | ring->status_page.obj = obj; | |
1829 | } | |
62fdfeaf | 1830 | |
f343c5f6 | 1831 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(obj); |
9da3da66 | 1832 | ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl)); |
8187a2b7 | 1833 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
62fdfeaf | 1834 | |
8187a2b7 ZN |
1835 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
1836 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
1837 | |
1838 | return 0; | |
62fdfeaf EA |
1839 | } |
1840 | ||
a4872ba6 | 1841 | static int init_phys_status_page(struct intel_engine_cs *ring) |
6b8294a4 CW |
1842 | { |
1843 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
6b8294a4 CW |
1844 | |
1845 | if (!dev_priv->status_page_dmah) { | |
1846 | dev_priv->status_page_dmah = | |
1847 | drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE); | |
1848 | if (!dev_priv->status_page_dmah) | |
1849 | return -ENOMEM; | |
1850 | } | |
1851 | ||
6b8294a4 CW |
1852 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1853 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | ||
7ba717cf | 1858 | void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf) |
2919d291 | 1859 | { |
2919d291 | 1860 | iounmap(ringbuf->virtual_start); |
7ba717cf | 1861 | ringbuf->virtual_start = NULL; |
2919d291 | 1862 | i915_gem_object_ggtt_unpin(ringbuf->obj); |
7ba717cf TD |
1863 | } |
1864 | ||
1865 | int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev, | |
1866 | struct intel_ringbuffer *ringbuf) | |
1867 | { | |
1868 | struct drm_i915_private *dev_priv = to_i915(dev); | |
1869 | struct drm_i915_gem_object *obj = ringbuf->obj; | |
1870 | int ret; | |
1871 | ||
1872 | ret = i915_gem_obj_ggtt_pin(obj, PAGE_SIZE, PIN_MAPPABLE); | |
1873 | if (ret) | |
1874 | return ret; | |
1875 | ||
1876 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1877 | if (ret) { | |
1878 | i915_gem_object_ggtt_unpin(obj); | |
1879 | return ret; | |
1880 | } | |
1881 | ||
1882 | ringbuf->virtual_start = ioremap_wc(dev_priv->gtt.mappable_base + | |
1883 | i915_gem_obj_ggtt_offset(obj), ringbuf->size); | |
1884 | if (ringbuf->virtual_start == NULL) { | |
1885 | i915_gem_object_ggtt_unpin(obj); | |
1886 | return -EINVAL; | |
1887 | } | |
1888 | ||
1889 | return 0; | |
1890 | } | |
1891 | ||
1892 | void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf) | |
1893 | { | |
2919d291 OM |
1894 | drm_gem_object_unreference(&ringbuf->obj->base); |
1895 | ringbuf->obj = NULL; | |
1896 | } | |
1897 | ||
84c2377f OM |
1898 | int intel_alloc_ringbuffer_obj(struct drm_device *dev, |
1899 | struct intel_ringbuffer *ringbuf) | |
62fdfeaf | 1900 | { |
05394f39 | 1901 | struct drm_i915_gem_object *obj; |
62fdfeaf | 1902 | |
ebc052e0 CW |
1903 | obj = NULL; |
1904 | if (!HAS_LLC(dev)) | |
93b0a4e0 | 1905 | obj = i915_gem_object_create_stolen(dev, ringbuf->size); |
ebc052e0 | 1906 | if (obj == NULL) |
93b0a4e0 | 1907 | obj = i915_gem_alloc_object(dev, ringbuf->size); |
e3efda49 CW |
1908 | if (obj == NULL) |
1909 | return -ENOMEM; | |
8187a2b7 | 1910 | |
24f3a8cf AG |
1911 | /* mark ring buffers as read-only from GPU side by default */ |
1912 | obj->gt_ro = 1; | |
1913 | ||
93b0a4e0 | 1914 | ringbuf->obj = obj; |
e3efda49 | 1915 | |
7ba717cf | 1916 | return 0; |
e3efda49 CW |
1917 | } |
1918 | ||
1919 | static int intel_init_ring_buffer(struct drm_device *dev, | |
a4872ba6 | 1920 | struct intel_engine_cs *ring) |
e3efda49 | 1921 | { |
bfc882b4 | 1922 | struct intel_ringbuffer *ringbuf; |
e3efda49 CW |
1923 | int ret; |
1924 | ||
bfc882b4 DV |
1925 | WARN_ON(ring->buffer); |
1926 | ||
1927 | ringbuf = kzalloc(sizeof(*ringbuf), GFP_KERNEL); | |
1928 | if (!ringbuf) | |
1929 | return -ENOMEM; | |
1930 | ring->buffer = ringbuf; | |
8ee14975 | 1931 | |
e3efda49 CW |
1932 | ring->dev = dev; |
1933 | INIT_LIST_HEAD(&ring->active_list); | |
1934 | INIT_LIST_HEAD(&ring->request_list); | |
cc9130be | 1935 | INIT_LIST_HEAD(&ring->execlist_queue); |
93b0a4e0 | 1936 | ringbuf->size = 32 * PAGE_SIZE; |
0c7dd53b | 1937 | ringbuf->ring = ring; |
ebc348b2 | 1938 | memset(ring->semaphore.sync_seqno, 0, sizeof(ring->semaphore.sync_seqno)); |
e3efda49 CW |
1939 | |
1940 | init_waitqueue_head(&ring->irq_queue); | |
1941 | ||
1942 | if (I915_NEED_GFX_HWS(dev)) { | |
1943 | ret = init_status_page(ring); | |
1944 | if (ret) | |
8ee14975 | 1945 | goto error; |
e3efda49 CW |
1946 | } else { |
1947 | BUG_ON(ring->id != RCS); | |
1948 | ret = init_phys_status_page(ring); | |
1949 | if (ret) | |
8ee14975 | 1950 | goto error; |
e3efda49 CW |
1951 | } |
1952 | ||
bfc882b4 | 1953 | WARN_ON(ringbuf->obj); |
7ba717cf | 1954 | |
bfc882b4 DV |
1955 | ret = intel_alloc_ringbuffer_obj(dev, ringbuf); |
1956 | if (ret) { | |
1957 | DRM_ERROR("Failed to allocate ringbuffer %s: %d\n", | |
1958 | ring->name, ret); | |
1959 | goto error; | |
1960 | } | |
1961 | ||
1962 | ret = intel_pin_and_map_ringbuffer_obj(dev, ringbuf); | |
1963 | if (ret) { | |
1964 | DRM_ERROR("Failed to pin and map ringbuffer %s: %d\n", | |
1965 | ring->name, ret); | |
1966 | intel_destroy_ringbuffer_obj(ringbuf); | |
1967 | goto error; | |
e3efda49 | 1968 | } |
62fdfeaf | 1969 | |
55249baa CW |
1970 | /* Workaround an erratum on the i830 which causes a hang if |
1971 | * the TAIL pointer points to within the last 2 cachelines | |
1972 | * of the buffer. | |
1973 | */ | |
93b0a4e0 | 1974 | ringbuf->effective_size = ringbuf->size; |
e3efda49 | 1975 | if (IS_I830(dev) || IS_845G(dev)) |
93b0a4e0 | 1976 | ringbuf->effective_size -= 2 * CACHELINE_BYTES; |
55249baa | 1977 | |
44e895a8 BV |
1978 | ret = i915_cmd_parser_init_ring(ring); |
1979 | if (ret) | |
8ee14975 OM |
1980 | goto error; |
1981 | ||
8ee14975 | 1982 | return 0; |
351e3db2 | 1983 | |
8ee14975 OM |
1984 | error: |
1985 | kfree(ringbuf); | |
1986 | ring->buffer = NULL; | |
1987 | return ret; | |
62fdfeaf EA |
1988 | } |
1989 | ||
a4872ba6 | 1990 | void intel_cleanup_ring_buffer(struct intel_engine_cs *ring) |
62fdfeaf | 1991 | { |
6402c330 JH |
1992 | struct drm_i915_private *dev_priv; |
1993 | struct intel_ringbuffer *ringbuf; | |
33626e6a | 1994 | |
93b0a4e0 | 1995 | if (!intel_ring_initialized(ring)) |
62fdfeaf EA |
1996 | return; |
1997 | ||
6402c330 JH |
1998 | dev_priv = to_i915(ring->dev); |
1999 | ringbuf = ring->buffer; | |
2000 | ||
e3efda49 | 2001 | intel_stop_ring_buffer(ring); |
de8f0a50 | 2002 | WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0); |
33626e6a | 2003 | |
7ba717cf | 2004 | intel_unpin_ringbuffer_obj(ringbuf); |
2919d291 | 2005 | intel_destroy_ringbuffer_obj(ringbuf); |
6259cead | 2006 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); |
78501eac | 2007 | |
8d19215b ZN |
2008 | if (ring->cleanup) |
2009 | ring->cleanup(ring); | |
2010 | ||
78501eac | 2011 | cleanup_status_page(ring); |
44e895a8 BV |
2012 | |
2013 | i915_cmd_parser_fini_ring(ring); | |
8ee14975 | 2014 | |
93b0a4e0 | 2015 | kfree(ringbuf); |
8ee14975 | 2016 | ring->buffer = NULL; |
62fdfeaf EA |
2017 | } |
2018 | ||
a4872ba6 | 2019 | static int intel_ring_wait_request(struct intel_engine_cs *ring, int n) |
a71d8d94 | 2020 | { |
93b0a4e0 | 2021 | struct intel_ringbuffer *ringbuf = ring->buffer; |
a71d8d94 | 2022 | struct drm_i915_gem_request *request; |
a71d8d94 CW |
2023 | int ret; |
2024 | ||
ebd0fd4b DG |
2025 | if (intel_ring_space(ringbuf) >= n) |
2026 | return 0; | |
a71d8d94 CW |
2027 | |
2028 | list_for_each_entry(request, &ring->request_list, list) { | |
72f95afa | 2029 | if (__intel_ring_space(request->postfix, ringbuf->tail, |
82e104cc | 2030 | ringbuf->size) >= n) { |
a71d8d94 CW |
2031 | break; |
2032 | } | |
a71d8d94 CW |
2033 | } |
2034 | ||
a4b3a571 | 2035 | if (&request->list == &ring->request_list) |
a71d8d94 CW |
2036 | return -ENOSPC; |
2037 | ||
a4b3a571 | 2038 | ret = i915_wait_request(request); |
a71d8d94 CW |
2039 | if (ret) |
2040 | return ret; | |
2041 | ||
1cf0ba14 | 2042 | i915_gem_retire_requests_ring(ring); |
a71d8d94 CW |
2043 | |
2044 | return 0; | |
2045 | } | |
2046 | ||
a4872ba6 | 2047 | static int ring_wait_for_space(struct intel_engine_cs *ring, int n) |
62fdfeaf | 2048 | { |
78501eac | 2049 | struct drm_device *dev = ring->dev; |
cae5852d | 2050 | struct drm_i915_private *dev_priv = dev->dev_private; |
93b0a4e0 | 2051 | struct intel_ringbuffer *ringbuf = ring->buffer; |
78501eac | 2052 | unsigned long end; |
a71d8d94 | 2053 | int ret; |
c7dca47b | 2054 | |
a71d8d94 CW |
2055 | ret = intel_ring_wait_request(ring, n); |
2056 | if (ret != -ENOSPC) | |
2057 | return ret; | |
2058 | ||
09246732 CW |
2059 | /* force the tail write in case we have been skipping them */ |
2060 | __intel_ring_advance(ring); | |
2061 | ||
63ed2cb2 DV |
2062 | /* With GEM the hangcheck timer should kick us out of the loop, |
2063 | * leaving it early runs the risk of corrupting GEM state (due | |
2064 | * to running on almost untested codepaths). But on resume | |
2065 | * timers don't work yet, so prevent a complete hang in that | |
2066 | * case by choosing an insanely large timeout. */ | |
2067 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 2068 | |
ebd0fd4b | 2069 | ret = 0; |
dcfe0506 | 2070 | trace_i915_ring_wait_begin(ring); |
8187a2b7 | 2071 | do { |
ebd0fd4b DG |
2072 | if (intel_ring_space(ringbuf) >= n) |
2073 | break; | |
93b0a4e0 | 2074 | ringbuf->head = I915_READ_HEAD(ring); |
ebd0fd4b | 2075 | if (intel_ring_space(ringbuf) >= n) |
dcfe0506 | 2076 | break; |
62fdfeaf | 2077 | |
e60a0b10 | 2078 | msleep(1); |
d6b2c790 | 2079 | |
dcfe0506 CW |
2080 | if (dev_priv->mm.interruptible && signal_pending(current)) { |
2081 | ret = -ERESTARTSYS; | |
2082 | break; | |
2083 | } | |
2084 | ||
33196ded DV |
2085 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2086 | dev_priv->mm.interruptible); | |
d6b2c790 | 2087 | if (ret) |
dcfe0506 CW |
2088 | break; |
2089 | ||
2090 | if (time_after(jiffies, end)) { | |
2091 | ret = -EBUSY; | |
2092 | break; | |
2093 | } | |
2094 | } while (1); | |
db53a302 | 2095 | trace_i915_ring_wait_end(ring); |
dcfe0506 | 2096 | return ret; |
8187a2b7 | 2097 | } |
62fdfeaf | 2098 | |
a4872ba6 | 2099 | static int intel_wrap_ring_buffer(struct intel_engine_cs *ring) |
3e960501 CW |
2100 | { |
2101 | uint32_t __iomem *virt; | |
93b0a4e0 OM |
2102 | struct intel_ringbuffer *ringbuf = ring->buffer; |
2103 | int rem = ringbuf->size - ringbuf->tail; | |
3e960501 | 2104 | |
93b0a4e0 | 2105 | if (ringbuf->space < rem) { |
3e960501 CW |
2106 | int ret = ring_wait_for_space(ring, rem); |
2107 | if (ret) | |
2108 | return ret; | |
2109 | } | |
2110 | ||
93b0a4e0 | 2111 | virt = ringbuf->virtual_start + ringbuf->tail; |
3e960501 CW |
2112 | rem /= 4; |
2113 | while (rem--) | |
2114 | iowrite32(MI_NOOP, virt++); | |
2115 | ||
93b0a4e0 | 2116 | ringbuf->tail = 0; |
ebd0fd4b | 2117 | intel_ring_update_space(ringbuf); |
3e960501 CW |
2118 | |
2119 | return 0; | |
2120 | } | |
2121 | ||
a4872ba6 | 2122 | int intel_ring_idle(struct intel_engine_cs *ring) |
3e960501 | 2123 | { |
a4b3a571 | 2124 | struct drm_i915_gem_request *req; |
3e960501 CW |
2125 | int ret; |
2126 | ||
2127 | /* We need to add any requests required to flush the objects and ring */ | |
6259cead | 2128 | if (ring->outstanding_lazy_request) { |
9400ae5c | 2129 | ret = i915_add_request(ring); |
3e960501 CW |
2130 | if (ret) |
2131 | return ret; | |
2132 | } | |
2133 | ||
2134 | /* Wait upon the last request to be completed */ | |
2135 | if (list_empty(&ring->request_list)) | |
2136 | return 0; | |
2137 | ||
a4b3a571 | 2138 | req = list_entry(ring->request_list.prev, |
3e960501 | 2139 | struct drm_i915_gem_request, |
a4b3a571 | 2140 | list); |
3e960501 | 2141 | |
a4b3a571 | 2142 | return i915_wait_request(req); |
3e960501 CW |
2143 | } |
2144 | ||
9d773091 | 2145 | static int |
6259cead | 2146 | intel_ring_alloc_request(struct intel_engine_cs *ring) |
9d773091 | 2147 | { |
9eba5d4a JH |
2148 | int ret; |
2149 | struct drm_i915_gem_request *request; | |
67e2937b | 2150 | struct drm_i915_private *dev_private = ring->dev->dev_private; |
9eba5d4a | 2151 | |
6259cead | 2152 | if (ring->outstanding_lazy_request) |
9d773091 | 2153 | return 0; |
3c0e234c | 2154 | |
aaeb1ba0 | 2155 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
9eba5d4a JH |
2156 | if (request == NULL) |
2157 | return -ENOMEM; | |
3c0e234c | 2158 | |
abfe262a | 2159 | kref_init(&request->ref); |
ff79e857 | 2160 | request->ring = ring; |
67e2937b | 2161 | request->uniq = dev_private->request_uniq++; |
abfe262a | 2162 | |
6259cead | 2163 | ret = i915_gem_get_seqno(ring->dev, &request->seqno); |
9eba5d4a JH |
2164 | if (ret) { |
2165 | kfree(request); | |
2166 | return ret; | |
3c0e234c CW |
2167 | } |
2168 | ||
6259cead | 2169 | ring->outstanding_lazy_request = request; |
9eba5d4a | 2170 | return 0; |
9d773091 CW |
2171 | } |
2172 | ||
a4872ba6 | 2173 | static int __intel_ring_prepare(struct intel_engine_cs *ring, |
304d695c | 2174 | int bytes) |
cbcc80df | 2175 | { |
93b0a4e0 | 2176 | struct intel_ringbuffer *ringbuf = ring->buffer; |
cbcc80df MK |
2177 | int ret; |
2178 | ||
93b0a4e0 | 2179 | if (unlikely(ringbuf->tail + bytes > ringbuf->effective_size)) { |
cbcc80df MK |
2180 | ret = intel_wrap_ring_buffer(ring); |
2181 | if (unlikely(ret)) | |
2182 | return ret; | |
2183 | } | |
2184 | ||
93b0a4e0 | 2185 | if (unlikely(ringbuf->space < bytes)) { |
cbcc80df MK |
2186 | ret = ring_wait_for_space(ring, bytes); |
2187 | if (unlikely(ret)) | |
2188 | return ret; | |
2189 | } | |
2190 | ||
cbcc80df MK |
2191 | return 0; |
2192 | } | |
2193 | ||
a4872ba6 | 2194 | int intel_ring_begin(struct intel_engine_cs *ring, |
e1f99ce6 | 2195 | int num_dwords) |
8187a2b7 | 2196 | { |
4640c4ff | 2197 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
e1f99ce6 | 2198 | int ret; |
78501eac | 2199 | |
33196ded DV |
2200 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
2201 | dev_priv->mm.interruptible); | |
de2b9985 DV |
2202 | if (ret) |
2203 | return ret; | |
21dd3734 | 2204 | |
304d695c CW |
2205 | ret = __intel_ring_prepare(ring, num_dwords * sizeof(uint32_t)); |
2206 | if (ret) | |
2207 | return ret; | |
2208 | ||
9d773091 | 2209 | /* Preallocate the olr before touching the ring */ |
6259cead | 2210 | ret = intel_ring_alloc_request(ring); |
9d773091 CW |
2211 | if (ret) |
2212 | return ret; | |
2213 | ||
ee1b1e5e | 2214 | ring->buffer->space -= num_dwords * sizeof(uint32_t); |
304d695c | 2215 | return 0; |
8187a2b7 | 2216 | } |
78501eac | 2217 | |
753b1ad4 | 2218 | /* Align the ring tail to a cacheline boundary */ |
a4872ba6 | 2219 | int intel_ring_cacheline_align(struct intel_engine_cs *ring) |
753b1ad4 | 2220 | { |
ee1b1e5e | 2221 | int num_dwords = (ring->buffer->tail & (CACHELINE_BYTES - 1)) / sizeof(uint32_t); |
753b1ad4 VS |
2222 | int ret; |
2223 | ||
2224 | if (num_dwords == 0) | |
2225 | return 0; | |
2226 | ||
18393f63 | 2227 | num_dwords = CACHELINE_BYTES / sizeof(uint32_t) - num_dwords; |
753b1ad4 VS |
2228 | ret = intel_ring_begin(ring, num_dwords); |
2229 | if (ret) | |
2230 | return ret; | |
2231 | ||
2232 | while (num_dwords--) | |
2233 | intel_ring_emit(ring, MI_NOOP); | |
2234 | ||
2235 | intel_ring_advance(ring); | |
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
a4872ba6 | 2240 | void intel_ring_init_seqno(struct intel_engine_cs *ring, u32 seqno) |
498d2ac1 | 2241 | { |
3b2cc8ab OM |
2242 | struct drm_device *dev = ring->dev; |
2243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
498d2ac1 | 2244 | |
6259cead | 2245 | BUG_ON(ring->outstanding_lazy_request); |
498d2ac1 | 2246 | |
3b2cc8ab | 2247 | if (INTEL_INFO(dev)->gen == 6 || INTEL_INFO(dev)->gen == 7) { |
f7e98ad4 MK |
2248 | I915_WRITE(RING_SYNC_0(ring->mmio_base), 0); |
2249 | I915_WRITE(RING_SYNC_1(ring->mmio_base), 0); | |
3b2cc8ab | 2250 | if (HAS_VEBOX(dev)) |
5020150b | 2251 | I915_WRITE(RING_SYNC_2(ring->mmio_base), 0); |
e1f99ce6 | 2252 | } |
d97ed339 | 2253 | |
f7e98ad4 | 2254 | ring->set_seqno(ring, seqno); |
92cab734 | 2255 | ring->hangcheck.seqno = seqno; |
8187a2b7 | 2256 | } |
62fdfeaf | 2257 | |
a4872ba6 | 2258 | static void gen6_bsd_ring_write_tail(struct intel_engine_cs *ring, |
297b0c5b | 2259 | u32 value) |
881f47b6 | 2260 | { |
4640c4ff | 2261 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
2262 | |
2263 | /* Every tail move must follow the sequence below */ | |
12f55818 CW |
2264 | |
2265 | /* Disable notification that the ring is IDLE. The GT | |
2266 | * will then assume that it is busy and bring it out of rc6. | |
2267 | */ | |
0206e353 | 2268 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 CW |
2269 | _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
2270 | ||
2271 | /* Clear the context id. Here be magic! */ | |
2272 | I915_WRITE64(GEN6_BSD_RNCID, 0x0); | |
0206e353 | 2273 | |
12f55818 | 2274 | /* Wait for the ring not to be idle, i.e. for it to wake up. */ |
0206e353 | 2275 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
12f55818 CW |
2276 | GEN6_BSD_SLEEP_INDICATOR) == 0, |
2277 | 50)) | |
2278 | DRM_ERROR("timed out waiting for the BSD ring to wake up\n"); | |
0206e353 | 2279 | |
12f55818 | 2280 | /* Now that the ring is fully powered up, update the tail */ |
0206e353 | 2281 | I915_WRITE_TAIL(ring, value); |
12f55818 CW |
2282 | POSTING_READ(RING_TAIL(ring->mmio_base)); |
2283 | ||
2284 | /* Let the ring send IDLE messages to the GT again, | |
2285 | * and so let it sleep to conserve power when idle. | |
2286 | */ | |
0206e353 | 2287 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
12f55818 | 2288 | _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE)); |
881f47b6 XH |
2289 | } |
2290 | ||
a4872ba6 | 2291 | static int gen6_bsd_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2292 | u32 invalidate, u32 flush) |
881f47b6 | 2293 | { |
71a77e07 | 2294 | uint32_t cmd; |
b72f3acb CW |
2295 | int ret; |
2296 | ||
b72f3acb CW |
2297 | ret = intel_ring_begin(ring, 4); |
2298 | if (ret) | |
2299 | return ret; | |
2300 | ||
71a77e07 | 2301 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2302 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2303 | cmd += 1; | |
9a289771 JB |
2304 | /* |
2305 | * Bspec vol 1c.5 - video engine command streamer: | |
2306 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2307 | * operation is complete. This bit is only valid when the | |
2308 | * Post-Sync Operation field is a value of 1h or 3h." | |
2309 | */ | |
71a77e07 | 2310 | if (invalidate & I915_GEM_GPU_DOMAINS) |
9a289771 JB |
2311 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | |
2312 | MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
71a77e07 | 2313 | intel_ring_emit(ring, cmd); |
9a289771 | 2314 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2315 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2316 | intel_ring_emit(ring, 0); /* upper addr */ | |
2317 | intel_ring_emit(ring, 0); /* value */ | |
2318 | } else { | |
2319 | intel_ring_emit(ring, 0); | |
2320 | intel_ring_emit(ring, MI_NOOP); | |
2321 | } | |
b72f3acb CW |
2322 | intel_ring_advance(ring); |
2323 | return 0; | |
881f47b6 XH |
2324 | } |
2325 | ||
1c7a0623 | 2326 | static int |
a4872ba6 | 2327 | gen8_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2328 | u64 offset, u32 len, |
1c7a0623 BW |
2329 | unsigned flags) |
2330 | { | |
896ab1a5 | 2331 | bool ppgtt = USES_PPGTT(ring->dev) && !(flags & I915_DISPATCH_SECURE); |
1c7a0623 BW |
2332 | int ret; |
2333 | ||
2334 | ret = intel_ring_begin(ring, 4); | |
2335 | if (ret) | |
2336 | return ret; | |
2337 | ||
2338 | /* FIXME(BDW): Address space and security selectors. */ | |
28cf5415 | 2339 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); |
9bcb144c BW |
2340 | intel_ring_emit(ring, lower_32_bits(offset)); |
2341 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1c7a0623 BW |
2342 | intel_ring_emit(ring, MI_NOOP); |
2343 | intel_ring_advance(ring); | |
2344 | ||
2345 | return 0; | |
2346 | } | |
2347 | ||
d7d4eedd | 2348 | static int |
a4872ba6 | 2349 | hsw_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2350 | u64 offset, u32 len, |
d7d4eedd CW |
2351 | unsigned flags) |
2352 | { | |
2353 | int ret; | |
2354 | ||
2355 | ret = intel_ring_begin(ring, 2); | |
2356 | if (ret) | |
2357 | return ret; | |
2358 | ||
2359 | intel_ring_emit(ring, | |
77072258 CW |
2360 | MI_BATCH_BUFFER_START | |
2361 | (flags & I915_DISPATCH_SECURE ? | |
2362 | 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW)); | |
d7d4eedd CW |
2363 | /* bit0-7 is the length on GEN6+ */ |
2364 | intel_ring_emit(ring, offset); | |
2365 | intel_ring_advance(ring); | |
2366 | ||
2367 | return 0; | |
2368 | } | |
2369 | ||
881f47b6 | 2370 | static int |
a4872ba6 | 2371 | gen6_ring_dispatch_execbuffer(struct intel_engine_cs *ring, |
9bcb144c | 2372 | u64 offset, u32 len, |
d7d4eedd | 2373 | unsigned flags) |
881f47b6 | 2374 | { |
0206e353 | 2375 | int ret; |
ab6f8e32 | 2376 | |
0206e353 AJ |
2377 | ret = intel_ring_begin(ring, 2); |
2378 | if (ret) | |
2379 | return ret; | |
e1f99ce6 | 2380 | |
d7d4eedd CW |
2381 | intel_ring_emit(ring, |
2382 | MI_BATCH_BUFFER_START | | |
2383 | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965)); | |
0206e353 AJ |
2384 | /* bit0-7 is the length on GEN6+ */ |
2385 | intel_ring_emit(ring, offset); | |
2386 | intel_ring_advance(ring); | |
ab6f8e32 | 2387 | |
0206e353 | 2388 | return 0; |
881f47b6 XH |
2389 | } |
2390 | ||
549f7365 CW |
2391 | /* Blitter support (SandyBridge+) */ |
2392 | ||
a4872ba6 | 2393 | static int gen6_ring_flush(struct intel_engine_cs *ring, |
ea251324 | 2394 | u32 invalidate, u32 flush) |
8d19215b | 2395 | { |
fd3da6c9 | 2396 | struct drm_device *dev = ring->dev; |
1d73c2a8 | 2397 | struct drm_i915_private *dev_priv = dev->dev_private; |
71a77e07 | 2398 | uint32_t cmd; |
b72f3acb CW |
2399 | int ret; |
2400 | ||
6a233c78 | 2401 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
2402 | if (ret) |
2403 | return ret; | |
2404 | ||
71a77e07 | 2405 | cmd = MI_FLUSH_DW; |
075b3bba BW |
2406 | if (INTEL_INFO(ring->dev)->gen >= 8) |
2407 | cmd += 1; | |
9a289771 JB |
2408 | /* |
2409 | * Bspec vol 1c.3 - blitter engine command streamer: | |
2410 | * "If ENABLED, all TLBs will be invalidated once the flush | |
2411 | * operation is complete. This bit is only valid when the | |
2412 | * Post-Sync Operation field is a value of 1h or 3h." | |
2413 | */ | |
71a77e07 | 2414 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
9a289771 | 2415 | cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | |
b3fcabb1 | 2416 | MI_FLUSH_DW_OP_STOREDW; |
71a77e07 | 2417 | intel_ring_emit(ring, cmd); |
9a289771 | 2418 | intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); |
075b3bba BW |
2419 | if (INTEL_INFO(ring->dev)->gen >= 8) { |
2420 | intel_ring_emit(ring, 0); /* upper addr */ | |
2421 | intel_ring_emit(ring, 0); /* value */ | |
2422 | } else { | |
2423 | intel_ring_emit(ring, 0); | |
2424 | intel_ring_emit(ring, MI_NOOP); | |
2425 | } | |
b72f3acb | 2426 | intel_ring_advance(ring); |
fd3da6c9 | 2427 | |
1d73c2a8 RV |
2428 | if (!invalidate && flush) { |
2429 | if (IS_GEN7(dev)) | |
2430 | return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); | |
2431 | else if (IS_BROADWELL(dev)) | |
2432 | dev_priv->fbc.need_sw_cache_clean = true; | |
2433 | } | |
fd3da6c9 | 2434 | |
b72f3acb | 2435 | return 0; |
8d19215b ZN |
2436 | } |
2437 | ||
5c1143bb XH |
2438 | int intel_init_render_ring_buffer(struct drm_device *dev) |
2439 | { | |
4640c4ff | 2440 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2441 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e78998a BW |
2442 | struct drm_i915_gem_object *obj; |
2443 | int ret; | |
5c1143bb | 2444 | |
59465b5f DV |
2445 | ring->name = "render ring"; |
2446 | ring->id = RCS; | |
2447 | ring->mmio_base = RENDER_RING_BASE; | |
2448 | ||
707d9cf9 | 2449 | if (INTEL_INFO(dev)->gen >= 8) { |
3e78998a BW |
2450 | if (i915_semaphore_is_enabled(dev)) { |
2451 | obj = i915_gem_alloc_object(dev, 4096); | |
2452 | if (obj == NULL) { | |
2453 | DRM_ERROR("Failed to allocate semaphore bo. Disabling semaphores\n"); | |
2454 | i915.semaphores = 0; | |
2455 | } else { | |
2456 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
2457 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_NONBLOCK); | |
2458 | if (ret != 0) { | |
2459 | drm_gem_object_unreference(&obj->base); | |
2460 | DRM_ERROR("Failed to pin semaphore bo. Disabling semaphores\n"); | |
2461 | i915.semaphores = 0; | |
2462 | } else | |
2463 | dev_priv->semaphore_obj = obj; | |
2464 | } | |
2465 | } | |
7225342a | 2466 | |
8f0e2b9d | 2467 | ring->init_context = intel_rcs_ctx_init; |
707d9cf9 BW |
2468 | ring->add_request = gen6_add_request; |
2469 | ring->flush = gen8_render_ring_flush; | |
2470 | ring->irq_get = gen8_ring_get_irq; | |
2471 | ring->irq_put = gen8_ring_put_irq; | |
2472 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; | |
2473 | ring->get_seqno = gen6_ring_get_seqno; | |
2474 | ring->set_seqno = ring_set_seqno; | |
2475 | if (i915_semaphore_is_enabled(dev)) { | |
3e78998a | 2476 | WARN_ON(!dev_priv->semaphore_obj); |
5ee426ca | 2477 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2478 | ring->semaphore.signal = gen8_rcs_signal; |
2479 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 BW |
2480 | } |
2481 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
1ec14ad3 | 2482 | ring->add_request = gen6_add_request; |
4772eaeb | 2483 | ring->flush = gen7_render_ring_flush; |
6c6cf5aa | 2484 | if (INTEL_INFO(dev)->gen == 6) |
b3111509 | 2485 | ring->flush = gen6_render_ring_flush; |
707d9cf9 BW |
2486 | ring->irq_get = gen6_ring_get_irq; |
2487 | ring->irq_put = gen6_ring_put_irq; | |
cc609d5d | 2488 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT; |
4cd53c0c | 2489 | ring->get_seqno = gen6_ring_get_seqno; |
b70ec5bf | 2490 | ring->set_seqno = ring_set_seqno; |
707d9cf9 BW |
2491 | if (i915_semaphore_is_enabled(dev)) { |
2492 | ring->semaphore.sync_to = gen6_ring_sync; | |
2493 | ring->semaphore.signal = gen6_signal; | |
2494 | /* | |
2495 | * The current semaphore is only applied on pre-gen8 | |
2496 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2497 | * platform. So the semaphore between RCS and VCS2 is | |
2498 | * initialized as INVALID. Gen8 will initialize the | |
2499 | * sema between VCS2 and RCS later. | |
2500 | */ | |
2501 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2502 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_RV; | |
2503 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_RB; | |
2504 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_RVE; | |
2505 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2506 | ring->semaphore.mbox.signal[RCS] = GEN6_NOSYNC; | |
2507 | ring->semaphore.mbox.signal[VCS] = GEN6_VRSYNC; | |
2508 | ring->semaphore.mbox.signal[BCS] = GEN6_BRSYNC; | |
2509 | ring->semaphore.mbox.signal[VECS] = GEN6_VERSYNC; | |
2510 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2511 | } | |
c6df541c CW |
2512 | } else if (IS_GEN5(dev)) { |
2513 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 2514 | ring->flush = gen4_render_ring_flush; |
c6df541c | 2515 | ring->get_seqno = pc_render_get_seqno; |
b70ec5bf | 2516 | ring->set_seqno = pc_render_set_seqno; |
e48d8634 DV |
2517 | ring->irq_get = gen5_ring_get_irq; |
2518 | ring->irq_put = gen5_ring_put_irq; | |
cc609d5d BW |
2519 | ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT | |
2520 | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT; | |
59465b5f | 2521 | } else { |
8620a3a9 | 2522 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
2523 | if (INTEL_INFO(dev)->gen < 4) |
2524 | ring->flush = gen2_render_ring_flush; | |
2525 | else | |
2526 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 2527 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2528 | ring->set_seqno = ring_set_seqno; |
c2798b19 CW |
2529 | if (IS_GEN2(dev)) { |
2530 | ring->irq_get = i8xx_ring_get_irq; | |
2531 | ring->irq_put = i8xx_ring_put_irq; | |
2532 | } else { | |
2533 | ring->irq_get = i9xx_ring_get_irq; | |
2534 | ring->irq_put = i9xx_ring_put_irq; | |
2535 | } | |
e3670319 | 2536 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 2537 | } |
59465b5f | 2538 | ring->write_tail = ring_write_tail; |
707d9cf9 | 2539 | |
d7d4eedd CW |
2540 | if (IS_HASWELL(dev)) |
2541 | ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer; | |
1c7a0623 BW |
2542 | else if (IS_GEN8(dev)) |
2543 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; | |
d7d4eedd | 2544 | else if (INTEL_INFO(dev)->gen >= 6) |
fb3256da DV |
2545 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
2546 | else if (INTEL_INFO(dev)->gen >= 4) | |
2547 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
2548 | else if (IS_I830(dev) || IS_845G(dev)) | |
2549 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
2550 | else | |
2551 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
ecfe00d8 | 2552 | ring->init_hw = init_render_ring; |
59465b5f DV |
2553 | ring->cleanup = render_ring_cleanup; |
2554 | ||
b45305fc DV |
2555 | /* Workaround batchbuffer to combat CS tlb bug. */ |
2556 | if (HAS_BROKEN_CS_TLB(dev)) { | |
c4d69da1 | 2557 | obj = i915_gem_alloc_object(dev, I830_WA_SIZE); |
b45305fc DV |
2558 | if (obj == NULL) { |
2559 | DRM_ERROR("Failed to allocate batch bo\n"); | |
2560 | return -ENOMEM; | |
2561 | } | |
2562 | ||
be1fa129 | 2563 | ret = i915_gem_obj_ggtt_pin(obj, 0, 0); |
b45305fc DV |
2564 | if (ret != 0) { |
2565 | drm_gem_object_unreference(&obj->base); | |
2566 | DRM_ERROR("Failed to ping batch bo\n"); | |
2567 | return ret; | |
2568 | } | |
2569 | ||
0d1aacac CW |
2570 | ring->scratch.obj = obj; |
2571 | ring->scratch.gtt_offset = i915_gem_obj_ggtt_offset(obj); | |
b45305fc DV |
2572 | } |
2573 | ||
99be1dfe DV |
2574 | ret = intel_init_ring_buffer(dev, ring); |
2575 | if (ret) | |
2576 | return ret; | |
2577 | ||
2578 | if (INTEL_INFO(dev)->gen >= 5) { | |
2579 | ret = intel_init_pipe_control(ring); | |
2580 | if (ret) | |
2581 | return ret; | |
2582 | } | |
2583 | ||
2584 | return 0; | |
5c1143bb XH |
2585 | } |
2586 | ||
2587 | int intel_init_bsd_ring_buffer(struct drm_device *dev) | |
2588 | { | |
4640c4ff | 2589 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2590 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; |
5c1143bb | 2591 | |
58fa3835 DV |
2592 | ring->name = "bsd ring"; |
2593 | ring->id = VCS; | |
2594 | ||
0fd2c201 | 2595 | ring->write_tail = ring_write_tail; |
780f18c8 | 2596 | if (INTEL_INFO(dev)->gen >= 6) { |
58fa3835 | 2597 | ring->mmio_base = GEN6_BSD_RING_BASE; |
0fd2c201 DV |
2598 | /* gen6 bsd needs a special wa for tail updates */ |
2599 | if (IS_GEN6(dev)) | |
2600 | ring->write_tail = gen6_bsd_ring_write_tail; | |
ea251324 | 2601 | ring->flush = gen6_bsd_ring_flush; |
58fa3835 DV |
2602 | ring->add_request = gen6_add_request; |
2603 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2604 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2605 | if (INTEL_INFO(dev)->gen >= 8) { |
2606 | ring->irq_enable_mask = | |
2607 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
2608 | ring->irq_get = gen8_ring_get_irq; | |
2609 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 BW |
2610 | ring->dispatch_execbuffer = |
2611 | gen8_ring_dispatch_execbuffer; | |
707d9cf9 | 2612 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2613 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2614 | ring->semaphore.signal = gen8_xcs_signal; |
2615 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2616 | } |
abd58f01 BW |
2617 | } else { |
2618 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; | |
2619 | ring->irq_get = gen6_ring_get_irq; | |
2620 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 BW |
2621 | ring->dispatch_execbuffer = |
2622 | gen6_ring_dispatch_execbuffer; | |
707d9cf9 BW |
2623 | if (i915_semaphore_is_enabled(dev)) { |
2624 | ring->semaphore.sync_to = gen6_ring_sync; | |
2625 | ring->semaphore.signal = gen6_signal; | |
2626 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VR; | |
2627 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2628 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VB; | |
2629 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_VVE; | |
2630 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2631 | ring->semaphore.mbox.signal[RCS] = GEN6_RVSYNC; | |
2632 | ring->semaphore.mbox.signal[VCS] = GEN6_NOSYNC; | |
2633 | ring->semaphore.mbox.signal[BCS] = GEN6_BVSYNC; | |
2634 | ring->semaphore.mbox.signal[VECS] = GEN6_VEVSYNC; | |
2635 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2636 | } | |
abd58f01 | 2637 | } |
58fa3835 DV |
2638 | } else { |
2639 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 2640 | ring->flush = bsd_ring_flush; |
8620a3a9 | 2641 | ring->add_request = i9xx_add_request; |
58fa3835 | 2642 | ring->get_seqno = ring_get_seqno; |
b70ec5bf | 2643 | ring->set_seqno = ring_set_seqno; |
e48d8634 | 2644 | if (IS_GEN5(dev)) { |
cc609d5d | 2645 | ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT; |
e48d8634 DV |
2646 | ring->irq_get = gen5_ring_get_irq; |
2647 | ring->irq_put = gen5_ring_put_irq; | |
2648 | } else { | |
e3670319 | 2649 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
2650 | ring->irq_get = i9xx_ring_get_irq; |
2651 | ring->irq_put = i9xx_ring_put_irq; | |
2652 | } | |
fb3256da | 2653 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 | 2654 | } |
ecfe00d8 | 2655 | ring->init_hw = init_ring_common; |
58fa3835 | 2656 | |
1ec14ad3 | 2657 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 2658 | } |
549f7365 | 2659 | |
845f74a7 | 2660 | /** |
62659920 | 2661 | * Initialize the second BSD ring (eg. Broadwell GT3, Skylake GT3) |
845f74a7 ZY |
2662 | */ |
2663 | int intel_init_bsd2_ring_buffer(struct drm_device *dev) | |
2664 | { | |
2665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 2666 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; |
845f74a7 | 2667 | |
f7b64236 | 2668 | ring->name = "bsd2 ring"; |
845f74a7 ZY |
2669 | ring->id = VCS2; |
2670 | ||
2671 | ring->write_tail = ring_write_tail; | |
2672 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2673 | ring->flush = gen6_bsd_ring_flush; | |
2674 | ring->add_request = gen6_add_request; | |
2675 | ring->get_seqno = gen6_ring_get_seqno; | |
2676 | ring->set_seqno = ring_set_seqno; | |
2677 | ring->irq_enable_mask = | |
2678 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
2679 | ring->irq_get = gen8_ring_get_irq; | |
2680 | ring->irq_put = gen8_ring_put_irq; | |
2681 | ring->dispatch_execbuffer = | |
2682 | gen8_ring_dispatch_execbuffer; | |
3e78998a | 2683 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2684 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2685 | ring->semaphore.signal = gen8_xcs_signal; |
2686 | GEN8_RING_SEMAPHORE_INIT; | |
2687 | } | |
ecfe00d8 | 2688 | ring->init_hw = init_ring_common; |
845f74a7 ZY |
2689 | |
2690 | return intel_init_ring_buffer(dev, ring); | |
2691 | } | |
2692 | ||
549f7365 CW |
2693 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
2694 | { | |
4640c4ff | 2695 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2696 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; |
549f7365 | 2697 | |
3535d9dd DV |
2698 | ring->name = "blitter ring"; |
2699 | ring->id = BCS; | |
2700 | ||
2701 | ring->mmio_base = BLT_RING_BASE; | |
2702 | ring->write_tail = ring_write_tail; | |
ea251324 | 2703 | ring->flush = gen6_ring_flush; |
3535d9dd DV |
2704 | ring->add_request = gen6_add_request; |
2705 | ring->get_seqno = gen6_ring_get_seqno; | |
b70ec5bf | 2706 | ring->set_seqno = ring_set_seqno; |
abd58f01 BW |
2707 | if (INTEL_INFO(dev)->gen >= 8) { |
2708 | ring->irq_enable_mask = | |
2709 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
2710 | ring->irq_get = gen8_ring_get_irq; | |
2711 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2712 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2713 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2714 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2715 | ring->semaphore.signal = gen8_xcs_signal; |
2716 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2717 | } |
abd58f01 BW |
2718 | } else { |
2719 | ring->irq_enable_mask = GT_BLT_USER_INTERRUPT; | |
2720 | ring->irq_get = gen6_ring_get_irq; | |
2721 | ring->irq_put = gen6_ring_put_irq; | |
1c7a0623 | 2722 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2723 | if (i915_semaphore_is_enabled(dev)) { |
2724 | ring->semaphore.signal = gen6_signal; | |
2725 | ring->semaphore.sync_to = gen6_ring_sync; | |
2726 | /* | |
2727 | * The current semaphore is only applied on pre-gen8 | |
2728 | * platform. And there is no VCS2 ring on the pre-gen8 | |
2729 | * platform. So the semaphore between BCS and VCS2 is | |
2730 | * initialized as INVALID. Gen8 will initialize the | |
2731 | * sema between BCS and VCS2 later. | |
2732 | */ | |
2733 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_BR; | |
2734 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_BV; | |
2735 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_INVALID; | |
2736 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_BVE; | |
2737 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2738 | ring->semaphore.mbox.signal[RCS] = GEN6_RBSYNC; | |
2739 | ring->semaphore.mbox.signal[VCS] = GEN6_VBSYNC; | |
2740 | ring->semaphore.mbox.signal[BCS] = GEN6_NOSYNC; | |
2741 | ring->semaphore.mbox.signal[VECS] = GEN6_VEBSYNC; | |
2742 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2743 | } | |
abd58f01 | 2744 | } |
ecfe00d8 | 2745 | ring->init_hw = init_ring_common; |
549f7365 | 2746 | |
1ec14ad3 | 2747 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 2748 | } |
a7b9761d | 2749 | |
9a8a2213 BW |
2750 | int intel_init_vebox_ring_buffer(struct drm_device *dev) |
2751 | { | |
4640c4ff | 2752 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2753 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; |
9a8a2213 BW |
2754 | |
2755 | ring->name = "video enhancement ring"; | |
2756 | ring->id = VECS; | |
2757 | ||
2758 | ring->mmio_base = VEBOX_RING_BASE; | |
2759 | ring->write_tail = ring_write_tail; | |
2760 | ring->flush = gen6_ring_flush; | |
2761 | ring->add_request = gen6_add_request; | |
2762 | ring->get_seqno = gen6_ring_get_seqno; | |
2763 | ring->set_seqno = ring_set_seqno; | |
abd58f01 BW |
2764 | |
2765 | if (INTEL_INFO(dev)->gen >= 8) { | |
2766 | ring->irq_enable_mask = | |
40c499f9 | 2767 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; |
abd58f01 BW |
2768 | ring->irq_get = gen8_ring_get_irq; |
2769 | ring->irq_put = gen8_ring_put_irq; | |
1c7a0623 | 2770 | ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer; |
707d9cf9 | 2771 | if (i915_semaphore_is_enabled(dev)) { |
5ee426ca | 2772 | ring->semaphore.sync_to = gen8_ring_sync; |
3e78998a BW |
2773 | ring->semaphore.signal = gen8_xcs_signal; |
2774 | GEN8_RING_SEMAPHORE_INIT; | |
707d9cf9 | 2775 | } |
abd58f01 BW |
2776 | } else { |
2777 | ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; | |
2778 | ring->irq_get = hsw_vebox_get_irq; | |
2779 | ring->irq_put = hsw_vebox_put_irq; | |
1c7a0623 | 2780 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
707d9cf9 BW |
2781 | if (i915_semaphore_is_enabled(dev)) { |
2782 | ring->semaphore.sync_to = gen6_ring_sync; | |
2783 | ring->semaphore.signal = gen6_signal; | |
2784 | ring->semaphore.mbox.wait[RCS] = MI_SEMAPHORE_SYNC_VER; | |
2785 | ring->semaphore.mbox.wait[VCS] = MI_SEMAPHORE_SYNC_VEV; | |
2786 | ring->semaphore.mbox.wait[BCS] = MI_SEMAPHORE_SYNC_VEB; | |
2787 | ring->semaphore.mbox.wait[VECS] = MI_SEMAPHORE_SYNC_INVALID; | |
2788 | ring->semaphore.mbox.wait[VCS2] = MI_SEMAPHORE_SYNC_INVALID; | |
2789 | ring->semaphore.mbox.signal[RCS] = GEN6_RVESYNC; | |
2790 | ring->semaphore.mbox.signal[VCS] = GEN6_VVESYNC; | |
2791 | ring->semaphore.mbox.signal[BCS] = GEN6_BVESYNC; | |
2792 | ring->semaphore.mbox.signal[VECS] = GEN6_NOSYNC; | |
2793 | ring->semaphore.mbox.signal[VCS2] = GEN6_NOSYNC; | |
2794 | } | |
abd58f01 | 2795 | } |
ecfe00d8 | 2796 | ring->init_hw = init_ring_common; |
9a8a2213 BW |
2797 | |
2798 | return intel_init_ring_buffer(dev, ring); | |
2799 | } | |
2800 | ||
a7b9761d | 2801 | int |
a4872ba6 | 2802 | intel_ring_flush_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2803 | { |
2804 | int ret; | |
2805 | ||
2806 | if (!ring->gpu_caches_dirty) | |
2807 | return 0; | |
2808 | ||
2809 | ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2810 | if (ret) | |
2811 | return ret; | |
2812 | ||
2813 | trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS); | |
2814 | ||
2815 | ring->gpu_caches_dirty = false; | |
2816 | return 0; | |
2817 | } | |
2818 | ||
2819 | int | |
a4872ba6 | 2820 | intel_ring_invalidate_all_caches(struct intel_engine_cs *ring) |
a7b9761d CW |
2821 | { |
2822 | uint32_t flush_domains; | |
2823 | int ret; | |
2824 | ||
2825 | flush_domains = 0; | |
2826 | if (ring->gpu_caches_dirty) | |
2827 | flush_domains = I915_GEM_GPU_DOMAINS; | |
2828 | ||
2829 | ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2830 | if (ret) | |
2831 | return ret; | |
2832 | ||
2833 | trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); | |
2834 | ||
2835 | ring->gpu_caches_dirty = false; | |
2836 | return 0; | |
2837 | } | |
e3efda49 CW |
2838 | |
2839 | void | |
a4872ba6 | 2840 | intel_stop_ring_buffer(struct intel_engine_cs *ring) |
e3efda49 CW |
2841 | { |
2842 | int ret; | |
2843 | ||
2844 | if (!intel_ring_initialized(ring)) | |
2845 | return; | |
2846 | ||
2847 | ret = intel_ring_idle(ring); | |
2848 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
2849 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
2850 | ring->name, ret); | |
2851 | ||
2852 | stop_ring(ring); | |
2853 | } |