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drm/i915/debugfs: Show the per-ring IMR
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
CommitLineData
62fdfeaf
EA		 1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include "drmP.h"
31#include "drm.h"
62fdfeaf 32#include "i915_drv.h"
8187a2b7 33#include "i915_drm.h"
62fdfeaf 34#include "i915_trace.h"
881f47b6 35#include "intel_drv.h"
62fdfeaf 36
6f392d54
CW		 37static u32 i915_gem_get_seqno(struct drm_device *dev)
38{
39 drm_i915_private_t *dev_priv = dev->dev_private;
40 u32 seqno;
41
42 seqno = dev_priv->next_seqno;
43
44 /* reserve 0 for non-seqno */
45 if (++dev_priv->next_seqno == 0)
46 dev_priv->next_seqno = 1;
47
48 return seqno;
49}
50
b72f3acb 51static int
78501eac 52render_ring_flush(struct intel_ring_buffer *ring,
ab6f8e32
CW		 53 u32 invalidate_domains,
54 u32 flush_domains)
62fdfeaf 55{
78501eac 56 struct drm_device *dev = ring->dev;
6f392d54
CW		 57 drm_i915_private_t *dev_priv = dev->dev_private;
58 u32 cmd;
b72f3acb 59 int ret;
6f392d54 60
62fdfeaf
EA		 61#if WATCH_EXEC
62 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
63 invalidate_domains, flush_domains);
64#endif
6f392d54
CW		 65
66 trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
62fdfeaf
EA		 67 invalidate_domains, flush_domains);
68
62fdfeaf
EA		 69 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
70 /*
71 * read/write caches:
72 *
73 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
74 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
75 * also flushed at 2d versus 3d pipeline switches.
76 *
77 * read-only caches:
78 *
79 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
80 * MI_READ_FLUSH is set, and is always flushed on 965.
81 *
82 * I915_GEM_DOMAIN_COMMAND may not exist?
83 *
84 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
85 * invalidated when MI_EXE_FLUSH is set.
86 *
87 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
88 * invalidated with every MI_FLUSH.
89 *
90 * TLBs:
91 *
92 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
93 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
94 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
95 * are flushed at any MI_FLUSH.
96 */
97
98 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
99 if ((invalidate_domains|flush_domains) &
100 I915_GEM_DOMAIN_RENDER)
101 cmd &= ~MI_NO_WRITE_FLUSH;
a6c45cf0 102 if (INTEL_INFO(dev)->gen < 4) {
62fdfeaf
EA		 103 /*
104 * On the 965, the sampler cache always gets flushed
105 * and this bit is reserved.
106 */
107 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
108 cmd |= MI_READ_FLUSH;
109 }
110 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
111 cmd |= MI_EXE_FLUSH;
112
70eac33e
CW		 113 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
114 (IS_G4X(dev) || IS_GEN5(dev)))
115 cmd |= MI_INVALIDATE_ISP;
116
62fdfeaf
EA		 117#if WATCH_EXEC
118 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
119#endif
b72f3acb
CW		 120 ret = intel_ring_begin(ring, 2);
121 if (ret)
122 return ret;
123
124 intel_ring_emit(ring, cmd);
125 intel_ring_emit(ring, MI_NOOP);
126 intel_ring_advance(ring);
62fdfeaf 127 }
b72f3acb
CW		 128
129 return 0;
8187a2b7
ZN		 130}
131
78501eac 132static void ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 133 u32 value)
d46eefa2 134{
78501eac 135 drm_i915_private_t *dev_priv = ring->dev->dev_private;
297b0c5b 136 I915_WRITE_TAIL(ring, value);
d46eefa2
XH		 137}
138
78501eac 139u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
8187a2b7 140{
78501eac
CW		 141 drm_i915_private_t *dev_priv = ring->dev->dev_private;
142 u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
3d281d8c 143 RING_ACTHD(ring->mmio_base) : ACTHD;
8187a2b7
ZN		 144
145 return I915_READ(acthd_reg);
146}
147
78501eac 148static int init_ring_common(struct intel_ring_buffer *ring)
8187a2b7 149{
78501eac 150 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 151 struct drm_i915_gem_object *obj = ring->obj;
8187a2b7 152 u32 head;
8187a2b7
ZN		 153
154 /* Stop the ring if it's running. */
7f2ab699 155 I915_WRITE_CTL(ring, 0);
570ef608 156 I915_WRITE_HEAD(ring, 0);
78501eac 157 ring->write_tail(ring, 0);
8187a2b7
ZN		 158
159 /* Initialize the ring. */
05394f39 160 I915_WRITE_START(ring, obj->gtt_offset);
570ef608 161 head = I915_READ_HEAD(ring) & HEAD_ADDR;
8187a2b7
ZN		 162
163 /* G45 ring initialization fails to reset head to zero */
164 if (head != 0) {
6fd0d56e
CW		 165 DRM_DEBUG_KMS("%s head not reset to zero "
166 "ctl %08x head %08x tail %08x start %08x\n",
167 ring->name,
168 I915_READ_CTL(ring),
169 I915_READ_HEAD(ring),
170 I915_READ_TAIL(ring),
171 I915_READ_START(ring));
8187a2b7 172
570ef608 173 I915_WRITE_HEAD(ring, 0);
8187a2b7 174
6fd0d56e
CW		 175 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
176 DRM_ERROR("failed to set %s head to zero "
177 "ctl %08x head %08x tail %08x start %08x\n",
178 ring->name,
179 I915_READ_CTL(ring),
180 I915_READ_HEAD(ring),
181 I915_READ_TAIL(ring),
182 I915_READ_START(ring));
183 }
8187a2b7
ZN		 184 }
185
7f2ab699 186 I915_WRITE_CTL(ring,
ae69b42a 187 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
6aa56062 188 | RING_REPORT_64K | RING_VALID);
8187a2b7 189
8187a2b7 190 /* If the head is still not zero, the ring is dead */
176f28eb 191 if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
05394f39 192 I915_READ_START(ring) != obj->gtt_offset ||
176f28eb 193 (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
e74cfed5
CW		 194 DRM_ERROR("%s initialization failed "
195 "ctl %08x head %08x tail %08x start %08x\n",
196 ring->name,
197 I915_READ_CTL(ring),
198 I915_READ_HEAD(ring),
199 I915_READ_TAIL(ring),
200 I915_READ_START(ring));
201 return -EIO;
8187a2b7
ZN		 202 }
203
78501eac
CW		 204 if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
205 i915_kernel_lost_context(ring->dev);
8187a2b7 206 else {
570ef608 207 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
870e86dd 208 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
8187a2b7
ZN		 209 ring->space = ring->head - (ring->tail + 8);
210 if (ring->space < 0)
211 ring->space += ring->size;
212 }
1ec14ad3 213
8187a2b7
ZN		 214 return 0;
215}
216
c6df541c
CW		 217/*
218 * 965+ support PIPE_CONTROL commands, which provide finer grained control
219 * over cache flushing.
220 */
221struct pipe_control {
222 struct drm_i915_gem_object *obj;
223 volatile u32 *cpu_page;
224 u32 gtt_offset;
225};
226
227static int
228init_pipe_control(struct intel_ring_buffer *ring)
229{
230 struct pipe_control *pc;
231 struct drm_i915_gem_object *obj;
232 int ret;
233
234 if (ring->private)
235 return 0;
236
237 pc = kmalloc(sizeof(*pc), GFP_KERNEL);
238 if (!pc)
239 return -ENOMEM;
240
241 obj = i915_gem_alloc_object(ring->dev, 4096);
242 if (obj == NULL) {
243 DRM_ERROR("Failed to allocate seqno page\n");
244 ret = -ENOMEM;
245 goto err;
246 }
247 obj->agp_type = AGP_USER_CACHED_MEMORY;
248
249 ret = i915_gem_object_pin(obj, 4096, true);
250 if (ret)
251 goto err_unref;
252
253 pc->gtt_offset = obj->gtt_offset;
254 pc->cpu_page = kmap(obj->pages[0]);
255 if (pc->cpu_page == NULL)
256 goto err_unpin;
257
258 pc->obj = obj;
259 ring->private = pc;
260 return 0;
261
262err_unpin:
263 i915_gem_object_unpin(obj);
264err_unref:
265 drm_gem_object_unreference(&obj->base);
266err:
267 kfree(pc);
268 return ret;
269}
270
271static void
272cleanup_pipe_control(struct intel_ring_buffer *ring)
273{
274 struct pipe_control *pc = ring->private;
275 struct drm_i915_gem_object *obj;
276
277 if (!ring->private)
278 return;
279
280 obj = pc->obj;
281 kunmap(obj->pages[0]);
282 i915_gem_object_unpin(obj);
283 drm_gem_object_unreference(&obj->base);
284
285 kfree(pc);
286 ring->private = NULL;
287}
288
78501eac 289static int init_render_ring(struct intel_ring_buffer *ring)
8187a2b7 290{
78501eac 291 struct drm_device *dev = ring->dev;
1ec14ad3 292 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 293 int ret = init_ring_common(ring);
a69ffdbf 294
a6c45cf0 295 if (INTEL_INFO(dev)->gen > 3) {
78501eac 296 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
a69ffdbf
ZW		 297 if (IS_GEN6(dev))
298 mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
299 I915_WRITE(MI_MODE, mode);
8187a2b7 300 }
78501eac 301
c6df541c
CW		 302 if (INTEL_INFO(dev)->gen >= 6) {
303 } else if (IS_GEN5(dev)) {
304 ret = init_pipe_control(ring);
305 if (ret)
306 return ret;
307 }
308
8187a2b7
ZN		 309 return ret;
310}
311
c6df541c
CW		 312static void render_ring_cleanup(struct intel_ring_buffer *ring)
313{
314 if (!ring->private)
315 return;
316
317 cleanup_pipe_control(ring);
318}
319
1ec14ad3
CW		 320static void
321update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
322{
323 struct drm_device *dev = ring->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325 int id;
326
327 /*
328 * cs -> 1 = vcs, 0 = bcs
329 * vcs -> 1 = bcs, 0 = cs,
330 * bcs -> 1 = cs, 0 = vcs.
331 */
332 id = ring - dev_priv->ring;
333 id += 2 - i;
334 id %= 3;
335
336 intel_ring_emit(ring,
337 MI_SEMAPHORE_MBOX |
338 MI_SEMAPHORE_REGISTER |
339 MI_SEMAPHORE_UPDATE);
340 intel_ring_emit(ring, seqno);
341 intel_ring_emit(ring,
342 RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
343}
344
345static int
346gen6_add_request(struct intel_ring_buffer *ring,
347 u32 *result)
348{
349 u32 seqno;
350 int ret;
351
352 ret = intel_ring_begin(ring, 10);
353 if (ret)
354 return ret;
355
356 seqno = i915_gem_get_seqno(ring->dev);
357 update_semaphore(ring, 0, seqno);
358 update_semaphore(ring, 1, seqno);
359
360 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
361 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
362 intel_ring_emit(ring, seqno);
363 intel_ring_emit(ring, MI_USER_INTERRUPT);
364 intel_ring_advance(ring);
365
366 *result = seqno;
367 return 0;
368}
369
370int
371intel_ring_sync(struct intel_ring_buffer *ring,
372 struct intel_ring_buffer *to,
373 u32 seqno)
374{
375 int ret;
376
377 ret = intel_ring_begin(ring, 4);
378 if (ret)
379 return ret;
380
381 intel_ring_emit(ring,
382 MI_SEMAPHORE_MBOX |
383 MI_SEMAPHORE_REGISTER |
384 intel_ring_sync_index(ring, to) << 17 |
385 MI_SEMAPHORE_COMPARE);
386 intel_ring_emit(ring, seqno);
387 intel_ring_emit(ring, 0);
388 intel_ring_emit(ring, MI_NOOP);
389 intel_ring_advance(ring);
390
391 return 0;
392}
393
c6df541c
CW		 394#define PIPE_CONTROL_FLUSH(ring__, addr__) \
395do { \
396 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
397 PIPE_CONTROL_DEPTH_STALL | 2); \
398 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
399 intel_ring_emit(ring__, 0); \
400 intel_ring_emit(ring__, 0); \
401} while (0)
402
403static int
404pc_render_add_request(struct intel_ring_buffer *ring,
405 u32 *result)
406{
407 struct drm_device *dev = ring->dev;
408 u32 seqno = i915_gem_get_seqno(dev);
409 struct pipe_control *pc = ring->private;
410 u32 scratch_addr = pc->gtt_offset + 128;
411 int ret;
412
413 /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
414 * incoherent with writes to memory, i.e. completely fubar,
415 * so we need to use PIPE_NOTIFY instead.
416 *
417 * However, we also need to workaround the qword write
418 * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
419 * memory before requesting an interrupt.
420 */
421 ret = intel_ring_begin(ring, 32);
422 if (ret)
423 return ret;
424
425 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
426 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
427 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
428 intel_ring_emit(ring, seqno);
429 intel_ring_emit(ring, 0);
430 PIPE_CONTROL_FLUSH(ring, scratch_addr);
431 scratch_addr += 128; /* write to separate cachelines */
432 PIPE_CONTROL_FLUSH(ring, scratch_addr);
433 scratch_addr += 128;
434 PIPE_CONTROL_FLUSH(ring, scratch_addr);
435 scratch_addr += 128;
436 PIPE_CONTROL_FLUSH(ring, scratch_addr);
437 scratch_addr += 128;
438 PIPE_CONTROL_FLUSH(ring, scratch_addr);
439 scratch_addr += 128;
440 PIPE_CONTROL_FLUSH(ring, scratch_addr);
441 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
442 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
443 PIPE_CONTROL_NOTIFY);
444 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
445 intel_ring_emit(ring, seqno);
446 intel_ring_emit(ring, 0);
447 intel_ring_advance(ring);
448
449 *result = seqno;
450 return 0;
451}
452
1ec14ad3
CW		 453static int
454render_ring_add_request(struct intel_ring_buffer *ring,
455 u32 *result)
456{
457 struct drm_device *dev = ring->dev;
458 u32 seqno = i915_gem_get_seqno(dev);
459 int ret;
3cce469c 460
1ec14ad3
CW		 461 ret = intel_ring_begin(ring, 4);
462 if (ret)
463 return ret;
3cce469c 464
1ec14ad3
CW		 465 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
466 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
467 intel_ring_emit(ring, seqno);
468 intel_ring_emit(ring, MI_USER_INTERRUPT);
3cce469c 469 intel_ring_advance(ring);
1ec14ad3 470
3cce469c
CW		 471 *result = seqno;
472 return 0;
62fdfeaf
EA		 473}
474
8187a2b7 475static u32
1ec14ad3 476ring_get_seqno(struct intel_ring_buffer *ring)
8187a2b7 477{
1ec14ad3
CW		 478 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
479}
480
c6df541c
CW		 481static u32
482pc_render_get_seqno(struct intel_ring_buffer *ring)
483{
484 struct pipe_control *pc = ring->private;
485 return pc->cpu_page[0];
486}
487
0f46832f
CW		 488static void
489ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
490{
491 dev_priv->gt_irq_mask &= ~mask;
492 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
493 POSTING_READ(GTIMR);
494}
495
496static void
497ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
498{
499 dev_priv->gt_irq_mask |= mask;
500 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
501 POSTING_READ(GTIMR);
502}
503
504static void
505i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
506{
507 dev_priv->irq_mask &= ~mask;
508 I915_WRITE(IMR, dev_priv->irq_mask);
509 POSTING_READ(IMR);
510}
511
512static void
513i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
514{
515 dev_priv->irq_mask |= mask;
516 I915_WRITE(IMR, dev_priv->irq_mask);
517 POSTING_READ(IMR);
518}
519
b13c2b96 520static bool
1ec14ad3 521render_ring_get_irq(struct intel_ring_buffer *ring)
62fdfeaf 522{
78501eac 523 struct drm_device *dev = ring->dev;
62fdfeaf 524
b13c2b96
CW		 525 if (!dev->irq_enabled)
526 return false;
527
528 if (atomic_inc_return(&ring->irq_refcount) == 1) {
1ec14ad3
CW		 529 drm_i915_private_t *dev_priv = dev->dev_private;
530 unsigned long irqflags;
531
532 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
62fdfeaf 533 if (HAS_PCH_SPLIT(dev))
0f46832f
CW		 534 ironlake_enable_irq(dev_priv,
535 GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
62fdfeaf
EA		 536 else
537 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
1ec14ad3 538 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
62fdfeaf 539 }
b13c2b96
CW		 540
541 return true;
62fdfeaf
EA		 542}
543
8187a2b7 544static void
1ec14ad3 545render_ring_put_irq(struct intel_ring_buffer *ring)
62fdfeaf 546{
78501eac 547 struct drm_device *dev = ring->dev;
62fdfeaf 548
b13c2b96 549 if (atomic_dec_and_test(&ring->irq_refcount)) {
1ec14ad3
CW		 550 drm_i915_private_t *dev_priv = dev->dev_private;
551 unsigned long irqflags;
552
553 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
62fdfeaf 554 if (HAS_PCH_SPLIT(dev))
0f46832f
CW		 555 ironlake_disable_irq(dev_priv,
556 GT_USER_INTERRUPT |
557 GT_PIPE_NOTIFY);
62fdfeaf
EA		 558 else
559 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
1ec14ad3 560 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
62fdfeaf 561 }
62fdfeaf
EA		 562}
563
78501eac 564void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
8187a2b7 565{
78501eac
CW		 566 drm_i915_private_t *dev_priv = ring->dev->dev_private;
567 u32 mmio = IS_GEN6(ring->dev) ?
568 RING_HWS_PGA_GEN6(ring->mmio_base) :
569 RING_HWS_PGA(ring->mmio_base);
570 I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
571 POSTING_READ(mmio);
8187a2b7
ZN		 572}
573
b72f3acb 574static int
78501eac
CW		 575bsd_ring_flush(struct intel_ring_buffer *ring,
576 u32 invalidate_domains,
577 u32 flush_domains)
d1b851fc 578{
b72f3acb
CW		 579 int ret;
580
1ec14ad3 581 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
b72f3acb 582 return 0;
1ec14ad3 583
b72f3acb
CW		 584 ret = intel_ring_begin(ring, 2);
585 if (ret)
586 return ret;
587
588 intel_ring_emit(ring, MI_FLUSH);
589 intel_ring_emit(ring, MI_NOOP);
590 intel_ring_advance(ring);
591 return 0;
d1b851fc
ZN		 592}
593
3cce469c 594static int
78501eac 595ring_add_request(struct intel_ring_buffer *ring,
3cce469c 596 u32 *result)
d1b851fc
ZN		 597{
598 u32 seqno;
3cce469c
CW		 599 int ret;
600
601 ret = intel_ring_begin(ring, 4);
602 if (ret)
603 return ret;
6f392d54 604
78501eac 605 seqno = i915_gem_get_seqno(ring->dev);
6f392d54 606
3cce469c
CW		 607 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
608 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
609 intel_ring_emit(ring, seqno);
610 intel_ring_emit(ring, MI_USER_INTERRUPT);
611 intel_ring_advance(ring);
d1b851fc
ZN		 612
613 DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
3cce469c
CW		 614 *result = seqno;
615 return 0;
d1b851fc
ZN		 616}
617
b13c2b96 618static bool
1ec14ad3 619ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
d1b851fc 620{
1ec14ad3
CW		 621 struct drm_device *dev = ring->dev;
622
b13c2b96
CW		 623 if (!dev->irq_enabled)
624 return false;
625
626 if (atomic_inc_return(&ring->irq_refcount) == 1) {
1ec14ad3
CW		 627 drm_i915_private_t *dev_priv = dev->dev_private;
628 unsigned long irqflags;
629
630 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
0f46832f 631 ironlake_enable_irq(dev_priv, flag);
1ec14ad3
CW		 632 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
633 }
b13c2b96
CW		 634
635 return true;
d1b851fc 636}
1ec14ad3 637
d1b851fc 638static void
1ec14ad3 639ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
d1b851fc 640{
1ec14ad3
CW		 641 struct drm_device *dev = ring->dev;
642
b13c2b96 643 if (atomic_dec_and_test(&ring->irq_refcount)) {
1ec14ad3
CW		 644 drm_i915_private_t *dev_priv = dev->dev_private;
645 unsigned long irqflags;
646
647 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
0f46832f
CW		 648 ironlake_disable_irq(dev_priv, flag);
649 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
650 }
651}
652
653static bool
654gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
655{
656 struct drm_device *dev = ring->dev;
657
658 if (!dev->irq_enabled)
659 return false;
660
661 if (atomic_inc_return(&ring->irq_refcount) == 1) {
662 drm_i915_private_t *dev_priv = dev->dev_private;
663 unsigned long irqflags;
664
665 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
666 ring->irq_mask &= ~rflag;
667 I915_WRITE_IMR(ring, ring->irq_mask);
668 ironlake_enable_irq(dev_priv, gflag);
669 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
670 }
671
672 return true;
673}
674
675static void
676gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
677{
678 struct drm_device *dev = ring->dev;
679
680 if (atomic_dec_and_test(&ring->irq_refcount)) {
681 drm_i915_private_t *dev_priv = dev->dev_private;
682 unsigned long irqflags;
683
684 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
685 ring->irq_mask |= rflag;
686 I915_WRITE_IMR(ring, ring->irq_mask);
687 ironlake_disable_irq(dev_priv, gflag);
1ec14ad3
CW		 688 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
689 }
d1b851fc
ZN		 690}
691
b13c2b96 692static bool
1ec14ad3 693bsd_ring_get_irq(struct intel_ring_buffer *ring)
d1b851fc 694{
b13c2b96 695 return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
1ec14ad3
CW		 696}
697static void
698bsd_ring_put_irq(struct intel_ring_buffer *ring)
699{
b13c2b96 700 ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
d1b851fc
ZN		 701}
702
703static int
c4e7a414 704ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
d1b851fc 705{
e1f99ce6 706 int ret;
78501eac 707
e1f99ce6
CW		 708 ret = intel_ring_begin(ring, 2);
709 if (ret)
710 return ret;
711
78501eac 712 intel_ring_emit(ring,
c4e7a414 713 MI_BATCH_BUFFER_START | (2 << 6) |
78501eac 714 MI_BATCH_NON_SECURE_I965);
c4e7a414 715 intel_ring_emit(ring, offset);
78501eac
CW		 716 intel_ring_advance(ring);
717
d1b851fc
ZN		 718 return 0;
719}
720
8187a2b7 721static int
78501eac 722render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 723 u32 offset, u32 len)
62fdfeaf 724{
78501eac 725 struct drm_device *dev = ring->dev;
62fdfeaf 726 drm_i915_private_t *dev_priv = dev->dev_private;
c4e7a414 727 int ret;
62fdfeaf 728
6f392d54 729 trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
62fdfeaf 730
c4e7a414
CW		 731 if (IS_I830(dev) || IS_845G(dev)) {
732 ret = intel_ring_begin(ring, 4);
733 if (ret)
734 return ret;
62fdfeaf 735
c4e7a414
CW		 736 intel_ring_emit(ring, MI_BATCH_BUFFER);
737 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
738 intel_ring_emit(ring, offset + len - 8);
739 intel_ring_emit(ring, 0);
740 } else {
741 ret = intel_ring_begin(ring, 2);
742 if (ret)
743 return ret;
e1f99ce6 744
c4e7a414
CW		 745 if (INTEL_INFO(dev)->gen >= 4) {
746 intel_ring_emit(ring,
747 MI_BATCH_BUFFER_START | (2 << 6) |
748 MI_BATCH_NON_SECURE_I965);
749 intel_ring_emit(ring, offset);
62fdfeaf 750 } else {
c4e7a414
CW		 751 intel_ring_emit(ring,
752 MI_BATCH_BUFFER_START | (2 << 6));
753 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
62fdfeaf
EA		 754 }
755 }
c4e7a414 756 intel_ring_advance(ring);
62fdfeaf 757
62fdfeaf
EA		 758 return 0;
759}
760
78501eac 761static void cleanup_status_page(struct intel_ring_buffer *ring)
62fdfeaf 762{
78501eac 763 drm_i915_private_t *dev_priv = ring->dev->dev_private;
05394f39 764 struct drm_i915_gem_object *obj;
62fdfeaf 765
8187a2b7
ZN		 766 obj = ring->status_page.obj;
767 if (obj == NULL)
62fdfeaf 768 return;
62fdfeaf 769
05394f39 770 kunmap(obj->pages[0]);
62fdfeaf 771 i915_gem_object_unpin(obj);
05394f39 772 drm_gem_object_unreference(&obj->base);
8187a2b7 773 ring->status_page.obj = NULL;
62fdfeaf
EA		 774
775 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 776}
777
78501eac 778static int init_status_page(struct intel_ring_buffer *ring)
62fdfeaf 779{
78501eac 780 struct drm_device *dev = ring->dev;
62fdfeaf 781 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 782 struct drm_i915_gem_object *obj;
62fdfeaf
EA		 783 int ret;
784
62fdfeaf
EA		 785 obj = i915_gem_alloc_object(dev, 4096);
786 if (obj == NULL) {
787 DRM_ERROR("Failed to allocate status page\n");
788 ret = -ENOMEM;
789 goto err;
790 }
05394f39 791 obj->agp_type = AGP_USER_CACHED_MEMORY;
62fdfeaf 792
75e9e915 793 ret = i915_gem_object_pin(obj, 4096, true);
62fdfeaf 794 if (ret != 0) {
62fdfeaf
EA		 795 goto err_unref;
796 }
797
05394f39
CW		 798 ring->status_page.gfx_addr = obj->gtt_offset;
799 ring->status_page.page_addr = kmap(obj->pages[0]);
8187a2b7 800 if (ring->status_page.page_addr == NULL) {
62fdfeaf 801 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
62fdfeaf
EA		 802 goto err_unpin;
803 }
8187a2b7
ZN		 804 ring->status_page.obj = obj;
805 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
62fdfeaf 806
78501eac 807 intel_ring_setup_status_page(ring);
8187a2b7
ZN		 808 DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
809 ring->name, ring->status_page.gfx_addr);
62fdfeaf
EA		 810
811 return 0;
812
813err_unpin:
814 i915_gem_object_unpin(obj);
815err_unref:
05394f39 816 drm_gem_object_unreference(&obj->base);
62fdfeaf 817err:
8187a2b7 818 return ret;
62fdfeaf
EA		 819}
820
8187a2b7 821int intel_init_ring_buffer(struct drm_device *dev,
ab6f8e32 822 struct intel_ring_buffer *ring)
62fdfeaf 823{
05394f39 824 struct drm_i915_gem_object *obj;
dd785e35
CW		 825 int ret;
826
8187a2b7 827 ring->dev = dev;
23bc5982
CW		 828 INIT_LIST_HEAD(&ring->active_list);
829 INIT_LIST_HEAD(&ring->request_list);
64193406 830 INIT_LIST_HEAD(&ring->gpu_write_list);
0f46832f 831 ring->irq_mask = ~0;
62fdfeaf 832
8187a2b7 833 if (I915_NEED_GFX_HWS(dev)) {
78501eac 834 ret = init_status_page(ring);
8187a2b7
ZN		 835 if (ret)
836 return ret;
837 }
62fdfeaf 838
8187a2b7 839 obj = i915_gem_alloc_object(dev, ring->size);
62fdfeaf
EA		 840 if (obj == NULL) {
841 DRM_ERROR("Failed to allocate ringbuffer\n");
8187a2b7 842 ret = -ENOMEM;
dd785e35 843 goto err_hws;
62fdfeaf 844 }
62fdfeaf 845
05394f39 846 ring->obj = obj;
8187a2b7 847
75e9e915 848 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
dd785e35
CW		 849 if (ret)
850 goto err_unref;
62fdfeaf 851
8187a2b7 852 ring->map.size = ring->size;
05394f39 853 ring->map.offset = dev->agp->base + obj->gtt_offset;
62fdfeaf
EA		 854 ring->map.type = 0;
855 ring->map.flags = 0;
856 ring->map.mtrr = 0;
857
858 drm_core_ioremap_wc(&ring->map, dev);
859 if (ring->map.handle == NULL) {
860 DRM_ERROR("Failed to map ringbuffer.\n");
8187a2b7 861 ret = -EINVAL;
dd785e35 862 goto err_unpin;
62fdfeaf
EA		 863 }
864
8187a2b7 865 ring->virtual_start = ring->map.handle;
78501eac 866 ret = ring->init(ring);
dd785e35
CW		 867 if (ret)
868 goto err_unmap;
62fdfeaf 869
55249baa
CW		 870 /* Workaround an erratum on the i830 which causes a hang if
871 * the TAIL pointer points to within the last 2 cachelines
872 * of the buffer.
873 */
874 ring->effective_size = ring->size;
875 if (IS_I830(ring->dev))
876 ring->effective_size -= 128;
877
c584fe47 878 return 0;
dd785e35
CW		 879
880err_unmap:
881 drm_core_ioremapfree(&ring->map, dev);
882err_unpin:
883 i915_gem_object_unpin(obj);
884err_unref:
05394f39
CW		 885 drm_gem_object_unreference(&obj->base);
886 ring->obj = NULL;
dd785e35 887err_hws:
78501eac 888 cleanup_status_page(ring);
8187a2b7 889 return ret;
62fdfeaf
EA		 890}
891
78501eac 892void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 893{
33626e6a
CW		 894 struct drm_i915_private *dev_priv;
895 int ret;
896
05394f39 897 if (ring->obj == NULL)
62fdfeaf
EA		 898 return;
899
33626e6a
CW		 900 /* Disable the ring buffer. The ring must be idle at this point */
901 dev_priv = ring->dev->dev_private;
902 ret = intel_wait_ring_buffer(ring, ring->size - 8);
903 I915_WRITE_CTL(ring, 0);
904
78501eac 905 drm_core_ioremapfree(&ring->map, ring->dev);
62fdfeaf 906
05394f39
CW		 907 i915_gem_object_unpin(ring->obj);
908 drm_gem_object_unreference(&ring->obj->base);
909 ring->obj = NULL;
78501eac 910
8d19215b
ZN		 911 if (ring->cleanup)
912 ring->cleanup(ring);
913
78501eac 914 cleanup_status_page(ring);
62fdfeaf
EA		 915}
916
78501eac 917static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
62fdfeaf 918{
8187a2b7 919 unsigned int *virt;
55249baa 920 int rem = ring->size - ring->tail;
62fdfeaf 921
8187a2b7 922 if (ring->space < rem) {
78501eac 923 int ret = intel_wait_ring_buffer(ring, rem);
62fdfeaf
EA		 924 if (ret)
925 return ret;
926 }
62fdfeaf 927
8187a2b7 928 virt = (unsigned int *)(ring->virtual_start + ring->tail);
1741dd4a
CW		 929 rem /= 8;
930 while (rem--) {
62fdfeaf 931 *virt++ = MI_NOOP;
1741dd4a
CW		 932 *virt++ = MI_NOOP;
933 }
62fdfeaf 934
8187a2b7 935 ring->tail = 0;
43ed340a 936 ring->space = ring->head - 8;
62fdfeaf
EA		 937
938 return 0;
939}
940
78501eac 941int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
62fdfeaf 942{
78501eac 943 struct drm_device *dev = ring->dev;
cae5852d 944 struct drm_i915_private *dev_priv = dev->dev_private;
78501eac 945 unsigned long end;
6aa56062
CW		 946 u32 head;
947
62fdfeaf 948 trace_i915_ring_wait_begin (dev);
8187a2b7
ZN		 949 end = jiffies + 3 * HZ;
950 do {
8c0a6bfe
CW		 951 /* If the reported head position has wrapped or hasn't advanced,
952 * fallback to the slow and accurate path.
953 */
954 head = intel_read_status_page(ring, 4);
955 if (head < ring->actual_head)
956 head = I915_READ_HEAD(ring);
957 ring->actual_head = head;
958 ring->head = head & HEAD_ADDR;
62fdfeaf
EA		 959 ring->space = ring->head - (ring->tail + 8);
960 if (ring->space < 0)
8187a2b7 961 ring->space += ring->size;
62fdfeaf 962 if (ring->space >= n) {
78501eac 963 trace_i915_ring_wait_end(dev);
62fdfeaf
EA		 964 return 0;
965 }
966
967 if (dev->primary->master) {
968 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
969 if (master_priv->sarea_priv)
970 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
971 }
d1b851fc 972
e60a0b10 973 msleep(1);
f4e0b29b
CW		 974 if (atomic_read(&dev_priv->mm.wedged))
975 return -EAGAIN;
8187a2b7
ZN		 976 } while (!time_after(jiffies, end));
977 trace_i915_ring_wait_end (dev);
978 return -EBUSY;
979}
62fdfeaf 980
e1f99ce6
CW		 981int intel_ring_begin(struct intel_ring_buffer *ring,
982 int num_dwords)
8187a2b7 983{
be26a10b 984 int n = 4*num_dwords;
e1f99ce6 985 int ret;
78501eac 986
55249baa 987 if (unlikely(ring->tail + n > ring->effective_size)) {
e1f99ce6
CW		 988 ret = intel_wrap_ring_buffer(ring);
989 if (unlikely(ret))
990 return ret;
991 }
78501eac 992
e1f99ce6
CW		 993 if (unlikely(ring->space < n)) {
994 ret = intel_wait_ring_buffer(ring, n);
995 if (unlikely(ret))
996 return ret;
997 }
d97ed339
CW		 998
999 ring->space -= n;
e1f99ce6 1000 return 0;
8187a2b7 1001}
62fdfeaf 1002
78501eac 1003void intel_ring_advance(struct intel_ring_buffer *ring)
8187a2b7 1004{
d97ed339 1005 ring->tail &= ring->size - 1;
78501eac 1006 ring->write_tail(ring, ring->tail);
8187a2b7 1007}
62fdfeaf 1008
e070868e 1009static const struct intel_ring_buffer render_ring = {
8187a2b7 1010 .name = "render ring",
9220434a 1011 .id = RING_RENDER,
333e9fe9 1012 .mmio_base = RENDER_RING_BASE,
8187a2b7 1013 .size = 32 * PAGE_SIZE,
8187a2b7 1014 .init = init_render_ring,
297b0c5b 1015 .write_tail = ring_write_tail,
8187a2b7
ZN		 1016 .flush = render_ring_flush,
1017 .add_request = render_ring_add_request,
1ec14ad3
CW		 1018 .get_seqno = ring_get_seqno,
1019 .irq_get = render_ring_get_irq,
1020 .irq_put = render_ring_put_irq,
78501eac 1021 .dispatch_execbuffer = render_ring_dispatch_execbuffer,
c6df541c 1022 .cleanup = render_ring_cleanup,
8187a2b7 1023};
d1b851fc
ZN		 1024
1025/* ring buffer for bit-stream decoder */
1026
e070868e 1027static const struct intel_ring_buffer bsd_ring = {
d1b851fc 1028 .name = "bsd ring",
9220434a 1029 .id = RING_BSD,
333e9fe9 1030 .mmio_base = BSD_RING_BASE,
d1b851fc 1031 .size = 32 * PAGE_SIZE,
78501eac 1032 .init = init_ring_common,
297b0c5b 1033 .write_tail = ring_write_tail,
d1b851fc 1034 .flush = bsd_ring_flush,
549f7365 1035 .add_request = ring_add_request,
1ec14ad3
CW		 1036 .get_seqno = ring_get_seqno,
1037 .irq_get = bsd_ring_get_irq,
1038 .irq_put = bsd_ring_put_irq,
78501eac 1039 .dispatch_execbuffer = ring_dispatch_execbuffer,
d1b851fc 1040};
5c1143bb 1041
881f47b6 1042
78501eac 1043static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
297b0c5b 1044 u32 value)
881f47b6 1045{
78501eac 1046 drm_i915_private_t *dev_priv = ring->dev->dev_private;
881f47b6
XH		 1047
1048 /* Every tail move must follow the sequence below */
1049 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1050 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1051 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1052 I915_WRITE(GEN6_BSD_RNCID, 0x0);
1053
1054 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1055 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1056 50))
1057 DRM_ERROR("timed out waiting for IDLE Indicator\n");
1058
870e86dd 1059 I915_WRITE_TAIL(ring, value);
881f47b6
XH		 1060 I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1061 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1062 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1063}
1064
b72f3acb
CW		 1065static int gen6_ring_flush(struct intel_ring_buffer *ring,
1066 u32 invalidate_domains,
1067 u32 flush_domains)
881f47b6 1068{
b72f3acb
CW		 1069 int ret;
1070
1ec14ad3 1071 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
b72f3acb 1072 return 0;
1ec14ad3 1073
b72f3acb
CW		 1074 ret = intel_ring_begin(ring, 4);
1075 if (ret)
1076 return ret;
1077
1078 intel_ring_emit(ring, MI_FLUSH_DW);
1079 intel_ring_emit(ring, 0);
1080 intel_ring_emit(ring, 0);
1081 intel_ring_emit(ring, 0);
1082 intel_ring_advance(ring);
1083 return 0;
881f47b6
XH		 1084}
1085
1086static int
78501eac 1087gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
c4e7a414 1088 u32 offset, u32 len)
881f47b6 1089{
e1f99ce6 1090 int ret;
ab6f8e32 1091
e1f99ce6
CW		 1092 ret = intel_ring_begin(ring, 2);
1093 if (ret)
1094 return ret;
1095
78501eac 1096 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
ab6f8e32 1097 /* bit0-7 is the length on GEN6+ */
c4e7a414 1098 intel_ring_emit(ring, offset);
78501eac 1099 intel_ring_advance(ring);
ab6f8e32 1100
881f47b6
XH		 1101 return 0;
1102}
1103
0f46832f
CW		 1104static bool
1105gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1106{
1107 return gen6_ring_get_irq(ring,
1108 GT_USER_INTERRUPT,
1109 GEN6_RENDER_USER_INTERRUPT);
1110}
1111
1112static void
1113gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1114{
1115 return gen6_ring_put_irq(ring,
1116 GT_USER_INTERRUPT,
1117 GEN6_RENDER_USER_INTERRUPT);
1118}
1119
b13c2b96 1120static bool
1ec14ad3
CW		 1121gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1122{
0f46832f
CW		 1123 return gen6_ring_get_irq(ring,
1124 GT_GEN6_BSD_USER_INTERRUPT,
1125 GEN6_BSD_USER_INTERRUPT);
1ec14ad3
CW		 1126}
1127
1128static void
1129gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1130{
0f46832f
CW		 1131 return gen6_ring_put_irq(ring,
1132 GT_GEN6_BSD_USER_INTERRUPT,
1133 GEN6_BSD_USER_INTERRUPT);
1ec14ad3
CW		 1134}
1135
881f47b6 1136/* ring buffer for Video Codec for Gen6+ */
e070868e 1137static const struct intel_ring_buffer gen6_bsd_ring = {
1ec14ad3
CW		 1138 .name = "gen6 bsd ring",
1139 .id = RING_BSD,
1140 .mmio_base = GEN6_BSD_RING_BASE,
1141 .size = 32 * PAGE_SIZE,
1142 .init = init_ring_common,
1143 .write_tail = gen6_bsd_ring_write_tail,
1144 .flush = gen6_ring_flush,
1145 .add_request = gen6_add_request,
1146 .get_seqno = ring_get_seqno,
1147 .irq_get = gen6_bsd_ring_get_irq,
1148 .irq_put = gen6_bsd_ring_put_irq,
1149 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
549f7365
CW		 1150};
1151
1152/* Blitter support (SandyBridge+) */
1153
b13c2b96 1154static bool
1ec14ad3 1155blt_ring_get_irq(struct intel_ring_buffer *ring)
549f7365 1156{
0f46832f
CW		 1157 return gen6_ring_get_irq(ring,
1158 GT_BLT_USER_INTERRUPT,
1159 GEN6_BLITTER_USER_INTERRUPT);
549f7365 1160}
1ec14ad3 1161
549f7365 1162static void
1ec14ad3 1163blt_ring_put_irq(struct intel_ring_buffer *ring)
549f7365 1164{
0f46832f
CW		 1165 gen6_ring_put_irq(ring,
1166 GT_BLT_USER_INTERRUPT,
1167 GEN6_BLITTER_USER_INTERRUPT);
549f7365
CW		 1168}
1169
8d19215b
ZN		 1170
1171/* Workaround for some stepping of SNB,
1172 * each time when BLT engine ring tail moved,
1173 * the first command in the ring to be parsed
1174 * should be MI_BATCH_BUFFER_START
1175 */
1176#define NEED_BLT_WORKAROUND(dev) \
1177 (IS_GEN6(dev) && (dev->pdev->revision < 8))
1178
1179static inline struct drm_i915_gem_object *
1180to_blt_workaround(struct intel_ring_buffer *ring)
1181{
1182 return ring->private;
1183}
1184
1185static int blt_ring_init(struct intel_ring_buffer *ring)
1186{
1187 if (NEED_BLT_WORKAROUND(ring->dev)) {
1188 struct drm_i915_gem_object *obj;
27153f72 1189 u32 *ptr;
8d19215b
ZN		 1190 int ret;
1191
05394f39 1192 obj = i915_gem_alloc_object(ring->dev, 4096);
8d19215b
ZN		 1193 if (obj == NULL)
1194 return -ENOMEM;
1195
05394f39 1196 ret = i915_gem_object_pin(obj, 4096, true);
8d19215b
ZN		 1197 if (ret) {
1198 drm_gem_object_unreference(&obj->base);
1199 return ret;
1200 }
1201
1202 ptr = kmap(obj->pages[0]);
27153f72
CW		 1203 *ptr++ = MI_BATCH_BUFFER_END;
1204 *ptr++ = MI_NOOP;
8d19215b
ZN		 1205 kunmap(obj->pages[0]);
1206
05394f39 1207 ret = i915_gem_object_set_to_gtt_domain(obj, false);
8d19215b 1208 if (ret) {
05394f39 1209 i915_gem_object_unpin(obj);
8d19215b
ZN		 1210 drm_gem_object_unreference(&obj->base);
1211 return ret;
1212 }
1213
1214 ring->private = obj;
1215 }
1216
1217 return init_ring_common(ring);
1218}
1219
1220static int blt_ring_begin(struct intel_ring_buffer *ring,
1221 int num_dwords)
1222{
1223 if (ring->private) {
1224 int ret = intel_ring_begin(ring, num_dwords+2);
1225 if (ret)
1226 return ret;
1227
1228 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1229 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1230
1231 return 0;
1232 } else
1233 return intel_ring_begin(ring, 4);
1234}
1235
b72f3acb 1236static int blt_ring_flush(struct intel_ring_buffer *ring,
8d19215b
ZN		 1237 u32 invalidate_domains,
1238 u32 flush_domains)
1239{
b72f3acb
CW		 1240 int ret;
1241
1ec14ad3 1242 if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
b72f3acb 1243 return 0;
1ec14ad3 1244
b72f3acb
CW		 1245 ret = blt_ring_begin(ring, 4);
1246 if (ret)
1247 return ret;
1248
1249 intel_ring_emit(ring, MI_FLUSH_DW);
1250 intel_ring_emit(ring, 0);
1251 intel_ring_emit(ring, 0);
1252 intel_ring_emit(ring, 0);
1253 intel_ring_advance(ring);
1254 return 0;
8d19215b
ZN		 1255}
1256
8d19215b
ZN		 1257static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1258{
1259 if (!ring->private)
1260 return;
1261
1262 i915_gem_object_unpin(ring->private);
1263 drm_gem_object_unreference(ring->private);
1264 ring->private = NULL;
1265}
1266
549f7365
CW		 1267static const struct intel_ring_buffer gen6_blt_ring = {
1268 .name = "blt ring",
1269 .id = RING_BLT,
1270 .mmio_base = BLT_RING_BASE,
1271 .size = 32 * PAGE_SIZE,
8d19215b 1272 .init = blt_ring_init,
297b0c5b 1273 .write_tail = ring_write_tail,
8d19215b 1274 .flush = blt_ring_flush,
1ec14ad3
CW		 1275 .add_request = gen6_add_request,
1276 .get_seqno = ring_get_seqno,
1277 .irq_get = blt_ring_get_irq,
1278 .irq_put = blt_ring_put_irq,
78501eac 1279 .dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
8d19215b 1280 .cleanup = blt_ring_cleanup,
881f47b6
XH		 1281};
1282
5c1143bb
XH		 1283int intel_init_render_ring_buffer(struct drm_device *dev)
1284{
1285 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1286 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
5c1143bb 1287
1ec14ad3
CW		 1288 *ring = render_ring;
1289 if (INTEL_INFO(dev)->gen >= 6) {
1290 ring->add_request = gen6_add_request;
0f46832f
CW		 1291 ring->irq_get = gen6_render_ring_get_irq;
1292 ring->irq_put = gen6_render_ring_put_irq;
c6df541c
CW		 1293 } else if (IS_GEN5(dev)) {
1294 ring->add_request = pc_render_add_request;
1295 ring->get_seqno = pc_render_get_seqno;
1ec14ad3 1296 }
5c1143bb
XH		 1297
1298 if (!I915_NEED_GFX_HWS(dev)) {
1ec14ad3
CW		 1299 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1300 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
5c1143bb
XH		 1301 }
1302
1ec14ad3 1303 return intel_init_ring_buffer(dev, ring);
5c1143bb
XH		 1304}
1305
1306int intel_init_bsd_ring_buffer(struct drm_device *dev)
1307{
1308 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1309 struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
5c1143bb 1310
881f47b6 1311 if (IS_GEN6(dev))
1ec14ad3 1312 *ring = gen6_bsd_ring;
881f47b6 1313 else
1ec14ad3 1314 *ring = bsd_ring;
5c1143bb 1315
1ec14ad3 1316 return intel_init_ring_buffer(dev, ring);
5c1143bb 1317}
549f7365
CW		 1318
1319int intel_init_blt_ring_buffer(struct drm_device *dev)
1320{
1321 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1322 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
549f7365 1323
1ec14ad3 1324 *ring = gen6_blt_ring;
549f7365 1325
1ec14ad3 1326 return intel_init_ring_buffer(dev, ring);
549f7365 1327}
Linux kernel - Deliverables
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