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62fdfeaf EA |
1 | /* |
2 | * Copyright © 2008-2010 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * Zou Nan hai <nanhai.zou@intel.com> | |
26 | * Xiang Hai hao<haihao.xiang@intel.com> | |
27 | * | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | #include "drm.h" | |
62fdfeaf | 32 | #include "i915_drv.h" |
8187a2b7 | 33 | #include "i915_drm.h" |
62fdfeaf | 34 | #include "i915_trace.h" |
881f47b6 | 35 | #include "intel_drv.h" |
62fdfeaf | 36 | |
8d315287 JB |
37 | /* |
38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
39 | * over cache flushing. | |
40 | */ | |
41 | struct pipe_control { | |
42 | struct drm_i915_gem_object *obj; | |
43 | volatile u32 *cpu_page; | |
44 | u32 gtt_offset; | |
45 | }; | |
46 | ||
c7dca47b CW |
47 | static inline int ring_space(struct intel_ring_buffer *ring) |
48 | { | |
49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); | |
50 | if (space < 0) | |
51 | space += ring->size; | |
52 | return space; | |
53 | } | |
54 | ||
b72f3acb | 55 | static int |
46f0f8d1 CW |
56 | gen2_render_ring_flush(struct intel_ring_buffer *ring, |
57 | u32 invalidate_domains, | |
58 | u32 flush_domains) | |
59 | { | |
60 | u32 cmd; | |
61 | int ret; | |
62 | ||
63 | cmd = MI_FLUSH; | |
31b14c9f | 64 | if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0) |
46f0f8d1 CW |
65 | cmd |= MI_NO_WRITE_FLUSH; |
66 | ||
67 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
68 | cmd |= MI_READ_FLUSH; | |
69 | ||
70 | ret = intel_ring_begin(ring, 2); | |
71 | if (ret) | |
72 | return ret; | |
73 | ||
74 | intel_ring_emit(ring, cmd); | |
75 | intel_ring_emit(ring, MI_NOOP); | |
76 | intel_ring_advance(ring); | |
77 | ||
78 | return 0; | |
79 | } | |
80 | ||
81 | static int | |
82 | gen4_render_ring_flush(struct intel_ring_buffer *ring, | |
83 | u32 invalidate_domains, | |
84 | u32 flush_domains) | |
62fdfeaf | 85 | { |
78501eac | 86 | struct drm_device *dev = ring->dev; |
6f392d54 | 87 | u32 cmd; |
b72f3acb | 88 | int ret; |
6f392d54 | 89 | |
36d527de CW |
90 | /* |
91 | * read/write caches: | |
92 | * | |
93 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
94 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
95 | * also flushed at 2d versus 3d pipeline switches. | |
96 | * | |
97 | * read-only caches: | |
98 | * | |
99 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
100 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
101 | * | |
102 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
103 | * | |
104 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
105 | * invalidated when MI_EXE_FLUSH is set. | |
106 | * | |
107 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
108 | * invalidated with every MI_FLUSH. | |
109 | * | |
110 | * TLBs: | |
111 | * | |
112 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
113 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
114 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
115 | * are flushed at any MI_FLUSH. | |
116 | */ | |
117 | ||
118 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
46f0f8d1 | 119 | if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) |
36d527de | 120 | cmd &= ~MI_NO_WRITE_FLUSH; |
36d527de CW |
121 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
122 | cmd |= MI_EXE_FLUSH; | |
62fdfeaf | 123 | |
36d527de CW |
124 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
125 | (IS_G4X(dev) || IS_GEN5(dev))) | |
126 | cmd |= MI_INVALIDATE_ISP; | |
70eac33e | 127 | |
36d527de CW |
128 | ret = intel_ring_begin(ring, 2); |
129 | if (ret) | |
130 | return ret; | |
b72f3acb | 131 | |
36d527de CW |
132 | intel_ring_emit(ring, cmd); |
133 | intel_ring_emit(ring, MI_NOOP); | |
134 | intel_ring_advance(ring); | |
b72f3acb CW |
135 | |
136 | return 0; | |
8187a2b7 ZN |
137 | } |
138 | ||
8d315287 JB |
139 | /** |
140 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for | |
141 | * implementing two workarounds on gen6. From section 1.4.7.1 | |
142 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: | |
143 | * | |
144 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those | |
145 | * produced by non-pipelined state commands), software needs to first | |
146 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != | |
147 | * 0. | |
148 | * | |
149 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable | |
150 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. | |
151 | * | |
152 | * And the workaround for these two requires this workaround first: | |
153 | * | |
154 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent | |
155 | * BEFORE the pipe-control with a post-sync op and no write-cache | |
156 | * flushes. | |
157 | * | |
158 | * And this last workaround is tricky because of the requirements on | |
159 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM | |
160 | * volume 2 part 1: | |
161 | * | |
162 | * "1 of the following must also be set: | |
163 | * - Render Target Cache Flush Enable ([12] of DW1) | |
164 | * - Depth Cache Flush Enable ([0] of DW1) | |
165 | * - Stall at Pixel Scoreboard ([1] of DW1) | |
166 | * - Depth Stall ([13] of DW1) | |
167 | * - Post-Sync Operation ([13] of DW1) | |
168 | * - Notify Enable ([8] of DW1)" | |
169 | * | |
170 | * The cache flushes require the workaround flush that triggered this | |
171 | * one, so we can't use it. Depth stall would trigger the same. | |
172 | * Post-sync nonzero is what triggered this second workaround, so we | |
173 | * can't use that one either. Notify enable is IRQs, which aren't | |
174 | * really our business. That leaves only stall at scoreboard. | |
175 | */ | |
176 | static int | |
177 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) | |
178 | { | |
179 | struct pipe_control *pc = ring->private; | |
180 | u32 scratch_addr = pc->gtt_offset + 128; | |
181 | int ret; | |
182 | ||
183 | ||
184 | ret = intel_ring_begin(ring, 6); | |
185 | if (ret) | |
186 | return ret; | |
187 | ||
188 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
189 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | | |
190 | PIPE_CONTROL_STALL_AT_SCOREBOARD); | |
191 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
192 | intel_ring_emit(ring, 0); /* low dword */ | |
193 | intel_ring_emit(ring, 0); /* high dword */ | |
194 | intel_ring_emit(ring, MI_NOOP); | |
195 | intel_ring_advance(ring); | |
196 | ||
197 | ret = intel_ring_begin(ring, 6); | |
198 | if (ret) | |
199 | return ret; | |
200 | ||
201 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
202 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); | |
203 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ | |
204 | intel_ring_emit(ring, 0); | |
205 | intel_ring_emit(ring, 0); | |
206 | intel_ring_emit(ring, MI_NOOP); | |
207 | intel_ring_advance(ring); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
212 | static int | |
213 | gen6_render_ring_flush(struct intel_ring_buffer *ring, | |
214 | u32 invalidate_domains, u32 flush_domains) | |
215 | { | |
216 | u32 flags = 0; | |
217 | struct pipe_control *pc = ring->private; | |
218 | u32 scratch_addr = pc->gtt_offset + 128; | |
219 | int ret; | |
220 | ||
221 | /* Force SNB workarounds for PIPE_CONTROL flushes */ | |
97f209bc DV |
222 | ret = intel_emit_post_sync_nonzero_flush(ring); |
223 | if (ret) | |
224 | return ret; | |
8d315287 JB |
225 | |
226 | /* Just flush everything. Experiments have shown that reducing the | |
227 | * number of bits based on the write domains has little performance | |
228 | * impact. | |
229 | */ | |
230 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
cc0f6398 | 231 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
8d315287 JB |
232 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
233 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
234 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
235 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
236 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
237 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
97f209bc DV |
238 | /* |
239 | * Ensure that any following seqno writes only happen when the render | |
240 | * cache is indeed flushed (but only if the caller actually wants that). | |
241 | */ | |
242 | if (flush_domains) | |
243 | flags |= PIPE_CONTROL_CS_STALL; | |
8d315287 JB |
244 | |
245 | ret = intel_ring_begin(ring, 6); | |
246 | if (ret) | |
247 | return ret; | |
248 | ||
249 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); | |
250 | intel_ring_emit(ring, flags); | |
251 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); | |
252 | intel_ring_emit(ring, 0); /* lower dword */ | |
253 | intel_ring_emit(ring, 0); /* uppwer dword */ | |
254 | intel_ring_emit(ring, MI_NOOP); | |
255 | intel_ring_advance(ring); | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
78501eac | 260 | static void ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 261 | u32 value) |
d46eefa2 | 262 | { |
78501eac | 263 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
297b0c5b | 264 | I915_WRITE_TAIL(ring, value); |
d46eefa2 XH |
265 | } |
266 | ||
78501eac | 267 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
8187a2b7 | 268 | { |
78501eac CW |
269 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
270 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? | |
3d281d8c | 271 | RING_ACTHD(ring->mmio_base) : ACTHD; |
8187a2b7 ZN |
272 | |
273 | return I915_READ(acthd_reg); | |
274 | } | |
275 | ||
78501eac | 276 | static int init_ring_common(struct intel_ring_buffer *ring) |
8187a2b7 | 277 | { |
b7884eb4 DV |
278 | struct drm_device *dev = ring->dev; |
279 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 | 280 | struct drm_i915_gem_object *obj = ring->obj; |
b7884eb4 | 281 | int ret = 0; |
8187a2b7 | 282 | u32 head; |
8187a2b7 | 283 | |
b7884eb4 DV |
284 | if (HAS_FORCE_WAKE(dev)) |
285 | gen6_gt_force_wake_get(dev_priv); | |
286 | ||
8187a2b7 | 287 | /* Stop the ring if it's running. */ |
7f2ab699 | 288 | I915_WRITE_CTL(ring, 0); |
570ef608 | 289 | I915_WRITE_HEAD(ring, 0); |
78501eac | 290 | ring->write_tail(ring, 0); |
8187a2b7 ZN |
291 | |
292 | /* Initialize the ring. */ | |
05394f39 | 293 | I915_WRITE_START(ring, obj->gtt_offset); |
570ef608 | 294 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
8187a2b7 ZN |
295 | |
296 | /* G45 ring initialization fails to reset head to zero */ | |
297 | if (head != 0) { | |
6fd0d56e CW |
298 | DRM_DEBUG_KMS("%s head not reset to zero " |
299 | "ctl %08x head %08x tail %08x start %08x\n", | |
300 | ring->name, | |
301 | I915_READ_CTL(ring), | |
302 | I915_READ_HEAD(ring), | |
303 | I915_READ_TAIL(ring), | |
304 | I915_READ_START(ring)); | |
8187a2b7 | 305 | |
570ef608 | 306 | I915_WRITE_HEAD(ring, 0); |
8187a2b7 | 307 | |
6fd0d56e CW |
308 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
309 | DRM_ERROR("failed to set %s head to zero " | |
310 | "ctl %08x head %08x tail %08x start %08x\n", | |
311 | ring->name, | |
312 | I915_READ_CTL(ring), | |
313 | I915_READ_HEAD(ring), | |
314 | I915_READ_TAIL(ring), | |
315 | I915_READ_START(ring)); | |
316 | } | |
8187a2b7 ZN |
317 | } |
318 | ||
7f2ab699 | 319 | I915_WRITE_CTL(ring, |
ae69b42a | 320 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
5d031e5b | 321 | | RING_VALID); |
8187a2b7 | 322 | |
8187a2b7 | 323 | /* If the head is still not zero, the ring is dead */ |
f01db988 SP |
324 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
325 | I915_READ_START(ring) == obj->gtt_offset && | |
326 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { | |
e74cfed5 CW |
327 | DRM_ERROR("%s initialization failed " |
328 | "ctl %08x head %08x tail %08x start %08x\n", | |
329 | ring->name, | |
330 | I915_READ_CTL(ring), | |
331 | I915_READ_HEAD(ring), | |
332 | I915_READ_TAIL(ring), | |
333 | I915_READ_START(ring)); | |
b7884eb4 DV |
334 | ret = -EIO; |
335 | goto out; | |
8187a2b7 ZN |
336 | } |
337 | ||
78501eac CW |
338 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
339 | i915_kernel_lost_context(ring->dev); | |
8187a2b7 | 340 | else { |
c7dca47b | 341 | ring->head = I915_READ_HEAD(ring); |
870e86dd | 342 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
c7dca47b | 343 | ring->space = ring_space(ring); |
c3b20037 | 344 | ring->last_retired_head = -1; |
8187a2b7 | 345 | } |
1ec14ad3 | 346 | |
b7884eb4 DV |
347 | out: |
348 | if (HAS_FORCE_WAKE(dev)) | |
349 | gen6_gt_force_wake_put(dev_priv); | |
350 | ||
351 | return ret; | |
8187a2b7 ZN |
352 | } |
353 | ||
c6df541c CW |
354 | static int |
355 | init_pipe_control(struct intel_ring_buffer *ring) | |
356 | { | |
357 | struct pipe_control *pc; | |
358 | struct drm_i915_gem_object *obj; | |
359 | int ret; | |
360 | ||
361 | if (ring->private) | |
362 | return 0; | |
363 | ||
364 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); | |
365 | if (!pc) | |
366 | return -ENOMEM; | |
367 | ||
368 | obj = i915_gem_alloc_object(ring->dev, 4096); | |
369 | if (obj == NULL) { | |
370 | DRM_ERROR("Failed to allocate seqno page\n"); | |
371 | ret = -ENOMEM; | |
372 | goto err; | |
373 | } | |
e4ffd173 CW |
374 | |
375 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
c6df541c CW |
376 | |
377 | ret = i915_gem_object_pin(obj, 4096, true); | |
378 | if (ret) | |
379 | goto err_unref; | |
380 | ||
381 | pc->gtt_offset = obj->gtt_offset; | |
382 | pc->cpu_page = kmap(obj->pages[0]); | |
383 | if (pc->cpu_page == NULL) | |
384 | goto err_unpin; | |
385 | ||
386 | pc->obj = obj; | |
387 | ring->private = pc; | |
388 | return 0; | |
389 | ||
390 | err_unpin: | |
391 | i915_gem_object_unpin(obj); | |
392 | err_unref: | |
393 | drm_gem_object_unreference(&obj->base); | |
394 | err: | |
395 | kfree(pc); | |
396 | return ret; | |
397 | } | |
398 | ||
399 | static void | |
400 | cleanup_pipe_control(struct intel_ring_buffer *ring) | |
401 | { | |
402 | struct pipe_control *pc = ring->private; | |
403 | struct drm_i915_gem_object *obj; | |
404 | ||
405 | if (!ring->private) | |
406 | return; | |
407 | ||
408 | obj = pc->obj; | |
409 | kunmap(obj->pages[0]); | |
410 | i915_gem_object_unpin(obj); | |
411 | drm_gem_object_unreference(&obj->base); | |
412 | ||
413 | kfree(pc); | |
414 | ring->private = NULL; | |
415 | } | |
416 | ||
78501eac | 417 | static int init_render_ring(struct intel_ring_buffer *ring) |
8187a2b7 | 418 | { |
78501eac | 419 | struct drm_device *dev = ring->dev; |
1ec14ad3 | 420 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 421 | int ret = init_ring_common(ring); |
a69ffdbf | 422 | |
a6c45cf0 | 423 | if (INTEL_INFO(dev)->gen > 3) { |
6b26c86d | 424 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); |
b095cd0a JB |
425 | if (IS_GEN7(dev)) |
426 | I915_WRITE(GFX_MODE_GEN7, | |
6b26c86d DV |
427 | _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
428 | _MASKED_BIT_ENABLE(GFX_REPLAY_MODE)); | |
8187a2b7 | 429 | } |
78501eac | 430 | |
8d315287 | 431 | if (INTEL_INFO(dev)->gen >= 5) { |
c6df541c CW |
432 | ret = init_pipe_control(ring); |
433 | if (ret) | |
434 | return ret; | |
435 | } | |
436 | ||
5e13a0c5 | 437 | if (IS_GEN6(dev)) { |
3a69ddd6 KG |
438 | /* From the Sandybridge PRM, volume 1 part 3, page 24: |
439 | * "If this bit is set, STCunit will have LRA as replacement | |
440 | * policy. [...] This bit must be reset. LRA replacement | |
441 | * policy is not supported." | |
442 | */ | |
443 | I915_WRITE(CACHE_MODE_0, | |
5e13a0c5 | 444 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
12b0286f BW |
445 | |
446 | /* This is not explicitly set for GEN6, so read the register. | |
447 | * see intel_ring_mi_set_context() for why we care. | |
448 | * TODO: consider explicitly setting the bit for GEN5 | |
449 | */ | |
450 | ring->itlb_before_ctx_switch = | |
451 | !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS); | |
84f9f938 BW |
452 | } |
453 | ||
6b26c86d DV |
454 | if (INTEL_INFO(dev)->gen >= 6) |
455 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); | |
84f9f938 | 456 | |
15b9f80e BW |
457 | if (IS_IVYBRIDGE(dev)) |
458 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); | |
459 | ||
8187a2b7 ZN |
460 | return ret; |
461 | } | |
462 | ||
c6df541c CW |
463 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
464 | { | |
465 | if (!ring->private) | |
466 | return; | |
467 | ||
468 | cleanup_pipe_control(ring); | |
469 | } | |
470 | ||
1ec14ad3 | 471 | static void |
c8c99b0f BW |
472 | update_mboxes(struct intel_ring_buffer *ring, |
473 | u32 seqno, | |
474 | u32 mmio_offset) | |
1ec14ad3 | 475 | { |
c8c99b0f BW |
476 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
477 | MI_SEMAPHORE_GLOBAL_GTT | | |
478 | MI_SEMAPHORE_REGISTER | | |
479 | MI_SEMAPHORE_UPDATE); | |
1ec14ad3 | 480 | intel_ring_emit(ring, seqno); |
c8c99b0f | 481 | intel_ring_emit(ring, mmio_offset); |
1ec14ad3 CW |
482 | } |
483 | ||
c8c99b0f BW |
484 | /** |
485 | * gen6_add_request - Update the semaphore mailbox registers | |
486 | * | |
487 | * @ring - ring that is adding a request | |
488 | * @seqno - return seqno stuck into the ring | |
489 | * | |
490 | * Update the mailbox registers in the *other* rings with the current seqno. | |
491 | * This acts like a signal in the canonical semaphore. | |
492 | */ | |
1ec14ad3 CW |
493 | static int |
494 | gen6_add_request(struct intel_ring_buffer *ring, | |
c8c99b0f | 495 | u32 *seqno) |
1ec14ad3 | 496 | { |
c8c99b0f BW |
497 | u32 mbox1_reg; |
498 | u32 mbox2_reg; | |
1ec14ad3 CW |
499 | int ret; |
500 | ||
501 | ret = intel_ring_begin(ring, 10); | |
502 | if (ret) | |
503 | return ret; | |
504 | ||
c8c99b0f BW |
505 | mbox1_reg = ring->signal_mbox[0]; |
506 | mbox2_reg = ring->signal_mbox[1]; | |
1ec14ad3 | 507 | |
53d227f2 | 508 | *seqno = i915_gem_next_request_seqno(ring); |
c8c99b0f BW |
509 | |
510 | update_mboxes(ring, *seqno, mbox1_reg); | |
511 | update_mboxes(ring, *seqno, mbox2_reg); | |
1ec14ad3 CW |
512 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
513 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
c8c99b0f | 514 | intel_ring_emit(ring, *seqno); |
1ec14ad3 CW |
515 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
516 | intel_ring_advance(ring); | |
517 | ||
1ec14ad3 CW |
518 | return 0; |
519 | } | |
520 | ||
c8c99b0f BW |
521 | /** |
522 | * intel_ring_sync - sync the waiter to the signaller on seqno | |
523 | * | |
524 | * @waiter - ring that is waiting | |
525 | * @signaller - ring which has, or will signal | |
526 | * @seqno - seqno which the waiter will block on | |
527 | */ | |
528 | static int | |
686cb5f9 DV |
529 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
530 | struct intel_ring_buffer *signaller, | |
531 | u32 seqno) | |
1ec14ad3 CW |
532 | { |
533 | int ret; | |
c8c99b0f BW |
534 | u32 dw1 = MI_SEMAPHORE_MBOX | |
535 | MI_SEMAPHORE_COMPARE | | |
536 | MI_SEMAPHORE_REGISTER; | |
1ec14ad3 | 537 | |
1500f7ea BW |
538 | /* Throughout all of the GEM code, seqno passed implies our current |
539 | * seqno is >= the last seqno executed. However for hardware the | |
540 | * comparison is strictly greater than. | |
541 | */ | |
542 | seqno -= 1; | |
543 | ||
686cb5f9 DV |
544 | WARN_ON(signaller->semaphore_register[waiter->id] == |
545 | MI_SEMAPHORE_SYNC_INVALID); | |
546 | ||
c8c99b0f | 547 | ret = intel_ring_begin(waiter, 4); |
1ec14ad3 CW |
548 | if (ret) |
549 | return ret; | |
550 | ||
686cb5f9 DV |
551 | intel_ring_emit(waiter, |
552 | dw1 | signaller->semaphore_register[waiter->id]); | |
c8c99b0f BW |
553 | intel_ring_emit(waiter, seqno); |
554 | intel_ring_emit(waiter, 0); | |
555 | intel_ring_emit(waiter, MI_NOOP); | |
556 | intel_ring_advance(waiter); | |
1ec14ad3 CW |
557 | |
558 | return 0; | |
559 | } | |
560 | ||
c6df541c CW |
561 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
562 | do { \ | |
fcbc34e4 KG |
563 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
564 | PIPE_CONTROL_DEPTH_STALL); \ | |
c6df541c CW |
565 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
566 | intel_ring_emit(ring__, 0); \ | |
567 | intel_ring_emit(ring__, 0); \ | |
568 | } while (0) | |
569 | ||
570 | static int | |
571 | pc_render_add_request(struct intel_ring_buffer *ring, | |
572 | u32 *result) | |
573 | { | |
53d227f2 | 574 | u32 seqno = i915_gem_next_request_seqno(ring); |
c6df541c CW |
575 | struct pipe_control *pc = ring->private; |
576 | u32 scratch_addr = pc->gtt_offset + 128; | |
577 | int ret; | |
578 | ||
579 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently | |
580 | * incoherent with writes to memory, i.e. completely fubar, | |
581 | * so we need to use PIPE_NOTIFY instead. | |
582 | * | |
583 | * However, we also need to workaround the qword write | |
584 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to | |
585 | * memory before requesting an interrupt. | |
586 | */ | |
587 | ret = intel_ring_begin(ring, 32); | |
588 | if (ret) | |
589 | return ret; | |
590 | ||
fcbc34e4 | 591 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
592 | PIPE_CONTROL_WRITE_FLUSH | |
593 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); | |
c6df541c CW |
594 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
595 | intel_ring_emit(ring, seqno); | |
596 | intel_ring_emit(ring, 0); | |
597 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
598 | scratch_addr += 128; /* write to separate cachelines */ | |
599 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
600 | scratch_addr += 128; | |
601 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
602 | scratch_addr += 128; | |
603 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
604 | scratch_addr += 128; | |
605 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
606 | scratch_addr += 128; | |
607 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | |
a71d8d94 | 608 | |
fcbc34e4 | 609 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
9d971b37 KG |
610 | PIPE_CONTROL_WRITE_FLUSH | |
611 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | | |
c6df541c CW |
612 | PIPE_CONTROL_NOTIFY); |
613 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | |
614 | intel_ring_emit(ring, seqno); | |
615 | intel_ring_emit(ring, 0); | |
616 | intel_ring_advance(ring); | |
617 | ||
618 | *result = seqno; | |
619 | return 0; | |
620 | } | |
621 | ||
4cd53c0c DV |
622 | static u32 |
623 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) | |
624 | { | |
625 | struct drm_device *dev = ring->dev; | |
626 | ||
627 | /* Workaround to force correct ordering between irq and seqno writes on | |
628 | * ivb (and maybe also on snb) by reading from a CS register (like | |
629 | * ACTHD) before reading the status page. */ | |
1c7eaac7 | 630 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
4cd53c0c DV |
631 | intel_ring_get_active_head(ring); |
632 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
633 | } | |
634 | ||
8187a2b7 | 635 | static u32 |
1ec14ad3 | 636 | ring_get_seqno(struct intel_ring_buffer *ring) |
8187a2b7 | 637 | { |
1ec14ad3 CW |
638 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
639 | } | |
640 | ||
c6df541c CW |
641 | static u32 |
642 | pc_render_get_seqno(struct intel_ring_buffer *ring) | |
643 | { | |
644 | struct pipe_control *pc = ring->private; | |
645 | return pc->cpu_page[0]; | |
646 | } | |
647 | ||
e48d8634 DV |
648 | static bool |
649 | gen5_ring_get_irq(struct intel_ring_buffer *ring) | |
650 | { | |
651 | struct drm_device *dev = ring->dev; | |
652 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 653 | unsigned long flags; |
e48d8634 DV |
654 | |
655 | if (!dev->irq_enabled) | |
656 | return false; | |
657 | ||
7338aefa | 658 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
659 | if (ring->irq_refcount++ == 0) { |
660 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; | |
661 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
662 | POSTING_READ(GTIMR); | |
663 | } | |
7338aefa | 664 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
665 | |
666 | return true; | |
667 | } | |
668 | ||
669 | static void | |
670 | gen5_ring_put_irq(struct intel_ring_buffer *ring) | |
671 | { | |
672 | struct drm_device *dev = ring->dev; | |
673 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 674 | unsigned long flags; |
e48d8634 | 675 | |
7338aefa | 676 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
677 | if (--ring->irq_refcount == 0) { |
678 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; | |
679 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
680 | POSTING_READ(GTIMR); | |
681 | } | |
7338aefa | 682 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
e48d8634 DV |
683 | } |
684 | ||
b13c2b96 | 685 | static bool |
e3670319 | 686 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 687 | { |
78501eac | 688 | struct drm_device *dev = ring->dev; |
01a03331 | 689 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 690 | unsigned long flags; |
62fdfeaf | 691 | |
b13c2b96 CW |
692 | if (!dev->irq_enabled) |
693 | return false; | |
694 | ||
7338aefa | 695 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
696 | if (ring->irq_refcount++ == 0) { |
697 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
698 | I915_WRITE(IMR, dev_priv->irq_mask); | |
699 | POSTING_READ(IMR); | |
700 | } | |
7338aefa | 701 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
b13c2b96 CW |
702 | |
703 | return true; | |
62fdfeaf EA |
704 | } |
705 | ||
8187a2b7 | 706 | static void |
e3670319 | 707 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
62fdfeaf | 708 | { |
78501eac | 709 | struct drm_device *dev = ring->dev; |
01a03331 | 710 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 711 | unsigned long flags; |
62fdfeaf | 712 | |
7338aefa | 713 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
f637fde4 DV |
714 | if (--ring->irq_refcount == 0) { |
715 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
716 | I915_WRITE(IMR, dev_priv->irq_mask); | |
717 | POSTING_READ(IMR); | |
718 | } | |
7338aefa | 719 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
62fdfeaf EA |
720 | } |
721 | ||
c2798b19 CW |
722 | static bool |
723 | i8xx_ring_get_irq(struct intel_ring_buffer *ring) | |
724 | { | |
725 | struct drm_device *dev = ring->dev; | |
726 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 727 | unsigned long flags; |
c2798b19 CW |
728 | |
729 | if (!dev->irq_enabled) | |
730 | return false; | |
731 | ||
7338aefa | 732 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
733 | if (ring->irq_refcount++ == 0) { |
734 | dev_priv->irq_mask &= ~ring->irq_enable_mask; | |
735 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
736 | POSTING_READ16(IMR); | |
737 | } | |
7338aefa | 738 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
739 | |
740 | return true; | |
741 | } | |
742 | ||
743 | static void | |
744 | i8xx_ring_put_irq(struct intel_ring_buffer *ring) | |
745 | { | |
746 | struct drm_device *dev = ring->dev; | |
747 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7338aefa | 748 | unsigned long flags; |
c2798b19 | 749 | |
7338aefa | 750 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
c2798b19 CW |
751 | if (--ring->irq_refcount == 0) { |
752 | dev_priv->irq_mask |= ring->irq_enable_mask; | |
753 | I915_WRITE16(IMR, dev_priv->irq_mask); | |
754 | POSTING_READ16(IMR); | |
755 | } | |
7338aefa | 756 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
c2798b19 CW |
757 | } |
758 | ||
78501eac | 759 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
8187a2b7 | 760 | { |
4593010b | 761 | struct drm_device *dev = ring->dev; |
78501eac | 762 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
4593010b EA |
763 | u32 mmio = 0; |
764 | ||
765 | /* The ring status page addresses are no longer next to the rest of | |
766 | * the ring registers as of gen7. | |
767 | */ | |
768 | if (IS_GEN7(dev)) { | |
769 | switch (ring->id) { | |
96154f2f | 770 | case RCS: |
4593010b EA |
771 | mmio = RENDER_HWS_PGA_GEN7; |
772 | break; | |
96154f2f | 773 | case BCS: |
4593010b EA |
774 | mmio = BLT_HWS_PGA_GEN7; |
775 | break; | |
96154f2f | 776 | case VCS: |
4593010b EA |
777 | mmio = BSD_HWS_PGA_GEN7; |
778 | break; | |
779 | } | |
780 | } else if (IS_GEN6(ring->dev)) { | |
781 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); | |
782 | } else { | |
783 | mmio = RING_HWS_PGA(ring->mmio_base); | |
784 | } | |
785 | ||
78501eac CW |
786 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
787 | POSTING_READ(mmio); | |
8187a2b7 ZN |
788 | } |
789 | ||
b72f3acb | 790 | static int |
78501eac CW |
791 | bsd_ring_flush(struct intel_ring_buffer *ring, |
792 | u32 invalidate_domains, | |
793 | u32 flush_domains) | |
d1b851fc | 794 | { |
b72f3acb CW |
795 | int ret; |
796 | ||
b72f3acb CW |
797 | ret = intel_ring_begin(ring, 2); |
798 | if (ret) | |
799 | return ret; | |
800 | ||
801 | intel_ring_emit(ring, MI_FLUSH); | |
802 | intel_ring_emit(ring, MI_NOOP); | |
803 | intel_ring_advance(ring); | |
804 | return 0; | |
d1b851fc ZN |
805 | } |
806 | ||
3cce469c | 807 | static int |
8620a3a9 | 808 | i9xx_add_request(struct intel_ring_buffer *ring, |
3cce469c | 809 | u32 *result) |
d1b851fc ZN |
810 | { |
811 | u32 seqno; | |
3cce469c CW |
812 | int ret; |
813 | ||
814 | ret = intel_ring_begin(ring, 4); | |
815 | if (ret) | |
816 | return ret; | |
6f392d54 | 817 | |
53d227f2 | 818 | seqno = i915_gem_next_request_seqno(ring); |
6f392d54 | 819 | |
3cce469c CW |
820 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
821 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
822 | intel_ring_emit(ring, seqno); | |
823 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
824 | intel_ring_advance(ring); | |
d1b851fc | 825 | |
3cce469c CW |
826 | *result = seqno; |
827 | return 0; | |
d1b851fc ZN |
828 | } |
829 | ||
0f46832f | 830 | static bool |
25c06300 | 831 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
832 | { |
833 | struct drm_device *dev = ring->dev; | |
01a03331 | 834 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 835 | unsigned long flags; |
0f46832f CW |
836 | |
837 | if (!dev->irq_enabled) | |
838 | return false; | |
839 | ||
4cd53c0c DV |
840 | /* It looks like we need to prevent the gt from suspending while waiting |
841 | * for an notifiy irq, otherwise irqs seem to get lost on at least the | |
842 | * blt/bsd rings on ivb. */ | |
99ffa162 | 843 | gen6_gt_force_wake_get(dev_priv); |
4cd53c0c | 844 | |
7338aefa | 845 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 846 | if (ring->irq_refcount++ == 0) { |
15b9f80e BW |
847 | if (IS_IVYBRIDGE(dev) && ring->id == RCS) |
848 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | | |
849 | GEN6_RENDER_L3_PARITY_ERROR)); | |
850 | else | |
851 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); | |
f637fde4 DV |
852 | dev_priv->gt_irq_mask &= ~ring->irq_enable_mask; |
853 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
854 | POSTING_READ(GTIMR); | |
0f46832f | 855 | } |
7338aefa | 856 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
0f46832f CW |
857 | |
858 | return true; | |
859 | } | |
860 | ||
861 | static void | |
25c06300 | 862 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
0f46832f CW |
863 | { |
864 | struct drm_device *dev = ring->dev; | |
01a03331 | 865 | drm_i915_private_t *dev_priv = dev->dev_private; |
7338aefa | 866 | unsigned long flags; |
0f46832f | 867 | |
7338aefa | 868 | spin_lock_irqsave(&dev_priv->irq_lock, flags); |
01a03331 | 869 | if (--ring->irq_refcount == 0) { |
15b9f80e BW |
870 | if (IS_IVYBRIDGE(dev) && ring->id == RCS) |
871 | I915_WRITE_IMR(ring, ~GEN6_RENDER_L3_PARITY_ERROR); | |
872 | else | |
873 | I915_WRITE_IMR(ring, ~0); | |
f637fde4 DV |
874 | dev_priv->gt_irq_mask |= ring->irq_enable_mask; |
875 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); | |
876 | POSTING_READ(GTIMR); | |
1ec14ad3 | 877 | } |
7338aefa | 878 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); |
4cd53c0c | 879 | |
99ffa162 | 880 | gen6_gt_force_wake_put(dev_priv); |
d1b851fc ZN |
881 | } |
882 | ||
d1b851fc | 883 | static int |
fb3256da | 884 | i965_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
d1b851fc | 885 | { |
e1f99ce6 | 886 | int ret; |
78501eac | 887 | |
e1f99ce6 CW |
888 | ret = intel_ring_begin(ring, 2); |
889 | if (ret) | |
890 | return ret; | |
891 | ||
78501eac | 892 | intel_ring_emit(ring, |
65f56876 CW |
893 | MI_BATCH_BUFFER_START | |
894 | MI_BATCH_GTT | | |
78501eac | 895 | MI_BATCH_NON_SECURE_I965); |
c4e7a414 | 896 | intel_ring_emit(ring, offset); |
78501eac CW |
897 | intel_ring_advance(ring); |
898 | ||
d1b851fc ZN |
899 | return 0; |
900 | } | |
901 | ||
8187a2b7 | 902 | static int |
fb3256da | 903 | i830_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 904 | u32 offset, u32 len) |
62fdfeaf | 905 | { |
c4e7a414 | 906 | int ret; |
62fdfeaf | 907 | |
fb3256da DV |
908 | ret = intel_ring_begin(ring, 4); |
909 | if (ret) | |
910 | return ret; | |
62fdfeaf | 911 | |
fb3256da DV |
912 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
913 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); | |
914 | intel_ring_emit(ring, offset + len - 8); | |
915 | intel_ring_emit(ring, 0); | |
916 | intel_ring_advance(ring); | |
e1f99ce6 | 917 | |
fb3256da DV |
918 | return 0; |
919 | } | |
920 | ||
921 | static int | |
922 | i915_dispatch_execbuffer(struct intel_ring_buffer *ring, | |
923 | u32 offset, u32 len) | |
924 | { | |
925 | int ret; | |
926 | ||
927 | ret = intel_ring_begin(ring, 2); | |
928 | if (ret) | |
929 | return ret; | |
930 | ||
65f56876 | 931 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); |
fb3256da | 932 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
c4e7a414 | 933 | intel_ring_advance(ring); |
62fdfeaf | 934 | |
62fdfeaf EA |
935 | return 0; |
936 | } | |
937 | ||
78501eac | 938 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 939 | { |
05394f39 | 940 | struct drm_i915_gem_object *obj; |
62fdfeaf | 941 | |
8187a2b7 ZN |
942 | obj = ring->status_page.obj; |
943 | if (obj == NULL) | |
62fdfeaf | 944 | return; |
62fdfeaf | 945 | |
05394f39 | 946 | kunmap(obj->pages[0]); |
62fdfeaf | 947 | i915_gem_object_unpin(obj); |
05394f39 | 948 | drm_gem_object_unreference(&obj->base); |
8187a2b7 | 949 | ring->status_page.obj = NULL; |
62fdfeaf EA |
950 | } |
951 | ||
78501eac | 952 | static int init_status_page(struct intel_ring_buffer *ring) |
62fdfeaf | 953 | { |
78501eac | 954 | struct drm_device *dev = ring->dev; |
05394f39 | 955 | struct drm_i915_gem_object *obj; |
62fdfeaf EA |
956 | int ret; |
957 | ||
62fdfeaf EA |
958 | obj = i915_gem_alloc_object(dev, 4096); |
959 | if (obj == NULL) { | |
960 | DRM_ERROR("Failed to allocate status page\n"); | |
961 | ret = -ENOMEM; | |
962 | goto err; | |
963 | } | |
e4ffd173 CW |
964 | |
965 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); | |
62fdfeaf | 966 | |
75e9e915 | 967 | ret = i915_gem_object_pin(obj, 4096, true); |
62fdfeaf | 968 | if (ret != 0) { |
62fdfeaf EA |
969 | goto err_unref; |
970 | } | |
971 | ||
05394f39 CW |
972 | ring->status_page.gfx_addr = obj->gtt_offset; |
973 | ring->status_page.page_addr = kmap(obj->pages[0]); | |
8187a2b7 | 974 | if (ring->status_page.page_addr == NULL) { |
62fdfeaf EA |
975 | goto err_unpin; |
976 | } | |
8187a2b7 ZN |
977 | ring->status_page.obj = obj; |
978 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
62fdfeaf | 979 | |
78501eac | 980 | intel_ring_setup_status_page(ring); |
8187a2b7 ZN |
981 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
982 | ring->name, ring->status_page.gfx_addr); | |
62fdfeaf EA |
983 | |
984 | return 0; | |
985 | ||
986 | err_unpin: | |
987 | i915_gem_object_unpin(obj); | |
988 | err_unref: | |
05394f39 | 989 | drm_gem_object_unreference(&obj->base); |
62fdfeaf | 990 | err: |
8187a2b7 | 991 | return ret; |
62fdfeaf EA |
992 | } |
993 | ||
c43b5634 BW |
994 | static int intel_init_ring_buffer(struct drm_device *dev, |
995 | struct intel_ring_buffer *ring) | |
62fdfeaf | 996 | { |
05394f39 | 997 | struct drm_i915_gem_object *obj; |
dd2757f8 | 998 | struct drm_i915_private *dev_priv = dev->dev_private; |
dd785e35 CW |
999 | int ret; |
1000 | ||
8187a2b7 | 1001 | ring->dev = dev; |
23bc5982 CW |
1002 | INIT_LIST_HEAD(&ring->active_list); |
1003 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 | 1004 | INIT_LIST_HEAD(&ring->gpu_write_list); |
dfc9ef2f | 1005 | ring->size = 32 * PAGE_SIZE; |
0dc79fb2 | 1006 | |
b259f673 | 1007 | init_waitqueue_head(&ring->irq_queue); |
62fdfeaf | 1008 | |
8187a2b7 | 1009 | if (I915_NEED_GFX_HWS(dev)) { |
78501eac | 1010 | ret = init_status_page(ring); |
8187a2b7 ZN |
1011 | if (ret) |
1012 | return ret; | |
1013 | } | |
62fdfeaf | 1014 | |
8187a2b7 | 1015 | obj = i915_gem_alloc_object(dev, ring->size); |
62fdfeaf EA |
1016 | if (obj == NULL) { |
1017 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
8187a2b7 | 1018 | ret = -ENOMEM; |
dd785e35 | 1019 | goto err_hws; |
62fdfeaf | 1020 | } |
62fdfeaf | 1021 | |
05394f39 | 1022 | ring->obj = obj; |
8187a2b7 | 1023 | |
75e9e915 | 1024 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
dd785e35 CW |
1025 | if (ret) |
1026 | goto err_unref; | |
62fdfeaf | 1027 | |
3eef8918 CW |
1028 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1029 | if (ret) | |
1030 | goto err_unpin; | |
1031 | ||
dd2757f8 DV |
1032 | ring->virtual_start = |
1033 | ioremap_wc(dev_priv->mm.gtt->gma_bus_addr + obj->gtt_offset, | |
1034 | ring->size); | |
4225d0f2 | 1035 | if (ring->virtual_start == NULL) { |
62fdfeaf | 1036 | DRM_ERROR("Failed to map ringbuffer.\n"); |
8187a2b7 | 1037 | ret = -EINVAL; |
dd785e35 | 1038 | goto err_unpin; |
62fdfeaf EA |
1039 | } |
1040 | ||
78501eac | 1041 | ret = ring->init(ring); |
dd785e35 CW |
1042 | if (ret) |
1043 | goto err_unmap; | |
62fdfeaf | 1044 | |
55249baa CW |
1045 | /* Workaround an erratum on the i830 which causes a hang if |
1046 | * the TAIL pointer points to within the last 2 cachelines | |
1047 | * of the buffer. | |
1048 | */ | |
1049 | ring->effective_size = ring->size; | |
27c1cbd0 | 1050 | if (IS_I830(ring->dev) || IS_845G(ring->dev)) |
55249baa CW |
1051 | ring->effective_size -= 128; |
1052 | ||
c584fe47 | 1053 | return 0; |
dd785e35 CW |
1054 | |
1055 | err_unmap: | |
4225d0f2 | 1056 | iounmap(ring->virtual_start); |
dd785e35 CW |
1057 | err_unpin: |
1058 | i915_gem_object_unpin(obj); | |
1059 | err_unref: | |
05394f39 CW |
1060 | drm_gem_object_unreference(&obj->base); |
1061 | ring->obj = NULL; | |
dd785e35 | 1062 | err_hws: |
78501eac | 1063 | cleanup_status_page(ring); |
8187a2b7 | 1064 | return ret; |
62fdfeaf EA |
1065 | } |
1066 | ||
78501eac | 1067 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1068 | { |
33626e6a CW |
1069 | struct drm_i915_private *dev_priv; |
1070 | int ret; | |
1071 | ||
05394f39 | 1072 | if (ring->obj == NULL) |
62fdfeaf EA |
1073 | return; |
1074 | ||
33626e6a CW |
1075 | /* Disable the ring buffer. The ring must be idle at this point */ |
1076 | dev_priv = ring->dev->dev_private; | |
96f298aa | 1077 | ret = intel_wait_ring_idle(ring); |
29ee3991 CW |
1078 | if (ret) |
1079 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
1080 | ring->name, ret); | |
1081 | ||
33626e6a CW |
1082 | I915_WRITE_CTL(ring, 0); |
1083 | ||
4225d0f2 | 1084 | iounmap(ring->virtual_start); |
62fdfeaf | 1085 | |
05394f39 CW |
1086 | i915_gem_object_unpin(ring->obj); |
1087 | drm_gem_object_unreference(&ring->obj->base); | |
1088 | ring->obj = NULL; | |
78501eac | 1089 | |
8d19215b ZN |
1090 | if (ring->cleanup) |
1091 | ring->cleanup(ring); | |
1092 | ||
78501eac | 1093 | cleanup_status_page(ring); |
62fdfeaf EA |
1094 | } |
1095 | ||
78501eac | 1096 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
62fdfeaf | 1097 | { |
4225d0f2 | 1098 | uint32_t __iomem *virt; |
55249baa | 1099 | int rem = ring->size - ring->tail; |
62fdfeaf | 1100 | |
8187a2b7 | 1101 | if (ring->space < rem) { |
78501eac | 1102 | int ret = intel_wait_ring_buffer(ring, rem); |
62fdfeaf EA |
1103 | if (ret) |
1104 | return ret; | |
1105 | } | |
62fdfeaf | 1106 | |
4225d0f2 DV |
1107 | virt = ring->virtual_start + ring->tail; |
1108 | rem /= 4; | |
1109 | while (rem--) | |
1110 | iowrite32(MI_NOOP, virt++); | |
62fdfeaf | 1111 | |
8187a2b7 | 1112 | ring->tail = 0; |
c7dca47b | 1113 | ring->space = ring_space(ring); |
62fdfeaf EA |
1114 | |
1115 | return 0; | |
1116 | } | |
1117 | ||
a71d8d94 CW |
1118 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
1119 | { | |
1120 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
1121 | bool was_interruptible; | |
1122 | int ret; | |
1123 | ||
1124 | /* XXX As we have not yet audited all the paths to check that | |
1125 | * they are ready for ERESTARTSYS from intel_ring_begin, do not | |
1126 | * allow us to be interruptible by a signal. | |
1127 | */ | |
1128 | was_interruptible = dev_priv->mm.interruptible; | |
1129 | dev_priv->mm.interruptible = false; | |
1130 | ||
199b2bc2 | 1131 | ret = i915_wait_seqno(ring, seqno); |
a71d8d94 CW |
1132 | |
1133 | dev_priv->mm.interruptible = was_interruptible; | |
b2da9fe5 BW |
1134 | if (!ret) |
1135 | i915_gem_retire_requests_ring(ring); | |
a71d8d94 CW |
1136 | |
1137 | return ret; | |
1138 | } | |
1139 | ||
1140 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) | |
1141 | { | |
1142 | struct drm_i915_gem_request *request; | |
1143 | u32 seqno = 0; | |
1144 | int ret; | |
1145 | ||
1146 | i915_gem_retire_requests_ring(ring); | |
1147 | ||
1148 | if (ring->last_retired_head != -1) { | |
1149 | ring->head = ring->last_retired_head; | |
1150 | ring->last_retired_head = -1; | |
1151 | ring->space = ring_space(ring); | |
1152 | if (ring->space >= n) | |
1153 | return 0; | |
1154 | } | |
1155 | ||
1156 | list_for_each_entry(request, &ring->request_list, list) { | |
1157 | int space; | |
1158 | ||
1159 | if (request->tail == -1) | |
1160 | continue; | |
1161 | ||
1162 | space = request->tail - (ring->tail + 8); | |
1163 | if (space < 0) | |
1164 | space += ring->size; | |
1165 | if (space >= n) { | |
1166 | seqno = request->seqno; | |
1167 | break; | |
1168 | } | |
1169 | ||
1170 | /* Consume this request in case we need more space than | |
1171 | * is available and so need to prevent a race between | |
1172 | * updating last_retired_head and direct reads of | |
1173 | * I915_RING_HEAD. It also provides a nice sanity check. | |
1174 | */ | |
1175 | request->tail = -1; | |
1176 | } | |
1177 | ||
1178 | if (seqno == 0) | |
1179 | return -ENOSPC; | |
1180 | ||
1181 | ret = intel_ring_wait_seqno(ring, seqno); | |
1182 | if (ret) | |
1183 | return ret; | |
1184 | ||
1185 | if (WARN_ON(ring->last_retired_head == -1)) | |
1186 | return -ENOSPC; | |
1187 | ||
1188 | ring->head = ring->last_retired_head; | |
1189 | ring->last_retired_head = -1; | |
1190 | ring->space = ring_space(ring); | |
1191 | if (WARN_ON(ring->space < n)) | |
1192 | return -ENOSPC; | |
1193 | ||
1194 | return 0; | |
1195 | } | |
1196 | ||
78501eac | 1197 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
62fdfeaf | 1198 | { |
78501eac | 1199 | struct drm_device *dev = ring->dev; |
cae5852d | 1200 | struct drm_i915_private *dev_priv = dev->dev_private; |
78501eac | 1201 | unsigned long end; |
a71d8d94 | 1202 | int ret; |
c7dca47b | 1203 | |
a71d8d94 CW |
1204 | ret = intel_ring_wait_request(ring, n); |
1205 | if (ret != -ENOSPC) | |
1206 | return ret; | |
1207 | ||
db53a302 | 1208 | trace_i915_ring_wait_begin(ring); |
63ed2cb2 DV |
1209 | /* With GEM the hangcheck timer should kick us out of the loop, |
1210 | * leaving it early runs the risk of corrupting GEM state (due | |
1211 | * to running on almost untested codepaths). But on resume | |
1212 | * timers don't work yet, so prevent a complete hang in that | |
1213 | * case by choosing an insanely large timeout. */ | |
1214 | end = jiffies + 60 * HZ; | |
e6bfaf85 | 1215 | |
8187a2b7 | 1216 | do { |
c7dca47b CW |
1217 | ring->head = I915_READ_HEAD(ring); |
1218 | ring->space = ring_space(ring); | |
62fdfeaf | 1219 | if (ring->space >= n) { |
db53a302 | 1220 | trace_i915_ring_wait_end(ring); |
62fdfeaf EA |
1221 | return 0; |
1222 | } | |
1223 | ||
1224 | if (dev->primary->master) { | |
1225 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; | |
1226 | if (master_priv->sarea_priv) | |
1227 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1228 | } | |
d1b851fc | 1229 | |
e60a0b10 | 1230 | msleep(1); |
f4e0b29b CW |
1231 | if (atomic_read(&dev_priv->mm.wedged)) |
1232 | return -EAGAIN; | |
8187a2b7 | 1233 | } while (!time_after(jiffies, end)); |
db53a302 | 1234 | trace_i915_ring_wait_end(ring); |
8187a2b7 ZN |
1235 | return -EBUSY; |
1236 | } | |
62fdfeaf | 1237 | |
e1f99ce6 CW |
1238 | int intel_ring_begin(struct intel_ring_buffer *ring, |
1239 | int num_dwords) | |
8187a2b7 | 1240 | { |
21dd3734 | 1241 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
be26a10b | 1242 | int n = 4*num_dwords; |
e1f99ce6 | 1243 | int ret; |
78501eac | 1244 | |
21dd3734 CW |
1245 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
1246 | return -EIO; | |
1247 | ||
55249baa | 1248 | if (unlikely(ring->tail + n > ring->effective_size)) { |
e1f99ce6 CW |
1249 | ret = intel_wrap_ring_buffer(ring); |
1250 | if (unlikely(ret)) | |
1251 | return ret; | |
1252 | } | |
78501eac | 1253 | |
e1f99ce6 CW |
1254 | if (unlikely(ring->space < n)) { |
1255 | ret = intel_wait_ring_buffer(ring, n); | |
1256 | if (unlikely(ret)) | |
1257 | return ret; | |
1258 | } | |
d97ed339 CW |
1259 | |
1260 | ring->space -= n; | |
e1f99ce6 | 1261 | return 0; |
8187a2b7 | 1262 | } |
62fdfeaf | 1263 | |
78501eac | 1264 | void intel_ring_advance(struct intel_ring_buffer *ring) |
8187a2b7 | 1265 | { |
e5eb3d63 DV |
1266 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
1267 | ||
d97ed339 | 1268 | ring->tail &= ring->size - 1; |
e5eb3d63 DV |
1269 | if (dev_priv->stop_rings & intel_ring_flag(ring)) |
1270 | return; | |
78501eac | 1271 | ring->write_tail(ring, ring->tail); |
8187a2b7 | 1272 | } |
62fdfeaf | 1273 | |
881f47b6 | 1274 | |
78501eac | 1275 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
297b0c5b | 1276 | u32 value) |
881f47b6 | 1277 | { |
0206e353 | 1278 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
881f47b6 XH |
1279 | |
1280 | /* Every tail move must follow the sequence below */ | |
0206e353 AJ |
1281 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
1282 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
1283 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); | |
1284 | I915_WRITE(GEN6_BSD_RNCID, 0x0); | |
1285 | ||
1286 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & | |
1287 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, | |
1288 | 50)) | |
1289 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); | |
1290 | ||
1291 | I915_WRITE_TAIL(ring, value); | |
1292 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, | |
1293 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | | |
1294 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); | |
881f47b6 XH |
1295 | } |
1296 | ||
b72f3acb | 1297 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1298 | u32 invalidate, u32 flush) |
881f47b6 | 1299 | { |
71a77e07 | 1300 | uint32_t cmd; |
b72f3acb CW |
1301 | int ret; |
1302 | ||
b72f3acb CW |
1303 | ret = intel_ring_begin(ring, 4); |
1304 | if (ret) | |
1305 | return ret; | |
1306 | ||
71a77e07 CW |
1307 | cmd = MI_FLUSH_DW; |
1308 | if (invalidate & I915_GEM_GPU_DOMAINS) | |
1309 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; | |
1310 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1311 | intel_ring_emit(ring, 0); |
1312 | intel_ring_emit(ring, 0); | |
71a77e07 | 1313 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1314 | intel_ring_advance(ring); |
1315 | return 0; | |
881f47b6 XH |
1316 | } |
1317 | ||
1318 | static int | |
78501eac | 1319 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
c4e7a414 | 1320 | u32 offset, u32 len) |
881f47b6 | 1321 | { |
0206e353 | 1322 | int ret; |
ab6f8e32 | 1323 | |
0206e353 AJ |
1324 | ret = intel_ring_begin(ring, 2); |
1325 | if (ret) | |
1326 | return ret; | |
e1f99ce6 | 1327 | |
0206e353 AJ |
1328 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
1329 | /* bit0-7 is the length on GEN6+ */ | |
1330 | intel_ring_emit(ring, offset); | |
1331 | intel_ring_advance(ring); | |
ab6f8e32 | 1332 | |
0206e353 | 1333 | return 0; |
881f47b6 XH |
1334 | } |
1335 | ||
549f7365 CW |
1336 | /* Blitter support (SandyBridge+) */ |
1337 | ||
b72f3acb | 1338 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
71a77e07 | 1339 | u32 invalidate, u32 flush) |
8d19215b | 1340 | { |
71a77e07 | 1341 | uint32_t cmd; |
b72f3acb CW |
1342 | int ret; |
1343 | ||
6a233c78 | 1344 | ret = intel_ring_begin(ring, 4); |
b72f3acb CW |
1345 | if (ret) |
1346 | return ret; | |
1347 | ||
71a77e07 CW |
1348 | cmd = MI_FLUSH_DW; |
1349 | if (invalidate & I915_GEM_DOMAIN_RENDER) | |
1350 | cmd |= MI_INVALIDATE_TLB; | |
1351 | intel_ring_emit(ring, cmd); | |
b72f3acb CW |
1352 | intel_ring_emit(ring, 0); |
1353 | intel_ring_emit(ring, 0); | |
71a77e07 | 1354 | intel_ring_emit(ring, MI_NOOP); |
b72f3acb CW |
1355 | intel_ring_advance(ring); |
1356 | return 0; | |
8d19215b ZN |
1357 | } |
1358 | ||
5c1143bb XH |
1359 | int intel_init_render_ring_buffer(struct drm_device *dev) |
1360 | { | |
1361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1362 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
5c1143bb | 1363 | |
59465b5f DV |
1364 | ring->name = "render ring"; |
1365 | ring->id = RCS; | |
1366 | ring->mmio_base = RENDER_RING_BASE; | |
1367 | ||
1ec14ad3 CW |
1368 | if (INTEL_INFO(dev)->gen >= 6) { |
1369 | ring->add_request = gen6_add_request; | |
8d315287 | 1370 | ring->flush = gen6_render_ring_flush; |
25c06300 BW |
1371 | ring->irq_get = gen6_ring_get_irq; |
1372 | ring->irq_put = gen6_ring_put_irq; | |
6a848ccb | 1373 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
4cd53c0c | 1374 | ring->get_seqno = gen6_ring_get_seqno; |
686cb5f9 | 1375 | ring->sync_to = gen6_ring_sync; |
59465b5f DV |
1376 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
1377 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; | |
1378 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; | |
1379 | ring->signal_mbox[0] = GEN6_VRSYNC; | |
1380 | ring->signal_mbox[1] = GEN6_BRSYNC; | |
c6df541c CW |
1381 | } else if (IS_GEN5(dev)) { |
1382 | ring->add_request = pc_render_add_request; | |
46f0f8d1 | 1383 | ring->flush = gen4_render_ring_flush; |
c6df541c | 1384 | ring->get_seqno = pc_render_get_seqno; |
e48d8634 DV |
1385 | ring->irq_get = gen5_ring_get_irq; |
1386 | ring->irq_put = gen5_ring_put_irq; | |
e3670319 | 1387 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
59465b5f | 1388 | } else { |
8620a3a9 | 1389 | ring->add_request = i9xx_add_request; |
46f0f8d1 CW |
1390 | if (INTEL_INFO(dev)->gen < 4) |
1391 | ring->flush = gen2_render_ring_flush; | |
1392 | else | |
1393 | ring->flush = gen4_render_ring_flush; | |
59465b5f | 1394 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1395 | if (IS_GEN2(dev)) { |
1396 | ring->irq_get = i8xx_ring_get_irq; | |
1397 | ring->irq_put = i8xx_ring_put_irq; | |
1398 | } else { | |
1399 | ring->irq_get = i9xx_ring_get_irq; | |
1400 | ring->irq_put = i9xx_ring_put_irq; | |
1401 | } | |
e3670319 | 1402 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
1ec14ad3 | 1403 | } |
59465b5f | 1404 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1405 | if (INTEL_INFO(dev)->gen >= 6) |
1406 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
1407 | else if (INTEL_INFO(dev)->gen >= 4) | |
1408 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1409 | else if (IS_I830(dev) || IS_845G(dev)) | |
1410 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1411 | else | |
1412 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1413 | ring->init = init_render_ring; |
1414 | ring->cleanup = render_ring_cleanup; | |
1415 | ||
5c1143bb XH |
1416 | |
1417 | if (!I915_NEED_GFX_HWS(dev)) { | |
1ec14ad3 CW |
1418 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
1419 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); | |
5c1143bb XH |
1420 | } |
1421 | ||
1ec14ad3 | 1422 | return intel_init_ring_buffer(dev, ring); |
5c1143bb XH |
1423 | } |
1424 | ||
e8616b6c CW |
1425 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
1426 | { | |
1427 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1428 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; | |
1429 | ||
59465b5f DV |
1430 | ring->name = "render ring"; |
1431 | ring->id = RCS; | |
1432 | ring->mmio_base = RENDER_RING_BASE; | |
1433 | ||
e8616b6c | 1434 | if (INTEL_INFO(dev)->gen >= 6) { |
b4178f8a DV |
1435 | /* non-kms not supported on gen6+ */ |
1436 | return -ENODEV; | |
e8616b6c | 1437 | } |
28f0cbf7 DV |
1438 | |
1439 | /* Note: gem is not supported on gen5/ilk without kms (the corresponding | |
1440 | * gem_init ioctl returns with -ENODEV). Hence we do not need to set up | |
1441 | * the special gen5 functions. */ | |
1442 | ring->add_request = i9xx_add_request; | |
46f0f8d1 CW |
1443 | if (INTEL_INFO(dev)->gen < 4) |
1444 | ring->flush = gen2_render_ring_flush; | |
1445 | else | |
1446 | ring->flush = gen4_render_ring_flush; | |
28f0cbf7 | 1447 | ring->get_seqno = ring_get_seqno; |
c2798b19 CW |
1448 | if (IS_GEN2(dev)) { |
1449 | ring->irq_get = i8xx_ring_get_irq; | |
1450 | ring->irq_put = i8xx_ring_put_irq; | |
1451 | } else { | |
1452 | ring->irq_get = i9xx_ring_get_irq; | |
1453 | ring->irq_put = i9xx_ring_put_irq; | |
1454 | } | |
28f0cbf7 | 1455 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
59465b5f | 1456 | ring->write_tail = ring_write_tail; |
fb3256da DV |
1457 | if (INTEL_INFO(dev)->gen >= 4) |
1458 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; | |
1459 | else if (IS_I830(dev) || IS_845G(dev)) | |
1460 | ring->dispatch_execbuffer = i830_dispatch_execbuffer; | |
1461 | else | |
1462 | ring->dispatch_execbuffer = i915_dispatch_execbuffer; | |
59465b5f DV |
1463 | ring->init = init_render_ring; |
1464 | ring->cleanup = render_ring_cleanup; | |
e8616b6c | 1465 | |
f3234706 KP |
1466 | if (!I915_NEED_GFX_HWS(dev)) |
1467 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; | |
1468 | ||
e8616b6c CW |
1469 | ring->dev = dev; |
1470 | INIT_LIST_HEAD(&ring->active_list); | |
1471 | INIT_LIST_HEAD(&ring->request_list); | |
1472 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
1473 | ||
1474 | ring->size = size; | |
1475 | ring->effective_size = ring->size; | |
1476 | if (IS_I830(ring->dev)) | |
1477 | ring->effective_size -= 128; | |
1478 | ||
4225d0f2 DV |
1479 | ring->virtual_start = ioremap_wc(start, size); |
1480 | if (ring->virtual_start == NULL) { | |
e8616b6c CW |
1481 | DRM_ERROR("can not ioremap virtual address for" |
1482 | " ring buffer\n"); | |
1483 | return -ENOMEM; | |
1484 | } | |
1485 | ||
e8616b6c CW |
1486 | return 0; |
1487 | } | |
1488 | ||
5c1143bb XH |
1489 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
1490 | { | |
1491 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1492 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
5c1143bb | 1493 | |
58fa3835 DV |
1494 | ring->name = "bsd ring"; |
1495 | ring->id = VCS; | |
1496 | ||
0fd2c201 | 1497 | ring->write_tail = ring_write_tail; |
58fa3835 DV |
1498 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1499 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
0fd2c201 DV |
1500 | /* gen6 bsd needs a special wa for tail updates */ |
1501 | if (IS_GEN6(dev)) | |
1502 | ring->write_tail = gen6_bsd_ring_write_tail; | |
58fa3835 DV |
1503 | ring->flush = gen6_ring_flush; |
1504 | ring->add_request = gen6_add_request; | |
1505 | ring->get_seqno = gen6_ring_get_seqno; | |
1506 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; | |
1507 | ring->irq_get = gen6_ring_get_irq; | |
1508 | ring->irq_put = gen6_ring_put_irq; | |
1509 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1510 | ring->sync_to = gen6_ring_sync; |
58fa3835 DV |
1511 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
1512 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; | |
1513 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; | |
1514 | ring->signal_mbox[0] = GEN6_RVSYNC; | |
1515 | ring->signal_mbox[1] = GEN6_BVSYNC; | |
1516 | } else { | |
1517 | ring->mmio_base = BSD_RING_BASE; | |
58fa3835 | 1518 | ring->flush = bsd_ring_flush; |
8620a3a9 | 1519 | ring->add_request = i9xx_add_request; |
58fa3835 | 1520 | ring->get_seqno = ring_get_seqno; |
e48d8634 | 1521 | if (IS_GEN5(dev)) { |
e3670319 | 1522 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
e48d8634 DV |
1523 | ring->irq_get = gen5_ring_get_irq; |
1524 | ring->irq_put = gen5_ring_put_irq; | |
1525 | } else { | |
e3670319 | 1526 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
e48d8634 DV |
1527 | ring->irq_get = i9xx_ring_get_irq; |
1528 | ring->irq_put = i9xx_ring_put_irq; | |
1529 | } | |
fb3256da | 1530 | ring->dispatch_execbuffer = i965_dispatch_execbuffer; |
58fa3835 DV |
1531 | } |
1532 | ring->init = init_ring_common; | |
1533 | ||
5c1143bb | 1534 | |
1ec14ad3 | 1535 | return intel_init_ring_buffer(dev, ring); |
5c1143bb | 1536 | } |
549f7365 CW |
1537 | |
1538 | int intel_init_blt_ring_buffer(struct drm_device *dev) | |
1539 | { | |
1540 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1541 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
549f7365 | 1542 | |
3535d9dd DV |
1543 | ring->name = "blitter ring"; |
1544 | ring->id = BCS; | |
1545 | ||
1546 | ring->mmio_base = BLT_RING_BASE; | |
1547 | ring->write_tail = ring_write_tail; | |
1548 | ring->flush = blt_ring_flush; | |
1549 | ring->add_request = gen6_add_request; | |
1550 | ring->get_seqno = gen6_ring_get_seqno; | |
1551 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; | |
1552 | ring->irq_get = gen6_ring_get_irq; | |
1553 | ring->irq_put = gen6_ring_put_irq; | |
1554 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; | |
686cb5f9 | 1555 | ring->sync_to = gen6_ring_sync; |
3535d9dd DV |
1556 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
1557 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; | |
1558 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; | |
1559 | ring->signal_mbox[0] = GEN6_RBSYNC; | |
1560 | ring->signal_mbox[1] = GEN6_VBSYNC; | |
1561 | ring->init = init_ring_common; | |
549f7365 | 1562 | |
1ec14ad3 | 1563 | return intel_init_ring_buffer(dev, ring); |
549f7365 | 1564 | } |