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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
79e53945 JB |
32 | #include "drmP.h" |
33 | #include "drm.h" | |
34 | #include "drm_crtc.h" | |
2b8d33f7 | 35 | #include "drm_edid.h" |
ea5b213a | 36 | #include "intel_drv.h" |
79e53945 JB |
37 | #include "i915_drm.h" |
38 | #include "i915_drv.h" | |
39 | #include "intel_sdvo_regs.h" | |
40 | ||
14571b4c ZW |
41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
a0b1c7a5 | 44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
14571b4c ZW |
45 | |
46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 47 | SDVO_TV_MASK) |
14571b4c ZW |
48 | |
49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 54 | |
79e53945 | 55 | |
2e88e40b | 56 | static const char *tv_format_names[] = { |
ce6feabd ZY |
57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
58 | "PAL_B" , "PAL_D" , "PAL_G" , | |
59 | "PAL_H" , "PAL_I" , "PAL_M" , | |
60 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
63 | "SECAM_60" | |
64 | }; | |
65 | ||
66 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
67 | ||
ea5b213a CW |
68 | struct intel_sdvo { |
69 | struct intel_encoder base; | |
70 | ||
f899fc64 | 71 | struct i2c_adapter *i2c; |
f9c10a9b | 72 | u8 slave_addr; |
e2f0ba97 | 73 | |
e957d772 CW |
74 | struct i2c_adapter ddc; |
75 | ||
e2f0ba97 | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
eef4eacb | 77 | uint32_t sdvo_reg; |
79e53945 | 78 | |
e2f0ba97 JB |
79 | /* Active outputs controlled by this SDVO output */ |
80 | uint16_t controlled_output; | |
79e53945 | 81 | |
e2f0ba97 JB |
82 | /* |
83 | * Capabilities of the SDVO device returned by | |
84 | * i830_sdvo_get_capabilities() | |
85 | */ | |
79e53945 | 86 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
87 | |
88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
89 | int pixel_clock_min, pixel_clock_max; |
90 | ||
fb7a46f3 | 91 | /* |
92 | * For multiple function SDVO device, | |
93 | * this is for current attached outputs. | |
94 | */ | |
95 | uint16_t attached_output; | |
96 | ||
cc68c81a SF |
97 | /* |
98 | * Hotplug activation bits for this device | |
99 | */ | |
100 | uint8_t hotplug_active[2]; | |
101 | ||
e953fd7b CW |
102 | /** |
103 | * This is used to select the color range of RBG outputs in HDMI mode. | |
104 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
105 | */ | |
106 | uint32_t color_range; | |
107 | ||
e2f0ba97 JB |
108 | /** |
109 | * This is set if we're going to treat the device as TV-out. | |
110 | * | |
111 | * While we have these nice friendly flags for output types that ought | |
112 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
113 | * shows up as RGB1 (VGA). | |
114 | */ | |
115 | bool is_tv; | |
116 | ||
eef4eacb DV |
117 | /* On different gens SDVOB is at different places. */ |
118 | bool is_sdvob; | |
119 | ||
ce6feabd | 120 | /* This is for current tv format name */ |
40039750 | 121 | int tv_format_index; |
ce6feabd | 122 | |
e2f0ba97 JB |
123 | /** |
124 | * This is set if we treat the device as HDMI, instead of DVI. | |
125 | */ | |
126 | bool is_hdmi; | |
da79de97 CW |
127 | bool has_hdmi_monitor; |
128 | bool has_hdmi_audio; | |
12682a97 | 129 | |
7086c87f | 130 | /** |
6c9547ff CW |
131 | * This is set if we detect output of sdvo device as LVDS and |
132 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
133 | */ |
134 | bool is_lvds; | |
e2f0ba97 | 135 | |
12682a97 | 136 | /** |
137 | * This is sdvo fixed pannel mode pointer | |
138 | */ | |
139 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
140 | ||
c751ce4f | 141 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 | 142 | uint8_t ddc_bus; |
14571b4c ZW |
143 | }; |
144 | ||
145 | struct intel_sdvo_connector { | |
615fb93f CW |
146 | struct intel_connector base; |
147 | ||
14571b4c ZW |
148 | /* Mark the type of connector */ |
149 | uint16_t output_flag; | |
150 | ||
c3e5f67b | 151 | enum hdmi_force_audio force_audio; |
7f36e7ed | 152 | |
14571b4c | 153 | /* This contains all current supported TV format */ |
40039750 | 154 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 155 | int format_supported_num; |
c5521706 | 156 | struct drm_property *tv_format; |
14571b4c | 157 | |
b9219c5e | 158 | /* add the property for the SDVO-TV */ |
c5521706 CW |
159 | struct drm_property *left; |
160 | struct drm_property *right; | |
161 | struct drm_property *top; | |
162 | struct drm_property *bottom; | |
163 | struct drm_property *hpos; | |
164 | struct drm_property *vpos; | |
165 | struct drm_property *contrast; | |
166 | struct drm_property *saturation; | |
167 | struct drm_property *hue; | |
168 | struct drm_property *sharpness; | |
169 | struct drm_property *flicker_filter; | |
170 | struct drm_property *flicker_filter_adaptive; | |
171 | struct drm_property *flicker_filter_2d; | |
172 | struct drm_property *tv_chroma_filter; | |
173 | struct drm_property *tv_luma_filter; | |
e044218a | 174 | struct drm_property *dot_crawl; |
b9219c5e ZY |
175 | |
176 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 177 | struct drm_property *brightness; |
b9219c5e ZY |
178 | |
179 | /* Add variable to record current setting for the above property */ | |
180 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 181 | |
b9219c5e ZY |
182 | /* this is to get the range of margin.*/ |
183 | u32 max_hscan, max_vscan; | |
184 | u32 max_hpos, cur_hpos; | |
185 | u32 max_vpos, cur_vpos; | |
186 | u32 cur_brightness, max_brightness; | |
187 | u32 cur_contrast, max_contrast; | |
188 | u32 cur_saturation, max_saturation; | |
189 | u32 cur_hue, max_hue; | |
c5521706 CW |
190 | u32 cur_sharpness, max_sharpness; |
191 | u32 cur_flicker_filter, max_flicker_filter; | |
192 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
193 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
194 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
195 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 196 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
197 | }; |
198 | ||
890f3359 | 199 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
ea5b213a | 200 | { |
4ef69c7a | 201 | return container_of(encoder, struct intel_sdvo, base.base); |
ea5b213a CW |
202 | } |
203 | ||
df0e9248 CW |
204 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
205 | { | |
206 | return container_of(intel_attached_encoder(connector), | |
207 | struct intel_sdvo, base); | |
208 | } | |
209 | ||
615fb93f CW |
210 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
211 | { | |
212 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
213 | } | |
214 | ||
fb7a46f3 | 215 | static bool |
ea5b213a | 216 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
217 | static bool |
218 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
219 | struct intel_sdvo_connector *intel_sdvo_connector, | |
220 | int type); | |
221 | static bool | |
222 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
223 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 224 | |
79e53945 JB |
225 | /** |
226 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
227 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
228 | * comments in the BIOS). | |
229 | */ | |
ea5b213a | 230 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 231 | { |
4ef69c7a | 232 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 233 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
234 | u32 bval = val, cval = val; |
235 | int i; | |
236 | ||
ea5b213a CW |
237 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
238 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
239 | I915_READ(intel_sdvo->sdvo_reg); | |
461ed3ca ZY |
240 | return; |
241 | } | |
242 | ||
ea5b213a | 243 | if (intel_sdvo->sdvo_reg == SDVOB) { |
79e53945 JB |
244 | cval = I915_READ(SDVOC); |
245 | } else { | |
246 | bval = I915_READ(SDVOB); | |
247 | } | |
248 | /* | |
249 | * Write the registers twice for luck. Sometimes, | |
250 | * writing them only once doesn't appear to 'stick'. | |
251 | * The BIOS does this too. Yay, magic | |
252 | */ | |
253 | for (i = 0; i < 2; i++) | |
254 | { | |
255 | I915_WRITE(SDVOB, bval); | |
256 | I915_READ(SDVOB); | |
257 | I915_WRITE(SDVOC, cval); | |
258 | I915_READ(SDVOC); | |
259 | } | |
260 | } | |
261 | ||
32aad86f | 262 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 263 | { |
79e53945 JB |
264 | struct i2c_msg msgs[] = { |
265 | { | |
e957d772 | 266 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
267 | .flags = 0, |
268 | .len = 1, | |
e957d772 | 269 | .buf = &addr, |
79e53945 JB |
270 | }, |
271 | { | |
e957d772 | 272 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
273 | .flags = I2C_M_RD, |
274 | .len = 1, | |
e957d772 | 275 | .buf = ch, |
79e53945 JB |
276 | } |
277 | }; | |
32aad86f | 278 | int ret; |
79e53945 | 279 | |
f899fc64 | 280 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 281 | return true; |
79e53945 | 282 | |
8a4c47f3 | 283 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
284 | return false; |
285 | } | |
286 | ||
79e53945 JB |
287 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
288 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 289 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 290 | u8 cmd; |
2e88e40b | 291 | const char *name; |
79e53945 | 292 | } sdvo_cmd_names[] = { |
0206e353 AJ |
293 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
294 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
295 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
296 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
297 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
298 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
336 | ||
337 | /* Add the op code for SDVO enhancements */ | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
342 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
343 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
382 | ||
383 | /* HDMI op code */ | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
388 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
389 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
404 | }; |
405 | ||
eef4eacb | 406 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
79e53945 | 407 | |
ea5b213a | 408 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 409 | const void *args, int args_len) |
79e53945 | 410 | { |
79e53945 JB |
411 | int i; |
412 | ||
8a4c47f3 | 413 | DRM_DEBUG_KMS("%s: W: %02X ", |
ea5b213a | 414 | SDVO_NAME(intel_sdvo), cmd); |
79e53945 | 415 | for (i = 0; i < args_len; i++) |
342dc382 | 416 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
79e53945 | 417 | for (; i < 8; i++) |
342dc382 | 418 | DRM_LOG_KMS(" "); |
04ad327f | 419 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 420 | if (cmd == sdvo_cmd_names[i].cmd) { |
342dc382 | 421 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
422 | break; |
423 | } | |
424 | } | |
04ad327f | 425 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
342dc382 | 426 | DRM_LOG_KMS("(%02X)", cmd); |
427 | DRM_LOG_KMS("\n"); | |
79e53945 | 428 | } |
79e53945 | 429 | |
e957d772 CW |
430 | static const char *cmd_status_names[] = { |
431 | "Power on", | |
432 | "Success", | |
433 | "Not supported", | |
434 | "Invalid arg", | |
435 | "Pending", | |
436 | "Target not specified", | |
437 | "Scaling not supported" | |
438 | }; | |
439 | ||
32aad86f CW |
440 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
441 | const void *args, int args_len) | |
79e53945 | 442 | { |
3bf3f452 BW |
443 | u8 *buf, status; |
444 | struct i2c_msg *msgs; | |
445 | int i, ret = true; | |
446 | ||
0274df3e | 447 | /* Would be simpler to allocate both in one go ? */ |
3bf3f452 BW |
448 | buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL); |
449 | if (!buf) | |
450 | return false; | |
451 | ||
452 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); | |
0274df3e AC |
453 | if (!msgs) { |
454 | kfree(buf); | |
3bf3f452 | 455 | return false; |
0274df3e | 456 | } |
79e53945 | 457 | |
ea5b213a | 458 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
459 | |
460 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
461 | msgs[i].addr = intel_sdvo->slave_addr; |
462 | msgs[i].flags = 0; | |
463 | msgs[i].len = 2; | |
464 | msgs[i].buf = buf + 2 *i; | |
465 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
466 | buf[2*i + 1] = ((u8*)args)[i]; | |
467 | } | |
468 | msgs[i].addr = intel_sdvo->slave_addr; | |
469 | msgs[i].flags = 0; | |
470 | msgs[i].len = 2; | |
471 | msgs[i].buf = buf + 2*i; | |
472 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
473 | buf[2*i + 1] = cmd; | |
474 | ||
475 | /* the following two are to read the response */ | |
476 | status = SDVO_I2C_CMD_STATUS; | |
477 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
478 | msgs[i+1].flags = 0; | |
479 | msgs[i+1].len = 1; | |
480 | msgs[i+1].buf = &status; | |
481 | ||
482 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
483 | msgs[i+2].flags = I2C_M_RD; | |
484 | msgs[i+2].len = 1; | |
485 | msgs[i+2].buf = &status; | |
486 | ||
487 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
488 | if (ret < 0) { | |
489 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
3bf3f452 BW |
490 | ret = false; |
491 | goto out; | |
e957d772 CW |
492 | } |
493 | if (ret != i+3) { | |
494 | /* failure in I2C transfer */ | |
495 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
3bf3f452 | 496 | ret = false; |
e957d772 CW |
497 | } |
498 | ||
3bf3f452 BW |
499 | out: |
500 | kfree(msgs); | |
501 | kfree(buf); | |
502 | return ret; | |
79e53945 JB |
503 | } |
504 | ||
b5c616a7 CW |
505 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
506 | void *response, int response_len) | |
79e53945 | 507 | { |
b5c616a7 CW |
508 | u8 retry = 5; |
509 | u8 status; | |
33b52961 | 510 | int i; |
79e53945 | 511 | |
d121a5d2 CW |
512 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
513 | ||
b5c616a7 CW |
514 | /* |
515 | * The documentation states that all commands will be | |
516 | * processed within 15µs, and that we need only poll | |
517 | * the status byte a maximum of 3 times in order for the | |
518 | * command to be complete. | |
519 | * | |
520 | * Check 5 times in case the hardware failed to read the docs. | |
521 | */ | |
d121a5d2 CW |
522 | if (!intel_sdvo_read_byte(intel_sdvo, |
523 | SDVO_I2C_CMD_STATUS, | |
524 | &status)) | |
525 | goto log_fail; | |
526 | ||
527 | while (status == SDVO_CMD_STATUS_PENDING && retry--) { | |
528 | udelay(15); | |
b5c616a7 CW |
529 | if (!intel_sdvo_read_byte(intel_sdvo, |
530 | SDVO_I2C_CMD_STATUS, | |
531 | &status)) | |
d121a5d2 CW |
532 | goto log_fail; |
533 | } | |
b5c616a7 | 534 | |
79e53945 | 535 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
342dc382 | 536 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
79e53945 | 537 | else |
342dc382 | 538 | DRM_LOG_KMS("(??? %d)", status); |
79e53945 | 539 | |
b5c616a7 CW |
540 | if (status != SDVO_CMD_STATUS_SUCCESS) |
541 | goto log_fail; | |
79e53945 | 542 | |
b5c616a7 CW |
543 | /* Read the command response */ |
544 | for (i = 0; i < response_len; i++) { | |
545 | if (!intel_sdvo_read_byte(intel_sdvo, | |
546 | SDVO_I2C_RETURN_0 + i, | |
547 | &((u8 *)response)[i])) | |
548 | goto log_fail; | |
e957d772 | 549 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 550 | } |
b5c616a7 | 551 | DRM_LOG_KMS("\n"); |
b5c616a7 | 552 | return true; |
79e53945 | 553 | |
b5c616a7 | 554 | log_fail: |
d121a5d2 | 555 | DRM_LOG_KMS("... failed\n"); |
b5c616a7 | 556 | return false; |
79e53945 JB |
557 | } |
558 | ||
b358d0a6 | 559 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
560 | { |
561 | if (mode->clock >= 100000) | |
562 | return 1; | |
563 | else if (mode->clock >= 50000) | |
564 | return 2; | |
565 | else | |
566 | return 4; | |
567 | } | |
568 | ||
e957d772 CW |
569 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
570 | u8 ddc_bus) | |
79e53945 | 571 | { |
d121a5d2 | 572 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
573 | return intel_sdvo_write_cmd(intel_sdvo, |
574 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
575 | &ddc_bus, 1); | |
79e53945 JB |
576 | } |
577 | ||
32aad86f | 578 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 579 | { |
d121a5d2 CW |
580 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
581 | return false; | |
582 | ||
583 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 584 | } |
79e53945 | 585 | |
32aad86f CW |
586 | static bool |
587 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
588 | { | |
589 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
590 | return false; | |
79e53945 | 591 | |
32aad86f CW |
592 | return intel_sdvo_read_response(intel_sdvo, value, len); |
593 | } | |
79e53945 | 594 | |
32aad86f CW |
595 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
596 | { | |
597 | struct intel_sdvo_set_target_input_args targets = {0}; | |
598 | return intel_sdvo_set_value(intel_sdvo, | |
599 | SDVO_CMD_SET_TARGET_INPUT, | |
600 | &targets, sizeof(targets)); | |
79e53945 JB |
601 | } |
602 | ||
603 | /** | |
604 | * Return whether each input is trained. | |
605 | * | |
606 | * This function is making an assumption about the layout of the response, | |
607 | * which should be checked against the docs. | |
608 | */ | |
ea5b213a | 609 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
610 | { |
611 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 612 | |
1a3665c8 | 613 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
614 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
615 | &response, sizeof(response))) | |
79e53945 JB |
616 | return false; |
617 | ||
618 | *input_1 = response.input0_trained; | |
619 | *input_2 = response.input1_trained; | |
620 | return true; | |
621 | } | |
622 | ||
ea5b213a | 623 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
624 | u16 outputs) |
625 | { | |
32aad86f CW |
626 | return intel_sdvo_set_value(intel_sdvo, |
627 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
628 | &outputs, sizeof(outputs)); | |
79e53945 JB |
629 | } |
630 | ||
ea5b213a | 631 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
632 | int mode) |
633 | { | |
32aad86f | 634 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
635 | |
636 | switch (mode) { | |
637 | case DRM_MODE_DPMS_ON: | |
638 | state = SDVO_ENCODER_STATE_ON; | |
639 | break; | |
640 | case DRM_MODE_DPMS_STANDBY: | |
641 | state = SDVO_ENCODER_STATE_STANDBY; | |
642 | break; | |
643 | case DRM_MODE_DPMS_SUSPEND: | |
644 | state = SDVO_ENCODER_STATE_SUSPEND; | |
645 | break; | |
646 | case DRM_MODE_DPMS_OFF: | |
647 | state = SDVO_ENCODER_STATE_OFF; | |
648 | break; | |
649 | } | |
650 | ||
32aad86f CW |
651 | return intel_sdvo_set_value(intel_sdvo, |
652 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
653 | } |
654 | ||
ea5b213a | 655 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
656 | int *clock_min, |
657 | int *clock_max) | |
658 | { | |
659 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 660 | |
1a3665c8 | 661 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
662 | if (!intel_sdvo_get_value(intel_sdvo, |
663 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
664 | &clocks, sizeof(clocks))) | |
79e53945 JB |
665 | return false; |
666 | ||
667 | /* Convert the values from units of 10 kHz to kHz. */ | |
668 | *clock_min = clocks.min * 10; | |
669 | *clock_max = clocks.max * 10; | |
79e53945 JB |
670 | return true; |
671 | } | |
672 | ||
ea5b213a | 673 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
674 | u16 outputs) |
675 | { | |
32aad86f CW |
676 | return intel_sdvo_set_value(intel_sdvo, |
677 | SDVO_CMD_SET_TARGET_OUTPUT, | |
678 | &outputs, sizeof(outputs)); | |
79e53945 JB |
679 | } |
680 | ||
ea5b213a | 681 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
682 | struct intel_sdvo_dtd *dtd) |
683 | { | |
32aad86f CW |
684 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
685 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
686 | } |
687 | ||
ea5b213a | 688 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
689 | struct intel_sdvo_dtd *dtd) |
690 | { | |
ea5b213a | 691 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
692 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
693 | } | |
694 | ||
ea5b213a | 695 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
696 | struct intel_sdvo_dtd *dtd) |
697 | { | |
ea5b213a | 698 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
699 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
700 | } | |
701 | ||
e2f0ba97 | 702 | static bool |
ea5b213a | 703 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
704 | uint16_t clock, |
705 | uint16_t width, | |
706 | uint16_t height) | |
707 | { | |
708 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 709 | |
e642c6f1 | 710 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
711 | args.clock = clock; |
712 | args.width = width; | |
713 | args.height = height; | |
e642c6f1 | 714 | args.interlace = 0; |
12682a97 | 715 | |
ea5b213a CW |
716 | if (intel_sdvo->is_lvds && |
717 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
718 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 719 | args.scaled = 1; |
720 | ||
32aad86f CW |
721 | return intel_sdvo_set_value(intel_sdvo, |
722 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
723 | &args, sizeof(args)); | |
e2f0ba97 JB |
724 | } |
725 | ||
ea5b213a | 726 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
727 | struct intel_sdvo_dtd *dtd) |
728 | { | |
1a3665c8 CW |
729 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
730 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
731 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
732 | &dtd->part1, sizeof(dtd->part1)) && | |
733 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
734 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 735 | } |
79e53945 | 736 | |
ea5b213a | 737 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 738 | { |
32aad86f | 739 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
740 | } |
741 | ||
e2f0ba97 | 742 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 743 | const struct drm_display_mode *mode) |
79e53945 | 744 | { |
e2f0ba97 JB |
745 | uint16_t width, height; |
746 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
747 | uint16_t h_sync_offset, v_sync_offset; | |
6651819b | 748 | int mode_clock; |
79e53945 | 749 | |
c6ebd4c0 DV |
750 | width = mode->hdisplay; |
751 | height = mode->vdisplay; | |
79e53945 JB |
752 | |
753 | /* do some mode translations */ | |
c6ebd4c0 DV |
754 | h_blank_len = mode->htotal - mode->hdisplay; |
755 | h_sync_len = mode->hsync_end - mode->hsync_start; | |
79e53945 | 756 | |
c6ebd4c0 DV |
757 | v_blank_len = mode->vtotal - mode->vdisplay; |
758 | v_sync_len = mode->vsync_end - mode->vsync_start; | |
79e53945 | 759 | |
c6ebd4c0 DV |
760 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
761 | v_sync_offset = mode->vsync_start - mode->vdisplay; | |
79e53945 | 762 | |
6651819b DV |
763 | mode_clock = mode->clock; |
764 | mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1; | |
765 | mode_clock /= 10; | |
766 | dtd->part1.clock = mode_clock; | |
767 | ||
e2f0ba97 JB |
768 | dtd->part1.h_active = width & 0xff; |
769 | dtd->part1.h_blank = h_blank_len & 0xff; | |
770 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 771 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
772 | dtd->part1.v_active = height & 0xff; |
773 | dtd->part1.v_blank = v_blank_len & 0xff; | |
774 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
775 | ((v_blank_len >> 8) & 0xf); |
776 | ||
171a9e96 | 777 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
778 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
779 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 780 | (v_sync_len & 0xf); |
e2f0ba97 | 781 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
782 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
783 | ((v_sync_len & 0x30) >> 4); | |
784 | ||
e2f0ba97 | 785 | dtd->part2.dtd_flags = 0x18; |
59d92bfa DV |
786 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
787 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; | |
79e53945 | 788 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
59d92bfa | 789 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
79e53945 | 790 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
59d92bfa | 791 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
e2f0ba97 JB |
792 | |
793 | dtd->part2.sdvo_flags = 0; | |
794 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; | |
795 | dtd->part2.reserved = 0; | |
796 | } | |
797 | ||
798 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |
32aad86f | 799 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 800 | { |
e2f0ba97 JB |
801 | mode->hdisplay = dtd->part1.h_active; |
802 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
803 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | |
171a9e96 | 804 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
e2f0ba97 JB |
805 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
806 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
807 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | |
808 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; | |
809 | ||
810 | mode->vdisplay = dtd->part1.v_active; | |
811 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
812 | mode->vsync_start = mode->vdisplay; | |
813 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
171a9e96 | 814 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
e2f0ba97 JB |
815 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
816 | mode->vsync_end = mode->vsync_start + | |
817 | (dtd->part2.v_sync_off_width & 0xf); | |
818 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; | |
819 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; | |
820 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; | |
821 | ||
822 | mode->clock = dtd->part1.clock * 10; | |
823 | ||
171a9e96 | 824 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
59d92bfa DV |
825 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
826 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
827 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) | |
e2f0ba97 | 828 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
59d92bfa | 829 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
e2f0ba97 JB |
830 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
831 | } | |
832 | ||
e27d8538 | 833 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 834 | { |
e27d8538 | 835 | struct intel_sdvo_encode encode; |
e2f0ba97 | 836 | |
1a3665c8 | 837 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
838 | return intel_sdvo_get_value(intel_sdvo, |
839 | SDVO_CMD_GET_SUPP_ENCODE, | |
840 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
841 | } |
842 | ||
ea5b213a | 843 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 844 | uint8_t mode) |
e2f0ba97 | 845 | { |
32aad86f | 846 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
847 | } |
848 | ||
ea5b213a | 849 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
850 | uint8_t mode) |
851 | { | |
32aad86f | 852 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
853 | } |
854 | ||
855 | #if 0 | |
ea5b213a | 856 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
857 | { |
858 | int i, j; | |
859 | uint8_t set_buf_index[2]; | |
860 | uint8_t av_split; | |
861 | uint8_t buf_size; | |
862 | uint8_t buf[48]; | |
863 | uint8_t *pos; | |
864 | ||
32aad86f | 865 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
866 | |
867 | for (i = 0; i <= av_split; i++) { | |
868 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 869 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 870 | set_buf_index, 2); |
c751ce4f EA |
871 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
872 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
873 | |
874 | pos = buf; | |
875 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 876 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 877 | NULL, 0); |
c751ce4f | 878 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
879 | pos += 8; |
880 | } | |
881 | } | |
882 | } | |
883 | #endif | |
884 | ||
3c17fe4b | 885 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
886 | { |
887 | struct dip_infoframe avi_if = { | |
888 | .type = DIP_TYPE_AVI, | |
3c17fe4b | 889 | .ver = DIP_VERSION_AVI, |
e2f0ba97 JB |
890 | .len = DIP_LEN_AVI, |
891 | }; | |
3c17fe4b DH |
892 | uint8_t tx_rate = SDVO_HBUF_TX_VSYNC; |
893 | uint8_t set_buf_index[2] = { 1, 0 }; | |
81014b9d DV |
894 | uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; |
895 | uint64_t *data = (uint64_t *)sdvo_data; | |
3c17fe4b DH |
896 | unsigned i; |
897 | ||
898 | intel_dip_infoframe_csum(&avi_if); | |
899 | ||
81014b9d DV |
900 | /* sdvo spec says that the ecc is handled by the hw, and it looks like |
901 | * we must not send the ecc field, either. */ | |
902 | memcpy(sdvo_data, &avi_if, 3); | |
903 | sdvo_data[3] = avi_if.checksum; | |
904 | memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi)); | |
905 | ||
d121a5d2 CW |
906 | if (!intel_sdvo_set_value(intel_sdvo, |
907 | SDVO_CMD_SET_HBUF_INDEX, | |
3c17fe4b DH |
908 | set_buf_index, 2)) |
909 | return false; | |
910 | ||
81014b9d | 911 | for (i = 0; i < sizeof(sdvo_data); i += 8) { |
d121a5d2 CW |
912 | if (!intel_sdvo_set_value(intel_sdvo, |
913 | SDVO_CMD_SET_HBUF_DATA, | |
3c17fe4b DH |
914 | data, 8)) |
915 | return false; | |
916 | data++; | |
917 | } | |
e2f0ba97 | 918 | |
d121a5d2 CW |
919 | return intel_sdvo_set_value(intel_sdvo, |
920 | SDVO_CMD_SET_HBUF_TXRATE, | |
3c17fe4b | 921 | &tx_rate, 1); |
e2f0ba97 JB |
922 | } |
923 | ||
32aad86f | 924 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 925 | { |
ce6feabd | 926 | struct intel_sdvo_tv_format format; |
40039750 | 927 | uint32_t format_map; |
ce6feabd | 928 | |
40039750 | 929 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 930 | memset(&format, 0, sizeof(format)); |
32aad86f | 931 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 932 | |
32aad86f CW |
933 | BUILD_BUG_ON(sizeof(format) != 6); |
934 | return intel_sdvo_set_value(intel_sdvo, | |
935 | SDVO_CMD_SET_TV_FORMAT, | |
936 | &format, sizeof(format)); | |
7026d4ac ZW |
937 | } |
938 | ||
32aad86f CW |
939 | static bool |
940 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
e811f5ae | 941 | const struct drm_display_mode *mode) |
e2f0ba97 | 942 | { |
32aad86f | 943 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 944 | |
32aad86f CW |
945 | if (!intel_sdvo_set_target_output(intel_sdvo, |
946 | intel_sdvo->attached_output)) | |
947 | return false; | |
e2f0ba97 | 948 | |
32aad86f CW |
949 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
950 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
951 | return false; | |
e2f0ba97 | 952 | |
32aad86f CW |
953 | return true; |
954 | } | |
955 | ||
c9a29698 DV |
956 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
957 | * Unfortunately we have to set up the full output mode to do that. */ | |
32aad86f | 958 | static bool |
c9a29698 | 959 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
e811f5ae | 960 | const struct drm_display_mode *mode, |
c9a29698 | 961 | struct drm_display_mode *adjusted_mode) |
32aad86f | 962 | { |
c9a29698 DV |
963 | struct intel_sdvo_dtd input_dtd; |
964 | ||
32aad86f CW |
965 | /* Reset the input timing to the screen. Assume always input 0. */ |
966 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
967 | return false; | |
e2f0ba97 | 968 | |
32aad86f CW |
969 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
970 | mode->clock / 10, | |
971 | mode->hdisplay, | |
972 | mode->vdisplay)) | |
973 | return false; | |
e2f0ba97 | 974 | |
32aad86f | 975 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
c9a29698 | 976 | &input_dtd)) |
32aad86f | 977 | return false; |
e2f0ba97 | 978 | |
c9a29698 | 979 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
79e53945 | 980 | |
32aad86f CW |
981 | return true; |
982 | } | |
12682a97 | 983 | |
32aad86f | 984 | static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 985 | const struct drm_display_mode *mode, |
32aad86f CW |
986 | struct drm_display_mode *adjusted_mode) |
987 | { | |
890f3359 | 988 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
6c9547ff | 989 | int multiplier; |
12682a97 | 990 | |
32aad86f CW |
991 | /* We need to construct preferred input timings based on our |
992 | * output timings. To do that, we have to set the output | |
993 | * timings, even though this isn't really the right place in | |
994 | * the sequence to do it. Oh well. | |
995 | */ | |
996 | if (intel_sdvo->is_tv) { | |
997 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
998 | return false; | |
12682a97 | 999 | |
c9a29698 DV |
1000 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1001 | mode, | |
1002 | adjusted_mode); | |
ea5b213a | 1003 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 1004 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 1005 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 1006 | return false; |
12682a97 | 1007 | |
c9a29698 DV |
1008 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1009 | mode, | |
1010 | adjusted_mode); | |
e2f0ba97 | 1011 | } |
32aad86f CW |
1012 | |
1013 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 1014 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 1015 | */ |
6c9547ff CW |
1016 | multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode); |
1017 | intel_mode_set_pixel_multiplier(adjusted_mode, multiplier); | |
32aad86f | 1018 | |
e2f0ba97 JB |
1019 | return true; |
1020 | } | |
1021 | ||
1022 | static void intel_sdvo_mode_set(struct drm_encoder *encoder, | |
1023 | struct drm_display_mode *mode, | |
1024 | struct drm_display_mode *adjusted_mode) | |
1025 | { | |
1026 | struct drm_device *dev = encoder->dev; | |
1027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1028 | struct drm_crtc *crtc = encoder->crtc; | |
1029 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
890f3359 | 1030 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
6c9547ff | 1031 | u32 sdvox; |
e2f0ba97 | 1032 | struct intel_sdvo_in_out_map in_out; |
6651819b | 1033 | struct intel_sdvo_dtd input_dtd, output_dtd; |
6c9547ff CW |
1034 | int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode); |
1035 | int rate; | |
e2f0ba97 JB |
1036 | |
1037 | if (!mode) | |
1038 | return; | |
1039 | ||
1040 | /* First, set the input mapping for the first input to our controlled | |
1041 | * output. This is only correct if we're a single-input device, in | |
1042 | * which case the first input is the output from the appropriate SDVO | |
1043 | * channel on the motherboard. In a two-input device, the first input | |
1044 | * will be SDVOB and the second SDVOC. | |
1045 | */ | |
ea5b213a | 1046 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1047 | in_out.in1 = 0; |
1048 | ||
c74696b9 PR |
1049 | intel_sdvo_set_value(intel_sdvo, |
1050 | SDVO_CMD_SET_IN_OUT_MAP, | |
1051 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1052 | |
6c9547ff CW |
1053 | /* Set the output timings to the screen */ |
1054 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1055 | intel_sdvo->attached_output)) | |
1056 | return; | |
e2f0ba97 | 1057 | |
6651819b DV |
1058 | /* lvds has a special fixed output timing. */ |
1059 | if (intel_sdvo->is_lvds) | |
1060 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1061 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1062 | else | |
1063 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
c8d4bb54 DV |
1064 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1065 | DRM_INFO("Setting output timings on %s failed\n", | |
1066 | SDVO_NAME(intel_sdvo)); | |
79e53945 JB |
1067 | |
1068 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1069 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1070 | return; | |
79e53945 | 1071 | |
97aaf910 CW |
1072 | if (intel_sdvo->has_hdmi_monitor) { |
1073 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); | |
1074 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1075 | SDVO_COLORIMETRY_RGB256); | |
1076 | intel_sdvo_set_avi_infoframe(intel_sdvo); | |
1077 | } else | |
1078 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1079 | |
6c9547ff CW |
1080 | if (intel_sdvo->is_tv && |
1081 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1082 | return; | |
e2f0ba97 | 1083 | |
6651819b DV |
1084 | /* We have tried to get input timing in mode_fixup, and filled into |
1085 | * adjusted_mode. | |
1086 | */ | |
1087 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); | |
c8d4bb54 DV |
1088 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1089 | DRM_INFO("Setting input timings on %s failed\n", | |
1090 | SDVO_NAME(intel_sdvo)); | |
79e53945 | 1091 | |
6c9547ff CW |
1092 | switch (pixel_multiplier) { |
1093 | default: | |
32aad86f CW |
1094 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1095 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1096 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1097 | } |
32aad86f CW |
1098 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1099 | return; | |
79e53945 JB |
1100 | |
1101 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1102 | if (INTEL_INFO(dev)->gen >= 4) { |
ba68e086 PZ |
1103 | /* The real mode polarity is set by the SDVO commands, using |
1104 | * struct intel_sdvo_dtd. */ | |
1105 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; | |
e953fd7b CW |
1106 | if (intel_sdvo->is_hdmi) |
1107 | sdvox |= intel_sdvo->color_range; | |
6714afb1 CW |
1108 | if (INTEL_INFO(dev)->gen < 5) |
1109 | sdvox |= SDVO_BORDER_ENABLE; | |
e2f0ba97 | 1110 | } else { |
6c9547ff | 1111 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
ea5b213a | 1112 | switch (intel_sdvo->sdvo_reg) { |
e2f0ba97 JB |
1113 | case SDVOB: |
1114 | sdvox &= SDVOB_PRESERVE_MASK; | |
1115 | break; | |
1116 | case SDVOC: | |
1117 | sdvox &= SDVOC_PRESERVE_MASK; | |
1118 | break; | |
1119 | } | |
1120 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1121 | } | |
3573c410 PZ |
1122 | |
1123 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
1124 | sdvox |= TRANSCODER_CPT(intel_crtc->pipe); | |
1125 | else | |
1126 | sdvox |= TRANSCODER(intel_crtc->pipe); | |
1127 | ||
da79de97 | 1128 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1129 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1130 | |
a6c45cf0 | 1131 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1132 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1133 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1134 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1135 | } else { |
6c9547ff | 1136 | sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT; |
79e53945 JB |
1137 | } |
1138 | ||
6714afb1 CW |
1139 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1140 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1141 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1142 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1143 | } |
1144 | ||
1145 | static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode) | |
1146 | { | |
1147 | struct drm_device *dev = encoder->dev; | |
1148 | struct drm_i915_private *dev_priv = dev->dev_private; | |
890f3359 | 1149 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
9d0498a2 | 1150 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
79e53945 JB |
1151 | u32 temp; |
1152 | ||
1153 | if (mode != DRM_MODE_DPMS_ON) { | |
ea5b213a | 1154 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
79e53945 | 1155 | if (0) |
ea5b213a | 1156 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
79e53945 JB |
1157 | |
1158 | if (mode == DRM_MODE_DPMS_OFF) { | |
ea5b213a | 1159 | temp = I915_READ(intel_sdvo->sdvo_reg); |
79e53945 | 1160 | if ((temp & SDVO_ENABLE) != 0) { |
ea5b213a | 1161 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
79e53945 JB |
1162 | } |
1163 | } | |
1164 | } else { | |
1165 | bool input1, input2; | |
1166 | int i; | |
1167 | u8 status; | |
1168 | ||
ea5b213a | 1169 | temp = I915_READ(intel_sdvo->sdvo_reg); |
79e53945 | 1170 | if ((temp & SDVO_ENABLE) == 0) |
ea5b213a | 1171 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
79e53945 | 1172 | for (i = 0; i < 2; i++) |
9d0498a2 | 1173 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
79e53945 | 1174 | |
32aad86f | 1175 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
79e53945 JB |
1176 | /* Warn if the device reported failure to sync. |
1177 | * A lot of SDVO devices fail to notify of sync, but it's | |
1178 | * a given it the status is a success, we succeeded. | |
1179 | */ | |
1180 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
8a4c47f3 | 1181 | DRM_DEBUG_KMS("First %s output reported failure to " |
ea5b213a | 1182 | "sync\n", SDVO_NAME(intel_sdvo)); |
79e53945 JB |
1183 | } |
1184 | ||
1185 | if (0) | |
ea5b213a CW |
1186 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1187 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
79e53945 JB |
1188 | } |
1189 | return; | |
1190 | } | |
1191 | ||
79e53945 JB |
1192 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
1193 | struct drm_display_mode *mode) | |
1194 | { | |
df0e9248 | 1195 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
79e53945 JB |
1196 | |
1197 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1198 | return MODE_NO_DBLESCAN; | |
1199 | ||
ea5b213a | 1200 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1201 | return MODE_CLOCK_LOW; |
1202 | ||
ea5b213a | 1203 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1204 | return MODE_CLOCK_HIGH; |
1205 | ||
8545423a | 1206 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1207 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1208 | return MODE_PANEL; |
1209 | ||
ea5b213a | 1210 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1211 | return MODE_PANEL; |
1212 | } | |
1213 | ||
79e53945 JB |
1214 | return MODE_OK; |
1215 | } | |
1216 | ||
ea5b213a | 1217 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1218 | { |
1a3665c8 | 1219 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1220 | if (!intel_sdvo_get_value(intel_sdvo, |
1221 | SDVO_CMD_GET_DEVICE_CAPS, | |
1222 | caps, sizeof(*caps))) | |
1223 | return false; | |
1224 | ||
1225 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1226 | " vendor_id: %d\n" | |
1227 | " device_id: %d\n" | |
1228 | " device_rev_id: %d\n" | |
1229 | " sdvo_version_major: %d\n" | |
1230 | " sdvo_version_minor: %d\n" | |
1231 | " sdvo_inputs_mask: %d\n" | |
1232 | " smooth_scaling: %d\n" | |
1233 | " sharp_scaling: %d\n" | |
1234 | " up_scaling: %d\n" | |
1235 | " down_scaling: %d\n" | |
1236 | " stall_support: %d\n" | |
1237 | " output_flags: %d\n", | |
1238 | caps->vendor_id, | |
1239 | caps->device_id, | |
1240 | caps->device_rev_id, | |
1241 | caps->sdvo_version_major, | |
1242 | caps->sdvo_version_minor, | |
1243 | caps->sdvo_inputs_mask, | |
1244 | caps->smooth_scaling, | |
1245 | caps->sharp_scaling, | |
1246 | caps->up_scaling, | |
1247 | caps->down_scaling, | |
1248 | caps->stall_support, | |
1249 | caps->output_flags); | |
1250 | ||
1251 | return true; | |
79e53945 JB |
1252 | } |
1253 | ||
cc68c81a | 1254 | static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo) |
79e53945 | 1255 | { |
768b107e | 1256 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 1257 | u8 response[2]; |
79e53945 | 1258 | |
768b107e DV |
1259 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1260 | * on the line. */ | |
1261 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1262 | return false; | |
1263 | ||
32aad86f CW |
1264 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1265 | &response, 2) && response[0]; | |
79e53945 JB |
1266 | } |
1267 | ||
cc68c81a | 1268 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1269 | { |
cc68c81a | 1270 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
79e53945 | 1271 | |
cc68c81a | 1272 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2); |
79e53945 JB |
1273 | } |
1274 | ||
fb7a46f3 | 1275 | static bool |
ea5b213a | 1276 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1277 | { |
bc65212c | 1278 | /* Is there more than one type of output? */ |
2294488d | 1279 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1280 | } |
1281 | ||
f899fc64 | 1282 | static struct edid * |
e957d772 | 1283 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1284 | { |
e957d772 CW |
1285 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1286 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1287 | } |
1288 | ||
ff482d83 CW |
1289 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1290 | static struct edid * | |
1291 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1292 | { | |
f899fc64 | 1293 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ff482d83 | 1294 | |
0c1dab89 | 1295 | return drm_get_edid(connector, |
3bd7d909 DK |
1296 | intel_gmbus_get_adapter(dev_priv, |
1297 | dev_priv->crt_ddc_pin)); | |
ff482d83 CW |
1298 | } |
1299 | ||
c43b5634 | 1300 | static enum drm_connector_status |
8bf38485 | 1301 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1302 | { |
df0e9248 | 1303 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1304 | enum drm_connector_status status; |
1305 | struct edid *edid; | |
9dff6af8 | 1306 | |
e957d772 | 1307 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1308 | |
ea5b213a | 1309 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1310 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1311 | |
7c3f0a27 ZY |
1312 | /* |
1313 | * Don't use the 1 as the argument of DDC bus switch to get | |
1314 | * the EDID. It is used for SDVO SPD ROM. | |
1315 | */ | |
9d1a903d | 1316 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1317 | intel_sdvo->ddc_bus = ddc; |
1318 | edid = intel_sdvo_get_edid(connector); | |
1319 | if (edid) | |
7c3f0a27 | 1320 | break; |
7c3f0a27 | 1321 | } |
e957d772 CW |
1322 | /* |
1323 | * If we found the EDID on the other bus, | |
1324 | * assume that is the correct DDC bus. | |
1325 | */ | |
1326 | if (edid == NULL) | |
1327 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1328 | } |
9d1a903d CW |
1329 | |
1330 | /* | |
1331 | * When there is no edid and no monitor is connected with VGA | |
1332 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1333 | */ |
ff482d83 CW |
1334 | if (edid == NULL) |
1335 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1336 | |
2f551c84 | 1337 | status = connector_status_unknown; |
9dff6af8 | 1338 | if (edid != NULL) { |
149c36a3 | 1339 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1340 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1341 | status = connector_status_connected; | |
da79de97 CW |
1342 | if (intel_sdvo->is_hdmi) { |
1343 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1344 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
1345 | } | |
13946743 CW |
1346 | } else |
1347 | status = connector_status_disconnected; | |
149c36a3 | 1348 | connector->display_info.raw_edid = NULL; |
9d1a903d CW |
1349 | kfree(edid); |
1350 | } | |
7f36e7ed CW |
1351 | |
1352 | if (status == connector_status_connected) { | |
1353 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
c3e5f67b DV |
1354 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1355 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); | |
7f36e7ed CW |
1356 | } |
1357 | ||
2b8d33f7 | 1358 | return status; |
9dff6af8 ML |
1359 | } |
1360 | ||
52220085 CW |
1361 | static bool |
1362 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1363 | struct edid *edid) | |
1364 | { | |
1365 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1366 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1367 | ||
1368 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1369 | connector_is_digital, monitor_is_digital); | |
1370 | return connector_is_digital == monitor_is_digital; | |
1371 | } | |
1372 | ||
7b334fcb | 1373 | static enum drm_connector_status |
930a9e28 | 1374 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1375 | { |
fb7a46f3 | 1376 | uint16_t response; |
df0e9248 | 1377 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1378 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1379 | enum drm_connector_status ret; |
79e53945 | 1380 | |
32aad86f | 1381 | if (!intel_sdvo_write_cmd(intel_sdvo, |
e957d772 | 1382 | SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0)) |
32aad86f | 1383 | return connector_status_unknown; |
ba84cd1f CW |
1384 | |
1385 | /* add 30ms delay when the output type might be TV */ | |
a0b1c7a5 | 1386 | if (intel_sdvo->caps.output_flags & SDVO_TV_MASK) |
6c982376 | 1387 | msleep(30); |
ba84cd1f | 1388 | |
32aad86f CW |
1389 | if (!intel_sdvo_read_response(intel_sdvo, &response, 2)) |
1390 | return connector_status_unknown; | |
79e53945 | 1391 | |
e957d772 CW |
1392 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1393 | response & 0xff, response >> 8, | |
1394 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1395 | |
fb7a46f3 | 1396 | if (response == 0) |
79e53945 | 1397 | return connector_status_disconnected; |
fb7a46f3 | 1398 | |
ea5b213a | 1399 | intel_sdvo->attached_output = response; |
14571b4c | 1400 | |
97aaf910 CW |
1401 | intel_sdvo->has_hdmi_monitor = false; |
1402 | intel_sdvo->has_hdmi_audio = false; | |
1403 | ||
615fb93f | 1404 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1405 | ret = connector_status_disconnected; |
13946743 | 1406 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1407 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1408 | else { |
1409 | struct edid *edid; | |
1410 | ||
1411 | /* if we have an edid check it matches the connection */ | |
1412 | edid = intel_sdvo_get_edid(connector); | |
1413 | if (edid == NULL) | |
1414 | edid = intel_sdvo_get_analog_edid(connector); | |
1415 | if (edid != NULL) { | |
52220085 CW |
1416 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1417 | edid)) | |
13946743 | 1418 | ret = connector_status_connected; |
52220085 CW |
1419 | else |
1420 | ret = connector_status_disconnected; | |
1421 | ||
13946743 CW |
1422 | connector->display_info.raw_edid = NULL; |
1423 | kfree(edid); | |
1424 | } else | |
1425 | ret = connector_status_connected; | |
1426 | } | |
14571b4c ZW |
1427 | |
1428 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1429 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1430 | intel_sdvo->is_tv = false; |
1431 | intel_sdvo->is_lvds = false; | |
1432 | intel_sdvo->base.needs_tv_clock = false; | |
14571b4c ZW |
1433 | |
1434 | if (response & SDVO_TV_MASK) { | |
ea5b213a CW |
1435 | intel_sdvo->is_tv = true; |
1436 | intel_sdvo->base.needs_tv_clock = true; | |
14571b4c ZW |
1437 | } |
1438 | if (response & SDVO_LVDS_MASK) | |
8545423a | 1439 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1440 | } |
14571b4c ZW |
1441 | |
1442 | return ret; | |
79e53945 JB |
1443 | } |
1444 | ||
e2f0ba97 | 1445 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1446 | { |
ff482d83 | 1447 | struct edid *edid; |
79e53945 JB |
1448 | |
1449 | /* set the bus switch and get the modes */ | |
e957d772 | 1450 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1451 | |
57cdaf90 KP |
1452 | /* |
1453 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1454 | * link between analog and digital outputs. So, if the regular SDVO | |
1455 | * DDC fails, check to see if the analog output is disconnected, in | |
1456 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1457 | */ |
f899fc64 CW |
1458 | if (edid == NULL) |
1459 | edid = intel_sdvo_get_analog_edid(connector); | |
1460 | ||
ff482d83 | 1461 | if (edid != NULL) { |
52220085 CW |
1462 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1463 | edid)) { | |
0c1dab89 CW |
1464 | drm_mode_connector_update_edid_property(connector, edid); |
1465 | drm_add_edid_modes(connector, edid); | |
1466 | } | |
13946743 | 1467 | |
ff482d83 CW |
1468 | connector->display_info.raw_edid = NULL; |
1469 | kfree(edid); | |
e2f0ba97 | 1470 | } |
e2f0ba97 JB |
1471 | } |
1472 | ||
1473 | /* | |
1474 | * Set of SDVO TV modes. | |
1475 | * Note! This is in reply order (see loop in get_tv_modes). | |
1476 | * XXX: all 60Hz refresh? | |
1477 | */ | |
b1f559ec | 1478 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1479 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1480 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1481 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1482 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1483 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1484 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1485 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1486 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1487 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1488 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1489 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1490 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1491 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1492 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1493 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1494 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1495 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1496 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1497 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1498 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1499 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1500 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1501 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1502 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1503 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1504 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1505 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1506 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1507 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1508 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1509 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1510 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1511 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1512 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1513 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1514 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1515 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1516 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1517 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1518 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1519 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1520 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1521 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1522 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1523 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1524 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1525 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1526 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1527 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1528 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1529 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1530 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1531 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1532 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1533 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1534 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1535 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1536 | }; | |
1537 | ||
1538 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1539 | { | |
df0e9248 | 1540 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1541 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1542 | uint32_t reply = 0, format_map = 0; |
1543 | int i; | |
e2f0ba97 JB |
1544 | |
1545 | /* Read the list of supported input resolutions for the selected TV | |
1546 | * format. | |
1547 | */ | |
40039750 | 1548 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1549 | memcpy(&tv_res, &format_map, |
32aad86f | 1550 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1551 | |
32aad86f CW |
1552 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1553 | return; | |
ce6feabd | 1554 | |
32aad86f | 1555 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1556 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1557 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1558 | &tv_res, sizeof(tv_res))) |
1559 | return; | |
1560 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1561 | return; |
1562 | ||
1563 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1564 | if (reply & (1 << i)) { |
1565 | struct drm_display_mode *nmode; | |
1566 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1567 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1568 | if (nmode) |
1569 | drm_mode_probed_add(connector, nmode); | |
1570 | } | |
e2f0ba97 JB |
1571 | } |
1572 | ||
7086c87f ML |
1573 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1574 | { | |
df0e9248 | 1575 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7086c87f | 1576 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1577 | struct drm_display_mode *newmode; |
7086c87f ML |
1578 | |
1579 | /* | |
1580 | * Attempt to get the mode list from DDC. | |
1581 | * Assume that the preferred modes are | |
1582 | * arranged in priority order. | |
1583 | */ | |
f899fc64 | 1584 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
7086c87f | 1585 | if (list_empty(&connector->probed_modes) == false) |
12682a97 | 1586 | goto end; |
7086c87f ML |
1587 | |
1588 | /* Fetch modes from VBT */ | |
1589 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { | |
7086c87f ML |
1590 | newmode = drm_mode_duplicate(connector->dev, |
1591 | dev_priv->sdvo_lvds_vbt_mode); | |
1592 | if (newmode != NULL) { | |
1593 | /* Guarantee the mode is preferred */ | |
1594 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1595 | DRM_MODE_TYPE_DRIVER); | |
1596 | drm_mode_probed_add(connector, newmode); | |
1597 | } | |
1598 | } | |
12682a97 | 1599 | |
1600 | end: | |
1601 | list_for_each_entry(newmode, &connector->probed_modes, head) { | |
1602 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1603 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1604 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff | 1605 | |
8545423a | 1606 | intel_sdvo->is_lvds = true; |
12682a97 | 1607 | break; |
1608 | } | |
1609 | } | |
1610 | ||
7086c87f ML |
1611 | } |
1612 | ||
e2f0ba97 JB |
1613 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1614 | { | |
615fb93f | 1615 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1616 | |
615fb93f | 1617 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1618 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1619 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1620 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1621 | else |
1622 | intel_sdvo_get_ddc_modes(connector); | |
1623 | ||
32aad86f | 1624 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1625 | } |
1626 | ||
fcc8d672 CW |
1627 | static void |
1628 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) | |
b9219c5e | 1629 | { |
615fb93f | 1630 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
b9219c5e ZY |
1631 | struct drm_device *dev = connector->dev; |
1632 | ||
c5521706 CW |
1633 | if (intel_sdvo_connector->left) |
1634 | drm_property_destroy(dev, intel_sdvo_connector->left); | |
1635 | if (intel_sdvo_connector->right) | |
1636 | drm_property_destroy(dev, intel_sdvo_connector->right); | |
1637 | if (intel_sdvo_connector->top) | |
1638 | drm_property_destroy(dev, intel_sdvo_connector->top); | |
1639 | if (intel_sdvo_connector->bottom) | |
1640 | drm_property_destroy(dev, intel_sdvo_connector->bottom); | |
1641 | if (intel_sdvo_connector->hpos) | |
1642 | drm_property_destroy(dev, intel_sdvo_connector->hpos); | |
1643 | if (intel_sdvo_connector->vpos) | |
1644 | drm_property_destroy(dev, intel_sdvo_connector->vpos); | |
1645 | if (intel_sdvo_connector->saturation) | |
1646 | drm_property_destroy(dev, intel_sdvo_connector->saturation); | |
1647 | if (intel_sdvo_connector->contrast) | |
1648 | drm_property_destroy(dev, intel_sdvo_connector->contrast); | |
1649 | if (intel_sdvo_connector->hue) | |
1650 | drm_property_destroy(dev, intel_sdvo_connector->hue); | |
1651 | if (intel_sdvo_connector->sharpness) | |
1652 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); | |
1653 | if (intel_sdvo_connector->flicker_filter) | |
1654 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); | |
1655 | if (intel_sdvo_connector->flicker_filter_2d) | |
1656 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); | |
1657 | if (intel_sdvo_connector->flicker_filter_adaptive) | |
1658 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); | |
1659 | if (intel_sdvo_connector->tv_luma_filter) | |
1660 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); | |
1661 | if (intel_sdvo_connector->tv_chroma_filter) | |
1662 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); | |
e044218a CW |
1663 | if (intel_sdvo_connector->dot_crawl) |
1664 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); | |
c5521706 CW |
1665 | if (intel_sdvo_connector->brightness) |
1666 | drm_property_destroy(dev, intel_sdvo_connector->brightness); | |
b9219c5e ZY |
1667 | } |
1668 | ||
79e53945 JB |
1669 | static void intel_sdvo_destroy(struct drm_connector *connector) |
1670 | { | |
615fb93f | 1671 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 1672 | |
c5521706 | 1673 | if (intel_sdvo_connector->tv_format) |
ce6feabd | 1674 | drm_property_destroy(connector->dev, |
c5521706 | 1675 | intel_sdvo_connector->tv_format); |
b9219c5e | 1676 | |
d2a82a6f | 1677 | intel_sdvo_destroy_enhance_property(connector); |
79e53945 JB |
1678 | drm_sysfs_connector_remove(connector); |
1679 | drm_connector_cleanup(connector); | |
d2a82a6f | 1680 | kfree(connector); |
79e53945 JB |
1681 | } |
1682 | ||
1aad7ac0 CW |
1683 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
1684 | { | |
1685 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1686 | struct edid *edid; | |
1687 | bool has_audio = false; | |
1688 | ||
1689 | if (!intel_sdvo->is_hdmi) | |
1690 | return false; | |
1691 | ||
1692 | edid = intel_sdvo_get_edid(connector); | |
1693 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1694 | has_audio = drm_detect_monitor_audio(edid); | |
38ab8a20 | 1695 | kfree(edid); |
1aad7ac0 CW |
1696 | |
1697 | return has_audio; | |
1698 | } | |
1699 | ||
ce6feabd ZY |
1700 | static int |
1701 | intel_sdvo_set_property(struct drm_connector *connector, | |
1702 | struct drm_property *property, | |
1703 | uint64_t val) | |
1704 | { | |
df0e9248 | 1705 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1706 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e953fd7b | 1707 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
b9219c5e | 1708 | uint16_t temp_value; |
32aad86f CW |
1709 | uint8_t cmd; |
1710 | int ret; | |
ce6feabd ZY |
1711 | |
1712 | ret = drm_connector_property_set_value(connector, property, val); | |
32aad86f CW |
1713 | if (ret) |
1714 | return ret; | |
ce6feabd | 1715 | |
3f43c48d | 1716 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1717 | int i = val; |
1718 | bool has_audio; | |
1719 | ||
1720 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
1721 | return 0; |
1722 | ||
1aad7ac0 | 1723 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 1724 | |
c3e5f67b | 1725 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1726 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
1727 | else | |
c3e5f67b | 1728 | has_audio = (i == HDMI_AUDIO_ON); |
7f36e7ed | 1729 | |
1aad7ac0 | 1730 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 1731 | return 0; |
7f36e7ed | 1732 | |
1aad7ac0 | 1733 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
1734 | goto done; |
1735 | } | |
1736 | ||
e953fd7b CW |
1737 | if (property == dev_priv->broadcast_rgb_property) { |
1738 | if (val == !!intel_sdvo->color_range) | |
7f36e7ed CW |
1739 | return 0; |
1740 | ||
e953fd7b | 1741 | intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0; |
7f36e7ed CW |
1742 | goto done; |
1743 | } | |
1744 | ||
c5521706 CW |
1745 | #define CHECK_PROPERTY(name, NAME) \ |
1746 | if (intel_sdvo_connector->name == property) { \ | |
1747 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
1748 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
1749 | cmd = SDVO_CMD_SET_##NAME; \ | |
1750 | intel_sdvo_connector->cur_##name = temp_value; \ | |
1751 | goto set_value; \ | |
1752 | } | |
1753 | ||
1754 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
1755 | if (val >= TV_FORMAT_NUM) |
1756 | return -EINVAL; | |
1757 | ||
40039750 | 1758 | if (intel_sdvo->tv_format_index == |
615fb93f | 1759 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 1760 | return 0; |
ce6feabd | 1761 | |
40039750 | 1762 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 1763 | goto done; |
32aad86f | 1764 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 1765 | temp_value = val; |
c5521706 | 1766 | if (intel_sdvo_connector->left == property) { |
b9219c5e | 1767 | drm_connector_property_set_value(connector, |
c5521706 | 1768 | intel_sdvo_connector->right, val); |
615fb93f | 1769 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 1770 | return 0; |
b9219c5e | 1771 | |
615fb93f CW |
1772 | intel_sdvo_connector->left_margin = temp_value; |
1773 | intel_sdvo_connector->right_margin = temp_value; | |
1774 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 1775 | intel_sdvo_connector->left_margin; |
b9219c5e | 1776 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
1777 | goto set_value; |
1778 | } else if (intel_sdvo_connector->right == property) { | |
b9219c5e | 1779 | drm_connector_property_set_value(connector, |
c5521706 | 1780 | intel_sdvo_connector->left, val); |
615fb93f | 1781 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 1782 | return 0; |
b9219c5e | 1783 | |
615fb93f CW |
1784 | intel_sdvo_connector->left_margin = temp_value; |
1785 | intel_sdvo_connector->right_margin = temp_value; | |
1786 | temp_value = intel_sdvo_connector->max_hscan - | |
1787 | intel_sdvo_connector->left_margin; | |
b9219c5e | 1788 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
1789 | goto set_value; |
1790 | } else if (intel_sdvo_connector->top == property) { | |
b9219c5e | 1791 | drm_connector_property_set_value(connector, |
c5521706 | 1792 | intel_sdvo_connector->bottom, val); |
615fb93f | 1793 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 1794 | return 0; |
b9219c5e | 1795 | |
615fb93f CW |
1796 | intel_sdvo_connector->top_margin = temp_value; |
1797 | intel_sdvo_connector->bottom_margin = temp_value; | |
1798 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 1799 | intel_sdvo_connector->top_margin; |
b9219c5e | 1800 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
1801 | goto set_value; |
1802 | } else if (intel_sdvo_connector->bottom == property) { | |
b9219c5e | 1803 | drm_connector_property_set_value(connector, |
c5521706 | 1804 | intel_sdvo_connector->top, val); |
615fb93f | 1805 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
1806 | return 0; |
1807 | ||
615fb93f CW |
1808 | intel_sdvo_connector->top_margin = temp_value; |
1809 | intel_sdvo_connector->bottom_margin = temp_value; | |
1810 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 1811 | intel_sdvo_connector->top_margin; |
b9219c5e | 1812 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
1813 | goto set_value; |
1814 | } | |
1815 | CHECK_PROPERTY(hpos, HPOS) | |
1816 | CHECK_PROPERTY(vpos, VPOS) | |
1817 | CHECK_PROPERTY(saturation, SATURATION) | |
1818 | CHECK_PROPERTY(contrast, CONTRAST) | |
1819 | CHECK_PROPERTY(hue, HUE) | |
1820 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
1821 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
1822 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
1823 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
1824 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
1825 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
1826 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 1827 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 1828 | } |
b9219c5e | 1829 | |
c5521706 | 1830 | return -EINVAL; /* unknown property */ |
b9219c5e | 1831 | |
c5521706 CW |
1832 | set_value: |
1833 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
1834 | return -EIO; | |
b9219c5e | 1835 | |
b9219c5e | 1836 | |
c5521706 | 1837 | done: |
df0e9248 CW |
1838 | if (intel_sdvo->base.base.crtc) { |
1839 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; | |
ce6feabd | 1840 | drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x, |
c5521706 CW |
1841 | crtc->y, crtc->fb); |
1842 | } | |
1843 | ||
32aad86f | 1844 | return 0; |
c5521706 | 1845 | #undef CHECK_PROPERTY |
ce6feabd ZY |
1846 | } |
1847 | ||
79e53945 JB |
1848 | static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = { |
1849 | .dpms = intel_sdvo_dpms, | |
1850 | .mode_fixup = intel_sdvo_mode_fixup, | |
1851 | .prepare = intel_encoder_prepare, | |
1852 | .mode_set = intel_sdvo_mode_set, | |
1853 | .commit = intel_encoder_commit, | |
1854 | }; | |
1855 | ||
1856 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { | |
c9fb15f6 | 1857 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
1858 | .detect = intel_sdvo_detect, |
1859 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 1860 | .set_property = intel_sdvo_set_property, |
79e53945 JB |
1861 | .destroy = intel_sdvo_destroy, |
1862 | }; | |
1863 | ||
1864 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
1865 | .get_modes = intel_sdvo_get_modes, | |
1866 | .mode_valid = intel_sdvo_mode_valid, | |
df0e9248 | 1867 | .best_encoder = intel_best_encoder, |
79e53945 JB |
1868 | }; |
1869 | ||
b358d0a6 | 1870 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 1871 | { |
890f3359 | 1872 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
d2a82a6f | 1873 | |
ea5b213a | 1874 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 1875 | drm_mode_destroy(encoder->dev, |
ea5b213a | 1876 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 1877 | |
e957d772 | 1878 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 1879 | intel_encoder_destroy(encoder); |
79e53945 JB |
1880 | } |
1881 | ||
1882 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
1883 | .destroy = intel_sdvo_enc_destroy, | |
1884 | }; | |
1885 | ||
b66d8424 CW |
1886 | static void |
1887 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
1888 | { | |
1889 | uint16_t mask = 0; | |
1890 | unsigned int num_bits; | |
1891 | ||
1892 | /* Make a mask of outputs less than or equal to our own priority in the | |
1893 | * list. | |
1894 | */ | |
1895 | switch (sdvo->controlled_output) { | |
1896 | case SDVO_OUTPUT_LVDS1: | |
1897 | mask |= SDVO_OUTPUT_LVDS1; | |
1898 | case SDVO_OUTPUT_LVDS0: | |
1899 | mask |= SDVO_OUTPUT_LVDS0; | |
1900 | case SDVO_OUTPUT_TMDS1: | |
1901 | mask |= SDVO_OUTPUT_TMDS1; | |
1902 | case SDVO_OUTPUT_TMDS0: | |
1903 | mask |= SDVO_OUTPUT_TMDS0; | |
1904 | case SDVO_OUTPUT_RGB1: | |
1905 | mask |= SDVO_OUTPUT_RGB1; | |
1906 | case SDVO_OUTPUT_RGB0: | |
1907 | mask |= SDVO_OUTPUT_RGB0; | |
1908 | break; | |
1909 | } | |
1910 | ||
1911 | /* Count bits to find what number we are in the priority list. */ | |
1912 | mask &= sdvo->caps.output_flags; | |
1913 | num_bits = hweight16(mask); | |
1914 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
1915 | if (num_bits > 3) | |
1916 | num_bits = 3; | |
1917 | ||
1918 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
1919 | sdvo->ddc_bus = 1 << num_bits; | |
1920 | } | |
79e53945 | 1921 | |
e2f0ba97 JB |
1922 | /** |
1923 | * Choose the appropriate DDC bus for control bus switch command for this | |
1924 | * SDVO output based on the controlled output. | |
1925 | * | |
1926 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
1927 | * outputs, then LVDS outputs. | |
1928 | */ | |
1929 | static void | |
b1083333 | 1930 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
ea5b213a | 1931 | struct intel_sdvo *sdvo, u32 reg) |
e2f0ba97 | 1932 | { |
b1083333 | 1933 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 1934 | |
eef4eacb | 1935 | if (sdvo->is_sdvob) |
b1083333 AJ |
1936 | mapping = &(dev_priv->sdvo_mappings[0]); |
1937 | else | |
1938 | mapping = &(dev_priv->sdvo_mappings[1]); | |
e2f0ba97 | 1939 | |
b66d8424 CW |
1940 | if (mapping->initialized) |
1941 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
1942 | else | |
1943 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
1944 | } |
1945 | ||
e957d772 CW |
1946 | static void |
1947 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
1948 | struct intel_sdvo *sdvo, u32 reg) | |
1949 | { | |
1950 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 1951 | u8 pin; |
e957d772 | 1952 | |
eef4eacb | 1953 | if (sdvo->is_sdvob) |
e957d772 CW |
1954 | mapping = &dev_priv->sdvo_mappings[0]; |
1955 | else | |
1956 | mapping = &dev_priv->sdvo_mappings[1]; | |
1957 | ||
1958 | pin = GMBUS_PORT_DPB; | |
46eb3036 | 1959 | if (mapping->initialized) |
e957d772 | 1960 | pin = mapping->i2c_pin; |
e957d772 | 1961 | |
3bd7d909 DK |
1962 | if (intel_gmbus_is_port_valid(pin)) { |
1963 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); | |
d5090b96 | 1964 | intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ); |
63abf3ed | 1965 | intel_gmbus_force_bit(sdvo->i2c, true); |
46eb3036 | 1966 | } else { |
3bd7d909 | 1967 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
46eb3036 | 1968 | } |
e957d772 CW |
1969 | } |
1970 | ||
e2f0ba97 | 1971 | static bool |
e27d8538 | 1972 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 1973 | { |
97aaf910 | 1974 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
1975 | } |
1976 | ||
714605e4 | 1977 | static u8 |
eef4eacb | 1978 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
714605e4 | 1979 | { |
1980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1981 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
1982 | ||
eef4eacb | 1983 | if (sdvo->is_sdvob) { |
714605e4 | 1984 | my_mapping = &dev_priv->sdvo_mappings[0]; |
1985 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
1986 | } else { | |
1987 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
1988 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
1989 | } | |
1990 | ||
1991 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
1992 | if (my_mapping->slave_addr) | |
1993 | return my_mapping->slave_addr; | |
1994 | ||
1995 | /* If the BIOS only described a different SDVO device, use the | |
1996 | * address that it isn't using. | |
1997 | */ | |
1998 | if (other_mapping->slave_addr) { | |
1999 | if (other_mapping->slave_addr == 0x70) | |
2000 | return 0x72; | |
2001 | else | |
2002 | return 0x70; | |
2003 | } | |
2004 | ||
2005 | /* No SDVO device info is found for another DVO port, | |
2006 | * so use mapping assumption we had before BIOS parsing. | |
2007 | */ | |
eef4eacb | 2008 | if (sdvo->is_sdvob) |
714605e4 | 2009 | return 0x70; |
2010 | else | |
2011 | return 0x72; | |
2012 | } | |
2013 | ||
14571b4c | 2014 | static void |
df0e9248 CW |
2015 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2016 | struct intel_sdvo *encoder) | |
14571b4c | 2017 | { |
df0e9248 CW |
2018 | drm_connector_init(encoder->base.base.dev, |
2019 | &connector->base.base, | |
2020 | &intel_sdvo_connector_funcs, | |
2021 | connector->base.base.connector_type); | |
6070a4a9 | 2022 | |
df0e9248 CW |
2023 | drm_connector_helper_add(&connector->base.base, |
2024 | &intel_sdvo_connector_helper_funcs); | |
14571b4c | 2025 | |
8f4839e2 | 2026 | connector->base.base.interlace_allowed = 1; |
df0e9248 CW |
2027 | connector->base.base.doublescan_allowed = 0; |
2028 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
14571b4c | 2029 | |
df0e9248 CW |
2030 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
2031 | drm_sysfs_connector_add(&connector->base.base); | |
14571b4c | 2032 | } |
6070a4a9 | 2033 | |
7f36e7ed CW |
2034 | static void |
2035 | intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector) | |
2036 | { | |
2037 | struct drm_device *dev = connector->base.base.dev; | |
2038 | ||
3f43c48d | 2039 | intel_attach_force_audio_property(&connector->base.base); |
e953fd7b CW |
2040 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) |
2041 | intel_attach_broadcast_rgb_property(&connector->base.base); | |
7f36e7ed CW |
2042 | } |
2043 | ||
fb7a46f3 | 2044 | static bool |
ea5b213a | 2045 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2046 | { |
4ef69c7a | 2047 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2048 | struct drm_connector *connector; |
cc68c81a | 2049 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2050 | struct intel_connector *intel_connector; |
615fb93f | 2051 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2052 | |
615fb93f CW |
2053 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2054 | if (!intel_sdvo_connector) | |
14571b4c ZW |
2055 | return false; |
2056 | ||
14571b4c | 2057 | if (device == 0) { |
ea5b213a | 2058 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2059 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2060 | } else if (device == 1) { |
ea5b213a | 2061 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2062 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2063 | } |
2064 | ||
615fb93f | 2065 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2066 | connector = &intel_connector->base; |
cc68c81a SF |
2067 | if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) { |
2068 | connector->polled = DRM_CONNECTOR_POLL_HPD; | |
2069 | intel_sdvo->hotplug_active[0] |= 1 << device; | |
2070 | /* Some SDVO devices have one-shot hotplug interrupts. | |
2071 | * Ensure that they get re-enabled when an interrupt happens. | |
2072 | */ | |
2073 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
2074 | intel_sdvo_enable_hotplug(intel_encoder); | |
2075 | } | |
2076 | else | |
2077 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; | |
14571b4c ZW |
2078 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2079 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2080 | ||
e27d8538 | 2081 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2082 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2083 | intel_sdvo->is_hdmi = true; |
14571b4c | 2084 | } |
ea5b213a CW |
2085 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | |
2086 | (1 << INTEL_ANALOG_CLONE_BIT)); | |
14571b4c | 2087 | |
df0e9248 | 2088 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
f797d221 CW |
2089 | if (intel_sdvo->is_hdmi) |
2090 | intel_sdvo_add_hdmi_properties(intel_sdvo_connector); | |
14571b4c ZW |
2091 | |
2092 | return true; | |
2093 | } | |
2094 | ||
2095 | static bool | |
ea5b213a | 2096 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2097 | { |
4ef69c7a CW |
2098 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2099 | struct drm_connector *connector; | |
2100 | struct intel_connector *intel_connector; | |
2101 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2102 | |
615fb93f CW |
2103 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2104 | if (!intel_sdvo_connector) | |
2105 | return false; | |
14571b4c | 2106 | |
615fb93f | 2107 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2108 | connector = &intel_connector->base; |
2109 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2110 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2111 | |
4ef69c7a CW |
2112 | intel_sdvo->controlled_output |= type; |
2113 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2114 | |
4ef69c7a CW |
2115 | intel_sdvo->is_tv = true; |
2116 | intel_sdvo->base.needs_tv_clock = true; | |
2117 | intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT; | |
14571b4c | 2118 | |
df0e9248 | 2119 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
14571b4c | 2120 | |
4ef69c7a | 2121 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2122 | goto err; |
14571b4c | 2123 | |
4ef69c7a | 2124 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2125 | goto err; |
14571b4c | 2126 | |
4ef69c7a | 2127 | return true; |
32aad86f CW |
2128 | |
2129 | err: | |
123d5c01 | 2130 | intel_sdvo_destroy(connector); |
32aad86f | 2131 | return false; |
14571b4c ZW |
2132 | } |
2133 | ||
2134 | static bool | |
ea5b213a | 2135 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2136 | { |
4ef69c7a CW |
2137 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2138 | struct drm_connector *connector; | |
2139 | struct intel_connector *intel_connector; | |
2140 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2141 | |
615fb93f CW |
2142 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2143 | if (!intel_sdvo_connector) | |
2144 | return false; | |
14571b4c | 2145 | |
615fb93f | 2146 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2147 | connector = &intel_connector->base; |
eb1f8e4f | 2148 | connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2149 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2150 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2151 | ||
2152 | if (device == 0) { | |
2153 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2154 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2155 | } else if (device == 1) { | |
2156 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2157 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2158 | } | |
2159 | ||
2160 | intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) | | |
ea5b213a | 2161 | (1 << INTEL_ANALOG_CLONE_BIT)); |
14571b4c | 2162 | |
df0e9248 CW |
2163 | intel_sdvo_connector_init(intel_sdvo_connector, |
2164 | intel_sdvo); | |
4ef69c7a | 2165 | return true; |
14571b4c ZW |
2166 | } |
2167 | ||
2168 | static bool | |
ea5b213a | 2169 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2170 | { |
4ef69c7a CW |
2171 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2172 | struct drm_connector *connector; | |
2173 | struct intel_connector *intel_connector; | |
2174 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2175 | |
615fb93f CW |
2176 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2177 | if (!intel_sdvo_connector) | |
2178 | return false; | |
14571b4c | 2179 | |
615fb93f CW |
2180 | intel_connector = &intel_sdvo_connector->base; |
2181 | connector = &intel_connector->base; | |
4ef69c7a CW |
2182 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2183 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2184 | ||
2185 | if (device == 0) { | |
2186 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2187 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2188 | } else if (device == 1) { | |
2189 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2190 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2191 | } | |
2192 | ||
2193 | intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) | | |
ea5b213a | 2194 | (1 << INTEL_SDVO_LVDS_CLONE_BIT)); |
14571b4c | 2195 | |
df0e9248 | 2196 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
4ef69c7a | 2197 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2198 | goto err; |
2199 | ||
2200 | return true; | |
2201 | ||
2202 | err: | |
123d5c01 | 2203 | intel_sdvo_destroy(connector); |
32aad86f | 2204 | return false; |
14571b4c ZW |
2205 | } |
2206 | ||
2207 | static bool | |
ea5b213a | 2208 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2209 | { |
ea5b213a CW |
2210 | intel_sdvo->is_tv = false; |
2211 | intel_sdvo->base.needs_tv_clock = false; | |
2212 | intel_sdvo->is_lvds = false; | |
fb7a46f3 | 2213 | |
14571b4c | 2214 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2215 | |
14571b4c | 2216 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2217 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2218 | return false; |
2219 | ||
2220 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2221 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2222 | return false; |
2223 | ||
2224 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2225 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2226 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2227 | return false; |
2228 | ||
2229 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2230 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2231 | return false; |
fb7a46f3 | 2232 | |
a0b1c7a5 CW |
2233 | if (flags & SDVO_OUTPUT_YPRPB0) |
2234 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) | |
2235 | return false; | |
2236 | ||
14571b4c | 2237 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2238 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2239 | return false; |
2240 | ||
2241 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2242 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2243 | return false; |
2244 | ||
2245 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2246 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2247 | return false; |
2248 | ||
2249 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2250 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2251 | return false; |
fb7a46f3 | 2252 | |
14571b4c | 2253 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2254 | unsigned char bytes[2]; |
2255 | ||
ea5b213a CW |
2256 | intel_sdvo->controlled_output = 0; |
2257 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2258 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2259 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2260 | bytes[0], bytes[1]); |
14571b4c | 2261 | return false; |
fb7a46f3 | 2262 | } |
27f8227b | 2263 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2264 | |
14571b4c | 2265 | return true; |
fb7a46f3 | 2266 | } |
2267 | ||
32aad86f CW |
2268 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2269 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2270 | int type) | |
ce6feabd | 2271 | { |
4ef69c7a | 2272 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2273 | struct intel_sdvo_tv_format format; |
2274 | uint32_t format_map, i; | |
ce6feabd | 2275 | |
32aad86f CW |
2276 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2277 | return false; | |
ce6feabd | 2278 | |
1a3665c8 | 2279 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2280 | if (!intel_sdvo_get_value(intel_sdvo, |
2281 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2282 | &format, sizeof(format))) | |
2283 | return false; | |
ce6feabd | 2284 | |
32aad86f | 2285 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2286 | |
2287 | if (format_map == 0) | |
32aad86f | 2288 | return false; |
ce6feabd | 2289 | |
615fb93f | 2290 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2291 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2292 | if (format_map & (1 << i)) |
2293 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2294 | |
2295 | ||
c5521706 | 2296 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2297 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2298 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2299 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2300 | return false; |
ce6feabd | 2301 | |
615fb93f | 2302 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2303 | drm_property_add_enum( |
c5521706 | 2304 | intel_sdvo_connector->tv_format, i, |
40039750 | 2305 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2306 | |
40039750 | 2307 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
32aad86f | 2308 | drm_connector_attach_property(&intel_sdvo_connector->base.base, |
c5521706 | 2309 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2310 | return true; |
ce6feabd ZY |
2311 | |
2312 | } | |
2313 | ||
c5521706 CW |
2314 | #define ENHANCEMENT(name, NAME) do { \ |
2315 | if (enhancements.name) { \ | |
2316 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2317 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2318 | return false; \ | |
2319 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2320 | intel_sdvo_connector->cur_##name = response; \ | |
2321 | intel_sdvo_connector->name = \ | |
d9bc3c02 | 2322 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
c5521706 | 2323 | if (!intel_sdvo_connector->name) return false; \ |
c5521706 CW |
2324 | drm_connector_attach_property(connector, \ |
2325 | intel_sdvo_connector->name, \ | |
2326 | intel_sdvo_connector->cur_##name); \ | |
2327 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2328 | data_value[0], data_value[1], response); \ | |
2329 | } \ | |
0206e353 | 2330 | } while (0) |
c5521706 CW |
2331 | |
2332 | static bool | |
2333 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2334 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2335 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2336 | { |
4ef69c7a | 2337 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2338 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2339 | uint16_t response, data_value[2]; |
2340 | ||
c5521706 CW |
2341 | /* when horizontal overscan is supported, Add the left/right property */ |
2342 | if (enhancements.overscan_h) { | |
2343 | if (!intel_sdvo_get_value(intel_sdvo, | |
2344 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2345 | &data_value, 4)) | |
2346 | return false; | |
32aad86f | 2347 | |
c5521706 CW |
2348 | if (!intel_sdvo_get_value(intel_sdvo, |
2349 | SDVO_CMD_GET_OVERSCAN_H, | |
2350 | &response, 2)) | |
2351 | return false; | |
fcc8d672 | 2352 | |
c5521706 CW |
2353 | intel_sdvo_connector->max_hscan = data_value[0]; |
2354 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2355 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2356 | intel_sdvo_connector->left = | |
d9bc3c02 | 2357 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
c5521706 CW |
2358 | if (!intel_sdvo_connector->left) |
2359 | return false; | |
fcc8d672 | 2360 | |
c5521706 CW |
2361 | drm_connector_attach_property(connector, |
2362 | intel_sdvo_connector->left, | |
2363 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2364 | |
c5521706 | 2365 | intel_sdvo_connector->right = |
d9bc3c02 | 2366 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
c5521706 CW |
2367 | if (!intel_sdvo_connector->right) |
2368 | return false; | |
32aad86f | 2369 | |
c5521706 CW |
2370 | drm_connector_attach_property(connector, |
2371 | intel_sdvo_connector->right, | |
2372 | intel_sdvo_connector->right_margin); | |
2373 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2374 | "default %d, current %d\n", | |
2375 | data_value[0], data_value[1], response); | |
2376 | } | |
32aad86f | 2377 | |
c5521706 CW |
2378 | if (enhancements.overscan_v) { |
2379 | if (!intel_sdvo_get_value(intel_sdvo, | |
2380 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2381 | &data_value, 4)) | |
2382 | return false; | |
fcc8d672 | 2383 | |
c5521706 CW |
2384 | if (!intel_sdvo_get_value(intel_sdvo, |
2385 | SDVO_CMD_GET_OVERSCAN_V, | |
2386 | &response, 2)) | |
2387 | return false; | |
32aad86f | 2388 | |
c5521706 CW |
2389 | intel_sdvo_connector->max_vscan = data_value[0]; |
2390 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2391 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2392 | intel_sdvo_connector->top = | |
d9bc3c02 SH |
2393 | drm_property_create_range(dev, 0, |
2394 | "top_margin", 0, data_value[0]); | |
c5521706 CW |
2395 | if (!intel_sdvo_connector->top) |
2396 | return false; | |
32aad86f | 2397 | |
c5521706 CW |
2398 | drm_connector_attach_property(connector, |
2399 | intel_sdvo_connector->top, | |
2400 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2401 | |
c5521706 | 2402 | intel_sdvo_connector->bottom = |
d9bc3c02 SH |
2403 | drm_property_create_range(dev, 0, |
2404 | "bottom_margin", 0, data_value[0]); | |
c5521706 CW |
2405 | if (!intel_sdvo_connector->bottom) |
2406 | return false; | |
32aad86f | 2407 | |
c5521706 CW |
2408 | drm_connector_attach_property(connector, |
2409 | intel_sdvo_connector->bottom, | |
2410 | intel_sdvo_connector->bottom_margin); | |
2411 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2412 | "default %d, current %d\n", | |
2413 | data_value[0], data_value[1], response); | |
2414 | } | |
32aad86f | 2415 | |
c5521706 CW |
2416 | ENHANCEMENT(hpos, HPOS); |
2417 | ENHANCEMENT(vpos, VPOS); | |
2418 | ENHANCEMENT(saturation, SATURATION); | |
2419 | ENHANCEMENT(contrast, CONTRAST); | |
2420 | ENHANCEMENT(hue, HUE); | |
2421 | ENHANCEMENT(sharpness, SHARPNESS); | |
2422 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2423 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2424 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2425 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2426 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2427 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2428 | |
e044218a CW |
2429 | if (enhancements.dot_crawl) { |
2430 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2431 | return false; | |
2432 | ||
2433 | intel_sdvo_connector->max_dot_crawl = 1; | |
2434 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2435 | intel_sdvo_connector->dot_crawl = | |
d9bc3c02 | 2436 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
e044218a CW |
2437 | if (!intel_sdvo_connector->dot_crawl) |
2438 | return false; | |
2439 | ||
e044218a CW |
2440 | drm_connector_attach_property(connector, |
2441 | intel_sdvo_connector->dot_crawl, | |
2442 | intel_sdvo_connector->cur_dot_crawl); | |
2443 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2444 | } | |
2445 | ||
c5521706 CW |
2446 | return true; |
2447 | } | |
32aad86f | 2448 | |
c5521706 CW |
2449 | static bool |
2450 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2451 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2452 | struct intel_sdvo_enhancements_reply enhancements) | |
2453 | { | |
4ef69c7a | 2454 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2455 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2456 | uint16_t response, data_value[2]; | |
32aad86f | 2457 | |
c5521706 | 2458 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2459 | |
c5521706 CW |
2460 | return true; |
2461 | } | |
2462 | #undef ENHANCEMENT | |
32aad86f | 2463 | |
c5521706 CW |
2464 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2465 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2466 | { | |
2467 | union { | |
2468 | struct intel_sdvo_enhancements_reply reply; | |
2469 | uint16_t response; | |
2470 | } enhancements; | |
32aad86f | 2471 | |
1a3665c8 CW |
2472 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2473 | ||
cf9a2f3a CW |
2474 | enhancements.response = 0; |
2475 | intel_sdvo_get_value(intel_sdvo, | |
2476 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2477 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2478 | if (enhancements.response == 0) { |
2479 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2480 | return true; | |
b9219c5e | 2481 | } |
32aad86f | 2482 | |
c5521706 CW |
2483 | if (IS_TV(intel_sdvo_connector)) |
2484 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2485 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2486 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2487 | else | |
2488 | return true; | |
e957d772 CW |
2489 | } |
2490 | ||
2491 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2492 | struct i2c_msg *msgs, | |
2493 | int num) | |
2494 | { | |
2495 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2496 | |
e957d772 CW |
2497 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2498 | return -EIO; | |
2499 | ||
2500 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2501 | } | |
2502 | ||
2503 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2504 | { | |
2505 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2506 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2507 | } | |
2508 | ||
2509 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2510 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2511 | .functionality = intel_sdvo_ddc_proxy_func | |
2512 | }; | |
2513 | ||
2514 | static bool | |
2515 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2516 | struct drm_device *dev) | |
2517 | { | |
2518 | sdvo->ddc.owner = THIS_MODULE; | |
2519 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2520 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
2521 | sdvo->ddc.dev.parent = &dev->pdev->dev; | |
2522 | sdvo->ddc.algo_data = sdvo; | |
2523 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2524 | ||
2525 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2526 | } |
2527 | ||
eef4eacb | 2528 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
79e53945 | 2529 | { |
b01f2c3a | 2530 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 2531 | struct intel_encoder *intel_encoder; |
ea5b213a | 2532 | struct intel_sdvo *intel_sdvo; |
084b612e | 2533 | u32 hotplug_mask; |
79e53945 | 2534 | int i; |
79e53945 | 2535 | |
ea5b213a CW |
2536 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
2537 | if (!intel_sdvo) | |
7d57382e | 2538 | return false; |
79e53945 | 2539 | |
56184e3d | 2540 | intel_sdvo->sdvo_reg = sdvo_reg; |
eef4eacb DV |
2541 | intel_sdvo->is_sdvob = is_sdvob; |
2542 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; | |
56184e3d | 2543 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
e957d772 CW |
2544 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) { |
2545 | kfree(intel_sdvo); | |
2546 | return false; | |
2547 | } | |
2548 | ||
56184e3d | 2549 | /* encoder type will be decided later */ |
ea5b213a | 2550 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2551 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
373a3cf7 | 2552 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
79e53945 | 2553 | |
79e53945 JB |
2554 | /* Read the regs to test if we can talk to the device */ |
2555 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2556 | u8 byte; |
2557 | ||
2558 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
eef4eacb DV |
2559 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2560 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2561 | goto err; |
79e53945 JB |
2562 | } |
2563 | } | |
2564 | ||
084b612e CW |
2565 | hotplug_mask = 0; |
2566 | if (IS_G4X(dev)) { | |
2567 | hotplug_mask = intel_sdvo->is_sdvob ? | |
2568 | SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X; | |
2569 | } else if (IS_GEN4(dev)) { | |
2570 | hotplug_mask = intel_sdvo->is_sdvob ? | |
2571 | SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965; | |
2572 | } else { | |
2573 | hotplug_mask = intel_sdvo->is_sdvob ? | |
2574 | SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; | |
2575 | } | |
619ac3b7 | 2576 | |
4ef69c7a | 2577 | drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs); |
14571b4c | 2578 | |
af901ca1 | 2579 | /* In default case sdvo lvds is false */ |
32aad86f | 2580 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 2581 | goto err; |
79e53945 | 2582 | |
ea5b213a CW |
2583 | if (intel_sdvo_output_setup(intel_sdvo, |
2584 | intel_sdvo->caps.output_flags) != true) { | |
eef4eacb DV |
2585 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
2586 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2587 | goto err; |
79e53945 JB |
2588 | } |
2589 | ||
fcbc50da JN |
2590 | /* Only enable the hotplug irq if we need it, to work around noisy |
2591 | * hotplug lines. | |
2592 | */ | |
2593 | if (intel_sdvo->hotplug_active[0]) | |
2594 | dev_priv->hotplug_supported_mask |= hotplug_mask; | |
2595 | ||
ea5b213a | 2596 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
e2f0ba97 | 2597 | |
79e53945 | 2598 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 2599 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
f899fc64 | 2600 | goto err; |
79e53945 | 2601 | |
32aad86f CW |
2602 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
2603 | &intel_sdvo->pixel_clock_min, | |
2604 | &intel_sdvo->pixel_clock_max)) | |
f899fc64 | 2605 | goto err; |
79e53945 | 2606 | |
8a4c47f3 | 2607 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 2608 | "clock range %dMHz - %dMHz, " |
2609 | "input 1: %c, input 2: %c, " | |
2610 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
2611 | SDVO_NAME(intel_sdvo), |
2612 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
2613 | intel_sdvo->caps.device_rev_id, | |
2614 | intel_sdvo->pixel_clock_min / 1000, | |
2615 | intel_sdvo->pixel_clock_max / 1000, | |
2616 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
2617 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 2618 | /* check currently supported outputs */ |
ea5b213a | 2619 | intel_sdvo->caps.output_flags & |
79e53945 | 2620 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 2621 | intel_sdvo->caps.output_flags & |
79e53945 | 2622 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 2623 | return true; |
79e53945 | 2624 | |
f899fc64 | 2625 | err: |
373a3cf7 | 2626 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 2627 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2628 | kfree(intel_sdvo); |
79e53945 | 2629 | |
7d57382e | 2630 | return false; |
79e53945 | 2631 | } |