drm/nvd0-/disp: handle case where display engine is missing/disabled
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / disp / nvf0.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <engine/software.h>
26#include <engine/disp.h>
27
28#include <core/class.h>
29
30#include "nv50.h"
31
32static struct nouveau_oclass
33nvf0_disp_sclass[] = {
34 { NVF0_DISP_MAST_CLASS, &nvd0_disp_mast_ofuncs },
35 { NVF0_DISP_SYNC_CLASS, &nvd0_disp_sync_ofuncs },
36 { NVF0_DISP_OVLY_CLASS, &nvd0_disp_ovly_ofuncs },
37 { NVF0_DISP_OIMM_CLASS, &nvd0_disp_oimm_ofuncs },
38 { NVF0_DISP_CURS_CLASS, &nvd0_disp_curs_ofuncs },
39 {}
40};
41
42static struct nouveau_oclass
43nvf0_disp_base_oclass[] = {
44 { NVF0_DISP_CLASS, &nvd0_disp_base_ofuncs, nva3_disp_base_omthds },
45 {}
46};
47
48static int
49nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
50 struct nouveau_oclass *oclass, void *data, u32 size,
51 struct nouveau_object **pobject)
52{
53 struct nv50_disp_priv *priv;
54 int heads = nv_rd32(parent, 0x022448);
55 int ret;
56
791dc143
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57 if (nv_rd32(parent, 0x022500) & 0x00000001)
58 return -ENODEV;
59
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60 ret = nouveau_disp_create(parent, engine, oclass, heads,
61 "PDISP", "display", &priv);
62 *pobject = nv_object(priv);
63 if (ret)
64 return ret;
65
66 nv_engine(priv)->sclass = nvf0_disp_base_oclass;
67 nv_engine(priv)->cclass = &nv50_disp_cclass;
68 nv_subdev(priv)->intr = nvd0_disp_intr;
69 INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
70 priv->sclass = nvf0_disp_sclass;
71 priv->head.nr = heads;
72 priv->dac.nr = 3;
73 priv->sor.nr = 4;
74 priv->dac.power = nv50_dac_power;
75 priv->dac.sense = nv50_dac_sense;
76 priv->sor.power = nv50_sor_power;
77 priv->sor.hda_eld = nvd0_hda_eld;
78 priv->sor.hdmi = nvd0_hdmi_ctrl;
79 priv->sor.dp = &nvd0_sor_dp_func;
80 return 0;
81}
82
83struct nouveau_oclass
84nvf0_disp_oclass = {
85 .handle = NV_ENGINE(DISP, 0x92),
86 .ofuncs = &(struct nouveau_ofuncs) {
87 .ctor = nvf0_disp_ctor,
88 .dtor = _nouveau_disp_dtor,
89 .init = _nouveau_disp_init,
90 .fini = _nouveau_disp_fini,
91 },
92};
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