[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / engine / disp / vga.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/subdev.h>
#include <core/device.h>
#include <subdev/vga.h>

u8
nv_rdport(void *obj, int head, u16 port)
{
	struct nouveau_device *device = nv_device(obj);

	if (device->card_type >= NV_50)
		return nv_rd08(obj, 0x601000 + port);

	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
	    port == 0x03d4 || port == 0x03d5)	/* CR */
		return nv_rd08(obj, 0x601000 + (head * 0x2000) + port);

	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
	    port == 0x03ce || port == 0x03cf) {	/* GR */
		if (device->card_type < NV_40)
			head = 0; /* CR44 selects head */
		return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port);
	}

	nv_error(obj, "unknown vga port 0x%04x\n", port);
	return 0x00;
}

void
nv_wrport(void *obj, int head, u16 port, u8 data)
{
	struct nouveau_device *device = nv_device(obj);

	if (device->card_type >= NV_50)
		nv_wr08(obj, 0x601000 + port, data);
	else
	if (port == 0x03c0 || port == 0x03c1 ||	/* AR */
	    port == 0x03c2 || port == 0x03da ||	/* INP0 */
	    port == 0x03d4 || port == 0x03d5)	/* CR */
		nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data);
	else
	if (port == 0x03c2 || port == 0x03cc ||	/* MISC */
	    port == 0x03c4 || port == 0x03c5 ||	/* SR */
	    port == 0x03ce || port == 0x03cf) {	/* GR */
		if (device->card_type < NV_40)
			head = 0; /* CR44 selects head */
		nv_wr08(obj, 0x0c0000 + (head * 0x2000) + port, data);
	} else
		nv_error(obj, "unknown vga port 0x%04x\n", port);
}

u8
nv_rdvgas(void *obj, int head, u8 index)
{
	nv_wrport(obj, head, 0x03c4, index);
	return nv_rdport(obj, head, 0x03c5);
}

void
nv_wrvgas(void *obj, int head, u8 index, u8 value)
{
	nv_wrport(obj, head, 0x03c4, index);
	nv_wrport(obj, head, 0x03c5, value);
}

u8
nv_rdvgag(void *obj, int head, u8 index)
{
	nv_wrport(obj, head, 0x03ce, index);
	return nv_rdport(obj, head, 0x03cf);
}

void
nv_wrvgag(void *obj, int head, u8 index, u8 value)
{
	nv_wrport(obj, head, 0x03ce, index);
	nv_wrport(obj, head, 0x03cf, value);
}

u8
nv_rdvgac(void *obj, int head, u8 index)
{
	nv_wrport(obj, head, 0x03d4, index);
	return nv_rdport(obj, head, 0x03d5);
}

void
nv_wrvgac(void *obj, int head, u8 index, u8 value)
{
	nv_wrport(obj, head, 0x03d4, index);
	nv_wrport(obj, head, 0x03d5, value);
}

u8
nv_rdvgai(void *obj, int head, u16 port, u8 index)
{
	if (port == 0x03c4) return nv_rdvgas(obj, head, index);
	if (port == 0x03ce) return nv_rdvgag(obj, head, index);
	if (port == 0x03d4) return nv_rdvgac(obj, head, index);
	nv_error(obj, "unknown indexed vga port 0x%04x\n", port);
	return 0x00;
}

void
nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
{
	if      (port == 0x03c4) nv_wrvgas(obj, head, index, value);
	else if (port == 0x03ce) nv_wrvgag(obj, head, index, value);
	else if (port == 0x03d4) nv_wrvgac(obj, head, index, value);
	else nv_error(obj, "unknown indexed vga port 0x%04x\n", port);
}

bool
nv_lockvgac(void *obj, bool lock)
{
	struct nouveau_device *dev = nv_device(obj);

	bool locked = !nv_rdvgac(obj, 0, 0x1f);
	u8 data = lock ? 0x99 : 0x57;
	if (dev->card_type < NV_50)
		nv_wrvgac(obj, 0, 0x1f, data);
	else
		nv_wrvgac(obj, 0, 0x3f, data);
	if (dev->chipset == 0x11) {
		if (!(nv_rd32(obj, 0x001084) & 0x10000000))
			nv_wrvgac(obj, 1, 0x1f, data);
	}
	return locked;
}

/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
 * it affects only the 8 bit vga io regs, which we access using mmio at
 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
 * in general, the set value of cr44 does not matter: reg access works as
 * expected and values can be set for the appropriate head by using a 0x2000
 * offset as required
 * however:
 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
 *    cr44 must be set to 0 or 3 for accessing values on the correct head
 *    through the common 0xc03c* addresses
 * b) in tied mode (4) head B is programmed to the values set on head A, and
 *    access using the head B addresses can have strange results, ergo we leave
 *    tied mode in init once we know to what cr44 should be restored on exit
 *
 * the owner parameter is slightly abused:
 * 0 and 1 are treated as head values and so the set value is (owner * 3)
 * other values are treated as literal values to set
 */
u8
nv_rdvgaowner(void *obj)
{
	if (nv_device(obj)->card_type < NV_50) {
		if (nv_device(obj)->chipset == 0x11) {
			u32 tied = nv_rd32(obj, 0x001084) & 0x10000000;
			if (tied == 0) {
				u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80;
				u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01;
				u8 slB = nv_rdvgac(obj, 1, 0x28) & 0x80;
				u8 tvB = nv_rdvgac(obj, 1, 0x33) & 0x01;
				if (slA && !tvA) return 0x00;
				if (slB && !tvB) return 0x03;
				if (slA) return 0x00;
				if (slB) return 0x03;
				return 0x00;
			}
			return 0x04;
		}

		return nv_rdvgac(obj, 0, 0x44);
	}

	nv_error(obj, "rdvgaowner after nv4x\n");
	return 0x00;
}

void
nv_wrvgaowner(void *obj, u8 select)
{
	if (nv_device(obj)->card_type < NV_50) {
		u8 owner = (select == 1) ? 3 : select;
		if (nv_device(obj)->chipset == 0x11) {
			/* workaround hw lockup bug */
			nv_rdvgac(obj, 0, 0x1f);
			nv_rdvgac(obj, 1, 0x1f);
		}

		nv_wrvgac(obj, 0, 0x44, owner);

		if (nv_device(obj)->chipset == 0x11) {
			nv_wrvgac(obj, 0, 0x2e, owner);
			nv_wrvgac(obj, 0, 0x2e, owner);
		}
	} else
		nv_error(obj, "wrvgaowner after nv4x\n");
}
Commit	Line	Data
4196faa8 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <core/subdev.h>
	26	#include <core/device.h>
5b8a43ae	27	#include <subdev/vga.h>
4196faa8 BS	28
	29	u8
	30	nv_rdport(void *obj, int head, u16 port)
	31	{
	32	struct nouveau_device *device = nv_device(obj);
	33
	34	if (device->card_type >= NV_50)
	35	return nv_rd08(obj, 0x601000 + port);
	36
	37	if (port == 0x03c0 \|\| port == 0x03c1 \|\| /* AR */
	38	port == 0x03c2 \|\| port == 0x03da \|\| /* INP0 */
	39	port == 0x03d4 \|\| port == 0x03d5) /* CR */
	40	return nv_rd08(obj, 0x601000 + (head * 0x2000) + port);
	41
	42	if (port == 0x03c2 \|\| port == 0x03cc \|\| /* MISC */
	43	port == 0x03c4 \|\| port == 0x03c5 \|\| /* SR */
	44	port == 0x03ce \|\| port == 0x03cf) { /* GR */
	45	if (device->card_type < NV_40)
	46	head = 0; /* CR44 selects head */
	47	return nv_rd08(obj, 0x0c0000 + (head * 0x2000) + port);
	48	}
	49
	50	nv_error(obj, "unknown vga port 0x%04x\n", port);
	51	return 0x00;
	52	}
	53
	54	void
	55	nv_wrport(void *obj, int head, u16 port, u8 data)
	56	{
	57	struct nouveau_device *device = nv_device(obj);
	58
	59	if (device->card_type >= NV_50)
	60	nv_wr08(obj, 0x601000 + port, data);
	61	else
	62	if (port == 0x03c0 \|\| port == 0x03c1 \|\| /* AR */
	63	port == 0x03c2 \|\| port == 0x03da \|\| /* INP0 */
	64	port == 0x03d4 \|\| port == 0x03d5) /* CR */
	65	nv_wr08(obj, 0x601000 + (head * 0x2000) + port, data);
	66	else
	67	if (port == 0x03c2 \|\| port == 0x03cc \|\| /* MISC */
	68	port == 0x03c4 \|\| port == 0x03c5 \|\| /* SR */
	69	port == 0x03ce \|\| port == 0x03cf) { /* GR */
	70	if (device->card_type < NV_40)
	71	head = 0; /* CR44 selects head */
	72	nv_wr08(obj, 0x0c0000 + (head * 0x2000) + port, data);
	73	} else
	74	nv_error(obj, "unknown vga port 0x%04x\n", port);
	75	}
	76
	77	u8
	78	nv_rdvgas(void *obj, int head, u8 index)
	79	{
	80	nv_wrport(obj, head, 0x03c4, index);
	81	return nv_rdport(obj, head, 0x03c5);
	82	}
	83
	84	void
	85	nv_wrvgas(void *obj, int head, u8 index, u8 value)
	86	{
	87	nv_wrport(obj, head, 0x03c4, index);
	88	nv_wrport(obj, head, 0x03c5, value);
	89	}
	90
	91	u8
92	nv_rdvgag(void *obj, int head, u8 index)
93	{
94	nv_wrport(obj, head, 0x03ce, index);
95	return nv_rdport(obj, head, 0x03cf);
96	}
97
98	void
99	nv_wrvgag(void *obj, int head, u8 index, u8 value)
100	{
101	nv_wrport(obj, head, 0x03ce, index);
102	nv_wrport(obj, head, 0x03cf, value);
103	}
104
105	u8
106	nv_rdvgac(void *obj, int head, u8 index)
107	{
108	nv_wrport(obj, head, 0x03d4, index);
109	return nv_rdport(obj, head, 0x03d5);
110	}
111
112	void
113	nv_wrvgac(void *obj, int head, u8 index, u8 value)
114	{
115	nv_wrport(obj, head, 0x03d4, index);
116	nv_wrport(obj, head, 0x03d5, value);
117	}
118
119	u8
120	nv_rdvgai(void *obj, int head, u16 port, u8 index)
121	{
122	if (port == 0x03c4) return nv_rdvgas(obj, head, index);
123	if (port == 0x03ce) return nv_rdvgag(obj, head, index);
124	if (port == 0x03d4) return nv_rdvgac(obj, head, index);
125	nv_error(obj, "unknown indexed vga port 0x%04x\n", port);
126	return 0x00;
127	}
128
129	void
130	nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
131	{
132	if (port == 0x03c4) nv_wrvgas(obj, head, index, value);
133	else if (port == 0x03ce) nv_wrvgag(obj, head, index, value);
134	else if (port == 0x03d4) nv_wrvgac(obj, head, index, value);
135	else nv_error(obj, "unknown indexed vga port 0x%04x\n", port);
136	}
137
138	bool
139	nv_lockvgac(void *obj, bool lock)
140	{
f87cd8b6 IM	141	struct nouveau_device *dev = nv_device(obj);
f87cd8b6 IM	142
4196faa8 BS	143	bool locked = !nv_rdvgac(obj, 0, 0x1f);
4196faa8 BS	144	u8 data = lock ? 0x99 : 0x57;
f87cd8b6 IM	145	if (dev->card_type < NV_50)
	146	nv_wrvgac(obj, 0, 0x1f, data);
	147	else
	148	nv_wrvgac(obj, 0, 0x3f, data);
	149	if (dev->chipset == 0x11) {
4196faa8 BS	150	if (!(nv_rd32(obj, 0x001084) & 0x10000000))
	151	nv_wrvgac(obj, 1, 0x1f, data);
	152	}
	153	return locked;
	154	}
	155
	156	/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
	157	* it affects only the 8 bit vga io regs, which we access using mmio at
	158	* 0xc{0,2}3c, 0x60{1,3}3, and 0x68{1,3}3d*
	159	* in general, the set value of cr44 does not matter: reg access works as
	160	* expected and values can be set for the appropriate head by using a 0x2000
	161	* offset as required
	162	* however:
	163	* a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
	164	* cr44 must be set to 0 or 3 for accessing values on the correct head
	165	* through the common 0xc03c* addresses
	166	* b) in tied mode (4) head B is programmed to the values set on head A, and
	167	* access using the head B addresses can have strange results, ergo we leave
	168	* tied mode in init once we know to what cr44 should be restored on exit
	169	*
	170	* the owner parameter is slightly abused:
	171	* 0 and 1 are treated as head values and so the set value is (owner * 3)
	172	* other values are treated as literal values to set
	173	*/
	174	u8
	175	nv_rdvgaowner(void *obj)
	176	{
	177	if (nv_device(obj)->card_type < NV_50) {
	178	if (nv_device(obj)->chipset == 0x11) {
	179	u32 tied = nv_rd32(obj, 0x001084) & 0x10000000;
	180	if (tied == 0) {
	181	u8 slA = nv_rdvgac(obj, 0, 0x28) & 0x80;
	182	u8 tvA = nv_rdvgac(obj, 0, 0x33) & 0x01;
	183	u8 slB = nv_rdvgac(obj, 1, 0x28) & 0x80;
	184	u8 tvB = nv_rdvgac(obj, 1, 0x33) & 0x01;
	185	if (slA && !tvA) return 0x00;
	186	if (slB && !tvB) return 0x03;
	187	if (slA) return 0x00;
	188	if (slB) return 0x03;
	189	return 0x00;
	190	}
	191	return 0x04;
	192	}
	193
	194	return nv_rdvgac(obj, 0, 0x44);
	195	}
	196
	197	nv_error(obj, "rdvgaowner after nv4x\n");
	198	return 0x00;
	199	}
	200
	201	void
	202	nv_wrvgaowner(void *obj, u8 select)
	203	{
	204	if (nv_device(obj)->card_type < NV_50) {
	205	u8 owner = (select == 1) ? 3 : select;
	206	if (nv_device(obj)->chipset == 0x11) {
	207	/* workaround hw lockup bug */
	208	nv_rdvgac(obj, 0, 0x1f);
	209	nv_rdvgac(obj, 1, 0x1f);
	210	}
	211
	212	nv_wrvgac(obj, 0, 0x44, owner);
	213
214	if (nv_device(obj)->chipset == 0x11) {
215	nv_wrvgac(obj, 0, 0x2e, owner);
216	nv_wrvgac(obj, 0, 0x2e, owner);
217	}
218	} else
219	nv_error(obj, "wrvgaowner after nv4x\n");
220	}