[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / clock / nv04.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/clock.h>
#include <subdev/bios.h>
#include <subdev/bios/pll.h>

#include "pll.h"

struct nv04_clock_priv {
	struct nouveau_clock base;
};

static int
powerctrl_1_shift(int chip_version, int reg)
{
	int shift = -4;

	if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
		return shift;

	switch (reg) {
	case 0x680520:
		shift += 4;
	case 0x680508:
		shift += 4;
	case 0x680504:
		shift += 4;
	case 0x680500:
		shift += 4;
	}

	/*
	 * the shift for vpll regs is only used for nv3x chips with a single
	 * stage pll
	 */
	if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
			  chip_version == 0x36 || chip_version >= 0x40))
		shift = -4;

	return shift;
}

static void
setPLL_single(struct nv04_clock_priv *priv, u32 reg,
	      struct nouveau_pll_vals *pv)
{
	int chip_version = nouveau_bios(priv)->version.chip;
	uint32_t oldpll = nv_rd32(priv, reg);
	int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
	uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
	uint32_t saved_powerctrl_1 = 0;
	int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);

	if (oldpll == pll)
		return;	/* already set */

	if (shift_powerctrl_1 >= 0) {
		saved_powerctrl_1 = nv_rd32(priv, 0x001584);
		nv_wr32(priv, 0x001584,
			(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
			1 << shift_powerctrl_1);
	}

	if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
		/* upclock -- write new post divider first */
		nv_wr32(priv, reg, pv->log2P << 16 | (oldpll & 0xffff));
	else
		/* downclock -- write new NM first */
		nv_wr32(priv, reg, (oldpll & 0xffff0000) | pv->NM1);

	if (chip_version < 0x17 && chip_version != 0x11)
		/* wait a bit on older chips */
		msleep(64);
	nv_rd32(priv, reg);

	/* then write the other half as well */
	nv_wr32(priv, reg, pll);

	if (shift_powerctrl_1 >= 0)
		nv_wr32(priv, 0x001584, saved_powerctrl_1);
}

static uint32_t
new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
{
	bool head_a = (reg1 == 0x680508);

	if (ss)	/* single stage pll mode */
		ramdac580 |= head_a ? 0x00000100 : 0x10000000;
	else
		ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;

	return ramdac580;
}

static void
setPLL_double_highregs(struct nv04_clock_priv *priv, u32 reg1,
		       struct nouveau_pll_vals *pv)
{
	int chip_version = nouveau_bios(priv)->version.chip;
	bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
	uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
	uint32_t oldpll1 = nv_rd32(priv, reg1);
	uint32_t oldpll2 = !nv3035 ? nv_rd32(priv, reg2) : 0;
	uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
	uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
	uint32_t oldramdac580 = 0, ramdac580 = 0;
	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;	/* nv41+ only */
	uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
	int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);

	/* model specific additions to generic pll1 and pll2 set up above */
	if (nv3035) {
		pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
		       (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
		pll2 = 0;
	}
	if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
		oldramdac580 = nv_rd32(priv, 0x680580);
		ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
		if (oldramdac580 != ramdac580)
			oldpll1 = ~0;	/* force mismatch */
		if (single_stage)
			/* magic value used by nvidia in single stage mode */
			pll2 |= 0x011f;
	}
	if (chip_version > 0x70)
		/* magic bits set by the blob (but not the bios) on g71-73 */
		pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;

	if (oldpll1 == pll1 && oldpll2 == pll2)
		return;	/* already set */

	if (shift_powerctrl_1 >= 0) {
		saved_powerctrl_1 = nv_rd32(priv, 0x001584);
		nv_wr32(priv, 0x001584,
			(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
			1 << shift_powerctrl_1);
	}

	if (chip_version >= 0x40) {
		int shift_c040 = 14;

		switch (reg1) {
		case 0x680504:
			shift_c040 += 2;
		case 0x680500:
			shift_c040 += 2;
		case 0x680520:
			shift_c040 += 2;
		case 0x680508:
			shift_c040 += 2;
		}

		savedc040 = nv_rd32(priv, 0xc040);
		if (shift_c040 != 14)
			nv_wr32(priv, 0xc040, savedc040 & ~(3 << shift_c040));
	}

	if (oldramdac580 != ramdac580)
		nv_wr32(priv, 0x680580, ramdac580);

	if (!nv3035)
		nv_wr32(priv, reg2, pll2);
	nv_wr32(priv, reg1, pll1);

	if (shift_powerctrl_1 >= 0)
		nv_wr32(priv, 0x001584, saved_powerctrl_1);
	if (chip_version >= 0x40)
		nv_wr32(priv, 0xc040, savedc040);
}

static void
setPLL_double_lowregs(struct nv04_clock_priv *priv, u32 NMNMreg,
		      struct nouveau_pll_vals *pv)
{
	/* When setting PLLs, there is a merry game of disabling and enabling
	 * various bits of hardware during the process. This function is a
	 * synthesis of six nv4x traces, nearly each card doing a subtly
	 * different thing. With luck all the necessary bits for each card are
	 * combined herein. Without luck it deviates from each card's formula
	 * so as to not work on any :)
	 */

	uint32_t Preg = NMNMreg - 4;
	bool mpll = Preg == 0x4020;
	uint32_t oldPval = nv_rd32(priv, Preg);
	uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
	uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
			0xc << 28 | pv->log2P << 16;
	uint32_t saved4600 = 0;
	/* some cards have different maskc040s */
	uint32_t maskc040 = ~(3 << 14), savedc040;
	bool single_stage = !pv->NM2 || pv->N2 == pv->M2;

	if (nv_rd32(priv, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
		return;

	if (Preg == 0x4000)
		maskc040 = ~0x333;
	if (Preg == 0x4058)
		maskc040 = ~(0xc << 24);

	if (mpll) {
		struct nvbios_pll info;
		uint8_t Pval2;

		if (nvbios_pll_parse(nouveau_bios(priv), Preg, &info))
			return;

		Pval2 = pv->log2P + info.bias_p;
		if (Pval2 > info.max_p)
			Pval2 = info.max_p;
		Pval |= 1 << 28 | Pval2 << 20;

		saved4600 = nv_rd32(priv, 0x4600);
		nv_wr32(priv, 0x4600, saved4600 | 8 << 28);
	}
	if (single_stage)
		Pval |= mpll ? 1 << 12 : 1 << 8;

	nv_wr32(priv, Preg, oldPval | 1 << 28);
	nv_wr32(priv, Preg, Pval & ~(4 << 28));
	if (mpll) {
		Pval |= 8 << 20;
		nv_wr32(priv, 0x4020, Pval & ~(0xc << 28));
		nv_wr32(priv, 0x4038, Pval & ~(0xc << 28));
	}

	savedc040 = nv_rd32(priv, 0xc040);
	nv_wr32(priv, 0xc040, savedc040 & maskc040);

	nv_wr32(priv, NMNMreg, NMNM);
	if (NMNMreg == 0x4024)
		nv_wr32(priv, 0x403c, NMNM);

	nv_wr32(priv, Preg, Pval);
	if (mpll) {
		Pval &= ~(8 << 20);
		nv_wr32(priv, 0x4020, Pval);
		nv_wr32(priv, 0x4038, Pval);
		nv_wr32(priv, 0x4600, saved4600);
	}

	nv_wr32(priv, 0xc040, savedc040);

	if (mpll) {
		nv_wr32(priv, 0x4020, Pval & ~(1 << 28));
		nv_wr32(priv, 0x4038, Pval & ~(1 << 28));
	}
}

int
nv04_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
{
	struct nv04_clock_priv *priv = (void *)clk;
	struct nouveau_pll_vals pv;
	struct nvbios_pll info;
	int ret;

	ret = nvbios_pll_parse(nouveau_bios(priv), type > 0x405c ?
			       type : type - 4, &info);
	if (ret)
		return ret;

	ret = clk->pll_calc(clk, &info, freq, &pv);
	if (!ret)
		return ret;

	return clk->pll_prog(clk, type, &pv);
}

int
nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
		    int clk, struct nouveau_pll_vals *pv)
{
	int N1, M1, N2, M2, P;
	int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
	if (ret) {
		pv->refclk = info->refclk;
		pv->N1 = N1;
		pv->M1 = M1;
		pv->N2 = N2;
		pv->M2 = M2;
		pv->log2P = P;
	}
	return ret;
}

int
nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
		    struct nouveau_pll_vals *pv)
{
	struct nv04_clock_priv *priv = (void *)clk;
	int cv = nouveau_bios(clk)->version.chip;

	if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
	    cv >= 0x40) {
		if (reg1 > 0x405c)
			setPLL_double_highregs(priv, reg1, pv);
		else
			setPLL_double_lowregs(priv, reg1, pv);
	} else
		setPLL_single(priv, reg1, pv);

	return 0;
}

static int
nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nv04_clock_priv *priv;
	int ret;

	ret = nouveau_clock_create(parent, engine, oclass, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.pll_set = nv04_clock_pll_set;
	priv->base.pll_calc = nv04_clock_pll_calc;
	priv->base.pll_prog = nv04_clock_pll_prog;
	return 0;
}

struct nouveau_oclass
nv04_clock_oclass = {
	.handle = NV_SUBDEV(CLOCK, 0x04),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_clock_ctor,
		.dtor = _nouveau_clock_dtor,
		.init = _nouveau_clock_init,
		.fini = _nouveau_clock_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <subdev/clock.h>
70790f4f BS	26	#include <subdev/bios.h>
	27	#include <subdev/bios/pll.h>
	28
	29	#include "pll.h"
8aceb7de BS	30
	31	struct nv04_clock_priv {
	32	struct nouveau_clock base;
	33	};
	34
70790f4f BS	35	static int
	36	powerctrl_1_shift(int chip_version, int reg)
	37	{
	38	int shift = -4;
	39
	40	if (chip_version < 0x17 \|\| chip_version == 0x1a \|\| chip_version == 0x20)
	41	return shift;
	42
	43	switch (reg) {
	44	case 0x680520:
	45	shift += 4;
	46	case 0x680508:
	47	shift += 4;
	48	case 0x680504:
	49	shift += 4;
	50	case 0x680500:
	51	shift += 4;
	52	}
	53
	54	/*
	55	* the shift for vpll regs is only used for nv3x chips with a single
	56	* stage pll
	57	*/
	58	if (shift > 4 && (chip_version < 0x32 \|\| chip_version == 0x35 \|\|
	59	chip_version == 0x36 \|\| chip_version >= 0x40))
	60	shift = -4;
	61
	62	return shift;
	63	}
	64
8aceb7de	65	static void
70790f4f BS	66	setPLL_single(struct nv04_clock_priv *priv, u32 reg,
	67	struct nouveau_pll_vals *pv)
	68	{
	69	int chip_version = nouveau_bios(priv)->version.chip;
	70	uint32_t oldpll = nv_rd32(priv, reg);
	71	int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
	72	uint32_t pll = (oldpll & 0xfff80000) \| pv->log2P << 16 \| pv->NM1;
	73	uint32_t saved_powerctrl_1 = 0;
	74	int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
	75
	76	if (oldpll == pll)
	77	return; /* already set */
	78
	79	if (shift_powerctrl_1 >= 0) {
	80	saved_powerctrl_1 = nv_rd32(priv, 0x001584);
	81	nv_wr32(priv, 0x001584,
	82	(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) \|
	83	1 << shift_powerctrl_1);
	84	}
	85
	86	if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
	87	/* upclock -- write new post divider first */
	88	nv_wr32(priv, reg, pv->log2P << 16 \| (oldpll & 0xffff));
	89	else
	90	/* downclock -- write new NM first */
	91	nv_wr32(priv, reg, (oldpll & 0xffff0000) \| pv->NM1);
	92
	93	if (chip_version < 0x17 && chip_version != 0x11)
	94	/* wait a bit on older chips */
	95	msleep(64);
	96	nv_rd32(priv, reg);
	97
	98	/* then write the other half as well */
	99	nv_wr32(priv, reg, pll);
	100
	101	if (shift_powerctrl_1 >= 0)
	102	nv_wr32(priv, 0x001584, saved_powerctrl_1);
	103	}
	104
	105	static uint32_t
	106	new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
	107	{
	108	bool head_a = (reg1 == 0x680508);
	109
	110	if (ss) /* single stage pll mode */
	111	ramdac580 \|= head_a ? 0x00000100 : 0x10000000;
	112	else
	113	ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
	114
	115	return ramdac580;
	116	}
	117
	118	static void
	119	setPLL_double_highregs(struct nv04_clock_priv *priv, u32 reg1,
	120	struct nouveau_pll_vals *pv)
	121	{
	122	int chip_version = nouveau_bios(priv)->version.chip;
	123	bool nv3035 = chip_version == 0x30 \|\| chip_version == 0x35;
	124	uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
	125	uint32_t oldpll1 = nv_rd32(priv, reg1);
	126	uint32_t oldpll2 = !nv3035 ? nv_rd32(priv, reg2) : 0;
	127	uint32_t pll1 = (oldpll1 & 0xfff80000) \| pv->log2P << 16 \| pv->NM1;
	128	uint32_t pll2 = (oldpll2 & 0x7fff0000) \| 1 << 31 \| pv->NM2;
	129	uint32_t oldramdac580 = 0, ramdac580 = 0;
130	bool single_stage = !pv->NM2 \|\| pv->N2 == pv->M2; /* nv41+ only */
131	uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
132	int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
133
134	/* model specific additions to generic pll1 and pll2 set up above */
135	if (nv3035) {
136	pll1 = (pll1 & 0xfcc7ffff) \| (pv->N2 & 0x18) << 21 \|
137	(pv->N2 & 0x7) << 19 \| 8 << 4 \| (pv->M2 & 7) << 4;
138	pll2 = 0;
139	}
140	if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
141	oldramdac580 = nv_rd32(priv, 0x680580);
142	ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
143	if (oldramdac580 != ramdac580)
144	oldpll1 = ~0; /* force mismatch */
145	if (single_stage)
146	/* magic value used by nvidia in single stage mode */
147	pll2 \|= 0x011f;
148	}
149	if (chip_version > 0x70)
150	/* magic bits set by the blob (but not the bios) on g71-73 */
151	pll1 = (pll1 & 0x7fffffff) \| (single_stage ? 0x4 : 0xc) << 28;
152
153	if (oldpll1 == pll1 && oldpll2 == pll2)
154	return; /* already set */
155
156	if (shift_powerctrl_1 >= 0) {
157	saved_powerctrl_1 = nv_rd32(priv, 0x001584);
158	nv_wr32(priv, 0x001584,
159	(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) \|
160	1 << shift_powerctrl_1);
161	}
162
163	if (chip_version >= 0x40) {
164	int shift_c040 = 14;
165
166	switch (reg1) {
167	case 0x680504:
168	shift_c040 += 2;
169	case 0x680500:
170	shift_c040 += 2;
171	case 0x680520:
172	shift_c040 += 2;
173	case 0x680508:
174	shift_c040 += 2;
175	}
176
177	savedc040 = nv_rd32(priv, 0xc040);
178	if (shift_c040 != 14)
179	nv_wr32(priv, 0xc040, savedc040 & ~(3 << shift_c040));
180	}
181
182	if (oldramdac580 != ramdac580)
183	nv_wr32(priv, 0x680580, ramdac580);
184
185	if (!nv3035)
186	nv_wr32(priv, reg2, pll2);
187	nv_wr32(priv, reg1, pll1);
188
189	if (shift_powerctrl_1 >= 0)
190	nv_wr32(priv, 0x001584, saved_powerctrl_1);
191	if (chip_version >= 0x40)
192	nv_wr32(priv, 0xc040, savedc040);
193	}
194
195	static void
196	setPLL_double_lowregs(struct nv04_clock_priv *priv, u32 NMNMreg,
197	struct nouveau_pll_vals *pv)
198	{
199	/* When setting PLLs, there is a merry game of disabling and enabling
200	* various bits of hardware during the process. This function is a
201	* synthesis of six nv4x traces, nearly each card doing a subtly
202	* different thing. With luck all the necessary bits for each card are
203	* combined herein. Without luck it deviates from each card's formula
204	* so as to not work on any :)
205	*/
206
207	uint32_t Preg = NMNMreg - 4;
208	bool mpll = Preg == 0x4020;
209	uint32_t oldPval = nv_rd32(priv, Preg);
210	uint32_t NMNM = pv->NM2 << 16 \| pv->NM1;
211	uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) \|
212	0xc << 28 \| pv->log2P << 16;
213	uint32_t saved4600 = 0;
214	/* some cards have different maskc040s */
215	uint32_t maskc040 = ~(3 << 14), savedc040;
216	bool single_stage = !pv->NM2 \|\| pv->N2 == pv->M2;
217
218	if (nv_rd32(priv, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
219	return;
220
221	if (Preg == 0x4000)
222	maskc040 = ~0x333;
223	if (Preg == 0x4058)
224	maskc040 = ~(0xc << 24);
225
226	if (mpll) {
227	struct nvbios_pll info;
228	uint8_t Pval2;
229
230	if (nvbios_pll_parse(nouveau_bios(priv), Preg, &info))
231	return;
232
233	Pval2 = pv->log2P + info.bias_p;
234	if (Pval2 > info.max_p)
235	Pval2 = info.max_p;
236	Pval \|= 1 << 28 \| Pval2 << 20;
237
238	saved4600 = nv_rd32(priv, 0x4600);
239	nv_wr32(priv, 0x4600, saved4600 \| 8 << 28);
240	}
241	if (single_stage)
242	Pval \|= mpll ? 1 << 12 : 1 << 8;
243
244	nv_wr32(priv, Preg, oldPval \| 1 << 28);
245	nv_wr32(priv, Preg, Pval & ~(4 << 28));
246	if (mpll) {
247	Pval \|= 8 << 20;
248	nv_wr32(priv, 0x4020, Pval & ~(0xc << 28));
249	nv_wr32(priv, 0x4038, Pval & ~(0xc << 28));
250	}
251
252	savedc040 = nv_rd32(priv, 0xc040);
253	nv_wr32(priv, 0xc040, savedc040 & maskc040);
254
255	nv_wr32(priv, NMNMreg, NMNM);
256	if (NMNMreg == 0x4024)
257	nv_wr32(priv, 0x403c, NMNM);
258
259	nv_wr32(priv, Preg, Pval);
260	if (mpll) {
261	Pval &= ~(8 << 20);
262	nv_wr32(priv, 0x4020, Pval);
263	nv_wr32(priv, 0x4038, Pval);
264	nv_wr32(priv, 0x4600, saved4600);
265	}
266
267	nv_wr32(priv, 0xc040, savedc040);
268
269	if (mpll) {
270	nv_wr32(priv, 0x4020, Pval & ~(1 << 28));
271	nv_wr32(priv, 0x4038, Pval & ~(1 << 28));
272	}
273	}
274
275	int
8aceb7de BS	276	nv04_clock_pll_set(struct nouveau_clock *clk, u32 type, u32 freq)
	277	{
	278	struct nv04_clock_priv priv = (void )clk;
70790f4f BS	279	struct nouveau_pll_vals pv;
	280	struct nvbios_pll info;
	281	int ret;
	282
	283	ret = nvbios_pll_parse(nouveau_bios(priv), type > 0x405c ?
	284	type : type - 4, &info);
	285	if (ret)
	286	return ret;
	287
	288	ret = clk->pll_calc(clk, &info, freq, &pv);
	289	if (!ret)
	290	return ret;
	291
	292	return clk->pll_prog(clk, type, &pv);
	293	}
8aceb7de	294
70790f4f BS	295	int
	296	nv04_clock_pll_calc(struct nouveau_clock clock, struct nvbios_pll info,
	297	int clk, struct nouveau_pll_vals *pv)
	298	{
	299	int N1, M1, N2, M2, P;
7ada785f	300	int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
70790f4f BS	301	if (ret) {
	302	pv->refclk = info->refclk;
	303	pv->N1 = N1;
	304	pv->M1 = M1;
	305	pv->N2 = N2;
	306	pv->M2 = M2;
	307	pv->log2P = P;
	308	}
	309	return ret;
	310	}
	311
	312	int
	313	nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
	314	struct nouveau_pll_vals *pv)
	315	{
	316	struct nv04_clock_priv priv = (void )clk;
	317	int cv = nouveau_bios(clk)->version.chip;
	318
	319	if (cv == 0x30 \|\| cv == 0x31 \|\| cv == 0x35 \|\| cv == 0x36 \|\|
	320	cv >= 0x40) {
	321	if (reg1 > 0x405c)
	322	setPLL_double_highregs(priv, reg1, pv);
	323	else
	324	setPLL_double_lowregs(priv, reg1, pv);
	325	} else
	326	setPLL_single(priv, reg1, pv);
	327
	328	return 0;
8aceb7de BS	329	}
	330
	331	static int
	332	nv04_clock_ctor(struct nouveau_object parent, struct nouveau_object engine,
	333	struct nouveau_oclass oclass, void data, u32 size,
	334	struct nouveau_object **pobject)
	335	{
	336	struct nv04_clock_priv *priv;
	337	int ret;
	338
	339	ret = nouveau_clock_create(parent, engine, oclass, &priv);
	340	*pobject = nv_object(priv);
	341	if (ret)
	342	return ret;
	343
	344	priv->base.pll_set = nv04_clock_pll_set;
70790f4f BS	345	priv->base.pll_calc = nv04_clock_pll_calc;
70790f4f BS	346	priv->base.pll_prog = nv04_clock_pll_prog;
8aceb7de BS	347	return 0;
	348	}
	349
	350	struct nouveau_oclass
	351	nv04_clock_oclass = {
	352	.handle = NV_SUBDEV(CLOCK, 0x04),
	353	.ofuncs = &(struct nouveau_ofuncs) {
	354	.ctor = nv04_clock_ctor,
	355	.dtor = _nouveau_clock_dtor,
	356	.init = _nouveau_clock_init,
	357	.fini = _nouveau_clock_fini,
	358	},
	359	};