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1 | #ifndef __NVKM_FBRAM_FUC_H__ |
2 | #define __NVKM_FBRAM_FUC_H__ | |
3 | ||
4 | #include <subdev/pwr.h> | |
5 | ||
6 | struct ramfuc { | |
7 | struct nouveau_memx *memx; | |
8 | struct nouveau_fb *pfb; | |
9 | int sequence; | |
10 | }; | |
11 | ||
12 | struct ramfuc_reg { | |
13 | int sequence; | |
14 | bool force; | |
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15 | u32 addr; |
16 | u32 stride; /* in bytes */ | |
17 | u32 mask; | |
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18 | u32 data; |
19 | }; | |
20 | ||
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21 | static inline struct ramfuc_reg |
22 | ramfuc_stride(u32 addr, u32 stride, u32 mask) | |
23 | { | |
24 | return (struct ramfuc_reg) { | |
25 | .sequence = 0, | |
26 | .addr = addr, | |
27 | .stride = stride, | |
28 | .mask = mask, | |
29 | .data = 0xdeadbeef, | |
30 | }; | |
31 | } | |
32 | ||
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33 | static inline struct ramfuc_reg |
34 | ramfuc_reg2(u32 addr1, u32 addr2) | |
35 | { | |
36 | return (struct ramfuc_reg) { | |
37 | .sequence = 0, | |
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38 | .addr = addr1, |
39 | .stride = addr2 - addr1, | |
40 | .mask = 0x3, | |
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41 | .data = 0xdeadbeef, |
42 | }; | |
43 | } | |
44 | ||
3c4be80b | 45 | static noinline struct ramfuc_reg |
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46 | ramfuc_reg(u32 addr) |
47 | { | |
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48 | return (struct ramfuc_reg) { |
49 | .sequence = 0, | |
50 | .addr = addr, | |
51 | .stride = 0, | |
52 | .mask = 0x1, | |
53 | .data = 0xdeadbeef, | |
54 | }; | |
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55 | } |
56 | ||
57 | static inline int | |
58 | ramfuc_init(struct ramfuc *ram, struct nouveau_fb *pfb) | |
59 | { | |
60 | struct nouveau_pwr *ppwr = nouveau_pwr(pfb); | |
61 | int ret; | |
62 | ||
63 | ret = nouveau_memx_init(ppwr, &ram->memx); | |
64 | if (ret) | |
65 | return ret; | |
66 | ||
67 | ram->sequence++; | |
68 | ram->pfb = pfb; | |
69 | return 0; | |
70 | } | |
71 | ||
72 | static inline int | |
73 | ramfuc_exec(struct ramfuc *ram, bool exec) | |
74 | { | |
75 | int ret = 0; | |
76 | if (ram->pfb) { | |
77 | ret = nouveau_memx_fini(&ram->memx, exec); | |
78 | ram->pfb = NULL; | |
79 | } | |
80 | return ret; | |
81 | } | |
82 | ||
83 | static inline u32 | |
84 | ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg) | |
85 | { | |
86 | if (reg->sequence != ram->sequence) | |
930da220 | 87 | reg->data = nv_rd32(ram->pfb, reg->addr); |
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88 | return reg->data; |
89 | } | |
90 | ||
91 | static inline void | |
92 | ramfuc_wr32(struct ramfuc *ram, struct ramfuc_reg *reg, u32 data) | |
93 | { | |
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94 | unsigned int mask, off = 0; |
95 | ||
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96 | reg->sequence = ram->sequence; |
97 | reg->data = data; | |
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98 | |
99 | for (mask = reg->mask; mask > 0; mask = (mask & ~1) >> 1) { | |
100 | if (mask & 1) { | |
101 | nouveau_memx_wr32(ram->memx, reg->addr+off, reg->data); | |
102 | } | |
103 | ||
104 | off += reg->stride; | |
105 | } | |
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106 | } |
107 | ||
108 | static inline void | |
109 | ramfuc_nuke(struct ramfuc *ram, struct ramfuc_reg *reg) | |
110 | { | |
111 | reg->force = true; | |
112 | } | |
113 | ||
114 | static inline u32 | |
115 | ramfuc_mask(struct ramfuc *ram, struct ramfuc_reg *reg, u32 mask, u32 data) | |
116 | { | |
117 | u32 temp = ramfuc_rd32(ram, reg); | |
118 | if (temp != ((temp & ~mask) | data) || reg->force) { | |
119 | ramfuc_wr32(ram, reg, (temp & ~mask) | data); | |
120 | reg->force = false; | |
121 | } | |
122 | return temp; | |
123 | } | |
124 | ||
125 | static inline void | |
126 | ramfuc_wait(struct ramfuc *ram, u32 addr, u32 mask, u32 data, u32 nsec) | |
127 | { | |
128 | nouveau_memx_wait(ram->memx, addr, mask, data, nsec); | |
129 | } | |
130 | ||
131 | static inline void | |
132 | ramfuc_nsec(struct ramfuc *ram, u32 nsec) | |
133 | { | |
134 | nouveau_memx_nsec(ram->memx, nsec); | |
135 | } | |
136 | ||
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137 | static inline void |
138 | ramfuc_wait_vblank(struct ramfuc *ram) | |
139 | { | |
140 | nouveau_memx_wait_vblank(ram->memx); | |
141 | } | |
142 | ||
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143 | static inline void |
144 | ramfuc_train(struct ramfuc *ram) | |
145 | { | |
146 | nouveau_memx_train(ram->memx); | |
147 | } | |
148 | ||
149 | static inline int | |
150 | ramfuc_train_result(struct nouveau_fb *pfb, u32 *result, u32 rsize) | |
151 | { | |
152 | struct nouveau_pwr *ppwr = nouveau_pwr(pfb); | |
153 | ||
154 | return nouveau_memx_train_result(ppwr, result, rsize); | |
155 | } | |
156 | ||
d93e996a | 157 | static inline void |
630a6a46 | 158 | ramfuc_block(struct ramfuc *ram) |
d93e996a | 159 | { |
630a6a46 | 160 | nouveau_memx_block(ram->memx); |
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161 | } |
162 | ||
163 | static inline void | |
630a6a46 | 164 | ramfuc_unblock(struct ramfuc *ram) |
d93e996a | 165 | { |
630a6a46 | 166 | nouveau_memx_unblock(ram->memx); |
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167 | } |
168 | ||
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169 | #define ram_init(s,p) ramfuc_init(&(s)->base, (p)) |
170 | #define ram_exec(s,e) ramfuc_exec(&(s)->base, (e)) | |
930da220 | 171 | #define ram_have(s,r) ((s)->r_##r.addr != 0x000000) |
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172 | #define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r) |
173 | #define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d)) | |
174 | #define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r) | |
175 | #define ram_mask(s,r,m,d) ramfuc_mask(&(s)->base, &(s)->r_##r, (m), (d)) | |
176 | #define ram_wait(s,r,m,d,n) ramfuc_wait(&(s)->base, (r), (m), (d), (n)) | |
177 | #define ram_nsec(s,n) ramfuc_nsec(&(s)->base, (n)) | |
178 | #define ram_wait_vblank(s) ramfuc_wait_vblank(&(s)->base) | |
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179 | #define ram_train(s) ramfuc_train(&(s)->base) |
180 | #define ram_train_result(s,r,l) ramfuc_train_result((s), (r), (l)) | |
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181 | #define ram_block(s) ramfuc_block(&(s)->base) |
182 | #define ram_unblock(s) ramfuc_unblock(&(s)->base) | |
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183 | |
184 | #endif |