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drm/nouveau/clk: rename from clock (no binary change)
[deliverable/linux.git] / drivers / gpu / drm / nouveau / dispnv04 / crtc.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
5addcf0a 25#include <linux/pm_runtime.h>
6ee73861 26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
3cb9ae4f 29#include <drm/drm_plane_helper.h>
6ee73861 30
77145f1c
BS		 31#include "nouveau_drm.h"
32#include "nouveau_reg.h"
33#include "nouveau_bo.h"
34#include "nouveau_gem.h"
6ee73861
BS		 35#include "nouveau_encoder.h"
36#include "nouveau_connector.h"
37#include "nouveau_crtc.h"
1a646342 38#include "hw.h"
6ee73861 39#include "nvreg.h"
a424d761 40#include "nouveau_fbcon.h"
1a646342 41#include "disp.h"
77145f1c
BS		 42
43#include <subdev/bios/pll.h>
f3867f43 44#include <subdev/clk.h>
6ee73861
BS		 45
46static int
47nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
48 struct drm_framebuffer *old_fb);
49
50static void
51crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
52{
53 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
54 crtcstate->CRTC[index]);
55}
56
57static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
58{
59 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 60 struct drm_device *dev = crtc->dev;
61 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 62
63 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
64 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
65 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
66 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
67 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
68 }
69 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
70}
71
72static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
73{
74 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 75 struct drm_device *dev = crtc->dev;
76 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 77
78 nv_crtc->sharpness = level;
79 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
80 level += 0x40;
81 regp->ramdac_634 = level;
82 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
83}
84
85#define PLLSEL_VPLL1_MASK \
86 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
87 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
88#define PLLSEL_VPLL2_MASK \
89 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
90 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
91#define PLLSEL_TV_MASK \
92 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
93 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
94 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
95 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
96
97/* NV4x 0x40.. pll notes:
98 * gpu pll: 0x4000 + 0x4004
99 * ?gpu? pll: 0x4008 + 0x400c
100 * vpll1: 0x4010 + 0x4014
101 * vpll2: 0x4018 + 0x401c
102 * mpll: 0x4020 + 0x4024
103 * mpll: 0x4038 + 0x403c
104 *
105 * the first register of each pair has some unknown details:
106 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
107 * bits 20-23: (mpll) something to do with post divider?
108 * bits 28-31: related to single stage mode? (bit 8/12)
109 */
110
111static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
112{
113 struct drm_device *dev = crtc->dev;
77145f1c 114 struct nouveau_drm *drm = nouveau_drm(dev);
967e7bde 115 struct nouveau_bios *bios = nvkm_bios(&drm->device);
f3867f43 116 struct nouveau_clk *clk = nvkm_clk(&drm->device);
6ee73861 117 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 118 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
6ee73861
BS		 119 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
120 struct nouveau_pll_vals *pv = &regp->pllvals;
70790f4f 121 struct nvbios_pll pll_lim;
6ee73861 122
77145f1c
BS		 123 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
124 &pll_lim))
6ee73861
BS		 125 return;
126
127 /* NM2 == 0 is used to determine single stage mode on two stage plls */
128 pv->NM2 = 0;
129
130 /* for newer nv4x the blob uses only the first stage of the vpll below a
131 * certain clock. for a certain nv4b this is 150MHz. since the max
132 * output frequency of the first stage for this card is 300MHz, it is
133 * assumed the threshold is given by vco1 maxfreq/2
134 */
135 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
136 * not 8, others unknown), the blob always uses both plls. no problem
137 * has yet been observed in allowing the use a single stage pll on all
138 * nv43 however. the behaviour of single stage use is untested on nv40
139 */
967e7bde 140 if (drm->device.info.chipset > 0x40 && dot_clock <= (pll_lim.vco1.max_freq / 2))
6ee73861
BS		 141 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
142
77145f1c
BS		 143
144 if (!clk->pll_calc(clk, &pll_lim, dot_clock, pv))
6ee73861
BS		 145 return;
146
147 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
148
149 /* The blob uses this always, so let's do the same */
967e7bde 150 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
6ee73861
BS		 151 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
152 /* again nv40 and some nv43 act more like nv3x as described above */
967e7bde 153 if (drm->device.info.chipset < 0x41)
6ee73861
BS		 154 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
155 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
156 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
157
158 if (pv->NM2)
77145f1c 159 NV_DEBUG(drm, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
6ee73861
BS		 160 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
161 else
77145f1c 162 NV_DEBUG(drm, "vpll: n %d m %d log2p %d\n",
6ee73861
BS		 163 pv->N1, pv->M1, pv->log2P);
164
165 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
166}
167
168static void
169nv_crtc_dpms(struct drm_crtc *crtc, int mode)
170{
171 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
77145f1c 173 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861
BS		 174 unsigned char seq1 = 0, crtc17 = 0;
175 unsigned char crtc1A;
176
77145f1c 177 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
6ee73861
BS		 178 nv_crtc->index);
179
25985edc 180 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
6ee73861
BS		 181 return;
182
183 nv_crtc->last_dpms = mode;
184
185 if (nv_two_heads(dev))
186 NVSetOwner(dev, nv_crtc->index);
187
188 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
189 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
190 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
191 switch (mode) {
192 case DRM_MODE_DPMS_STANDBY:
193 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
194 seq1 = 0x20;
195 crtc17 = 0x80;
196 crtc1A |= 0x80;
197 break;
198 case DRM_MODE_DPMS_SUSPEND:
199 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
200 seq1 = 0x20;
201 crtc17 = 0x80;
202 crtc1A |= 0x40;
203 break;
204 case DRM_MODE_DPMS_OFF:
205 /* Screen: Off; HSync: Off, VSync: Off */
206 seq1 = 0x20;
207 crtc17 = 0x00;
208 crtc1A |= 0xC0;
209 break;
210 case DRM_MODE_DPMS_ON:
211 default:
212 /* Screen: On; HSync: On, VSync: On */
213 seq1 = 0x00;
214 crtc17 = 0x80;
215 break;
216 }
217
218 NVVgaSeqReset(dev, nv_crtc->index, true);
219 /* Each head has it's own sequencer, so we can turn it off when we want */
220 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
221 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
222 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
223 mdelay(10);
224 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
225 NVVgaSeqReset(dev, nv_crtc->index, false);
226
227 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
228}
229
230static bool
e811f5ae 231nv_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
6ee73861
BS		 232 struct drm_display_mode *adjusted_mode)
233{
234 return true;
235}
236
237static void
238nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
239{
240 struct drm_device *dev = crtc->dev;
6ee73861 241 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 242 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
f4510a27 243 struct drm_framebuffer *fb = crtc->primary->fb;
6ee73861
BS		 244
245 /* Calculate our timings */
e5ec882c
FJ		 246 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
247 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
248 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
6ee73861
BS		 249 int horizTotal = (mode->crtc_htotal >> 3) - 5;
250 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
251 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
252 int vertDisplay = mode->crtc_vdisplay - 1;
253 int vertStart = mode->crtc_vsync_start - 1;
254 int vertEnd = mode->crtc_vsync_end - 1;
255 int vertTotal = mode->crtc_vtotal - 2;
256 int vertBlankStart = mode->crtc_vdisplay - 1;
257 int vertBlankEnd = mode->crtc_vtotal - 1;
258
259 struct drm_encoder *encoder;
260 bool fp_output = false;
261
262 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
263 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
264
265 if (encoder->crtc == crtc &&
cb75d97e
BS		 266 (nv_encoder->dcb->type == DCB_OUTPUT_LVDS ||
267 nv_encoder->dcb->type == DCB_OUTPUT_TMDS))
6ee73861
BS		 268 fp_output = true;
269 }
270
271 if (fp_output) {
272 vertStart = vertTotal - 3;
273 vertEnd = vertTotal - 2;
274 vertBlankStart = vertStart;
275 horizStart = horizTotal - 5;
276 horizEnd = horizTotal - 2;
277 horizBlankEnd = horizTotal + 4;
278#if 0
967e7bde 279 if (dev->overlayAdaptor && drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
6ee73861
BS		 280 /* This reportedly works around some video overlay bandwidth problems */
281 horizTotal += 2;
282#endif
283 }
284
285 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
286 vertTotal |= 1;
287
288#if 0
289 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
290 ErrorF("horizStart: 0x%X \n", horizStart);
291 ErrorF("horizEnd: 0x%X \n", horizEnd);
292 ErrorF("horizTotal: 0x%X \n", horizTotal);
293 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
294 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
295 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
296 ErrorF("vertStart: 0x%X \n", vertStart);
297 ErrorF("vertEnd: 0x%X \n", vertEnd);
298 ErrorF("vertTotal: 0x%X \n", vertTotal);
299 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
300 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
301#endif
302
303 /*
304 * compute correct Hsync & Vsync polarity
305 */
306 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
307 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
308
309 regp->MiscOutReg = 0x23;
310 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
311 regp->MiscOutReg |= 0x40;
312 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
313 regp->MiscOutReg |= 0x80;
314 } else {
315 int vdisplay = mode->vdisplay;
316 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
317 vdisplay *= 2;
318 if (mode->vscan > 1)
319 vdisplay *= mode->vscan;
320 if (vdisplay < 400)
321 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
322 else if (vdisplay < 480)
323 regp->MiscOutReg = 0x63; /* -hsync +vsync */
324 else if (vdisplay < 768)
325 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
326 else
327 regp->MiscOutReg = 0x23; /* +hsync +vsync */
328 }
329
6ee73861
BS		 330 /*
331 * Time Sequencer
332 */
333 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
334 /* 0x20 disables the sequencer */
335 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
336 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
337 else
338 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
339 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
340 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
341 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
342
343 /*
344 * CRTC
345 */
346 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
347 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
348 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
349 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
350 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
351 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
352 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
353 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
354 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
355 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
356 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
357 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
358 (1 << 4) |
359 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
360 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
361 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
362 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
363 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
364 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
365 1 << 6 |
366 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
367 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
368 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
369 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
370 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
371 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
372 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
373 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
374 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
375 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
376 /* framebuffer can be larger than crtc scanout area. */
01f2c773 377 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8;
6ee73861
BS		 378 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
379 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
380 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
381 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
382 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
383
384 /*
385 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
386 */
387
388 /* framebuffer can be larger than crtc scanout area. */
c1003d9c 389 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
01f2c773 390 XLATE(fb->pitches[0] / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c 391 regp->CRTC[NV_CIO_CRE_42] =
01f2c773 392 XLATE(fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 393 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
394 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
395 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
396 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
397 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
398 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
399 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
400 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
401 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
402 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
403 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
404 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
405 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
406 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
407 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
408
409 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
410 horizTotal = (horizTotal >> 1) & ~1;
411 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
412 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
413 } else
414 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
415
416 /*
417 * Graphics Display Controller
418 */
419 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
420 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
421 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
422 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
423 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
424 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
425 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
426 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
427 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
428
429 regp->Attribute[0] = 0x00; /* standard colormap translation */
430 regp->Attribute[1] = 0x01;
431 regp->Attribute[2] = 0x02;
432 regp->Attribute[3] = 0x03;
433 regp->Attribute[4] = 0x04;
434 regp->Attribute[5] = 0x05;
435 regp->Attribute[6] = 0x06;
436 regp->Attribute[7] = 0x07;
437 regp->Attribute[8] = 0x08;
438 regp->Attribute[9] = 0x09;
439 regp->Attribute[10] = 0x0A;
440 regp->Attribute[11] = 0x0B;
441 regp->Attribute[12] = 0x0C;
442 regp->Attribute[13] = 0x0D;
443 regp->Attribute[14] = 0x0E;
444 regp->Attribute[15] = 0x0F;
445 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
446 /* Non-vga */
447 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
448 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
449 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
450 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
451}
452
453/**
454 * Sets up registers for the given mode/adjusted_mode pair.
455 *
456 * The clocks, CRTCs and outputs attached to this CRTC must be off.
457 *
458 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
459 * be easily turned on/off after this.
460 */
461static void
462nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
463{
464 struct drm_device *dev = crtc->dev;
77145f1c 465 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 466 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 467 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
468 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
6ee73861
BS		 469 struct drm_encoder *encoder;
470 bool lvds_output = false, tmds_output = false, tv_output = false,
471 off_chip_digital = false;
472
473 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
474 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
475 bool digital = false;
476
477 if (encoder->crtc != crtc)
478 continue;
479
cb75d97e 480 if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS)
6ee73861 481 digital = lvds_output = true;
cb75d97e 482 if (nv_encoder->dcb->type == DCB_OUTPUT_TV)
6ee73861 483 tv_output = true;
cb75d97e 484 if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS)
6ee73861
BS		 485 digital = tmds_output = true;
486 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
487 off_chip_digital = true;
488 }
489
490 /* Registers not directly related to the (s)vga mode */
491
492 /* What is the meaning of this register? */
493 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
494 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
495
496 regp->crtc_eng_ctrl = 0;
497 /* Except for rare conditions I2C is enabled on the primary crtc */
498 if (nv_crtc->index == 0)
499 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
500#if 0
501 /* Set overlay to desired crtc. */
502 if (dev->overlayAdaptor) {
503 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
504 if (pPriv->overlayCRTC == nv_crtc->index)
505 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
506 }
507#endif
508
509 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
510 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
511 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
512 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
967e7bde 513 if (drm->device.info.chipset >= 0x11)
6ee73861
BS		 514 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
516 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
517
518 /* Unblock some timings */
519 regp->CRTC[NV_CIO_CRE_53] = 0;
520 regp->CRTC[NV_CIO_CRE_54] = 0;
521
522 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
523 if (lvds_output)
524 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
525 else if (tmds_output)
526 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
527 else
528 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
529
530 /* These values seem to vary */
531 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
532 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
533
534 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
535
536 /* probably a scratch reg, but kept for cargo-cult purposes:
537 * bit0: crtc0?, head A
538 * bit6: lvds, head A
539 * bit7: (only in X), head A
540 */
541 if (nv_crtc->index == 0)
542 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
543
544 /* The blob seems to take the current value from crtc 0, add 4 to that
545 * and reuse the old value for crtc 1 */
017e6e29 546 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
6ee73861
BS		 547 if (!nv_crtc->index)
548 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
549
550 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
551 * 1 << 30 on 0x60.830), for no apparent reason */
552 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
553
967e7bde 554 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
4a9f822f
FJ		 555 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
556
6ee73861
BS		 557 regp->crtc_830 = mode->crtc_vdisplay - 3;
558 regp->crtc_834 = mode->crtc_vdisplay - 1;
559
967e7bde 560 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
6ee73861
BS		 561 /* This is what the blob does */
562 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
563
967e7bde 564 if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE)
6ee73861
BS		 565 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
566
967e7bde 567 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
63f7fcfe
FJ		 568 regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
569 else
570 regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
6ee73861
BS		 571
572 /* Some misc regs */
967e7bde 573 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
6ee73861
BS		 574 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
575 regp->CRTC[NV_CIO_CRE_86] = 0x1;
576 }
577
f4510a27 578 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->primary->fb->depth + 1) / 8;
6ee73861
BS		 579 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
580 if (lvds_output || tmds_output || tv_output)
581 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
582
583 /* Generic PRAMDAC regs */
584
967e7bde 585 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
6ee73861
BS		 586 /* Only bit that bios and blob set. */
587 regp->nv10_cursync = (1 << 25);
588
589 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
590 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
591 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
f4510a27 592 if (crtc->primary->fb->depth == 16)
6ee73861 593 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
967e7bde 594 if (drm->device.info.chipset >= 0x11)
6ee73861
BS		 595 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
596
597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
598 regp->tv_setup = 0;
599
600 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
601
602 /* Some values the blob sets */
603 regp->ramdac_8c0 = 0x100;
604 regp->ramdac_a20 = 0x0;
605 regp->ramdac_a24 = 0xfffff;
606 regp->ramdac_a34 = 0x1;
607}
608
78ae0ad4
BS		 609static int
610nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
611{
612 struct nv04_display *disp = nv04_display(crtc->dev);
f4510a27 613 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
78ae0ad4
BS		 614 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
615 int ret;
616
ad76b3f7 617 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM, false);
78ae0ad4
BS		 618 if (ret == 0) {
619 if (disp->image[nv_crtc->index])
620 nouveau_bo_unpin(disp->image[nv_crtc->index]);
621 nouveau_bo_ref(nvfb->nvbo, &disp->image[nv_crtc->index]);
622 }
623
624 return ret;
625}
626
6ee73861
BS		 627/**
628 * Sets up registers for the given mode/adjusted_mode pair.
629 *
630 * The clocks, CRTCs and outputs attached to this CRTC must be off.
631 *
632 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
633 * be easily turned on/off after this.
634 */
635static int
636nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
637 struct drm_display_mode *adjusted_mode,
638 int x, int y, struct drm_framebuffer *old_fb)
639{
640 struct drm_device *dev = crtc->dev;
641 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
77145f1c 642 struct nouveau_drm *drm = nouveau_drm(dev);
78ae0ad4 643 int ret;
6ee73861 644
77145f1c 645 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
6ee73861
BS		 646 drm_mode_debug_printmodeline(adjusted_mode);
647
78ae0ad4
BS		 648 ret = nv_crtc_swap_fbs(crtc, old_fb);
649 if (ret)
650 return ret;
651
6ee73861
BS		 652 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
653 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
654
655 nv_crtc_mode_set_vga(crtc, adjusted_mode);
656 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
967e7bde 657 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE)
017e6e29 658 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk);
6ee73861
BS		 659 nv_crtc_mode_set_regs(crtc, adjusted_mode);
660 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
661 return 0;
662}
663
664static void nv_crtc_save(struct drm_crtc *crtc)
665{
666 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29
BS		 667 struct drm_device *dev = crtc->dev;
668 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg;
6ee73861 669 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
017e6e29 670 struct nv04_mode_state *saved = &nv04_display(dev)->saved_reg;
6ee73861
BS		 671 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
672
673 if (nv_two_heads(crtc->dev))
674 NVSetOwner(crtc->dev, nv_crtc->index);
675
676 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
677
678 /* init some state to saved value */
679 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
680 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
681 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
682 crtc_state->gpio_ext = crtc_saved->gpio_ext;
683}
684
685static void nv_crtc_restore(struct drm_crtc *crtc)
686{
687 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
017e6e29 688 struct drm_device *dev = crtc->dev;
6ee73861 689 int head = nv_crtc->index;
017e6e29 690 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
6ee73861
BS		 691
692 if (nv_two_heads(crtc->dev))
693 NVSetOwner(crtc->dev, head);
694
017e6e29 695 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg);
6ee73861
BS		 696 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
697
698 nv_crtc->last_dpms = NV_DPMS_CLEARED;
699}
700
701static void nv_crtc_prepare(struct drm_crtc *crtc)
702{
703 struct drm_device *dev = crtc->dev;
77145f1c 704 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861
BS		 705 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
706 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
707
708 if (nv_two_heads(dev))
709 NVSetOwner(dev, nv_crtc->index);
710
1c180fa5 711 drm_vblank_pre_modeset(dev, nv_crtc->index);
6ee73861
BS		 712 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
713
714 NVBlankScreen(dev, nv_crtc->index, true);
715
25985edc 716 /* Some more preparation. */
6ee73861 717 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
967e7bde 718 if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
6ee73861
BS		 719 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
720 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
721 }
722}
723
724static void nv_crtc_commit(struct drm_crtc *crtc)
725{
726 struct drm_device *dev = crtc->dev;
727 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
6ee73861
BS		 728 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
729
017e6e29 730 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
6ee73861
BS		 731 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
732
733#ifdef __BIG_ENDIAN
734 /* turn on LFB swapping */
735 {
736 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
737 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
738 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
739 }
740#endif
741
742 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1c180fa5 743 drm_vblank_post_modeset(dev, nv_crtc->index);
6ee73861
BS		 744}
745
746static void nv_crtc_destroy(struct drm_crtc *crtc)
747{
78ae0ad4 748 struct nv04_display *disp = nv04_display(crtc->dev);
6ee73861
BS		 749 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
750
6ee73861
BS		 751 if (!nv_crtc)
752 return;
753
754 drm_crtc_cleanup(crtc);
755
78ae0ad4
BS		 756 if (disp->image[nv_crtc->index])
757 nouveau_bo_unpin(disp->image[nv_crtc->index]);
758 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
759
9d59e8a1 760 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210 761 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
6ee73861
BS		 762 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
763 kfree(nv_crtc);
764}
765
766static void
767nv_crtc_gamma_load(struct drm_crtc *crtc)
768{
769 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
770 struct drm_device *dev = nv_crtc->base.dev;
6ee73861
BS		 771 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
772 int i;
773
017e6e29 774 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
6ee73861
BS		 775 for (i = 0; i < 256; i++) {
776 rgbs[i].r = nv_crtc->lut.r[i] >> 8;
777 rgbs[i].g = nv_crtc->lut.g[i] >> 8;
778 rgbs[i].b = nv_crtc->lut.b[i] >> 8;
779 }
780
017e6e29 781 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
6ee73861
BS		 782}
783
78ae0ad4
BS		 784static void
785nv_crtc_disable(struct drm_crtc *crtc)
786{
787 struct nv04_display *disp = nv04_display(crtc->dev);
788 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
789 if (disp->image[nv_crtc->index])
790 nouveau_bo_unpin(disp->image[nv_crtc->index]);
791 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
792}
793
6ee73861 794static void
7203425a
JS		 795nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t start,
796 uint32_t size)
6ee73861 797{
7203425a 798 int end = (start + size > 256) ? 256 : start + size, i;
6ee73861 799 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
6ee73861 800
7203425a 801 for (i = start; i < end; i++) {
6ee73861
BS		 802 nv_crtc->lut.r[i] = r[i];
803 nv_crtc->lut.g[i] = g[i];
804 nv_crtc->lut.b[i] = b[i];
805 }
806
807 /* We need to know the depth before we upload, but it's possible to
808 * get called before a framebuffer is bound. If this is the case,
809 * mark the lut values as dirty by setting depth==0, and it'll be
810 * uploaded on the first mode_set_base()
811 */
f4510a27 812 if (!nv_crtc->base.primary->fb) {
6ee73861
BS		 813 nv_crtc->lut.depth = 0;
814 return;
815 }
816
817 nv_crtc_gamma_load(crtc);
818}
819
820static int
be64c2bb
CB		 821nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
822 struct drm_framebuffer *passed_fb,
823 int x, int y, bool atomic)
6ee73861
BS		 824{
825 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
826 struct drm_device *dev = crtc->dev;
77145f1c 827 struct nouveau_drm *drm = nouveau_drm(dev);
017e6e29 828 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
0e83bb4e
EV		 829 struct drm_framebuffer *drm_fb;
830 struct nouveau_framebuffer *fb;
6ee73861 831 int arb_burst, arb_lwm;
6ee73861 832
77145f1c 833 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
0e83bb4e
EV		 834
835 /* no fb bound */
f4510a27 836 if (!atomic && !crtc->primary->fb) {
77145f1c 837 NV_DEBUG(drm, "No FB bound\n");
0e83bb4e
EV		 838 return 0;
839 }
840
be64c2bb 841 /* If atomic, we want to switch to the fb we were passed, so
78ae0ad4 842 * now we update pointers to do that.
be64c2bb
CB		 843 */
844 if (atomic) {
845 drm_fb = passed_fb;
846 fb = nouveau_framebuffer(passed_fb);
f9ec8f6c 847 } else {
f4510a27
MR		 848 drm_fb = crtc->primary->fb;
849 fb = nouveau_framebuffer(crtc->primary->fb);
6ee73861
BS		 850 }
851
852 nv_crtc->fb.offset = fb->nvbo->bo.offset;
853
854 if (nv_crtc->lut.depth != drm_fb->depth) {
855 nv_crtc->lut.depth = drm_fb->depth;
856 nv_crtc_gamma_load(crtc);
857 }
858
859 /* Update the framebuffer format. */
860 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
f4510a27 861 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->primary->fb->depth + 1) / 8;
6ee73861 862 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
f4510a27 863 if (crtc->primary->fb->depth == 16)
6ee73861
BS		 864 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
865 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
866 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
867 regp->ramdac_gen_ctrl);
868
01f2c773 869 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3;
6ee73861 870 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
01f2c773 871 XLATE(drm_fb->pitches[0] >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
c1003d9c 872 regp->CRTC[NV_CIO_CRE_42] =
01f2c773 873 XLATE(drm_fb->pitches[0] / 8, 11, NV_CIO_CRE_42_OFFSET_11);
6ee73861
BS		 874 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
875 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
c1003d9c 876 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
6ee73861
BS		 877
878 /* Update the framebuffer location. */
879 regp->fb_start = nv_crtc->fb.offset & ~3;
01f2c773 880 regp->fb_start += (y * drm_fb->pitches[0]) + (x * drm_fb->bits_per_pixel / 8);
5794b5fd 881 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
6ee73861
BS		 882
883 /* Update the arbitration parameters. */
884 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
885 &arb_burst, &arb_lwm);
886
887 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
888 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
889 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
891
967e7bde 892 if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) {
6ee73861
BS		 893 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
894 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
895 }
896
897 return 0;
898}
899
be64c2bb
CB		 900static int
901nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
902 struct drm_framebuffer *old_fb)
903{
78ae0ad4
BS		 904 int ret = nv_crtc_swap_fbs(crtc, old_fb);
905 if (ret)
906 return ret;
be64c2bb
CB		 907 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
908}
909
910static int
911nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
912 struct drm_framebuffer *fb,
21c74a8e 913 int x, int y, enum mode_set_atomic state)
be64c2bb 914{
77145f1c
BS		 915 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
916 struct drm_device *dev = drm->dev;
a424d761 917
21c74a8e 918 if (state == ENTER_ATOMIC_MODE_SET)
4b5098f3 919 nouveau_fbcon_accel_save_disable(dev);
a424d761 920 else
4b5098f3 921 nouveau_fbcon_accel_restore(dev);
a424d761 922
be64c2bb
CB		 923 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true);
924}
925
6ee73861
BS		 926static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
927 struct nouveau_bo *dst)
928{
929 int width = nv_cursor_width(dev);
930 uint32_t pixel;
931 int i, j;
932
933 for (i = 0; i < width; i++) {
934 for (j = 0; j < width; j++) {
935 pixel = nouveau_bo_rd32(src, i*64 + j);
936
937 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
938 | (pixel & 0xf80000) >> 9
939 | (pixel & 0xf800) >> 6
940 | (pixel & 0xf8) >> 3);
941 }
942 }
943}
944
945static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
946 struct nouveau_bo *dst)
947{
948 uint32_t pixel;
949 int alpha, i;
950
951 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
952 * cursors (though NPM in combination with fp dithering may not work on
953 * nv11, from "nv" driver history)
954 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
955 * blob uses, however we get given PM cursors so we use PM mode
956 */
957 for (i = 0; i < 64 * 64; i++) {
958 pixel = nouveau_bo_rd32(src, i);
959
960 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
961 * than" shouldn't happen; fix "equal to" case by adding one to
962 * alpha channel (slightly inaccurate, but so is attempting to
963 * get back to NPM images, due to limits of integer precision)
964 */
965 alpha = pixel >> 24;
966 if (alpha > 0 && alpha < 255)
967 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
968
969#ifdef __BIG_ENDIAN
970 {
77145f1c 971 struct nouveau_drm *drm = nouveau_drm(dev);
6ee73861 972
967e7bde 973 if (drm->device.info.chipset == 0x11) {
6ee73861
BS		 974 pixel = ((pixel & 0x000000ff) << 24) |
975 ((pixel & 0x0000ff00) << 8) |
976 ((pixel & 0x00ff0000) >> 8) |
977 ((pixel & 0xff000000) >> 24);
978 }
979 }
980#endif
981
982 nouveau_bo_wr32(dst, i, pixel);
983 }
984}
985
986static int
987nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
988 uint32_t buffer_handle, uint32_t width, uint32_t height)
989{
77145f1c
BS		 990 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
991 struct drm_device *dev = drm->dev;
6ee73861
BS		 992 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
993 struct nouveau_bo *cursor = NULL;
994 struct drm_gem_object *gem;
995 int ret = 0;
996
6ee73861
BS		 997 if (!buffer_handle) {
998 nv_crtc->cursor.hide(nv_crtc, true);
999 return 0;
1000 }
1001
b4fa9d0f
MS		 1002 if (width != 64 || height != 64)
1003 return -EINVAL;
1004
6ee73861
BS		 1005 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
1006 if (!gem)
bf79cb91 1007 return -ENOENT;
6ee73861
BS		 1008 cursor = nouveau_gem_object(gem);
1009
1010 ret = nouveau_bo_map(cursor);
1011 if (ret)
1012 goto out;
1013
967e7bde 1014 if (drm->device.info.chipset >= 0x11)
6ee73861
BS		 1015 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1016 else
1017 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
1018
1019 nouveau_bo_unmap(cursor);
1020 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
1021 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
1022 nv_crtc->cursor.show(nv_crtc, true);
1023out:
bc9025bd 1024 drm_gem_object_unreference_unlocked(gem);
6ee73861
BS		 1025 return ret;
1026}
1027
1028static int
1029nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1030{
1031 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1032
1033 nv_crtc->cursor.set_pos(nv_crtc, x, y);
1034 return 0;
1035}
1036
5addcf0a
DA		 1037int
1038nouveau_crtc_set_config(struct drm_mode_set *set)
1039{
1040 struct drm_device *dev;
1041 struct nouveau_drm *drm;
1042 int ret;
1043 struct drm_crtc *crtc;
1044 bool active = false;
1045 if (!set || !set->crtc)
1046 return -EINVAL;
1047
1048 dev = set->crtc->dev;
1049
1050 /* get a pm reference here */
1051 ret = pm_runtime_get_sync(dev->dev);
b6c4285a 1052 if (ret < 0 && ret != -EACCES)
5addcf0a
DA		 1053 return ret;
1054
1055 ret = drm_crtc_helper_set_config(set);
1056
1057 drm = nouveau_drm(dev);
1058
1059 /* if we get here with no crtcs active then we can drop a reference */
1060 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1061 if (crtc->enabled)
1062 active = true;
1063 }
1064
1065 pm_runtime_mark_last_busy(dev->dev);
1066 /* if we have active crtcs and we don't have a power ref,
1067 take the current one */
1068 if (active && !drm->have_disp_power_ref) {
1069 drm->have_disp_power_ref = true;
1070 return ret;
1071 }
1072 /* if we have no active crtcs, then drop the power ref
1073 we got before */
1074 if (!active && drm->have_disp_power_ref) {
1075 pm_runtime_put_autosuspend(dev->dev);
1076 drm->have_disp_power_ref = false;
1077 }
1078 /* drop the power reference we got coming in here */
1079 pm_runtime_put_autosuspend(dev->dev);
1080 return ret;
1081}
1082
6ee73861
BS		 1083static const struct drm_crtc_funcs nv04_crtc_funcs = {
1084 .save = nv_crtc_save,
1085 .restore = nv_crtc_restore,
1086 .cursor_set = nv04_crtc_cursor_set,
1087 .cursor_move = nv04_crtc_cursor_move,
1088 .gamma_set = nv_crtc_gamma_set,
5addcf0a 1089 .set_config = nouveau_crtc_set_config,
332b242f 1090 .page_flip = nouveau_crtc_page_flip,
6ee73861
BS		 1091 .destroy = nv_crtc_destroy,
1092};
1093
1094static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
1095 .dpms = nv_crtc_dpms,
1096 .prepare = nv_crtc_prepare,
1097 .commit = nv_crtc_commit,
1098 .mode_fixup = nv_crtc_mode_fixup,
1099 .mode_set = nv_crtc_mode_set,
1100 .mode_set_base = nv04_crtc_mode_set_base,
be64c2bb 1101 .mode_set_base_atomic = nv04_crtc_mode_set_base_atomic,
6ee73861 1102 .load_lut = nv_crtc_gamma_load,
78ae0ad4 1103 .disable = nv_crtc_disable,
6ee73861
BS		 1104};
1105
1106int
1107nv04_crtc_create(struct drm_device *dev, int crtc_num)
1108{
1109 struct nouveau_crtc *nv_crtc;
1110 int ret, i;
1111
1112 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
1113 if (!nv_crtc)
1114 return -ENOMEM;
1115
1116 for (i = 0; i < 256; i++) {
1117 nv_crtc->lut.r[i] = i << 8;
1118 nv_crtc->lut.g[i] = i << 8;
1119 nv_crtc->lut.b[i] = i << 8;
1120 }
1121 nv_crtc->lut.depth = 0;
1122
1123 nv_crtc->index = crtc_num;
1124 nv_crtc->last_dpms = NV_DPMS_CLEARED;
1125
1126 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs);
1127 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
1128 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
1129
7375c95b 1130 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
bb6178b0 1131 0, 0x0000, NULL, NULL, &nv_crtc->cursor.nvbo);
6ee73861 1132 if (!ret) {
ad76b3f7 1133 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM, false);
04c8c210 1134 if (!ret) {
6ee73861 1135 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
04c8c210
MS		 1136 if (ret)
1137 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1138 }
6ee73861
BS		 1139 if (ret)
1140 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1141 }
1142
1143 nv04_cursor_init(nv_crtc);
1144
1145 return 0;
1146}
Linux kernel - Deliverables
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