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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef __NOUVEAU_DRV_H__ | |
26 | #define __NOUVEAU_DRV_H__ | |
27 | ||
28 | #define DRIVER_AUTHOR "Stephane Marchesin" | |
29 | #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" | |
30 | ||
31 | #define DRIVER_NAME "nouveau" | |
32 | #define DRIVER_DESC "nVidia Riva/TNT/GeForce" | |
33 | #define DRIVER_DATE "20090420" | |
34 | ||
35 | #define DRIVER_MAJOR 0 | |
36 | #define DRIVER_MINOR 0 | |
a1606a95 | 37 | #define DRIVER_PATCHLEVEL 16 |
6ee73861 BS |
38 | |
39 | #define NOUVEAU_FAMILY 0x0000FFFF | |
40 | #define NOUVEAU_FLAGS 0xFFFF0000 | |
41 | ||
42 | #include "ttm/ttm_bo_api.h" | |
43 | #include "ttm/ttm_bo_driver.h" | |
44 | #include "ttm/ttm_placement.h" | |
45 | #include "ttm/ttm_memory.h" | |
46 | #include "ttm/ttm_module.h" | |
47 | ||
48 | struct nouveau_fpriv { | |
49 | struct ttm_object_file *tfile; | |
50 | }; | |
51 | ||
52 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
53 | ||
54 | #include "nouveau_drm.h" | |
55 | #include "nouveau_reg.h" | |
56 | #include "nouveau_bios.h" | |
054b93e4 | 57 | struct nouveau_grctx; |
6ee73861 BS |
58 | |
59 | #define MAX_NUM_DCB_ENTRIES 16 | |
60 | ||
61 | #define NOUVEAU_MAX_CHANNEL_NR 128 | |
a0af9add | 62 | #define NOUVEAU_MAX_TILE_NR 15 |
6ee73861 BS |
63 | |
64 | #define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL) | |
65 | #define NV50_VM_BLOCK (512*1024*1024ULL) | |
66 | #define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK) | |
67 | ||
a0af9add FJ |
68 | struct nouveau_tile_reg { |
69 | struct nouveau_fence *fence; | |
70 | uint32_t addr; | |
71 | uint32_t size; | |
72 | bool used; | |
73 | }; | |
74 | ||
6ee73861 BS |
75 | struct nouveau_bo { |
76 | struct ttm_buffer_object bo; | |
77 | struct ttm_placement placement; | |
78 | u32 placements[3]; | |
78ad0f7b | 79 | u32 busy_placements[3]; |
6ee73861 BS |
80 | struct ttm_bo_kmap_obj kmap; |
81 | struct list_head head; | |
82 | ||
83 | /* protected by ttm_bo_reserve() */ | |
84 | struct drm_file *reserved_by; | |
85 | struct list_head entry; | |
86 | int pbbo_index; | |
a1606a95 | 87 | bool validate_mapped; |
6ee73861 BS |
88 | |
89 | struct nouveau_channel *channel; | |
90 | ||
91 | bool mappable; | |
92 | bool no_vm; | |
93 | ||
94 | uint32_t tile_mode; | |
95 | uint32_t tile_flags; | |
a0af9add | 96 | struct nouveau_tile_reg *tile; |
6ee73861 BS |
97 | |
98 | struct drm_gem_object *gem; | |
99 | struct drm_file *cpu_filp; | |
100 | int pin_refcnt; | |
101 | }; | |
102 | ||
103 | static inline struct nouveau_bo * | |
104 | nouveau_bo(struct ttm_buffer_object *bo) | |
105 | { | |
106 | return container_of(bo, struct nouveau_bo, bo); | |
107 | } | |
108 | ||
109 | static inline struct nouveau_bo * | |
110 | nouveau_gem_object(struct drm_gem_object *gem) | |
111 | { | |
112 | return gem ? gem->driver_private : NULL; | |
113 | } | |
114 | ||
115 | /* TODO: submit equivalent to TTM generic API upstream? */ | |
116 | static inline void __iomem * | |
117 | nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) | |
118 | { | |
119 | bool is_iomem; | |
120 | void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( | |
121 | &nvbo->kmap, &is_iomem); | |
122 | WARN_ON_ONCE(ioptr && !is_iomem); | |
123 | return ioptr; | |
124 | } | |
125 | ||
6ee73861 BS |
126 | enum nouveau_flags { |
127 | NV_NFORCE = 0x10000000, | |
128 | NV_NFORCE2 = 0x20000000 | |
129 | }; | |
130 | ||
131 | #define NVOBJ_ENGINE_SW 0 | |
132 | #define NVOBJ_ENGINE_GR 1 | |
133 | #define NVOBJ_ENGINE_DISPLAY 2 | |
134 | #define NVOBJ_ENGINE_INT 0xdeadbeef | |
135 | ||
136 | #define NVOBJ_FLAG_ALLOW_NO_REFS (1 << 0) | |
137 | #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) | |
138 | #define NVOBJ_FLAG_ZERO_FREE (1 << 2) | |
139 | #define NVOBJ_FLAG_FAKE (1 << 3) | |
140 | struct nouveau_gpuobj { | |
141 | struct list_head list; | |
142 | ||
143 | struct nouveau_channel *im_channel; | |
b833ac26 | 144 | struct drm_mm_node *im_pramin; |
6ee73861 BS |
145 | struct nouveau_bo *im_backing; |
146 | uint32_t im_backing_start; | |
147 | uint32_t *im_backing_suspend; | |
148 | int im_bound; | |
149 | ||
150 | uint32_t flags; | |
151 | int refcount; | |
152 | ||
153 | uint32_t engine; | |
154 | uint32_t class; | |
155 | ||
156 | void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); | |
157 | void *priv; | |
158 | }; | |
159 | ||
160 | struct nouveau_gpuobj_ref { | |
161 | struct list_head list; | |
162 | ||
163 | struct nouveau_gpuobj *gpuobj; | |
164 | uint32_t instance; | |
165 | ||
166 | struct nouveau_channel *channel; | |
167 | int handle; | |
168 | }; | |
169 | ||
170 | struct nouveau_channel { | |
171 | struct drm_device *dev; | |
172 | int id; | |
173 | ||
174 | /* owner of this fifo */ | |
175 | struct drm_file *file_priv; | |
176 | /* mapping of the fifo itself */ | |
177 | struct drm_local_map *map; | |
178 | ||
179 | /* mapping of the regs controling the fifo */ | |
180 | void __iomem *user; | |
181 | uint32_t user_get; | |
182 | uint32_t user_put; | |
183 | ||
184 | /* Fencing */ | |
185 | struct { | |
186 | /* lock protects the pending list only */ | |
187 | spinlock_t lock; | |
188 | struct list_head pending; | |
189 | uint32_t sequence; | |
190 | uint32_t sequence_ack; | |
047d1d3c | 191 | atomic_t last_sequence_irq; |
6ee73861 BS |
192 | } fence; |
193 | ||
194 | /* DMA push buffer */ | |
195 | struct nouveau_gpuobj_ref *pushbuf; | |
196 | struct nouveau_bo *pushbuf_bo; | |
197 | uint32_t pushbuf_base; | |
198 | ||
199 | /* Notifier memory */ | |
200 | struct nouveau_bo *notifier_bo; | |
b833ac26 | 201 | struct drm_mm notifier_heap; |
6ee73861 BS |
202 | |
203 | /* PFIFO context */ | |
204 | struct nouveau_gpuobj_ref *ramfc; | |
205 | struct nouveau_gpuobj_ref *cache; | |
206 | ||
207 | /* PGRAPH context */ | |
208 | /* XXX may be merge 2 pointers as private data ??? */ | |
209 | struct nouveau_gpuobj_ref *ramin_grctx; | |
210 | void *pgraph_ctx; | |
211 | ||
212 | /* NV50 VM */ | |
213 | struct nouveau_gpuobj *vm_pd; | |
214 | struct nouveau_gpuobj_ref *vm_gart_pt; | |
215 | struct nouveau_gpuobj_ref *vm_vram_pt[NV50_VM_VRAM_NR]; | |
216 | ||
217 | /* Objects */ | |
218 | struct nouveau_gpuobj_ref *ramin; /* Private instmem */ | |
b833ac26 | 219 | struct drm_mm ramin_heap; /* Private PRAMIN heap */ |
6ee73861 BS |
220 | struct nouveau_gpuobj_ref *ramht; /* Hash table */ |
221 | struct list_head ramht_refs; /* Objects referenced by RAMHT */ | |
222 | ||
223 | /* GPU object info for stuff used in-kernel (mm_enabled) */ | |
224 | uint32_t m2mf_ntfy; | |
225 | uint32_t vram_handle; | |
226 | uint32_t gart_handle; | |
227 | bool accel_done; | |
228 | ||
229 | /* Push buffer state (only for drm's channel on !mm_enabled) */ | |
230 | struct { | |
231 | int max; | |
232 | int free; | |
233 | int cur; | |
234 | int put; | |
235 | /* access via pushbuf_bo */ | |
9a391ad8 BS |
236 | |
237 | int ib_base; | |
238 | int ib_max; | |
239 | int ib_free; | |
240 | int ib_put; | |
6ee73861 BS |
241 | } dma; |
242 | ||
243 | uint32_t sw_subchannel[8]; | |
244 | ||
245 | struct { | |
246 | struct nouveau_gpuobj *vblsem; | |
247 | uint32_t vblsem_offset; | |
248 | uint32_t vblsem_rval; | |
249 | struct list_head vbl_wait; | |
250 | } nvsw; | |
251 | ||
252 | struct { | |
253 | bool active; | |
254 | char name[32]; | |
255 | struct drm_info_list info; | |
256 | } debugfs; | |
257 | }; | |
258 | ||
259 | struct nouveau_instmem_engine { | |
260 | void *priv; | |
261 | ||
262 | int (*init)(struct drm_device *dev); | |
263 | void (*takedown)(struct drm_device *dev); | |
264 | int (*suspend)(struct drm_device *dev); | |
265 | void (*resume)(struct drm_device *dev); | |
266 | ||
267 | int (*populate)(struct drm_device *, struct nouveau_gpuobj *, | |
268 | uint32_t *size); | |
269 | void (*clear)(struct drm_device *, struct nouveau_gpuobj *); | |
270 | int (*bind)(struct drm_device *, struct nouveau_gpuobj *); | |
271 | int (*unbind)(struct drm_device *, struct nouveau_gpuobj *); | |
f56cb86f | 272 | void (*flush)(struct drm_device *); |
6ee73861 BS |
273 | }; |
274 | ||
275 | struct nouveau_mc_engine { | |
276 | int (*init)(struct drm_device *dev); | |
277 | void (*takedown)(struct drm_device *dev); | |
278 | }; | |
279 | ||
280 | struct nouveau_timer_engine { | |
281 | int (*init)(struct drm_device *dev); | |
282 | void (*takedown)(struct drm_device *dev); | |
283 | uint64_t (*read)(struct drm_device *dev); | |
284 | }; | |
285 | ||
286 | struct nouveau_fb_engine { | |
cb00f7c1 FJ |
287 | int num_tiles; |
288 | ||
6ee73861 BS |
289 | int (*init)(struct drm_device *dev); |
290 | void (*takedown)(struct drm_device *dev); | |
cb00f7c1 FJ |
291 | |
292 | void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, | |
293 | uint32_t size, uint32_t pitch); | |
6ee73861 BS |
294 | }; |
295 | ||
296 | struct nouveau_fifo_engine { | |
6ee73861 BS |
297 | int channels; |
298 | ||
ac94a343 BS |
299 | struct nouveau_gpuobj_ref *playlist[2]; |
300 | int cur_playlist; | |
301 | ||
6ee73861 BS |
302 | int (*init)(struct drm_device *); |
303 | void (*takedown)(struct drm_device *); | |
304 | ||
305 | void (*disable)(struct drm_device *); | |
306 | void (*enable)(struct drm_device *); | |
307 | bool (*reassign)(struct drm_device *, bool enable); | |
588d7d12 FJ |
308 | bool (*cache_flush)(struct drm_device *dev); |
309 | bool (*cache_pull)(struct drm_device *dev, bool enable); | |
6ee73861 BS |
310 | |
311 | int (*channel_id)(struct drm_device *); | |
312 | ||
313 | int (*create_context)(struct nouveau_channel *); | |
314 | void (*destroy_context)(struct nouveau_channel *); | |
315 | int (*load_context)(struct nouveau_channel *); | |
316 | int (*unload_context)(struct drm_device *); | |
317 | }; | |
318 | ||
319 | struct nouveau_pgraph_object_method { | |
320 | int id; | |
321 | int (*exec)(struct nouveau_channel *chan, int grclass, int mthd, | |
322 | uint32_t data); | |
323 | }; | |
324 | ||
325 | struct nouveau_pgraph_object_class { | |
326 | int id; | |
327 | bool software; | |
328 | struct nouveau_pgraph_object_method *methods; | |
329 | }; | |
330 | ||
331 | struct nouveau_pgraph_engine { | |
332 | struct nouveau_pgraph_object_class *grclass; | |
333 | bool accel_blocked; | |
054b93e4 | 334 | int grctx_size; |
6ee73861 | 335 | |
c50a5681 BS |
336 | /* NV2x/NV3x context table (0x400780) */ |
337 | struct nouveau_gpuobj_ref *ctx_table; | |
338 | ||
6ee73861 BS |
339 | int (*init)(struct drm_device *); |
340 | void (*takedown)(struct drm_device *); | |
341 | ||
342 | void (*fifo_access)(struct drm_device *, bool); | |
343 | ||
344 | struct nouveau_channel *(*channel)(struct drm_device *); | |
345 | int (*create_context)(struct nouveau_channel *); | |
346 | void (*destroy_context)(struct nouveau_channel *); | |
347 | int (*load_context)(struct nouveau_channel *); | |
348 | int (*unload_context)(struct drm_device *); | |
cb00f7c1 FJ |
349 | |
350 | void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr, | |
351 | uint32_t size, uint32_t pitch); | |
6ee73861 BS |
352 | }; |
353 | ||
c88c2e06 FJ |
354 | struct nouveau_display_engine { |
355 | int (*early_init)(struct drm_device *); | |
356 | void (*late_takedown)(struct drm_device *); | |
357 | int (*create)(struct drm_device *); | |
358 | int (*init)(struct drm_device *); | |
359 | void (*destroy)(struct drm_device *); | |
360 | }; | |
361 | ||
ee2e0131 BS |
362 | struct nouveau_gpio_engine { |
363 | int (*init)(struct drm_device *); | |
364 | void (*takedown)(struct drm_device *); | |
365 | ||
366 | int (*get)(struct drm_device *, enum dcb_gpio_tag); | |
367 | int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); | |
368 | ||
369 | void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); | |
370 | }; | |
371 | ||
6ee73861 BS |
372 | struct nouveau_engine { |
373 | struct nouveau_instmem_engine instmem; | |
374 | struct nouveau_mc_engine mc; | |
375 | struct nouveau_timer_engine timer; | |
376 | struct nouveau_fb_engine fb; | |
377 | struct nouveau_pgraph_engine graph; | |
378 | struct nouveau_fifo_engine fifo; | |
c88c2e06 | 379 | struct nouveau_display_engine display; |
ee2e0131 | 380 | struct nouveau_gpio_engine gpio; |
6ee73861 BS |
381 | }; |
382 | ||
383 | struct nouveau_pll_vals { | |
384 | union { | |
385 | struct { | |
386 | #ifdef __BIG_ENDIAN | |
387 | uint8_t N1, M1, N2, M2; | |
388 | #else | |
389 | uint8_t M1, N1, M2, N2; | |
390 | #endif | |
391 | }; | |
392 | struct { | |
393 | uint16_t NM1, NM2; | |
394 | } __attribute__((packed)); | |
395 | }; | |
396 | int log2P; | |
397 | ||
398 | int refclk; | |
399 | }; | |
400 | ||
401 | enum nv04_fp_display_regs { | |
402 | FP_DISPLAY_END, | |
403 | FP_TOTAL, | |
404 | FP_CRTC, | |
405 | FP_SYNC_START, | |
406 | FP_SYNC_END, | |
407 | FP_VALID_START, | |
408 | FP_VALID_END | |
409 | }; | |
410 | ||
411 | struct nv04_crtc_reg { | |
412 | unsigned char MiscOutReg; /* */ | |
4a9f822f | 413 | uint8_t CRTC[0xa0]; |
6ee73861 BS |
414 | uint8_t CR58[0x10]; |
415 | uint8_t Sequencer[5]; | |
416 | uint8_t Graphics[9]; | |
417 | uint8_t Attribute[21]; | |
418 | unsigned char DAC[768]; /* Internal Colorlookuptable */ | |
419 | ||
420 | /* PCRTC regs */ | |
421 | uint32_t fb_start; | |
422 | uint32_t crtc_cfg; | |
423 | uint32_t cursor_cfg; | |
424 | uint32_t gpio_ext; | |
425 | uint32_t crtc_830; | |
426 | uint32_t crtc_834; | |
427 | uint32_t crtc_850; | |
428 | uint32_t crtc_eng_ctrl; | |
429 | ||
430 | /* PRAMDAC regs */ | |
431 | uint32_t nv10_cursync; | |
432 | struct nouveau_pll_vals pllvals; | |
433 | uint32_t ramdac_gen_ctrl; | |
434 | uint32_t ramdac_630; | |
435 | uint32_t ramdac_634; | |
436 | uint32_t tv_setup; | |
437 | uint32_t tv_vtotal; | |
438 | uint32_t tv_vskew; | |
439 | uint32_t tv_vsync_delay; | |
440 | uint32_t tv_htotal; | |
441 | uint32_t tv_hskew; | |
442 | uint32_t tv_hsync_delay; | |
443 | uint32_t tv_hsync_delay2; | |
444 | uint32_t fp_horiz_regs[7]; | |
445 | uint32_t fp_vert_regs[7]; | |
446 | uint32_t dither; | |
447 | uint32_t fp_control; | |
448 | uint32_t dither_regs[6]; | |
449 | uint32_t fp_debug_0; | |
450 | uint32_t fp_debug_1; | |
451 | uint32_t fp_debug_2; | |
452 | uint32_t fp_margin_color; | |
453 | uint32_t ramdac_8c0; | |
454 | uint32_t ramdac_a20; | |
455 | uint32_t ramdac_a24; | |
456 | uint32_t ramdac_a34; | |
457 | uint32_t ctv_regs[38]; | |
458 | }; | |
459 | ||
460 | struct nv04_output_reg { | |
461 | uint32_t output; | |
462 | int head; | |
463 | }; | |
464 | ||
465 | struct nv04_mode_state { | |
466 | uint32_t bpp; | |
467 | uint32_t width; | |
468 | uint32_t height; | |
469 | uint32_t interlace; | |
470 | uint32_t repaint0; | |
471 | uint32_t repaint1; | |
472 | uint32_t screen; | |
473 | uint32_t scale; | |
474 | uint32_t dither; | |
475 | uint32_t extra; | |
476 | uint32_t fifo; | |
477 | uint32_t pixel; | |
478 | uint32_t horiz; | |
479 | int arbitration0; | |
480 | int arbitration1; | |
481 | uint32_t pll; | |
482 | uint32_t pllB; | |
483 | uint32_t vpll; | |
484 | uint32_t vpll2; | |
485 | uint32_t vpllB; | |
486 | uint32_t vpll2B; | |
487 | uint32_t pllsel; | |
488 | uint32_t sel_clk; | |
489 | uint32_t general; | |
490 | uint32_t crtcOwner; | |
491 | uint32_t head; | |
492 | uint32_t head2; | |
493 | uint32_t cursorConfig; | |
494 | uint32_t cursor0; | |
495 | uint32_t cursor1; | |
496 | uint32_t cursor2; | |
497 | uint32_t timingH; | |
498 | uint32_t timingV; | |
499 | uint32_t displayV; | |
500 | uint32_t crtcSync; | |
501 | ||
502 | struct nv04_crtc_reg crtc_reg[2]; | |
503 | }; | |
504 | ||
505 | enum nouveau_card_type { | |
506 | NV_04 = 0x00, | |
507 | NV_10 = 0x10, | |
508 | NV_20 = 0x20, | |
509 | NV_30 = 0x30, | |
510 | NV_40 = 0x40, | |
511 | NV_50 = 0x50, | |
512 | }; | |
513 | ||
514 | struct drm_nouveau_private { | |
515 | struct drm_device *dev; | |
6ee73861 BS |
516 | |
517 | /* the card type, takes NV_* as values */ | |
518 | enum nouveau_card_type card_type; | |
519 | /* exact chipset, derived from NV_PMC_BOOT_0 */ | |
520 | int chipset; | |
521 | int flags; | |
522 | ||
523 | void __iomem *mmio; | |
524 | void __iomem *ramin; | |
525 | uint32_t ramin_size; | |
526 | ||
ac8fb975 BS |
527 | struct nouveau_bo *vga_ram; |
528 | ||
6ee73861 BS |
529 | struct workqueue_struct *wq; |
530 | struct work_struct irq_work; | |
a5acac66 | 531 | struct work_struct hpd_work; |
6ee73861 BS |
532 | |
533 | struct list_head vbl_waiting; | |
534 | ||
535 | struct { | |
ba4420c2 | 536 | struct drm_global_reference mem_global_ref; |
6ee73861 BS |
537 | struct ttm_bo_global_ref bo_global_ref; |
538 | struct ttm_bo_device bdev; | |
6ee73861 BS |
539 | atomic_t validate_sequence; |
540 | } ttm; | |
541 | ||
6ee73861 BS |
542 | int fifo_alloc_count; |
543 | struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR]; | |
544 | ||
545 | struct nouveau_engine engine; | |
546 | struct nouveau_channel *channel; | |
547 | ||
ff9e5279 MM |
548 | /* For PFIFO and PGRAPH. */ |
549 | spinlock_t context_switch_lock; | |
550 | ||
6ee73861 BS |
551 | /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ |
552 | struct nouveau_gpuobj *ramht; | |
553 | uint32_t ramin_rsvd_vram; | |
554 | uint32_t ramht_offset; | |
555 | uint32_t ramht_size; | |
556 | uint32_t ramht_bits; | |
557 | uint32_t ramfc_offset; | |
558 | uint32_t ramfc_size; | |
559 | uint32_t ramro_offset; | |
560 | uint32_t ramro_size; | |
561 | ||
6ee73861 BS |
562 | struct { |
563 | enum { | |
564 | NOUVEAU_GART_NONE = 0, | |
565 | NOUVEAU_GART_AGP, | |
566 | NOUVEAU_GART_SGDMA | |
567 | } type; | |
568 | uint64_t aper_base; | |
569 | uint64_t aper_size; | |
570 | uint64_t aper_free; | |
571 | ||
572 | struct nouveau_gpuobj *sg_ctxdma; | |
573 | struct page *sg_dummy_page; | |
574 | dma_addr_t sg_dummy_bus; | |
6ee73861 BS |
575 | } gart_info; |
576 | ||
a0af9add FJ |
577 | /* nv10-nv40 tiling regions */ |
578 | struct { | |
579 | struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; | |
580 | spinlock_t lock; | |
581 | } tile; | |
582 | ||
a76fb4e8 BS |
583 | /* VRAM/fb configuration */ |
584 | uint64_t vram_size; | |
585 | uint64_t vram_sys_base; | |
586 | ||
587 | uint64_t fb_phys; | |
588 | uint64_t fb_available_size; | |
589 | uint64_t fb_mappable_pages; | |
590 | uint64_t fb_aper_free; | |
591 | int fb_mtrr; | |
592 | ||
6ee73861 BS |
593 | /* G8x/G9x virtual address space */ |
594 | uint64_t vm_gart_base; | |
595 | uint64_t vm_gart_size; | |
596 | uint64_t vm_vram_base; | |
597 | uint64_t vm_vram_size; | |
598 | uint64_t vm_end; | |
599 | struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR]; | |
600 | int vm_vram_pt_nr; | |
6ee73861 | 601 | |
b833ac26 | 602 | struct drm_mm ramin_heap; |
6ee73861 | 603 | |
6ee73861 BS |
604 | struct list_head gpuobj_list; |
605 | ||
04a39c57 | 606 | struct nvbios vbios; |
6ee73861 BS |
607 | |
608 | struct nv04_mode_state mode_reg; | |
609 | struct nv04_mode_state saved_reg; | |
610 | uint32_t saved_vga_font[4][16384]; | |
611 | uint32_t crtc_owner; | |
612 | uint32_t dac_users[4]; | |
613 | ||
614 | struct nouveau_suspend_resume { | |
6ee73861 | 615 | uint32_t *ramin_copy; |
6ee73861 BS |
616 | } susres; |
617 | ||
618 | struct backlight_device *backlight; | |
6ee73861 BS |
619 | |
620 | struct nouveau_channel *evo; | |
87c0e0e5 BS |
621 | struct { |
622 | struct dcb_entry *dcb; | |
623 | u16 script; | |
624 | u32 pclk; | |
625 | } evo_irq; | |
6ee73861 BS |
626 | |
627 | struct { | |
628 | struct dentry *channel_root; | |
629 | } debugfs; | |
38651674 | 630 | |
8be48d92 | 631 | struct nouveau_fbdev *nfbdev; |
06415c56 | 632 | struct apertures_struct *apertures; |
6ee73861 BS |
633 | }; |
634 | ||
635 | static inline struct drm_nouveau_private * | |
636 | nouveau_bdev(struct ttm_bo_device *bd) | |
637 | { | |
638 | return container_of(bd, struct drm_nouveau_private, ttm.bdev); | |
639 | } | |
640 | ||
641 | static inline int | |
642 | nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) | |
643 | { | |
644 | struct nouveau_bo *prev; | |
645 | ||
646 | if (!pnvbo) | |
647 | return -EINVAL; | |
648 | prev = *pnvbo; | |
649 | ||
650 | *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; | |
651 | if (prev) { | |
652 | struct ttm_buffer_object *bo = &prev->bo; | |
653 | ||
654 | ttm_bo_unref(&bo); | |
655 | } | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
6ee73861 BS |
660 | #define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \ |
661 | struct drm_nouveau_private *nv = dev->dev_private; \ | |
662 | if (!nouveau_channel_owner(dev, (cl), (id))) { \ | |
663 | NV_ERROR(dev, "pid %d doesn't own channel %d\n", \ | |
664 | DRM_CURRENTPID, (id)); \ | |
665 | return -EPERM; \ | |
666 | } \ | |
667 | (ch) = nv->fifos[(id)]; \ | |
668 | } while (0) | |
669 | ||
670 | /* nouveau_drv.c */ | |
671 | extern int nouveau_noagp; | |
672 | extern int nouveau_duallink; | |
673 | extern int nouveau_uscript_lvds; | |
674 | extern int nouveau_uscript_tmds; | |
675 | extern int nouveau_vram_pushbuf; | |
676 | extern int nouveau_vram_notify; | |
677 | extern int nouveau_fbpercrtc; | |
f4053509 | 678 | extern int nouveau_tv_disable; |
6ee73861 BS |
679 | extern char *nouveau_tv_norm; |
680 | extern int nouveau_reg_debug; | |
681 | extern char *nouveau_vbios; | |
a1470890 | 682 | extern int nouveau_ignorelid; |
a32ed69d MK |
683 | extern int nouveau_nofbaccel; |
684 | extern int nouveau_noaccel; | |
da647d5b | 685 | extern int nouveau_override_conntype; |
6ee73861 | 686 | |
6a9ee8af DA |
687 | extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); |
688 | extern int nouveau_pci_resume(struct pci_dev *pdev); | |
689 | ||
6ee73861 BS |
690 | /* nouveau_state.c */ |
691 | extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); | |
692 | extern int nouveau_load(struct drm_device *, unsigned long flags); | |
693 | extern int nouveau_firstopen(struct drm_device *); | |
694 | extern void nouveau_lastclose(struct drm_device *); | |
695 | extern int nouveau_unload(struct drm_device *); | |
696 | extern int nouveau_ioctl_getparam(struct drm_device *, void *data, | |
697 | struct drm_file *); | |
698 | extern int nouveau_ioctl_setparam(struct drm_device *, void *data, | |
699 | struct drm_file *); | |
700 | extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout, | |
701 | uint32_t reg, uint32_t mask, uint32_t val); | |
702 | extern bool nouveau_wait_for_idle(struct drm_device *); | |
703 | extern int nouveau_card_init(struct drm_device *); | |
6ee73861 BS |
704 | |
705 | /* nouveau_mem.c */ | |
a76fb4e8 | 706 | extern int nouveau_mem_detect(struct drm_device *dev); |
6ee73861 BS |
707 | extern int nouveau_mem_init(struct drm_device *); |
708 | extern int nouveau_mem_init_agp(struct drm_device *); | |
e04d8e82 | 709 | extern int nouveau_mem_reset_agp(struct drm_device *); |
6ee73861 | 710 | extern void nouveau_mem_close(struct drm_device *); |
a0af9add FJ |
711 | extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev, |
712 | uint32_t addr, | |
713 | uint32_t size, | |
714 | uint32_t pitch); | |
715 | extern void nv10_mem_expire_tiling(struct drm_device *dev, | |
716 | struct nouveau_tile_reg *tile, | |
717 | struct nouveau_fence *fence); | |
6ee73861 BS |
718 | extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt, |
719 | uint32_t size, uint32_t flags, | |
720 | uint64_t phys); | |
721 | extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt, | |
722 | uint32_t size); | |
723 | ||
724 | /* nouveau_notifier.c */ | |
725 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); | |
726 | extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); | |
727 | extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, | |
728 | int cout, uint32_t *offset); | |
729 | extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); | |
730 | extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, | |
731 | struct drm_file *); | |
732 | extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, | |
733 | struct drm_file *); | |
734 | ||
735 | /* nouveau_channel.c */ | |
736 | extern struct drm_ioctl_desc nouveau_ioctls[]; | |
737 | extern int nouveau_max_ioctl; | |
738 | extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); | |
739 | extern int nouveau_channel_owner(struct drm_device *, struct drm_file *, | |
740 | int channel); | |
741 | extern int nouveau_channel_alloc(struct drm_device *dev, | |
742 | struct nouveau_channel **chan, | |
743 | struct drm_file *file_priv, | |
744 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); | |
745 | extern void nouveau_channel_free(struct nouveau_channel *); | |
6ee73861 BS |
746 | |
747 | /* nouveau_object.c */ | |
748 | extern int nouveau_gpuobj_early_init(struct drm_device *); | |
749 | extern int nouveau_gpuobj_init(struct drm_device *); | |
750 | extern void nouveau_gpuobj_takedown(struct drm_device *); | |
751 | extern void nouveau_gpuobj_late_takedown(struct drm_device *); | |
752 | extern int nouveau_gpuobj_suspend(struct drm_device *dev); | |
753 | extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev); | |
754 | extern void nouveau_gpuobj_resume(struct drm_device *dev); | |
755 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, | |
756 | uint32_t vram_h, uint32_t tt_h); | |
757 | extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); | |
758 | extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, | |
759 | uint32_t size, int align, uint32_t flags, | |
760 | struct nouveau_gpuobj **); | |
761 | extern int nouveau_gpuobj_del(struct drm_device *, struct nouveau_gpuobj **); | |
762 | extern int nouveau_gpuobj_ref_add(struct drm_device *, struct nouveau_channel *, | |
763 | uint32_t handle, struct nouveau_gpuobj *, | |
764 | struct nouveau_gpuobj_ref **); | |
765 | extern int nouveau_gpuobj_ref_del(struct drm_device *, | |
766 | struct nouveau_gpuobj_ref **); | |
767 | extern int nouveau_gpuobj_ref_find(struct nouveau_channel *, uint32_t handle, | |
768 | struct nouveau_gpuobj_ref **ref_ret); | |
769 | extern int nouveau_gpuobj_new_ref(struct drm_device *, | |
770 | struct nouveau_channel *alloc_chan, | |
771 | struct nouveau_channel *ref_chan, | |
772 | uint32_t handle, uint32_t size, int align, | |
773 | uint32_t flags, struct nouveau_gpuobj_ref **); | |
774 | extern int nouveau_gpuobj_new_fake(struct drm_device *, | |
775 | uint32_t p_offset, uint32_t b_offset, | |
776 | uint32_t size, uint32_t flags, | |
777 | struct nouveau_gpuobj **, | |
778 | struct nouveau_gpuobj_ref**); | |
779 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, | |
780 | uint64_t offset, uint64_t size, int access, | |
781 | int target, struct nouveau_gpuobj **); | |
782 | extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *, | |
783 | uint64_t offset, uint64_t size, | |
784 | int access, struct nouveau_gpuobj **, | |
785 | uint32_t *o_ret); | |
786 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class, | |
787 | struct nouveau_gpuobj **); | |
f03a314b FJ |
788 | extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class, |
789 | struct nouveau_gpuobj **); | |
6ee73861 BS |
790 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, |
791 | struct drm_file *); | |
792 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, | |
793 | struct drm_file *); | |
794 | ||
795 | /* nouveau_irq.c */ | |
796 | extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); | |
797 | extern void nouveau_irq_preinstall(struct drm_device *); | |
798 | extern int nouveau_irq_postinstall(struct drm_device *); | |
799 | extern void nouveau_irq_uninstall(struct drm_device *); | |
800 | ||
801 | /* nouveau_sgdma.c */ | |
802 | extern int nouveau_sgdma_init(struct drm_device *); | |
803 | extern void nouveau_sgdma_takedown(struct drm_device *); | |
804 | extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset, | |
805 | uint32_t *page); | |
806 | extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); | |
807 | ||
808 | /* nouveau_debugfs.c */ | |
809 | #if defined(CONFIG_DRM_NOUVEAU_DEBUG) | |
810 | extern int nouveau_debugfs_init(struct drm_minor *); | |
811 | extern void nouveau_debugfs_takedown(struct drm_minor *); | |
812 | extern int nouveau_debugfs_channel_init(struct nouveau_channel *); | |
813 | extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); | |
814 | #else | |
815 | static inline int | |
816 | nouveau_debugfs_init(struct drm_minor *minor) | |
817 | { | |
818 | return 0; | |
819 | } | |
820 | ||
821 | static inline void nouveau_debugfs_takedown(struct drm_minor *minor) | |
822 | { | |
823 | } | |
824 | ||
825 | static inline int | |
826 | nouveau_debugfs_channel_init(struct nouveau_channel *chan) | |
827 | { | |
828 | return 0; | |
829 | } | |
830 | ||
831 | static inline void | |
832 | nouveau_debugfs_channel_fini(struct nouveau_channel *chan) | |
833 | { | |
834 | } | |
835 | #endif | |
836 | ||
837 | /* nouveau_dma.c */ | |
75c99da6 | 838 | extern void nouveau_dma_pre_init(struct nouveau_channel *); |
6ee73861 | 839 | extern int nouveau_dma_init(struct nouveau_channel *); |
9a391ad8 | 840 | extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); |
6ee73861 BS |
841 | |
842 | /* nouveau_acpi.c */ | |
afeb3e11 | 843 | #define ROM_BIOS_PAGE 4096 |
2f41a7f1 | 844 | #if defined(CONFIG_ACPI) |
6a9ee8af DA |
845 | void nouveau_register_dsm_handler(void); |
846 | void nouveau_unregister_dsm_handler(void); | |
afeb3e11 DA |
847 | int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); |
848 | bool nouveau_acpi_rom_supported(struct pci_dev *pdev); | |
a6ed76d7 | 849 | int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); |
8edb381d DA |
850 | #else |
851 | static inline void nouveau_register_dsm_handler(void) {} | |
852 | static inline void nouveau_unregister_dsm_handler(void) {} | |
afeb3e11 DA |
853 | static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } |
854 | static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } | |
5620ba46 | 855 | static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } |
8edb381d | 856 | #endif |
6ee73861 BS |
857 | |
858 | /* nouveau_backlight.c */ | |
859 | #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT | |
860 | extern int nouveau_backlight_init(struct drm_device *); | |
861 | extern void nouveau_backlight_exit(struct drm_device *); | |
862 | #else | |
863 | static inline int nouveau_backlight_init(struct drm_device *dev) | |
864 | { | |
865 | return 0; | |
866 | } | |
867 | ||
868 | static inline void nouveau_backlight_exit(struct drm_device *dev) { } | |
869 | #endif | |
870 | ||
871 | /* nouveau_bios.c */ | |
872 | extern int nouveau_bios_init(struct drm_device *); | |
873 | extern void nouveau_bios_takedown(struct drm_device *dev); | |
874 | extern int nouveau_run_vbios_init(struct drm_device *); | |
875 | extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, | |
876 | struct dcb_entry *); | |
877 | extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, | |
878 | enum dcb_gpio_tag); | |
879 | extern struct dcb_connector_table_entry * | |
880 | nouveau_bios_connector_entry(struct drm_device *, int index); | |
881 | extern int get_pll_limits(struct drm_device *, uint32_t limit_match, | |
882 | struct pll_lims *); | |
883 | extern int nouveau_bios_run_display_table(struct drm_device *, | |
884 | struct dcb_entry *, | |
885 | uint32_t script, int pxclk); | |
886 | extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, | |
887 | int *length); | |
888 | extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); | |
889 | extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); | |
890 | extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, | |
891 | bool *dl, bool *if_is_24bit); | |
892 | extern int run_tmds_table(struct drm_device *, struct dcb_entry *, | |
893 | int head, int pxclk); | |
894 | extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, | |
895 | enum LVDS_script, int pxclk); | |
896 | ||
897 | /* nouveau_ttm.c */ | |
898 | int nouveau_ttm_global_init(struct drm_nouveau_private *); | |
899 | void nouveau_ttm_global_release(struct drm_nouveau_private *); | |
900 | int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); | |
901 | ||
902 | /* nouveau_dp.c */ | |
903 | int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, | |
904 | uint8_t *data, int data_nr); | |
905 | bool nouveau_dp_detect(struct drm_encoder *); | |
906 | bool nouveau_dp_link_train(struct drm_encoder *); | |
907 | ||
908 | /* nv04_fb.c */ | |
909 | extern int nv04_fb_init(struct drm_device *); | |
910 | extern void nv04_fb_takedown(struct drm_device *); | |
911 | ||
912 | /* nv10_fb.c */ | |
913 | extern int nv10_fb_init(struct drm_device *); | |
914 | extern void nv10_fb_takedown(struct drm_device *); | |
cb00f7c1 FJ |
915 | extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t, |
916 | uint32_t, uint32_t); | |
6ee73861 | 917 | |
8bded189 FJ |
918 | /* nv30_fb.c */ |
919 | extern int nv30_fb_init(struct drm_device *); | |
920 | extern void nv30_fb_takedown(struct drm_device *); | |
921 | ||
6ee73861 BS |
922 | /* nv40_fb.c */ |
923 | extern int nv40_fb_init(struct drm_device *); | |
924 | extern void nv40_fb_takedown(struct drm_device *); | |
cb00f7c1 FJ |
925 | extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t, |
926 | uint32_t, uint32_t); | |
6ee73861 | 927 | |
304424e1 MK |
928 | /* nv50_fb.c */ |
929 | extern int nv50_fb_init(struct drm_device *); | |
930 | extern void nv50_fb_takedown(struct drm_device *); | |
931 | ||
6ee73861 BS |
932 | /* nv04_fifo.c */ |
933 | extern int nv04_fifo_init(struct drm_device *); | |
934 | extern void nv04_fifo_disable(struct drm_device *); | |
935 | extern void nv04_fifo_enable(struct drm_device *); | |
936 | extern bool nv04_fifo_reassign(struct drm_device *, bool); | |
588d7d12 FJ |
937 | extern bool nv04_fifo_cache_flush(struct drm_device *); |
938 | extern bool nv04_fifo_cache_pull(struct drm_device *, bool); | |
6ee73861 BS |
939 | extern int nv04_fifo_channel_id(struct drm_device *); |
940 | extern int nv04_fifo_create_context(struct nouveau_channel *); | |
941 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); | |
942 | extern int nv04_fifo_load_context(struct nouveau_channel *); | |
943 | extern int nv04_fifo_unload_context(struct drm_device *); | |
944 | ||
945 | /* nv10_fifo.c */ | |
946 | extern int nv10_fifo_init(struct drm_device *); | |
947 | extern int nv10_fifo_channel_id(struct drm_device *); | |
948 | extern int nv10_fifo_create_context(struct nouveau_channel *); | |
949 | extern void nv10_fifo_destroy_context(struct nouveau_channel *); | |
950 | extern int nv10_fifo_load_context(struct nouveau_channel *); | |
951 | extern int nv10_fifo_unload_context(struct drm_device *); | |
952 | ||
953 | /* nv40_fifo.c */ | |
954 | extern int nv40_fifo_init(struct drm_device *); | |
955 | extern int nv40_fifo_create_context(struct nouveau_channel *); | |
956 | extern void nv40_fifo_destroy_context(struct nouveau_channel *); | |
957 | extern int nv40_fifo_load_context(struct nouveau_channel *); | |
958 | extern int nv40_fifo_unload_context(struct drm_device *); | |
959 | ||
960 | /* nv50_fifo.c */ | |
961 | extern int nv50_fifo_init(struct drm_device *); | |
962 | extern void nv50_fifo_takedown(struct drm_device *); | |
963 | extern int nv50_fifo_channel_id(struct drm_device *); | |
964 | extern int nv50_fifo_create_context(struct nouveau_channel *); | |
965 | extern void nv50_fifo_destroy_context(struct nouveau_channel *); | |
966 | extern int nv50_fifo_load_context(struct nouveau_channel *); | |
967 | extern int nv50_fifo_unload_context(struct drm_device *); | |
968 | ||
969 | /* nv04_graph.c */ | |
970 | extern struct nouveau_pgraph_object_class nv04_graph_grclass[]; | |
971 | extern int nv04_graph_init(struct drm_device *); | |
972 | extern void nv04_graph_takedown(struct drm_device *); | |
973 | extern void nv04_graph_fifo_access(struct drm_device *, bool); | |
974 | extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); | |
975 | extern int nv04_graph_create_context(struct nouveau_channel *); | |
976 | extern void nv04_graph_destroy_context(struct nouveau_channel *); | |
977 | extern int nv04_graph_load_context(struct nouveau_channel *); | |
978 | extern int nv04_graph_unload_context(struct drm_device *); | |
979 | extern void nv04_graph_context_switch(struct drm_device *); | |
980 | ||
981 | /* nv10_graph.c */ | |
982 | extern struct nouveau_pgraph_object_class nv10_graph_grclass[]; | |
983 | extern int nv10_graph_init(struct drm_device *); | |
984 | extern void nv10_graph_takedown(struct drm_device *); | |
985 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); | |
986 | extern int nv10_graph_create_context(struct nouveau_channel *); | |
987 | extern void nv10_graph_destroy_context(struct nouveau_channel *); | |
988 | extern int nv10_graph_load_context(struct nouveau_channel *); | |
989 | extern int nv10_graph_unload_context(struct drm_device *); | |
990 | extern void nv10_graph_context_switch(struct drm_device *); | |
cb00f7c1 FJ |
991 | extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t, |
992 | uint32_t, uint32_t); | |
6ee73861 BS |
993 | |
994 | /* nv20_graph.c */ | |
995 | extern struct nouveau_pgraph_object_class nv20_graph_grclass[]; | |
996 | extern struct nouveau_pgraph_object_class nv30_graph_grclass[]; | |
997 | extern int nv20_graph_create_context(struct nouveau_channel *); | |
998 | extern void nv20_graph_destroy_context(struct nouveau_channel *); | |
999 | extern int nv20_graph_load_context(struct nouveau_channel *); | |
1000 | extern int nv20_graph_unload_context(struct drm_device *); | |
1001 | extern int nv20_graph_init(struct drm_device *); | |
1002 | extern void nv20_graph_takedown(struct drm_device *); | |
1003 | extern int nv30_graph_init(struct drm_device *); | |
cb00f7c1 FJ |
1004 | extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t, |
1005 | uint32_t, uint32_t); | |
6ee73861 BS |
1006 | |
1007 | /* nv40_graph.c */ | |
1008 | extern struct nouveau_pgraph_object_class nv40_graph_grclass[]; | |
1009 | extern int nv40_graph_init(struct drm_device *); | |
1010 | extern void nv40_graph_takedown(struct drm_device *); | |
1011 | extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); | |
1012 | extern int nv40_graph_create_context(struct nouveau_channel *); | |
1013 | extern void nv40_graph_destroy_context(struct nouveau_channel *); | |
1014 | extern int nv40_graph_load_context(struct nouveau_channel *); | |
1015 | extern int nv40_graph_unload_context(struct drm_device *); | |
054b93e4 | 1016 | extern void nv40_grctx_init(struct nouveau_grctx *); |
cb00f7c1 FJ |
1017 | extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t, |
1018 | uint32_t, uint32_t); | |
6ee73861 BS |
1019 | |
1020 | /* nv50_graph.c */ | |
1021 | extern struct nouveau_pgraph_object_class nv50_graph_grclass[]; | |
1022 | extern int nv50_graph_init(struct drm_device *); | |
1023 | extern void nv50_graph_takedown(struct drm_device *); | |
1024 | extern void nv50_graph_fifo_access(struct drm_device *, bool); | |
1025 | extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); | |
1026 | extern int nv50_graph_create_context(struct nouveau_channel *); | |
1027 | extern void nv50_graph_destroy_context(struct nouveau_channel *); | |
1028 | extern int nv50_graph_load_context(struct nouveau_channel *); | |
1029 | extern int nv50_graph_unload_context(struct drm_device *); | |
1030 | extern void nv50_graph_context_switch(struct drm_device *); | |
d5f3c90d | 1031 | extern int nv50_grctx_init(struct nouveau_grctx *); |
6ee73861 BS |
1032 | |
1033 | /* nv04_instmem.c */ | |
1034 | extern int nv04_instmem_init(struct drm_device *); | |
1035 | extern void nv04_instmem_takedown(struct drm_device *); | |
1036 | extern int nv04_instmem_suspend(struct drm_device *); | |
1037 | extern void nv04_instmem_resume(struct drm_device *); | |
1038 | extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, | |
1039 | uint32_t *size); | |
1040 | extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); | |
1041 | extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); | |
1042 | extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); | |
f56cb86f | 1043 | extern void nv04_instmem_flush(struct drm_device *); |
6ee73861 BS |
1044 | |
1045 | /* nv50_instmem.c */ | |
1046 | extern int nv50_instmem_init(struct drm_device *); | |
1047 | extern void nv50_instmem_takedown(struct drm_device *); | |
1048 | extern int nv50_instmem_suspend(struct drm_device *); | |
1049 | extern void nv50_instmem_resume(struct drm_device *); | |
1050 | extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *, | |
1051 | uint32_t *size); | |
1052 | extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *); | |
1053 | extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *); | |
1054 | extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *); | |
f56cb86f | 1055 | extern void nv50_instmem_flush(struct drm_device *); |
734ee835 | 1056 | extern void nv84_instmem_flush(struct drm_device *); |
63187215 | 1057 | extern void nv50_vm_flush(struct drm_device *, int engine); |
6ee73861 BS |
1058 | |
1059 | /* nv04_mc.c */ | |
1060 | extern int nv04_mc_init(struct drm_device *); | |
1061 | extern void nv04_mc_takedown(struct drm_device *); | |
1062 | ||
1063 | /* nv40_mc.c */ | |
1064 | extern int nv40_mc_init(struct drm_device *); | |
1065 | extern void nv40_mc_takedown(struct drm_device *); | |
1066 | ||
1067 | /* nv50_mc.c */ | |
1068 | extern int nv50_mc_init(struct drm_device *); | |
1069 | extern void nv50_mc_takedown(struct drm_device *); | |
1070 | ||
1071 | /* nv04_timer.c */ | |
1072 | extern int nv04_timer_init(struct drm_device *); | |
1073 | extern uint64_t nv04_timer_read(struct drm_device *); | |
1074 | extern void nv04_timer_takedown(struct drm_device *); | |
1075 | ||
1076 | extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, | |
1077 | unsigned long arg); | |
1078 | ||
1079 | /* nv04_dac.c */ | |
8f1a6086 | 1080 | extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); |
11d6eb2a | 1081 | extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); |
6ee73861 BS |
1082 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); |
1083 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); | |
8ccfe9e0 | 1084 | extern bool nv04_dac_in_use(struct drm_encoder *encoder); |
6ee73861 BS |
1085 | |
1086 | /* nv04_dfp.c */ | |
8f1a6086 | 1087 | extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1088 | extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); |
1089 | extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, | |
1090 | int head, bool dl); | |
1091 | extern void nv04_dfp_disable(struct drm_device *dev, int head); | |
1092 | extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); | |
1093 | ||
1094 | /* nv04_tv.c */ | |
1095 | extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); | |
8f1a6086 | 1096 | extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1097 | |
1098 | /* nv17_tv.c */ | |
8f1a6086 | 1099 | extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1100 | |
1101 | /* nv04_display.c */ | |
c88c2e06 FJ |
1102 | extern int nv04_display_early_init(struct drm_device *); |
1103 | extern void nv04_display_late_takedown(struct drm_device *); | |
6ee73861 | 1104 | extern int nv04_display_create(struct drm_device *); |
c88c2e06 | 1105 | extern int nv04_display_init(struct drm_device *); |
6ee73861 | 1106 | extern void nv04_display_destroy(struct drm_device *); |
6ee73861 BS |
1107 | |
1108 | /* nv04_crtc.c */ | |
1109 | extern int nv04_crtc_create(struct drm_device *, int index); | |
1110 | ||
1111 | /* nouveau_bo.c */ | |
1112 | extern struct ttm_bo_driver nouveau_bo_driver; | |
1113 | extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, | |
1114 | int size, int align, uint32_t flags, | |
1115 | uint32_t tile_mode, uint32_t tile_flags, | |
1116 | bool no_vm, bool mappable, struct nouveau_bo **); | |
1117 | extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); | |
1118 | extern int nouveau_bo_unpin(struct nouveau_bo *); | |
1119 | extern int nouveau_bo_map(struct nouveau_bo *); | |
1120 | extern void nouveau_bo_unmap(struct nouveau_bo *); | |
78ad0f7b FJ |
1121 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, |
1122 | uint32_t busy); | |
6ee73861 BS |
1123 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); |
1124 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); | |
1125 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); | |
1126 | extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); | |
1127 | ||
1128 | /* nouveau_fence.c */ | |
1129 | struct nouveau_fence; | |
1130 | extern int nouveau_fence_init(struct nouveau_channel *); | |
1131 | extern void nouveau_fence_fini(struct nouveau_channel *); | |
1132 | extern void nouveau_fence_update(struct nouveau_channel *); | |
1133 | extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, | |
1134 | bool emit); | |
1135 | extern int nouveau_fence_emit(struct nouveau_fence *); | |
1136 | struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); | |
1137 | extern bool nouveau_fence_signalled(void *obj, void *arg); | |
1138 | extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); | |
1139 | extern int nouveau_fence_flush(void *obj, void *arg); | |
1140 | extern void nouveau_fence_unref(void **obj); | |
1141 | extern void *nouveau_fence_ref(void *obj); | |
6ee73861 BS |
1142 | |
1143 | /* nouveau_gem.c */ | |
1144 | extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, | |
1145 | int size, int align, uint32_t flags, | |
1146 | uint32_t tile_mode, uint32_t tile_flags, | |
1147 | bool no_vm, bool mappable, struct nouveau_bo **); | |
1148 | extern int nouveau_gem_object_new(struct drm_gem_object *); | |
1149 | extern void nouveau_gem_object_del(struct drm_gem_object *); | |
1150 | extern int nouveau_gem_ioctl_new(struct drm_device *, void *, | |
1151 | struct drm_file *); | |
1152 | extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, | |
1153 | struct drm_file *); | |
6ee73861 BS |
1154 | extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, |
1155 | struct drm_file *); | |
1156 | extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, | |
1157 | struct drm_file *); | |
1158 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | |
1159 | struct drm_file *); | |
1160 | ||
ee2e0131 BS |
1161 | /* nv10_gpio.c */ |
1162 | int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | |
1163 | int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
6ee73861 | 1164 | |
45284162 | 1165 | /* nv50_gpio.c */ |
ee2e0131 | 1166 | int nv50_gpio_init(struct drm_device *dev); |
45284162 BS |
1167 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1168 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
d0875edd | 1169 | void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); |
45284162 | 1170 | |
e9ebb68b BS |
1171 | /* nv50_calc. */ |
1172 | int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, | |
1173 | int *N1, int *M1, int *N2, int *M2, int *P); | |
1174 | int nv50_calc_pll2(struct drm_device *, struct pll_lims *, | |
1175 | int clk, int *N, int *fN, int *M, int *P); | |
1176 | ||
6ee73861 BS |
1177 | #ifndef ioread32_native |
1178 | #ifdef __BIG_ENDIAN | |
1179 | #define ioread16_native ioread16be | |
1180 | #define iowrite16_native iowrite16be | |
1181 | #define ioread32_native ioread32be | |
1182 | #define iowrite32_native iowrite32be | |
1183 | #else /* def __BIG_ENDIAN */ | |
1184 | #define ioread16_native ioread16 | |
1185 | #define iowrite16_native iowrite16 | |
1186 | #define ioread32_native ioread32 | |
1187 | #define iowrite32_native iowrite32 | |
1188 | #endif /* def __BIG_ENDIAN else */ | |
1189 | #endif /* !ioread32_native */ | |
1190 | ||
1191 | /* channel control reg access */ | |
1192 | static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) | |
1193 | { | |
1194 | return ioread32_native(chan->user + reg); | |
1195 | } | |
1196 | ||
1197 | static inline void nvchan_wr32(struct nouveau_channel *chan, | |
1198 | unsigned reg, u32 val) | |
1199 | { | |
1200 | iowrite32_native(val, chan->user + reg); | |
1201 | } | |
1202 | ||
1203 | /* register access */ | |
1204 | static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) | |
1205 | { | |
1206 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1207 | return ioread32_native(dev_priv->mmio + reg); | |
1208 | } | |
1209 | ||
1210 | static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) | |
1211 | { | |
1212 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1213 | iowrite32_native(val, dev_priv->mmio + reg); | |
1214 | } | |
1215 | ||
49eed80a BS |
1216 | static inline void nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) |
1217 | { | |
1218 | u32 tmp = nv_rd32(dev, reg); | |
1219 | tmp &= ~mask; | |
1220 | tmp |= val; | |
1221 | nv_wr32(dev, reg, tmp); | |
1222 | } | |
1223 | ||
6ee73861 BS |
1224 | static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) |
1225 | { | |
1226 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1227 | return ioread8(dev_priv->mmio + reg); | |
1228 | } | |
1229 | ||
1230 | static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) | |
1231 | { | |
1232 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1233 | iowrite8(val, dev_priv->mmio + reg); | |
1234 | } | |
1235 | ||
1236 | #define nv_wait(reg, mask, val) \ | |
1237 | nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val)) | |
1238 | ||
1239 | /* PRAMIN access */ | |
1240 | static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) | |
1241 | { | |
1242 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1243 | return ioread32_native(dev_priv->ramin + offset); | |
1244 | } | |
1245 | ||
1246 | static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) | |
1247 | { | |
1248 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1249 | iowrite32_native(val, dev_priv->ramin + offset); | |
1250 | } | |
1251 | ||
1252 | /* object access */ | |
1253 | static inline u32 nv_ro32(struct drm_device *dev, struct nouveau_gpuobj *obj, | |
1254 | unsigned index) | |
1255 | { | |
1256 | return nv_ri32(dev, obj->im_pramin->start + index * 4); | |
1257 | } | |
1258 | ||
1259 | static inline void nv_wo32(struct drm_device *dev, struct nouveau_gpuobj *obj, | |
1260 | unsigned index, u32 val) | |
1261 | { | |
1262 | nv_wi32(dev, obj->im_pramin->start + index * 4, val); | |
1263 | } | |
1264 | ||
1265 | /* | |
1266 | * Logging | |
1267 | * Argument d is (struct drm_device *). | |
1268 | */ | |
1269 | #define NV_PRINTK(level, d, fmt, arg...) \ | |
1270 | printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ | |
1271 | pci_name(d->pdev), ##arg) | |
1272 | #ifndef NV_DEBUG_NOTRACE | |
1273 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1274 | if (drm_debug & DRM_UT_DRIVER) { \ |
1275 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ | |
1276 | __LINE__, ##arg); \ | |
1277 | } \ | |
1278 | } while (0) | |
1279 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1280 | if (drm_debug & DRM_UT_KMS) { \ | |
6ee73861 BS |
1281 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ |
1282 | __LINE__, ##arg); \ | |
1283 | } \ | |
1284 | } while (0) | |
1285 | #else | |
1286 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1287 | if (drm_debug & DRM_UT_DRIVER) \ |
1288 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ | |
1289 | } while (0) | |
1290 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1291 | if (drm_debug & DRM_UT_KMS) \ | |
6ee73861 BS |
1292 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ |
1293 | } while (0) | |
1294 | #endif | |
1295 | #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) | |
1296 | #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1297 | #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) | |
1298 | #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1299 | #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) | |
1300 | ||
1301 | /* nouveau_reg_debug bitmask */ | |
1302 | enum { | |
1303 | NOUVEAU_REG_DEBUG_MC = 0x1, | |
1304 | NOUVEAU_REG_DEBUG_VIDEO = 0x2, | |
1305 | NOUVEAU_REG_DEBUG_FB = 0x4, | |
1306 | NOUVEAU_REG_DEBUG_EXTDEV = 0x8, | |
1307 | NOUVEAU_REG_DEBUG_CRTC = 0x10, | |
1308 | NOUVEAU_REG_DEBUG_RAMDAC = 0x20, | |
1309 | NOUVEAU_REG_DEBUG_VGACRTC = 0x40, | |
1310 | NOUVEAU_REG_DEBUG_RMVIO = 0x80, | |
1311 | NOUVEAU_REG_DEBUG_VGAATTR = 0x100, | |
1312 | NOUVEAU_REG_DEBUG_EVO = 0x200, | |
1313 | }; | |
1314 | ||
1315 | #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ | |
1316 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ | |
1317 | NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ | |
1318 | } while (0) | |
1319 | ||
1320 | static inline bool | |
1321 | nv_two_heads(struct drm_device *dev) | |
1322 | { | |
1323 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1324 | const int impl = dev->pci_device & 0x0ff0; | |
1325 | ||
1326 | if (dev_priv->card_type >= NV_10 && impl != 0x0100 && | |
1327 | impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) | |
1328 | return true; | |
1329 | ||
1330 | return false; | |
1331 | } | |
1332 | ||
1333 | static inline bool | |
1334 | nv_gf4_disp_arch(struct drm_device *dev) | |
1335 | { | |
1336 | return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; | |
1337 | } | |
1338 | ||
1339 | static inline bool | |
1340 | nv_two_reg_pll(struct drm_device *dev) | |
1341 | { | |
1342 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1343 | const int impl = dev->pci_device & 0x0ff0; | |
1344 | ||
1345 | if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) | |
1346 | return true; | |
1347 | return false; | |
1348 | } | |
1349 | ||
f03a314b FJ |
1350 | #define NV_SW 0x0000506e |
1351 | #define NV_SW_DMA_SEMAPHORE 0x00000060 | |
1352 | #define NV_SW_SEMAPHORE_OFFSET 0x00000064 | |
1353 | #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 | |
1354 | #define NV_SW_SEMAPHORE_RELEASE 0x0000006c | |
1355 | #define NV_SW_DMA_VBLSEM 0x0000018c | |
1356 | #define NV_SW_VBLSEM_OFFSET 0x00000400 | |
1357 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 | |
1358 | #define NV_SW_VBLSEM_RELEASE 0x00000408 | |
6ee73861 BS |
1359 | |
1360 | #endif /* __NOUVEAU_DRV_H__ */ |