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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef __NOUVEAU_DRV_H__ | |
26 | #define __NOUVEAU_DRV_H__ | |
27 | ||
28 | #define DRIVER_AUTHOR "Stephane Marchesin" | |
29 | #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" | |
30 | ||
31 | #define DRIVER_NAME "nouveau" | |
32 | #define DRIVER_DESC "nVidia Riva/TNT/GeForce" | |
33 | #define DRIVER_DATE "20090420" | |
34 | ||
35 | #define DRIVER_MAJOR 0 | |
36 | #define DRIVER_MINOR 0 | |
a1606a95 | 37 | #define DRIVER_PATCHLEVEL 16 |
6ee73861 BS |
38 | |
39 | #define NOUVEAU_FAMILY 0x0000FFFF | |
40 | #define NOUVEAU_FLAGS 0xFFFF0000 | |
41 | ||
42 | #include "ttm/ttm_bo_api.h" | |
43 | #include "ttm/ttm_bo_driver.h" | |
44 | #include "ttm/ttm_placement.h" | |
45 | #include "ttm/ttm_memory.h" | |
46 | #include "ttm/ttm_module.h" | |
47 | ||
48 | struct nouveau_fpriv { | |
3f0a68d8 | 49 | spinlock_t lock; |
e8a863c1 | 50 | struct list_head channels; |
fe32b16e | 51 | struct nouveau_vm *vm; |
6ee73861 BS |
52 | }; |
53 | ||
3f0a68d8 BS |
54 | static inline struct nouveau_fpriv * |
55 | nouveau_fpriv(struct drm_file *file_priv) | |
56 | { | |
57 | return file_priv ? file_priv->driver_priv : NULL; | |
58 | } | |
59 | ||
6ee73861 BS |
60 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
61 | ||
62 | #include "nouveau_drm.h" | |
63 | #include "nouveau_reg.h" | |
64 | #include "nouveau_bios.h" | |
274fec93 | 65 | #include "nouveau_util.h" |
f869ef88 | 66 | |
054b93e4 | 67 | struct nouveau_grctx; |
d5f42394 | 68 | struct nouveau_mem; |
f869ef88 | 69 | #include "nouveau_vm.h" |
6ee73861 BS |
70 | |
71 | #define MAX_NUM_DCB_ENTRIES 16 | |
72 | ||
73 | #define NOUVEAU_MAX_CHANNEL_NR 128 | |
a0af9add | 74 | #define NOUVEAU_MAX_TILE_NR 15 |
6ee73861 | 75 | |
d5f42394 | 76 | struct nouveau_mem { |
573a2a37 BS |
77 | struct drm_device *dev; |
78 | ||
f869ef88 | 79 | struct nouveau_vma bar_vma; |
d2f96666 | 80 | struct nouveau_vma vma[2]; |
4c74eb7f | 81 | u8 page_shift; |
f869ef88 | 82 | |
8f7286f8 | 83 | struct drm_mm_node *tag; |
573a2a37 | 84 | struct list_head regions; |
26c0c9e3 | 85 | dma_addr_t *pages; |
573a2a37 BS |
86 | u32 memtype; |
87 | u64 offset; | |
88 | u64 size; | |
89 | }; | |
90 | ||
a0af9add | 91 | struct nouveau_tile_reg { |
a0af9add | 92 | bool used; |
a5cf68b0 FJ |
93 | uint32_t addr; |
94 | uint32_t limit; | |
95 | uint32_t pitch; | |
87a326a3 FJ |
96 | uint32_t zcomp; |
97 | struct drm_mm_node *tag_mem; | |
a5cf68b0 | 98 | struct nouveau_fence *fence; |
a0af9add FJ |
99 | }; |
100 | ||
6ee73861 BS |
101 | struct nouveau_bo { |
102 | struct ttm_buffer_object bo; | |
103 | struct ttm_placement placement; | |
db5c8e29 | 104 | u32 valid_domains; |
6ee73861 | 105 | u32 placements[3]; |
78ad0f7b | 106 | u32 busy_placements[3]; |
6ee73861 BS |
107 | struct ttm_bo_kmap_obj kmap; |
108 | struct list_head head; | |
109 | ||
110 | /* protected by ttm_bo_reserve() */ | |
111 | struct drm_file *reserved_by; | |
112 | struct list_head entry; | |
113 | int pbbo_index; | |
a1606a95 | 114 | bool validate_mapped; |
6ee73861 BS |
115 | |
116 | struct nouveau_channel *channel; | |
117 | ||
fd2871af | 118 | struct list_head vma_list; |
f91bac5b | 119 | unsigned page_shift; |
6ee73861 BS |
120 | |
121 | uint32_t tile_mode; | |
122 | uint32_t tile_flags; | |
a0af9add | 123 | struct nouveau_tile_reg *tile; |
6ee73861 BS |
124 | |
125 | struct drm_gem_object *gem; | |
6ee73861 BS |
126 | int pin_refcnt; |
127 | }; | |
128 | ||
f13b3263 FJ |
129 | #define nouveau_bo_tile_layout(nvbo) \ |
130 | ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) | |
131 | ||
6ee73861 BS |
132 | static inline struct nouveau_bo * |
133 | nouveau_bo(struct ttm_buffer_object *bo) | |
134 | { | |
135 | return container_of(bo, struct nouveau_bo, bo); | |
136 | } | |
137 | ||
138 | static inline struct nouveau_bo * | |
139 | nouveau_gem_object(struct drm_gem_object *gem) | |
140 | { | |
141 | return gem ? gem->driver_private : NULL; | |
142 | } | |
143 | ||
144 | /* TODO: submit equivalent to TTM generic API upstream? */ | |
145 | static inline void __iomem * | |
146 | nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) | |
147 | { | |
148 | bool is_iomem; | |
149 | void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( | |
150 | &nvbo->kmap, &is_iomem); | |
151 | WARN_ON_ONCE(ioptr && !is_iomem); | |
152 | return ioptr; | |
153 | } | |
154 | ||
6ee73861 BS |
155 | enum nouveau_flags { |
156 | NV_NFORCE = 0x10000000, | |
157 | NV_NFORCE2 = 0x20000000 | |
158 | }; | |
159 | ||
160 | #define NVOBJ_ENGINE_SW 0 | |
161 | #define NVOBJ_ENGINE_GR 1 | |
6dfdd7a6 | 162 | #define NVOBJ_ENGINE_CRYPT 2 |
7ff5441e BS |
163 | #define NVOBJ_ENGINE_COPY0 3 |
164 | #define NVOBJ_ENGINE_COPY1 4 | |
a02ccc7f | 165 | #define NVOBJ_ENGINE_MPEG 5 |
6dfdd7a6 BS |
166 | #define NVOBJ_ENGINE_DISPLAY 15 |
167 | #define NVOBJ_ENGINE_NR 16 | |
6ee73861 | 168 | |
a11c3198 | 169 | #define NVOBJ_FLAG_DONT_MAP (1 << 0) |
6ee73861 BS |
170 | #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) |
171 | #define NVOBJ_FLAG_ZERO_FREE (1 << 2) | |
34cf01bc | 172 | #define NVOBJ_FLAG_VM (1 << 3) |
c906ca0f | 173 | #define NVOBJ_FLAG_VM_USER (1 << 4) |
e41115d0 BS |
174 | |
175 | #define NVOBJ_CINST_GLOBAL 0xdeadbeef | |
176 | ||
6ee73861 | 177 | struct nouveau_gpuobj { |
b3beb167 | 178 | struct drm_device *dev; |
eb9bcbdc | 179 | struct kref refcount; |
6ee73861 BS |
180 | struct list_head list; |
181 | ||
e41115d0 | 182 | void *node; |
dc1e5c0d | 183 | u32 *suspend; |
6ee73861 BS |
184 | |
185 | uint32_t flags; | |
6ee73861 | 186 | |
43efc9ce | 187 | u32 size; |
f8522fc8 BS |
188 | u32 pinst; /* PRAMIN BAR offset */ |
189 | u32 cinst; /* Channel offset */ | |
190 | u64 vinst; /* VRAM address */ | |
191 | u64 linst; /* VM address */ | |
de3a6c0a | 192 | |
6ee73861 BS |
193 | uint32_t engine; |
194 | uint32_t class; | |
195 | ||
196 | void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); | |
197 | void *priv; | |
198 | }; | |
199 | ||
332b242f FJ |
200 | struct nouveau_page_flip_state { |
201 | struct list_head head; | |
202 | struct drm_pending_vblank_event *event; | |
203 | int crtc, bpp, pitch, x, y; | |
204 | uint64_t offset; | |
205 | }; | |
206 | ||
e419cf09 FJ |
207 | enum nouveau_channel_mutex_class { |
208 | NOUVEAU_UCHANNEL_MUTEX, | |
209 | NOUVEAU_KCHANNEL_MUTEX | |
210 | }; | |
211 | ||
6ee73861 BS |
212 | struct nouveau_channel { |
213 | struct drm_device *dev; | |
e8a863c1 | 214 | struct list_head list; |
6ee73861 BS |
215 | int id; |
216 | ||
f091a3d4 FJ |
217 | /* references to the channel data structure */ |
218 | struct kref ref; | |
219 | /* users of the hardware channel resources, the hardware | |
220 | * context will be kicked off when it reaches zero. */ | |
221 | atomic_t users; | |
6a6b73f2 BS |
222 | struct mutex mutex; |
223 | ||
6ee73861 BS |
224 | /* owner of this fifo */ |
225 | struct drm_file *file_priv; | |
226 | /* mapping of the fifo itself */ | |
227 | struct drm_local_map *map; | |
228 | ||
25985edc | 229 | /* mapping of the regs controlling the fifo */ |
6ee73861 BS |
230 | void __iomem *user; |
231 | uint32_t user_get; | |
232 | uint32_t user_put; | |
233 | ||
234 | /* Fencing */ | |
235 | struct { | |
236 | /* lock protects the pending list only */ | |
237 | spinlock_t lock; | |
238 | struct list_head pending; | |
239 | uint32_t sequence; | |
240 | uint32_t sequence_ack; | |
047d1d3c | 241 | atomic_t last_sequence_irq; |
d02836b4 | 242 | struct nouveau_vma vma; |
6ee73861 BS |
243 | } fence; |
244 | ||
245 | /* DMA push buffer */ | |
a8eaebc6 BS |
246 | struct nouveau_gpuobj *pushbuf; |
247 | struct nouveau_bo *pushbuf_bo; | |
ce163f69 | 248 | struct nouveau_vma pushbuf_vma; |
a8eaebc6 | 249 | uint32_t pushbuf_base; |
6ee73861 BS |
250 | |
251 | /* Notifier memory */ | |
252 | struct nouveau_bo *notifier_bo; | |
0b718733 | 253 | struct nouveau_vma notifier_vma; |
b833ac26 | 254 | struct drm_mm notifier_heap; |
6ee73861 BS |
255 | |
256 | /* PFIFO context */ | |
a8eaebc6 BS |
257 | struct nouveau_gpuobj *ramfc; |
258 | struct nouveau_gpuobj *cache; | |
b2b09938 | 259 | void *fifo_priv; |
6ee73861 | 260 | |
a82dd49f | 261 | /* Execution engine contexts */ |
6dfdd7a6 | 262 | void *engctx[NVOBJ_ENGINE_NR]; |
6ee73861 BS |
263 | |
264 | /* NV50 VM */ | |
f869ef88 | 265 | struct nouveau_vm *vm; |
a8eaebc6 | 266 | struct nouveau_gpuobj *vm_pd; |
6ee73861 BS |
267 | |
268 | /* Objects */ | |
a8eaebc6 BS |
269 | struct nouveau_gpuobj *ramin; /* Private instmem */ |
270 | struct drm_mm ramin_heap; /* Private PRAMIN heap */ | |
271 | struct nouveau_ramht *ramht; /* Hash table */ | |
6ee73861 BS |
272 | |
273 | /* GPU object info for stuff used in-kernel (mm_enabled) */ | |
274 | uint32_t m2mf_ntfy; | |
275 | uint32_t vram_handle; | |
276 | uint32_t gart_handle; | |
277 | bool accel_done; | |
278 | ||
279 | /* Push buffer state (only for drm's channel on !mm_enabled) */ | |
280 | struct { | |
281 | int max; | |
282 | int free; | |
283 | int cur; | |
284 | int put; | |
285 | /* access via pushbuf_bo */ | |
9a391ad8 BS |
286 | |
287 | int ib_base; | |
288 | int ib_max; | |
289 | int ib_free; | |
290 | int ib_put; | |
6ee73861 BS |
291 | } dma; |
292 | ||
293 | uint32_t sw_subchannel[8]; | |
294 | ||
3d483d57 | 295 | struct nouveau_vma dispc_vma[2]; |
6ee73861 BS |
296 | struct { |
297 | struct nouveau_gpuobj *vblsem; | |
1f6d2de2 | 298 | uint32_t vblsem_head; |
6ee73861 BS |
299 | uint32_t vblsem_offset; |
300 | uint32_t vblsem_rval; | |
301 | struct list_head vbl_wait; | |
332b242f | 302 | struct list_head flip; |
6ee73861 BS |
303 | } nvsw; |
304 | ||
305 | struct { | |
306 | bool active; | |
307 | char name[32]; | |
308 | struct drm_info_list info; | |
309 | } debugfs; | |
310 | }; | |
311 | ||
6dfdd7a6 BS |
312 | struct nouveau_exec_engine { |
313 | void (*destroy)(struct drm_device *, int engine); | |
314 | int (*init)(struct drm_device *, int engine); | |
6c320fef | 315 | int (*fini)(struct drm_device *, int engine, bool suspend); |
6dfdd7a6 BS |
316 | int (*context_new)(struct nouveau_channel *, int engine); |
317 | void (*context_del)(struct nouveau_channel *, int engine); | |
318 | int (*object_new)(struct nouveau_channel *, int engine, | |
319 | u32 handle, u16 class); | |
96c50082 | 320 | void (*set_tile_region)(struct drm_device *dev, int i); |
6dfdd7a6 BS |
321 | void (*tlb_flush)(struct drm_device *, int engine); |
322 | }; | |
323 | ||
6ee73861 BS |
324 | struct nouveau_instmem_engine { |
325 | void *priv; | |
326 | ||
327 | int (*init)(struct drm_device *dev); | |
328 | void (*takedown)(struct drm_device *dev); | |
329 | int (*suspend)(struct drm_device *dev); | |
330 | void (*resume)(struct drm_device *dev); | |
331 | ||
6e32fedc BS |
332 | int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, |
333 | u32 size, u32 align); | |
e41115d0 BS |
334 | void (*put)(struct nouveau_gpuobj *); |
335 | int (*map)(struct nouveau_gpuobj *); | |
336 | void (*unmap)(struct nouveau_gpuobj *); | |
337 | ||
f56cb86f | 338 | void (*flush)(struct drm_device *); |
6ee73861 BS |
339 | }; |
340 | ||
341 | struct nouveau_mc_engine { | |
342 | int (*init)(struct drm_device *dev); | |
343 | void (*takedown)(struct drm_device *dev); | |
344 | }; | |
345 | ||
346 | struct nouveau_timer_engine { | |
347 | int (*init)(struct drm_device *dev); | |
348 | void (*takedown)(struct drm_device *dev); | |
349 | uint64_t (*read)(struct drm_device *dev); | |
350 | }; | |
351 | ||
352 | struct nouveau_fb_engine { | |
cb00f7c1 | 353 | int num_tiles; |
87a326a3 | 354 | struct drm_mm tag_heap; |
20f63afe | 355 | void *priv; |
cb00f7c1 | 356 | |
6ee73861 BS |
357 | int (*init)(struct drm_device *dev); |
358 | void (*takedown)(struct drm_device *dev); | |
cb00f7c1 | 359 | |
a5cf68b0 FJ |
360 | void (*init_tile_region)(struct drm_device *dev, int i, |
361 | uint32_t addr, uint32_t size, | |
362 | uint32_t pitch, uint32_t flags); | |
363 | void (*set_tile_region)(struct drm_device *dev, int i); | |
364 | void (*free_tile_region)(struct drm_device *dev, int i); | |
6ee73861 BS |
365 | }; |
366 | ||
367 | struct nouveau_fifo_engine { | |
b2b09938 | 368 | void *priv; |
6ee73861 BS |
369 | int channels; |
370 | ||
a8eaebc6 | 371 | struct nouveau_gpuobj *playlist[2]; |
ac94a343 BS |
372 | int cur_playlist; |
373 | ||
6ee73861 BS |
374 | int (*init)(struct drm_device *); |
375 | void (*takedown)(struct drm_device *); | |
376 | ||
377 | void (*disable)(struct drm_device *); | |
378 | void (*enable)(struct drm_device *); | |
379 | bool (*reassign)(struct drm_device *, bool enable); | |
588d7d12 | 380 | bool (*cache_pull)(struct drm_device *dev, bool enable); |
6ee73861 BS |
381 | |
382 | int (*channel_id)(struct drm_device *); | |
383 | ||
384 | int (*create_context)(struct nouveau_channel *); | |
385 | void (*destroy_context)(struct nouveau_channel *); | |
386 | int (*load_context)(struct nouveau_channel *); | |
387 | int (*unload_context)(struct drm_device *); | |
56ac7475 | 388 | void (*tlb_flush)(struct drm_device *dev); |
6ee73861 BS |
389 | }; |
390 | ||
c88c2e06 | 391 | struct nouveau_display_engine { |
ef8389a8 | 392 | void *priv; |
c88c2e06 FJ |
393 | int (*early_init)(struct drm_device *); |
394 | void (*late_takedown)(struct drm_device *); | |
395 | int (*create)(struct drm_device *); | |
396 | int (*init)(struct drm_device *); | |
397 | void (*destroy)(struct drm_device *); | |
398 | }; | |
399 | ||
ee2e0131 | 400 | struct nouveau_gpio_engine { |
fce2bad0 BS |
401 | void *priv; |
402 | ||
ee2e0131 BS |
403 | int (*init)(struct drm_device *); |
404 | void (*takedown)(struct drm_device *); | |
405 | ||
406 | int (*get)(struct drm_device *, enum dcb_gpio_tag); | |
407 | int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); | |
408 | ||
fce2bad0 BS |
409 | int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, |
410 | void (*)(void *, int), void *); | |
411 | void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, | |
412 | void (*)(void *, int), void *); | |
413 | bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); | |
ee2e0131 BS |
414 | }; |
415 | ||
330c5988 | 416 | struct nouveau_pm_voltage_level { |
c3450239 BS |
417 | u32 voltage; /* microvolts */ |
418 | u8 vid; | |
330c5988 BS |
419 | }; |
420 | ||
421 | struct nouveau_pm_voltage { | |
422 | bool supported; | |
03ce8d9e | 423 | u8 version; |
330c5988 BS |
424 | u8 vid_mask; |
425 | ||
426 | struct nouveau_pm_voltage_level *level; | |
427 | int nr_level; | |
428 | }; | |
429 | ||
e614b2e7 MP |
430 | struct nouveau_pm_memtiming { |
431 | int id; | |
432 | u32 reg_100220; | |
433 | u32 reg_100224; | |
434 | u32 reg_100228; | |
435 | u32 reg_10022c; | |
436 | u32 reg_100230; | |
437 | u32 reg_100234; | |
438 | u32 reg_100238; | |
439 | u32 reg_10023c; | |
440 | u32 reg_100240; | |
441 | }; | |
442 | ||
330c5988 BS |
443 | #define NOUVEAU_PM_MAX_LEVEL 8 |
444 | struct nouveau_pm_level { | |
445 | struct device_attribute dev_attr; | |
446 | char name[32]; | |
447 | int id; | |
448 | ||
449 | u32 core; | |
450 | u32 memory; | |
451 | u32 shader; | |
9698b9a6 BS |
452 | u32 rop; |
453 | u32 copy; | |
454 | u32 daemon; | |
4fd2847e | 455 | u32 vdec; |
9698b9a6 BS |
456 | u32 unk05; /* nv50:nva3, roughly.. */ |
457 | u32 unka0; /* nva3:nvc0 */ | |
458 | u32 hub01; /* nvc0- */ | |
459 | u32 hub06; /* nvc0- */ | |
460 | u32 hub07; /* nvc0- */ | |
330c5988 | 461 | |
3b5565dd BS |
462 | u32 volt_min; /* microvolts */ |
463 | u32 volt_max; | |
c3450239 | 464 | u8 fanspeed; |
aee582de BS |
465 | |
466 | u16 memscript; | |
e614b2e7 | 467 | struct nouveau_pm_memtiming *timing; |
330c5988 BS |
468 | }; |
469 | ||
34e9d85a MP |
470 | struct nouveau_pm_temp_sensor_constants { |
471 | u16 offset_constant; | |
472 | s16 offset_mult; | |
40ce4279 EV |
473 | s16 offset_div; |
474 | s16 slope_mult; | |
475 | s16 slope_div; | |
34e9d85a MP |
476 | }; |
477 | ||
478 | struct nouveau_pm_threshold_temp { | |
479 | s16 critical; | |
480 | s16 down_clock; | |
481 | s16 fan_boost; | |
482 | }; | |
483 | ||
7760fcb0 RS |
484 | struct nouveau_pm_memtimings { |
485 | bool supported; | |
486 | struct nouveau_pm_memtiming *timing; | |
487 | int nr_timing; | |
488 | }; | |
489 | ||
330c5988 BS |
490 | struct nouveau_pm_engine { |
491 | struct nouveau_pm_voltage voltage; | |
492 | struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; | |
493 | int nr_perflvl; | |
7760fcb0 | 494 | struct nouveau_pm_memtimings memtimings; |
34e9d85a MP |
495 | struct nouveau_pm_temp_sensor_constants sensor_constants; |
496 | struct nouveau_pm_threshold_temp threshold_temp; | |
330c5988 BS |
497 | |
498 | struct nouveau_pm_level boot; | |
499 | struct nouveau_pm_level *cur; | |
500 | ||
8155cac4 | 501 | struct device *hwmon; |
6032649d | 502 | struct notifier_block acpi_nb; |
8155cac4 | 503 | |
330c5988 | 504 | int (*clock_get)(struct drm_device *, u32 id); |
5c6dc657 BS |
505 | void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, |
506 | u32 id, int khz); | |
330c5988 | 507 | void (*clock_set)(struct drm_device *, void *); |
77e7da68 BS |
508 | |
509 | int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); | |
510 | void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); | |
511 | void (*clocks_set)(struct drm_device *, void *); | |
512 | ||
330c5988 BS |
513 | int (*voltage_get)(struct drm_device *); |
514 | int (*voltage_set)(struct drm_device *, int voltage); | |
515 | int (*fanspeed_get)(struct drm_device *); | |
516 | int (*fanspeed_set)(struct drm_device *, int fanspeed); | |
8155cac4 | 517 | int (*temp_get)(struct drm_device *); |
330c5988 BS |
518 | }; |
519 | ||
60d2a88a | 520 | struct nouveau_vram_engine { |
24f246ac BS |
521 | struct nouveau_mm *mm; |
522 | ||
60d2a88a | 523 | int (*init)(struct drm_device *); |
24f246ac | 524 | void (*takedown)(struct drm_device *dev); |
60d2a88a | 525 | int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, |
d5f42394 BS |
526 | u32 type, struct nouveau_mem **); |
527 | void (*put)(struct drm_device *, struct nouveau_mem **); | |
60d2a88a BS |
528 | |
529 | bool (*flags_valid)(struct drm_device *, u32 tile_flags); | |
530 | }; | |
531 | ||
6ee73861 BS |
532 | struct nouveau_engine { |
533 | struct nouveau_instmem_engine instmem; | |
534 | struct nouveau_mc_engine mc; | |
535 | struct nouveau_timer_engine timer; | |
536 | struct nouveau_fb_engine fb; | |
6ee73861 | 537 | struct nouveau_fifo_engine fifo; |
c88c2e06 | 538 | struct nouveau_display_engine display; |
ee2e0131 | 539 | struct nouveau_gpio_engine gpio; |
330c5988 | 540 | struct nouveau_pm_engine pm; |
60d2a88a | 541 | struct nouveau_vram_engine vram; |
6ee73861 BS |
542 | }; |
543 | ||
544 | struct nouveau_pll_vals { | |
545 | union { | |
546 | struct { | |
547 | #ifdef __BIG_ENDIAN | |
548 | uint8_t N1, M1, N2, M2; | |
549 | #else | |
550 | uint8_t M1, N1, M2, N2; | |
551 | #endif | |
552 | }; | |
553 | struct { | |
554 | uint16_t NM1, NM2; | |
555 | } __attribute__((packed)); | |
556 | }; | |
557 | int log2P; | |
558 | ||
559 | int refclk; | |
560 | }; | |
561 | ||
562 | enum nv04_fp_display_regs { | |
563 | FP_DISPLAY_END, | |
564 | FP_TOTAL, | |
565 | FP_CRTC, | |
566 | FP_SYNC_START, | |
567 | FP_SYNC_END, | |
568 | FP_VALID_START, | |
569 | FP_VALID_END | |
570 | }; | |
571 | ||
572 | struct nv04_crtc_reg { | |
cbab95db | 573 | unsigned char MiscOutReg; |
4a9f822f | 574 | uint8_t CRTC[0xa0]; |
6ee73861 BS |
575 | uint8_t CR58[0x10]; |
576 | uint8_t Sequencer[5]; | |
577 | uint8_t Graphics[9]; | |
578 | uint8_t Attribute[21]; | |
cbab95db | 579 | unsigned char DAC[768]; |
6ee73861 BS |
580 | |
581 | /* PCRTC regs */ | |
582 | uint32_t fb_start; | |
583 | uint32_t crtc_cfg; | |
584 | uint32_t cursor_cfg; | |
585 | uint32_t gpio_ext; | |
586 | uint32_t crtc_830; | |
587 | uint32_t crtc_834; | |
588 | uint32_t crtc_850; | |
589 | uint32_t crtc_eng_ctrl; | |
590 | ||
591 | /* PRAMDAC regs */ | |
592 | uint32_t nv10_cursync; | |
593 | struct nouveau_pll_vals pllvals; | |
594 | uint32_t ramdac_gen_ctrl; | |
595 | uint32_t ramdac_630; | |
596 | uint32_t ramdac_634; | |
597 | uint32_t tv_setup; | |
598 | uint32_t tv_vtotal; | |
599 | uint32_t tv_vskew; | |
600 | uint32_t tv_vsync_delay; | |
601 | uint32_t tv_htotal; | |
602 | uint32_t tv_hskew; | |
603 | uint32_t tv_hsync_delay; | |
604 | uint32_t tv_hsync_delay2; | |
605 | uint32_t fp_horiz_regs[7]; | |
606 | uint32_t fp_vert_regs[7]; | |
607 | uint32_t dither; | |
608 | uint32_t fp_control; | |
609 | uint32_t dither_regs[6]; | |
610 | uint32_t fp_debug_0; | |
611 | uint32_t fp_debug_1; | |
612 | uint32_t fp_debug_2; | |
613 | uint32_t fp_margin_color; | |
614 | uint32_t ramdac_8c0; | |
615 | uint32_t ramdac_a20; | |
616 | uint32_t ramdac_a24; | |
617 | uint32_t ramdac_a34; | |
618 | uint32_t ctv_regs[38]; | |
619 | }; | |
620 | ||
621 | struct nv04_output_reg { | |
622 | uint32_t output; | |
623 | int head; | |
624 | }; | |
625 | ||
626 | struct nv04_mode_state { | |
cbab95db | 627 | struct nv04_crtc_reg crtc_reg[2]; |
6ee73861 BS |
628 | uint32_t pllsel; |
629 | uint32_t sel_clk; | |
6ee73861 BS |
630 | }; |
631 | ||
632 | enum nouveau_card_type { | |
633 | NV_04 = 0x00, | |
634 | NV_10 = 0x10, | |
635 | NV_20 = 0x20, | |
636 | NV_30 = 0x30, | |
637 | NV_40 = 0x40, | |
638 | NV_50 = 0x50, | |
4b223eef | 639 | NV_C0 = 0xc0, |
6ee73861 BS |
640 | }; |
641 | ||
642 | struct drm_nouveau_private { | |
643 | struct drm_device *dev; | |
aba99a84 | 644 | bool noaccel; |
6ee73861 BS |
645 | |
646 | /* the card type, takes NV_* as values */ | |
647 | enum nouveau_card_type card_type; | |
648 | /* exact chipset, derived from NV_PMC_BOOT_0 */ | |
649 | int chipset; | |
50066f81 | 650 | int stepping; |
6ee73861 BS |
651 | int flags; |
652 | ||
653 | void __iomem *mmio; | |
5125bfd8 | 654 | |
e05d7eae | 655 | spinlock_t ramin_lock; |
6ee73861 | 656 | void __iomem *ramin; |
5125bfd8 BS |
657 | u32 ramin_size; |
658 | u32 ramin_base; | |
659 | bool ramin_available; | |
e05d7eae | 660 | struct drm_mm ramin_heap; |
6dfdd7a6 | 661 | struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; |
e05d7eae | 662 | struct list_head gpuobj_list; |
b8c157d3 | 663 | struct list_head classes; |
6ee73861 | 664 | |
ac8fb975 BS |
665 | struct nouveau_bo *vga_ram; |
666 | ||
35fa2f2a | 667 | /* interrupt handling */ |
8f8a5448 | 668 | void (*irq_handler[32])(struct drm_device *); |
35fa2f2a | 669 | bool msi_enabled; |
ab838338 | 670 | |
6ee73861 BS |
671 | struct list_head vbl_waiting; |
672 | ||
673 | struct { | |
ba4420c2 | 674 | struct drm_global_reference mem_global_ref; |
6ee73861 BS |
675 | struct ttm_bo_global_ref bo_global_ref; |
676 | struct ttm_bo_device bdev; | |
6ee73861 BS |
677 | atomic_t validate_sequence; |
678 | } ttm; | |
679 | ||
0c6c1c2f FJ |
680 | struct { |
681 | spinlock_t lock; | |
682 | struct drm_mm heap; | |
683 | struct nouveau_bo *bo; | |
684 | } fence; | |
685 | ||
cff5c133 BS |
686 | struct { |
687 | spinlock_t lock; | |
688 | struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; | |
689 | } channels; | |
6ee73861 BS |
690 | |
691 | struct nouveau_engine engine; | |
692 | struct nouveau_channel *channel; | |
693 | ||
ff9e5279 MM |
694 | /* For PFIFO and PGRAPH. */ |
695 | spinlock_t context_switch_lock; | |
696 | ||
04eb34a4 BS |
697 | /* VM/PRAMIN flush, legacy PRAMIN aperture */ |
698 | spinlock_t vm_lock; | |
699 | ||
6ee73861 | 700 | /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ |
e05c5a31 BS |
701 | struct nouveau_ramht *ramht; |
702 | struct nouveau_gpuobj *ramfc; | |
703 | struct nouveau_gpuobj *ramro; | |
704 | ||
6ee73861 | 705 | uint32_t ramin_rsvd_vram; |
6ee73861 | 706 | |
6ee73861 BS |
707 | struct { |
708 | enum { | |
709 | NOUVEAU_GART_NONE = 0, | |
58e6c7a9 BS |
710 | NOUVEAU_GART_AGP, /* AGP */ |
711 | NOUVEAU_GART_PDMA, /* paged dma object */ | |
712 | NOUVEAU_GART_HW /* on-chip gart/vm */ | |
6ee73861 BS |
713 | } type; |
714 | uint64_t aper_base; | |
715 | uint64_t aper_size; | |
716 | uint64_t aper_free; | |
717 | ||
7948758d BS |
718 | struct ttm_backend_func *func; |
719 | ||
720 | struct { | |
721 | struct page *page; | |
722 | dma_addr_t addr; | |
723 | } dummy; | |
724 | ||
6ee73861 | 725 | struct nouveau_gpuobj *sg_ctxdma; |
6ee73861 BS |
726 | } gart_info; |
727 | ||
a0af9add | 728 | /* nv10-nv40 tiling regions */ |
a5cf68b0 FJ |
729 | struct { |
730 | struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; | |
731 | spinlock_t lock; | |
732 | } tile; | |
a0af9add | 733 | |
a76fb4e8 BS |
734 | /* VRAM/fb configuration */ |
735 | uint64_t vram_size; | |
736 | uint64_t vram_sys_base; | |
737 | ||
738 | uint64_t fb_phys; | |
739 | uint64_t fb_available_size; | |
740 | uint64_t fb_mappable_pages; | |
741 | uint64_t fb_aper_free; | |
742 | int fb_mtrr; | |
743 | ||
f869ef88 BS |
744 | /* BAR control (NV50-) */ |
745 | struct nouveau_vm *bar1_vm; | |
746 | struct nouveau_vm *bar3_vm; | |
747 | ||
6ee73861 | 748 | /* G8x/G9x virtual address space */ |
4c136142 | 749 | struct nouveau_vm *chan_vm; |
6ee73861 | 750 | |
04a39c57 | 751 | struct nvbios vbios; |
6ee73861 BS |
752 | |
753 | struct nv04_mode_state mode_reg; | |
754 | struct nv04_mode_state saved_reg; | |
755 | uint32_t saved_vga_font[4][16384]; | |
756 | uint32_t crtc_owner; | |
757 | uint32_t dac_users[4]; | |
758 | ||
6ee73861 | 759 | struct backlight_device *backlight; |
6ee73861 | 760 | |
6ee73861 BS |
761 | struct { |
762 | struct dentry *channel_root; | |
763 | } debugfs; | |
38651674 | 764 | |
8be48d92 | 765 | struct nouveau_fbdev *nfbdev; |
06415c56 | 766 | struct apertures_struct *apertures; |
6ee73861 BS |
767 | }; |
768 | ||
2730723b FJ |
769 | static inline struct drm_nouveau_private * |
770 | nouveau_private(struct drm_device *dev) | |
771 | { | |
772 | return dev->dev_private; | |
773 | } | |
774 | ||
6ee73861 BS |
775 | static inline struct drm_nouveau_private * |
776 | nouveau_bdev(struct ttm_bo_device *bd) | |
777 | { | |
778 | return container_of(bd, struct drm_nouveau_private, ttm.bdev); | |
779 | } | |
780 | ||
781 | static inline int | |
782 | nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) | |
783 | { | |
784 | struct nouveau_bo *prev; | |
785 | ||
786 | if (!pnvbo) | |
787 | return -EINVAL; | |
788 | prev = *pnvbo; | |
789 | ||
790 | *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; | |
791 | if (prev) { | |
792 | struct ttm_buffer_object *bo = &prev->bo; | |
793 | ||
794 | ttm_bo_unref(&bo); | |
795 | } | |
796 | ||
797 | return 0; | |
798 | } | |
799 | ||
6ee73861 | 800 | /* nouveau_drv.c */ |
de5899bd | 801 | extern int nouveau_agpmode; |
6ee73861 BS |
802 | extern int nouveau_duallink; |
803 | extern int nouveau_uscript_lvds; | |
804 | extern int nouveau_uscript_tmds; | |
805 | extern int nouveau_vram_pushbuf; | |
806 | extern int nouveau_vram_notify; | |
807 | extern int nouveau_fbpercrtc; | |
f4053509 | 808 | extern int nouveau_tv_disable; |
6ee73861 BS |
809 | extern char *nouveau_tv_norm; |
810 | extern int nouveau_reg_debug; | |
811 | extern char *nouveau_vbios; | |
a1470890 | 812 | extern int nouveau_ignorelid; |
a32ed69d MK |
813 | extern int nouveau_nofbaccel; |
814 | extern int nouveau_noaccel; | |
0cba1b76 | 815 | extern int nouveau_force_post; |
da647d5b | 816 | extern int nouveau_override_conntype; |
6f876986 BS |
817 | extern char *nouveau_perflvl; |
818 | extern int nouveau_perflvl_wr; | |
35fa2f2a | 819 | extern int nouveau_msi; |
0411de85 | 820 | extern int nouveau_ctxfw; |
6ee73861 | 821 | |
6a9ee8af DA |
822 | extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); |
823 | extern int nouveau_pci_resume(struct pci_dev *pdev); | |
824 | ||
6ee73861 | 825 | /* nouveau_state.c */ |
3f0a68d8 | 826 | extern int nouveau_open(struct drm_device *, struct drm_file *); |
6ee73861 | 827 | extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); |
3f0a68d8 | 828 | extern void nouveau_postclose(struct drm_device *, struct drm_file *); |
6ee73861 BS |
829 | extern int nouveau_load(struct drm_device *, unsigned long flags); |
830 | extern int nouveau_firstopen(struct drm_device *); | |
831 | extern void nouveau_lastclose(struct drm_device *); | |
832 | extern int nouveau_unload(struct drm_device *); | |
833 | extern int nouveau_ioctl_getparam(struct drm_device *, void *data, | |
834 | struct drm_file *); | |
835 | extern int nouveau_ioctl_setparam(struct drm_device *, void *data, | |
836 | struct drm_file *); | |
12fb9525 BS |
837 | extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, |
838 | uint32_t reg, uint32_t mask, uint32_t val); | |
839 | extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, | |
840 | uint32_t reg, uint32_t mask, uint32_t val); | |
78e2933d BS |
841 | extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, |
842 | bool (*cond)(void *), void *); | |
6ee73861 BS |
843 | extern bool nouveau_wait_for_idle(struct drm_device *); |
844 | extern int nouveau_card_init(struct drm_device *); | |
6ee73861 BS |
845 | |
846 | /* nouveau_mem.c */ | |
fbd2895e BS |
847 | extern int nouveau_mem_vram_init(struct drm_device *); |
848 | extern void nouveau_mem_vram_fini(struct drm_device *); | |
849 | extern int nouveau_mem_gart_init(struct drm_device *); | |
850 | extern void nouveau_mem_gart_fini(struct drm_device *); | |
6ee73861 | 851 | extern int nouveau_mem_init_agp(struct drm_device *); |
e04d8e82 | 852 | extern int nouveau_mem_reset_agp(struct drm_device *); |
6ee73861 | 853 | extern void nouveau_mem_close(struct drm_device *); |
60d2a88a BS |
854 | extern int nouveau_mem_detect(struct drm_device *); |
855 | extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); | |
a5cf68b0 FJ |
856 | extern struct nouveau_tile_reg *nv10_mem_set_tiling( |
857 | struct drm_device *dev, uint32_t addr, uint32_t size, | |
858 | uint32_t pitch, uint32_t flags); | |
859 | extern void nv10_mem_put_tile_region(struct drm_device *dev, | |
860 | struct nouveau_tile_reg *tile, | |
861 | struct nouveau_fence *fence); | |
573a2a37 | 862 | extern const struct ttm_mem_type_manager_func nouveau_vram_manager; |
26c0c9e3 | 863 | extern const struct ttm_mem_type_manager_func nouveau_gart_manager; |
6ee73861 BS |
864 | |
865 | /* nouveau_notifier.c */ | |
866 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); | |
867 | extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); | |
868 | extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, | |
73412c38 BS |
869 | int cout, uint32_t start, uint32_t end, |
870 | uint32_t *offset); | |
6ee73861 BS |
871 | extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); |
872 | extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, | |
873 | struct drm_file *); | |
874 | extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, | |
875 | struct drm_file *); | |
876 | ||
877 | /* nouveau_channel.c */ | |
878 | extern struct drm_ioctl_desc nouveau_ioctls[]; | |
879 | extern int nouveau_max_ioctl; | |
880 | extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); | |
6ee73861 BS |
881 | extern int nouveau_channel_alloc(struct drm_device *dev, |
882 | struct nouveau_channel **chan, | |
883 | struct drm_file *file_priv, | |
884 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); | |
cff5c133 | 885 | extern struct nouveau_channel * |
feeb0aec FJ |
886 | nouveau_channel_get_unlocked(struct nouveau_channel *); |
887 | extern struct nouveau_channel * | |
e8a863c1 | 888 | nouveau_channel_get(struct drm_file *, int id); |
feeb0aec | 889 | extern void nouveau_channel_put_unlocked(struct nouveau_channel **); |
cff5c133 | 890 | extern void nouveau_channel_put(struct nouveau_channel **); |
f091a3d4 FJ |
891 | extern void nouveau_channel_ref(struct nouveau_channel *chan, |
892 | struct nouveau_channel **pchan); | |
6dccd311 | 893 | extern void nouveau_channel_idle(struct nouveau_channel *chan); |
6ee73861 BS |
894 | |
895 | /* nouveau_object.c */ | |
6dfdd7a6 BS |
896 | #define NVOBJ_ENGINE_ADD(d, e, p) do { \ |
897 | struct drm_nouveau_private *dev_priv = (d)->dev_private; \ | |
898 | dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ | |
899 | } while (0) | |
900 | ||
901 | #define NVOBJ_ENGINE_DEL(d, e) do { \ | |
902 | struct drm_nouveau_private *dev_priv = (d)->dev_private; \ | |
903 | dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ | |
904 | } while (0) | |
905 | ||
0b89a072 | 906 | #define NVOBJ_CLASS(d, c, e) do { \ |
b8c157d3 BS |
907 | int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ |
908 | if (ret) \ | |
909 | return ret; \ | |
71298e2f | 910 | } while (0) |
b8c157d3 | 911 | |
0b89a072 | 912 | #define NVOBJ_MTHD(d, c, m, e) do { \ |
b8c157d3 BS |
913 | int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ |
914 | if (ret) \ | |
915 | return ret; \ | |
71298e2f | 916 | } while (0) |
b8c157d3 | 917 | |
6ee73861 BS |
918 | extern int nouveau_gpuobj_early_init(struct drm_device *); |
919 | extern int nouveau_gpuobj_init(struct drm_device *); | |
920 | extern void nouveau_gpuobj_takedown(struct drm_device *); | |
6ee73861 | 921 | extern int nouveau_gpuobj_suspend(struct drm_device *dev); |
6ee73861 | 922 | extern void nouveau_gpuobj_resume(struct drm_device *dev); |
b8c157d3 BS |
923 | extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); |
924 | extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, | |
925 | int (*exec)(struct nouveau_channel *, | |
71298e2f | 926 | u32 class, u32 mthd, u32 data)); |
b8c157d3 | 927 | extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); |
274fec93 | 928 | extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); |
6ee73861 BS |
929 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, |
930 | uint32_t vram_h, uint32_t tt_h); | |
931 | extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); | |
932 | extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, | |
933 | uint32_t size, int align, uint32_t flags, | |
934 | struct nouveau_gpuobj **); | |
a8eaebc6 BS |
935 | extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, |
936 | struct nouveau_gpuobj **); | |
43efc9ce BS |
937 | extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, |
938 | u32 size, u32 flags, | |
a8eaebc6 | 939 | struct nouveau_gpuobj **); |
6ee73861 BS |
940 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, |
941 | uint64_t offset, uint64_t size, int access, | |
942 | int target, struct nouveau_gpuobj **); | |
ceac3099 | 943 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); |
7f4a195f BS |
944 | extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, |
945 | u64 size, int target, int access, u32 type, | |
946 | u32 comp, struct nouveau_gpuobj **pobj); | |
947 | extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, | |
948 | int class, u64 base, u64 size, int target, | |
949 | int access, u32 type, u32 comp); | |
6ee73861 BS |
950 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, |
951 | struct drm_file *); | |
952 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, | |
953 | struct drm_file *); | |
954 | ||
955 | /* nouveau_irq.c */ | |
35fa2f2a BS |
956 | extern int nouveau_irq_init(struct drm_device *); |
957 | extern void nouveau_irq_fini(struct drm_device *); | |
6ee73861 | 958 | extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); |
8f8a5448 BS |
959 | extern void nouveau_irq_register(struct drm_device *, int status_bit, |
960 | void (*)(struct drm_device *)); | |
961 | extern void nouveau_irq_unregister(struct drm_device *, int status_bit); | |
6ee73861 BS |
962 | extern void nouveau_irq_preinstall(struct drm_device *); |
963 | extern int nouveau_irq_postinstall(struct drm_device *); | |
964 | extern void nouveau_irq_uninstall(struct drm_device *); | |
965 | ||
966 | /* nouveau_sgdma.c */ | |
967 | extern int nouveau_sgdma_init(struct drm_device *); | |
968 | extern void nouveau_sgdma_takedown(struct drm_device *); | |
fd70b6cd FJ |
969 | extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, |
970 | uint32_t offset); | |
6ee73861 BS |
971 | extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); |
972 | ||
973 | /* nouveau_debugfs.c */ | |
974 | #if defined(CONFIG_DRM_NOUVEAU_DEBUG) | |
975 | extern int nouveau_debugfs_init(struct drm_minor *); | |
976 | extern void nouveau_debugfs_takedown(struct drm_minor *); | |
977 | extern int nouveau_debugfs_channel_init(struct nouveau_channel *); | |
978 | extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); | |
979 | #else | |
980 | static inline int | |
981 | nouveau_debugfs_init(struct drm_minor *minor) | |
982 | { | |
983 | return 0; | |
984 | } | |
985 | ||
986 | static inline void nouveau_debugfs_takedown(struct drm_minor *minor) | |
987 | { | |
988 | } | |
989 | ||
990 | static inline int | |
991 | nouveau_debugfs_channel_init(struct nouveau_channel *chan) | |
992 | { | |
993 | return 0; | |
994 | } | |
995 | ||
996 | static inline void | |
997 | nouveau_debugfs_channel_fini(struct nouveau_channel *chan) | |
998 | { | |
999 | } | |
1000 | #endif | |
1001 | ||
1002 | /* nouveau_dma.c */ | |
75c99da6 | 1003 | extern void nouveau_dma_pre_init(struct nouveau_channel *); |
6ee73861 | 1004 | extern int nouveau_dma_init(struct nouveau_channel *); |
9a391ad8 | 1005 | extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); |
6ee73861 BS |
1006 | |
1007 | /* nouveau_acpi.c */ | |
afeb3e11 | 1008 | #define ROM_BIOS_PAGE 4096 |
2f41a7f1 | 1009 | #if defined(CONFIG_ACPI) |
6a9ee8af DA |
1010 | void nouveau_register_dsm_handler(void); |
1011 | void nouveau_unregister_dsm_handler(void); | |
afeb3e11 DA |
1012 | int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); |
1013 | bool nouveau_acpi_rom_supported(struct pci_dev *pdev); | |
a6ed76d7 | 1014 | int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); |
8edb381d DA |
1015 | #else |
1016 | static inline void nouveau_register_dsm_handler(void) {} | |
1017 | static inline void nouveau_unregister_dsm_handler(void) {} | |
afeb3e11 DA |
1018 | static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } |
1019 | static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } | |
5620ba46 | 1020 | static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } |
8edb381d | 1021 | #endif |
6ee73861 BS |
1022 | |
1023 | /* nouveau_backlight.c */ | |
1024 | #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT | |
7eae3efa MG |
1025 | extern int nouveau_backlight_init(struct drm_connector *); |
1026 | extern void nouveau_backlight_exit(struct drm_connector *); | |
6ee73861 | 1027 | #else |
7eae3efa | 1028 | static inline int nouveau_backlight_init(struct drm_connector *dev) |
6ee73861 BS |
1029 | { |
1030 | return 0; | |
1031 | } | |
1032 | ||
7eae3efa | 1033 | static inline void nouveau_backlight_exit(struct drm_connector *dev) { } |
6ee73861 BS |
1034 | #endif |
1035 | ||
1036 | /* nouveau_bios.c */ | |
1037 | extern int nouveau_bios_init(struct drm_device *); | |
1038 | extern void nouveau_bios_takedown(struct drm_device *dev); | |
1039 | extern int nouveau_run_vbios_init(struct drm_device *); | |
1040 | extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, | |
1041 | struct dcb_entry *); | |
1042 | extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, | |
1043 | enum dcb_gpio_tag); | |
1044 | extern struct dcb_connector_table_entry * | |
1045 | nouveau_bios_connector_entry(struct drm_device *, int index); | |
855a95e4 | 1046 | extern u32 get_pll_register(struct drm_device *, enum pll_types); |
6ee73861 BS |
1047 | extern int get_pll_limits(struct drm_device *, uint32_t limit_match, |
1048 | struct pll_lims *); | |
1049 | extern int nouveau_bios_run_display_table(struct drm_device *, | |
1050 | struct dcb_entry *, | |
1051 | uint32_t script, int pxclk); | |
1052 | extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, | |
1053 | int *length); | |
1054 | extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); | |
1055 | extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); | |
1056 | extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, | |
1057 | bool *dl, bool *if_is_24bit); | |
1058 | extern int run_tmds_table(struct drm_device *, struct dcb_entry *, | |
1059 | int head, int pxclk); | |
1060 | extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, | |
1061 | enum LVDS_script, int pxclk); | |
1062 | ||
1063 | /* nouveau_ttm.c */ | |
1064 | int nouveau_ttm_global_init(struct drm_nouveau_private *); | |
1065 | void nouveau_ttm_global_release(struct drm_nouveau_private *); | |
1066 | int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); | |
1067 | ||
1068 | /* nouveau_dp.c */ | |
1069 | int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, | |
1070 | uint8_t *data, int data_nr); | |
1071 | bool nouveau_dp_detect(struct drm_encoder *); | |
1072 | bool nouveau_dp_link_train(struct drm_encoder *); | |
1073 | ||
1074 | /* nv04_fb.c */ | |
1075 | extern int nv04_fb_init(struct drm_device *); | |
1076 | extern void nv04_fb_takedown(struct drm_device *); | |
1077 | ||
1078 | /* nv10_fb.c */ | |
1079 | extern int nv10_fb_init(struct drm_device *); | |
1080 | extern void nv10_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1081 | extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, |
1082 | uint32_t addr, uint32_t size, | |
1083 | uint32_t pitch, uint32_t flags); | |
1084 | extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); | |
1085 | extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); | |
6ee73861 | 1086 | |
8bded189 FJ |
1087 | /* nv30_fb.c */ |
1088 | extern int nv30_fb_init(struct drm_device *); | |
1089 | extern void nv30_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1090 | extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, |
1091 | uint32_t addr, uint32_t size, | |
1092 | uint32_t pitch, uint32_t flags); | |
1093 | extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); | |
8bded189 | 1094 | |
6ee73861 BS |
1095 | /* nv40_fb.c */ |
1096 | extern int nv40_fb_init(struct drm_device *); | |
1097 | extern void nv40_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1098 | extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); |
1099 | ||
304424e1 MK |
1100 | /* nv50_fb.c */ |
1101 | extern int nv50_fb_init(struct drm_device *); | |
1102 | extern void nv50_fb_takedown(struct drm_device *); | |
6fdb383e | 1103 | extern void nv50_fb_vm_trap(struct drm_device *, int display); |
304424e1 | 1104 | |
4b223eef BS |
1105 | /* nvc0_fb.c */ |
1106 | extern int nvc0_fb_init(struct drm_device *); | |
1107 | extern void nvc0_fb_takedown(struct drm_device *); | |
1108 | ||
6ee73861 BS |
1109 | /* nv04_fifo.c */ |
1110 | extern int nv04_fifo_init(struct drm_device *); | |
5178d40d | 1111 | extern void nv04_fifo_fini(struct drm_device *); |
6ee73861 BS |
1112 | extern void nv04_fifo_disable(struct drm_device *); |
1113 | extern void nv04_fifo_enable(struct drm_device *); | |
1114 | extern bool nv04_fifo_reassign(struct drm_device *, bool); | |
588d7d12 | 1115 | extern bool nv04_fifo_cache_pull(struct drm_device *, bool); |
6ee73861 BS |
1116 | extern int nv04_fifo_channel_id(struct drm_device *); |
1117 | extern int nv04_fifo_create_context(struct nouveau_channel *); | |
1118 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); | |
1119 | extern int nv04_fifo_load_context(struct nouveau_channel *); | |
1120 | extern int nv04_fifo_unload_context(struct drm_device *); | |
5178d40d | 1121 | extern void nv04_fifo_isr(struct drm_device *); |
6ee73861 BS |
1122 | |
1123 | /* nv10_fifo.c */ | |
1124 | extern int nv10_fifo_init(struct drm_device *); | |
1125 | extern int nv10_fifo_channel_id(struct drm_device *); | |
1126 | extern int nv10_fifo_create_context(struct nouveau_channel *); | |
6ee73861 BS |
1127 | extern int nv10_fifo_load_context(struct nouveau_channel *); |
1128 | extern int nv10_fifo_unload_context(struct drm_device *); | |
1129 | ||
1130 | /* nv40_fifo.c */ | |
1131 | extern int nv40_fifo_init(struct drm_device *); | |
1132 | extern int nv40_fifo_create_context(struct nouveau_channel *); | |
6ee73861 BS |
1133 | extern int nv40_fifo_load_context(struct nouveau_channel *); |
1134 | extern int nv40_fifo_unload_context(struct drm_device *); | |
1135 | ||
1136 | /* nv50_fifo.c */ | |
1137 | extern int nv50_fifo_init(struct drm_device *); | |
1138 | extern void nv50_fifo_takedown(struct drm_device *); | |
1139 | extern int nv50_fifo_channel_id(struct drm_device *); | |
1140 | extern int nv50_fifo_create_context(struct nouveau_channel *); | |
1141 | extern void nv50_fifo_destroy_context(struct nouveau_channel *); | |
1142 | extern int nv50_fifo_load_context(struct nouveau_channel *); | |
1143 | extern int nv50_fifo_unload_context(struct drm_device *); | |
56ac7475 | 1144 | extern void nv50_fifo_tlb_flush(struct drm_device *dev); |
6ee73861 | 1145 | |
4b223eef BS |
1146 | /* nvc0_fifo.c */ |
1147 | extern int nvc0_fifo_init(struct drm_device *); | |
1148 | extern void nvc0_fifo_takedown(struct drm_device *); | |
1149 | extern void nvc0_fifo_disable(struct drm_device *); | |
1150 | extern void nvc0_fifo_enable(struct drm_device *); | |
1151 | extern bool nvc0_fifo_reassign(struct drm_device *, bool); | |
4b223eef BS |
1152 | extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); |
1153 | extern int nvc0_fifo_channel_id(struct drm_device *); | |
1154 | extern int nvc0_fifo_create_context(struct nouveau_channel *); | |
1155 | extern void nvc0_fifo_destroy_context(struct nouveau_channel *); | |
1156 | extern int nvc0_fifo_load_context(struct nouveau_channel *); | |
1157 | extern int nvc0_fifo_unload_context(struct drm_device *); | |
1158 | ||
6ee73861 | 1159 | /* nv04_graph.c */ |
4976986b | 1160 | extern int nv04_graph_create(struct drm_device *); |
4976986b | 1161 | extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); |
332b242f FJ |
1162 | extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, |
1163 | u32 class, u32 mthd, u32 data); | |
274fec93 | 1164 | extern struct nouveau_bitfield nv04_graph_nsource[]; |
6ee73861 BS |
1165 | |
1166 | /* nv10_graph.c */ | |
d11db279 | 1167 | extern int nv10_graph_create(struct drm_device *); |
6ee73861 | 1168 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); |
274fec93 BS |
1169 | extern struct nouveau_bitfield nv10_graph_intr[]; |
1170 | extern struct nouveau_bitfield nv10_graph_nstatus[]; | |
6ee73861 BS |
1171 | |
1172 | /* nv20_graph.c */ | |
a0b1de84 | 1173 | extern int nv20_graph_create(struct drm_device *); |
6ee73861 BS |
1174 | |
1175 | /* nv40_graph.c */ | |
39c8d368 | 1176 | extern int nv40_graph_create(struct drm_device *); |
054b93e4 | 1177 | extern void nv40_grctx_init(struct nouveau_grctx *); |
6ee73861 BS |
1178 | |
1179 | /* nv50_graph.c */ | |
2703c21a | 1180 | extern int nv50_graph_create(struct drm_device *); |
d5f3c90d | 1181 | extern int nv50_grctx_init(struct nouveau_grctx *); |
6effe393 | 1182 | extern struct nouveau_enum nv50_data_error_names[]; |
7ff5441e | 1183 | extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); |
6ee73861 | 1184 | |
4b223eef | 1185 | /* nvc0_graph.c */ |
7a45cd19 | 1186 | extern int nvc0_graph_create(struct drm_device *); |
d5a27370 | 1187 | extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); |
4b223eef | 1188 | |
bd2e597d | 1189 | /* nv84_crypt.c */ |
6dfdd7a6 | 1190 | extern int nv84_crypt_create(struct drm_device *); |
bd2e597d | 1191 | |
7ff5441e BS |
1192 | /* nva3_copy.c */ |
1193 | extern int nva3_copy_create(struct drm_device *dev); | |
1194 | ||
1195 | /* nvc0_copy.c */ | |
1196 | extern int nvc0_copy_create(struct drm_device *dev, int engine); | |
1197 | ||
a02ccc7f BS |
1198 | /* nv40_mpeg.c */ |
1199 | extern int nv40_mpeg_create(struct drm_device *dev); | |
1200 | ||
93187450 BS |
1201 | /* nv50_mpeg.c */ |
1202 | extern int nv50_mpeg_create(struct drm_device *dev); | |
c0924326 | 1203 | |
6ee73861 BS |
1204 | /* nv04_instmem.c */ |
1205 | extern int nv04_instmem_init(struct drm_device *); | |
1206 | extern void nv04_instmem_takedown(struct drm_device *); | |
1207 | extern int nv04_instmem_suspend(struct drm_device *); | |
1208 | extern void nv04_instmem_resume(struct drm_device *); | |
6e32fedc BS |
1209 | extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, |
1210 | u32 size, u32 align); | |
e41115d0 BS |
1211 | extern void nv04_instmem_put(struct nouveau_gpuobj *); |
1212 | extern int nv04_instmem_map(struct nouveau_gpuobj *); | |
1213 | extern void nv04_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1214 | extern void nv04_instmem_flush(struct drm_device *); |
6ee73861 BS |
1215 | |
1216 | /* nv50_instmem.c */ | |
1217 | extern int nv50_instmem_init(struct drm_device *); | |
1218 | extern void nv50_instmem_takedown(struct drm_device *); | |
1219 | extern int nv50_instmem_suspend(struct drm_device *); | |
1220 | extern void nv50_instmem_resume(struct drm_device *); | |
6e32fedc BS |
1221 | extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, |
1222 | u32 size, u32 align); | |
e41115d0 BS |
1223 | extern void nv50_instmem_put(struct nouveau_gpuobj *); |
1224 | extern int nv50_instmem_map(struct nouveau_gpuobj *); | |
1225 | extern void nv50_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1226 | extern void nv50_instmem_flush(struct drm_device *); |
734ee835 | 1227 | extern void nv84_instmem_flush(struct drm_device *); |
6ee73861 | 1228 | |
4b223eef BS |
1229 | /* nvc0_instmem.c */ |
1230 | extern int nvc0_instmem_init(struct drm_device *); | |
1231 | extern void nvc0_instmem_takedown(struct drm_device *); | |
1232 | extern int nvc0_instmem_suspend(struct drm_device *); | |
1233 | extern void nvc0_instmem_resume(struct drm_device *); | |
4b223eef | 1234 | |
6ee73861 BS |
1235 | /* nv04_mc.c */ |
1236 | extern int nv04_mc_init(struct drm_device *); | |
1237 | extern void nv04_mc_takedown(struct drm_device *); | |
1238 | ||
1239 | /* nv40_mc.c */ | |
1240 | extern int nv40_mc_init(struct drm_device *); | |
1241 | extern void nv40_mc_takedown(struct drm_device *); | |
1242 | ||
1243 | /* nv50_mc.c */ | |
1244 | extern int nv50_mc_init(struct drm_device *); | |
1245 | extern void nv50_mc_takedown(struct drm_device *); | |
1246 | ||
1247 | /* nv04_timer.c */ | |
1248 | extern int nv04_timer_init(struct drm_device *); | |
1249 | extern uint64_t nv04_timer_read(struct drm_device *); | |
1250 | extern void nv04_timer_takedown(struct drm_device *); | |
1251 | ||
1252 | extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, | |
1253 | unsigned long arg); | |
1254 | ||
1255 | /* nv04_dac.c */ | |
8f1a6086 | 1256 | extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); |
11d6eb2a | 1257 | extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); |
6ee73861 BS |
1258 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); |
1259 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); | |
8ccfe9e0 | 1260 | extern bool nv04_dac_in_use(struct drm_encoder *encoder); |
6ee73861 BS |
1261 | |
1262 | /* nv04_dfp.c */ | |
8f1a6086 | 1263 | extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1264 | extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); |
1265 | extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, | |
1266 | int head, bool dl); | |
1267 | extern void nv04_dfp_disable(struct drm_device *dev, int head); | |
1268 | extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); | |
1269 | ||
1270 | /* nv04_tv.c */ | |
1271 | extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); | |
8f1a6086 | 1272 | extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1273 | |
1274 | /* nv17_tv.c */ | |
8f1a6086 | 1275 | extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1276 | |
1277 | /* nv04_display.c */ | |
c88c2e06 FJ |
1278 | extern int nv04_display_early_init(struct drm_device *); |
1279 | extern void nv04_display_late_takedown(struct drm_device *); | |
6ee73861 | 1280 | extern int nv04_display_create(struct drm_device *); |
c88c2e06 | 1281 | extern int nv04_display_init(struct drm_device *); |
6ee73861 | 1282 | extern void nv04_display_destroy(struct drm_device *); |
6ee73861 BS |
1283 | |
1284 | /* nv04_crtc.c */ | |
1285 | extern int nv04_crtc_create(struct drm_device *, int index); | |
1286 | ||
1287 | /* nouveau_bo.c */ | |
1288 | extern struct ttm_bo_driver nouveau_bo_driver; | |
7375c95b BS |
1289 | extern int nouveau_bo_new(struct drm_device *, int size, int align, |
1290 | uint32_t flags, uint32_t tile_mode, | |
1291 | uint32_t tile_flags, struct nouveau_bo **); | |
6ee73861 BS |
1292 | extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); |
1293 | extern int nouveau_bo_unpin(struct nouveau_bo *); | |
1294 | extern int nouveau_bo_map(struct nouveau_bo *); | |
1295 | extern void nouveau_bo_unmap(struct nouveau_bo *); | |
78ad0f7b FJ |
1296 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, |
1297 | uint32_t busy); | |
6ee73861 BS |
1298 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); |
1299 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); | |
1300 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); | |
1301 | extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); | |
332b242f | 1302 | extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); |
7a45d764 BS |
1303 | extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, |
1304 | bool no_wait_reserve, bool no_wait_gpu); | |
6ee73861 | 1305 | |
fd2871af BS |
1306 | extern struct nouveau_vma * |
1307 | nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); | |
1308 | extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, | |
1309 | struct nouveau_vma *); | |
1310 | extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); | |
1311 | ||
6ee73861 BS |
1312 | /* nouveau_fence.c */ |
1313 | struct nouveau_fence; | |
0c6c1c2f FJ |
1314 | extern int nouveau_fence_init(struct drm_device *); |
1315 | extern void nouveau_fence_fini(struct drm_device *); | |
2730723b FJ |
1316 | extern int nouveau_fence_channel_init(struct nouveau_channel *); |
1317 | extern void nouveau_fence_channel_fini(struct nouveau_channel *); | |
6ee73861 BS |
1318 | extern void nouveau_fence_update(struct nouveau_channel *); |
1319 | extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, | |
1320 | bool emit); | |
1321 | extern int nouveau_fence_emit(struct nouveau_fence *); | |
8ac3891b FJ |
1322 | extern void nouveau_fence_work(struct nouveau_fence *fence, |
1323 | void (*work)(void *priv, bool signalled), | |
1324 | void *priv); | |
6ee73861 | 1325 | struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); |
382d62e5 MS |
1326 | |
1327 | extern bool __nouveau_fence_signalled(void *obj, void *arg); | |
1328 | extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); | |
1329 | extern int __nouveau_fence_flush(void *obj, void *arg); | |
1330 | extern void __nouveau_fence_unref(void **obj); | |
1331 | extern void *__nouveau_fence_ref(void *obj); | |
1332 | ||
1333 | static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) | |
1334 | { | |
1335 | return __nouveau_fence_signalled(obj, NULL); | |
1336 | } | |
1337 | static inline int | |
1338 | nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) | |
1339 | { | |
1340 | return __nouveau_fence_wait(obj, NULL, lazy, intr); | |
1341 | } | |
2730723b | 1342 | extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); |
382d62e5 MS |
1343 | static inline int nouveau_fence_flush(struct nouveau_fence *obj) |
1344 | { | |
1345 | return __nouveau_fence_flush(obj, NULL); | |
1346 | } | |
1347 | static inline void nouveau_fence_unref(struct nouveau_fence **obj) | |
1348 | { | |
1349 | __nouveau_fence_unref((void **)obj); | |
1350 | } | |
1351 | static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) | |
1352 | { | |
1353 | return __nouveau_fence_ref(obj); | |
1354 | } | |
6ee73861 BS |
1355 | |
1356 | /* nouveau_gem.c */ | |
f6d4e621 BS |
1357 | extern int nouveau_gem_new(struct drm_device *, int size, int align, |
1358 | uint32_t domain, uint32_t tile_mode, | |
1359 | uint32_t tile_flags, struct nouveau_bo **); | |
6ee73861 BS |
1360 | extern int nouveau_gem_object_new(struct drm_gem_object *); |
1361 | extern void nouveau_gem_object_del(struct drm_gem_object *); | |
639212d0 BS |
1362 | extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); |
1363 | extern void nouveau_gem_object_close(struct drm_gem_object *, | |
1364 | struct drm_file *); | |
6ee73861 BS |
1365 | extern int nouveau_gem_ioctl_new(struct drm_device *, void *, |
1366 | struct drm_file *); | |
1367 | extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, | |
1368 | struct drm_file *); | |
6ee73861 BS |
1369 | extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, |
1370 | struct drm_file *); | |
1371 | extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, | |
1372 | struct drm_file *); | |
1373 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | |
1374 | struct drm_file *); | |
1375 | ||
042206c0 FJ |
1376 | /* nouveau_display.c */ |
1377 | int nouveau_vblank_enable(struct drm_device *dev, int crtc); | |
1378 | void nouveau_vblank_disable(struct drm_device *dev, int crtc); | |
332b242f FJ |
1379 | int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1380 | struct drm_pending_vblank_event *event); | |
1381 | int nouveau_finish_page_flip(struct nouveau_channel *, | |
1382 | struct nouveau_page_flip_state *); | |
042206c0 | 1383 | |
ee2e0131 BS |
1384 | /* nv10_gpio.c */ |
1385 | int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | |
1386 | int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
6ee73861 | 1387 | |
45284162 | 1388 | /* nv50_gpio.c */ |
ee2e0131 | 1389 | int nv50_gpio_init(struct drm_device *dev); |
2cbd4c81 | 1390 | void nv50_gpio_fini(struct drm_device *dev); |
45284162 BS |
1391 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1392 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
fce2bad0 BS |
1393 | int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, |
1394 | void (*)(void *, int), void *); | |
1395 | void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, | |
1396 | void (*)(void *, int), void *); | |
1397 | bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); | |
45284162 | 1398 | |
e9ebb68b BS |
1399 | /* nv50_calc. */ |
1400 | int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, | |
1401 | int *N1, int *M1, int *N2, int *M2, int *P); | |
52eba8dd BS |
1402 | int nva3_calc_pll(struct drm_device *, struct pll_lims *, |
1403 | int clk, int *N, int *fN, int *M, int *P); | |
e9ebb68b | 1404 | |
6ee73861 BS |
1405 | #ifndef ioread32_native |
1406 | #ifdef __BIG_ENDIAN | |
1407 | #define ioread16_native ioread16be | |
1408 | #define iowrite16_native iowrite16be | |
1409 | #define ioread32_native ioread32be | |
1410 | #define iowrite32_native iowrite32be | |
1411 | #else /* def __BIG_ENDIAN */ | |
1412 | #define ioread16_native ioread16 | |
1413 | #define iowrite16_native iowrite16 | |
1414 | #define ioread32_native ioread32 | |
1415 | #define iowrite32_native iowrite32 | |
1416 | #endif /* def __BIG_ENDIAN else */ | |
1417 | #endif /* !ioread32_native */ | |
1418 | ||
1419 | /* channel control reg access */ | |
1420 | static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) | |
1421 | { | |
1422 | return ioread32_native(chan->user + reg); | |
1423 | } | |
1424 | ||
1425 | static inline void nvchan_wr32(struct nouveau_channel *chan, | |
1426 | unsigned reg, u32 val) | |
1427 | { | |
1428 | iowrite32_native(val, chan->user + reg); | |
1429 | } | |
1430 | ||
1431 | /* register access */ | |
1432 | static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) | |
1433 | { | |
1434 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1435 | return ioread32_native(dev_priv->mmio + reg); | |
1436 | } | |
1437 | ||
1438 | static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) | |
1439 | { | |
1440 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1441 | iowrite32_native(val, dev_priv->mmio + reg); | |
1442 | } | |
1443 | ||
2a7fdb2b | 1444 | static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) |
49eed80a BS |
1445 | { |
1446 | u32 tmp = nv_rd32(dev, reg); | |
2a7fdb2b BS |
1447 | nv_wr32(dev, reg, (tmp & ~mask) | val); |
1448 | return tmp; | |
49eed80a BS |
1449 | } |
1450 | ||
6ee73861 BS |
1451 | static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) |
1452 | { | |
1453 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1454 | return ioread8(dev_priv->mmio + reg); | |
1455 | } | |
1456 | ||
1457 | static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) | |
1458 | { | |
1459 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1460 | iowrite8(val, dev_priv->mmio + reg); | |
1461 | } | |
1462 | ||
4b5c152a | 1463 | #define nv_wait(dev, reg, mask, val) \ |
12fb9525 BS |
1464 | nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) |
1465 | #define nv_wait_ne(dev, reg, mask, val) \ | |
1466 | nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) | |
78e2933d BS |
1467 | #define nv_wait_cb(dev, func, data) \ |
1468 | nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) | |
6ee73861 BS |
1469 | |
1470 | /* PRAMIN access */ | |
1471 | static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) | |
1472 | { | |
1473 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1474 | return ioread32_native(dev_priv->ramin + offset); | |
1475 | } | |
1476 | ||
1477 | static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) | |
1478 | { | |
1479 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1480 | iowrite32_native(val, dev_priv->ramin + offset); | |
1481 | } | |
1482 | ||
1483 | /* object access */ | |
b3beb167 BS |
1484 | extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); |
1485 | extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); | |
6ee73861 BS |
1486 | |
1487 | /* | |
1488 | * Logging | |
1489 | * Argument d is (struct drm_device *). | |
1490 | */ | |
1491 | #define NV_PRINTK(level, d, fmt, arg...) \ | |
1492 | printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ | |
1493 | pci_name(d->pdev), ##arg) | |
1494 | #ifndef NV_DEBUG_NOTRACE | |
1495 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1496 | if (drm_debug & DRM_UT_DRIVER) { \ |
1497 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ | |
1498 | __LINE__, ##arg); \ | |
1499 | } \ | |
1500 | } while (0) | |
1501 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1502 | if (drm_debug & DRM_UT_KMS) { \ | |
6ee73861 BS |
1503 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ |
1504 | __LINE__, ##arg); \ | |
1505 | } \ | |
1506 | } while (0) | |
1507 | #else | |
1508 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1509 | if (drm_debug & DRM_UT_DRIVER) \ |
1510 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ | |
1511 | } while (0) | |
1512 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1513 | if (drm_debug & DRM_UT_KMS) \ | |
6ee73861 BS |
1514 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ |
1515 | } while (0) | |
1516 | #endif | |
1517 | #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) | |
1518 | #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1519 | #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) | |
1520 | #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1521 | #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) | |
1522 | ||
1523 | /* nouveau_reg_debug bitmask */ | |
1524 | enum { | |
1525 | NOUVEAU_REG_DEBUG_MC = 0x1, | |
1526 | NOUVEAU_REG_DEBUG_VIDEO = 0x2, | |
1527 | NOUVEAU_REG_DEBUG_FB = 0x4, | |
1528 | NOUVEAU_REG_DEBUG_EXTDEV = 0x8, | |
1529 | NOUVEAU_REG_DEBUG_CRTC = 0x10, | |
1530 | NOUVEAU_REG_DEBUG_RAMDAC = 0x20, | |
1531 | NOUVEAU_REG_DEBUG_VGACRTC = 0x40, | |
1532 | NOUVEAU_REG_DEBUG_RMVIO = 0x80, | |
1533 | NOUVEAU_REG_DEBUG_VGAATTR = 0x100, | |
1534 | NOUVEAU_REG_DEBUG_EVO = 0x200, | |
1535 | }; | |
1536 | ||
1537 | #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ | |
1538 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ | |
1539 | NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ | |
1540 | } while (0) | |
1541 | ||
1542 | static inline bool | |
1543 | nv_two_heads(struct drm_device *dev) | |
1544 | { | |
1545 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1546 | const int impl = dev->pci_device & 0x0ff0; | |
1547 | ||
1548 | if (dev_priv->card_type >= NV_10 && impl != 0x0100 && | |
1549 | impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) | |
1550 | return true; | |
1551 | ||
1552 | return false; | |
1553 | } | |
1554 | ||
1555 | static inline bool | |
1556 | nv_gf4_disp_arch(struct drm_device *dev) | |
1557 | { | |
1558 | return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; | |
1559 | } | |
1560 | ||
1561 | static inline bool | |
1562 | nv_two_reg_pll(struct drm_device *dev) | |
1563 | { | |
1564 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1565 | const int impl = dev->pci_device & 0x0ff0; | |
1566 | ||
1567 | if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) | |
1568 | return true; | |
1569 | return false; | |
1570 | } | |
1571 | ||
acae116c FJ |
1572 | static inline bool |
1573 | nv_match_device(struct drm_device *dev, unsigned device, | |
1574 | unsigned sub_vendor, unsigned sub_device) | |
1575 | { | |
1576 | return dev->pdev->device == device && | |
1577 | dev->pdev->subsystem_vendor == sub_vendor && | |
1578 | dev->pdev->subsystem_device == sub_device; | |
1579 | } | |
1580 | ||
6dfdd7a6 BS |
1581 | static inline void * |
1582 | nv_engine(struct drm_device *dev, int engine) | |
1583 | { | |
1584 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1585 | return (void *)dev_priv->eng[engine]; | |
1586 | } | |
1587 | ||
c693931d BS |
1588 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, |
1589 | * helpful to determine a number of other hardware features | |
1590 | */ | |
1591 | static inline int | |
1592 | nv44_graph_class(struct drm_device *dev) | |
1593 | { | |
1594 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1595 | ||
1596 | if ((dev_priv->chipset & 0xf0) == 0x60) | |
1597 | return 1; | |
1598 | ||
1599 | return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); | |
1600 | } | |
1601 | ||
7f4a195f | 1602 | /* memory type/access flags, do not match hardware values */ |
a11c3198 BS |
1603 | #define NV_MEM_ACCESS_RO 1 |
1604 | #define NV_MEM_ACCESS_WO 2 | |
7f4a195f | 1605 | #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) |
a11c3198 BS |
1606 | #define NV_MEM_ACCESS_SYS 4 |
1607 | #define NV_MEM_ACCESS_VM 8 | |
7f4a195f BS |
1608 | |
1609 | #define NV_MEM_TARGET_VRAM 0 | |
1610 | #define NV_MEM_TARGET_PCI 1 | |
1611 | #define NV_MEM_TARGET_PCI_NOSNOOP 2 | |
1612 | #define NV_MEM_TARGET_VM 3 | |
1613 | #define NV_MEM_TARGET_GART 4 | |
1614 | ||
1615 | #define NV_MEM_TYPE_VM 0x7f | |
1616 | #define NV_MEM_COMP_VM 0x03 | |
1617 | ||
1618 | /* NV_SW object class */ | |
f03a314b FJ |
1619 | #define NV_SW 0x0000506e |
1620 | #define NV_SW_DMA_SEMAPHORE 0x00000060 | |
1621 | #define NV_SW_SEMAPHORE_OFFSET 0x00000064 | |
1622 | #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 | |
1623 | #define NV_SW_SEMAPHORE_RELEASE 0x0000006c | |
8af29ccd | 1624 | #define NV_SW_YIELD 0x00000080 |
f03a314b FJ |
1625 | #define NV_SW_DMA_VBLSEM 0x0000018c |
1626 | #define NV_SW_VBLSEM_OFFSET 0x00000400 | |
1627 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 | |
1628 | #define NV_SW_VBLSEM_RELEASE 0x00000408 | |
332b242f | 1629 | #define NV_SW_PAGE_FLIP 0x00000500 |
6ee73861 BS |
1630 | |
1631 | #endif /* __NOUVEAU_DRV_H__ */ |