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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef __NOUVEAU_DRV_H__ | |
26 | #define __NOUVEAU_DRV_H__ | |
27 | ||
28 | #define DRIVER_AUTHOR "Stephane Marchesin" | |
29 | #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" | |
30 | ||
31 | #define DRIVER_NAME "nouveau" | |
32 | #define DRIVER_DESC "nVidia Riva/TNT/GeForce" | |
33 | #define DRIVER_DATE "20090420" | |
34 | ||
35 | #define DRIVER_MAJOR 0 | |
36 | #define DRIVER_MINOR 0 | |
a1606a95 | 37 | #define DRIVER_PATCHLEVEL 16 |
6ee73861 BS |
38 | |
39 | #define NOUVEAU_FAMILY 0x0000FFFF | |
40 | #define NOUVEAU_FLAGS 0xFFFF0000 | |
41 | ||
42 | #include "ttm/ttm_bo_api.h" | |
43 | #include "ttm/ttm_bo_driver.h" | |
44 | #include "ttm/ttm_placement.h" | |
45 | #include "ttm/ttm_memory.h" | |
46 | #include "ttm/ttm_module.h" | |
47 | ||
48 | struct nouveau_fpriv { | |
49 | struct ttm_object_file *tfile; | |
50 | }; | |
51 | ||
52 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) | |
53 | ||
54 | #include "nouveau_drm.h" | |
55 | #include "nouveau_reg.h" | |
56 | #include "nouveau_bios.h" | |
274fec93 | 57 | #include "nouveau_util.h" |
f869ef88 | 58 | |
054b93e4 | 59 | struct nouveau_grctx; |
f869ef88 BS |
60 | struct nouveau_vram; |
61 | #include "nouveau_vm.h" | |
6ee73861 BS |
62 | |
63 | #define MAX_NUM_DCB_ENTRIES 16 | |
64 | ||
65 | #define NOUVEAU_MAX_CHANNEL_NR 128 | |
a0af9add | 66 | #define NOUVEAU_MAX_TILE_NR 15 |
6ee73861 | 67 | |
573a2a37 BS |
68 | struct nouveau_vram { |
69 | struct drm_device *dev; | |
70 | ||
f869ef88 | 71 | struct nouveau_vma bar_vma; |
4c74eb7f | 72 | u8 page_shift; |
f869ef88 | 73 | |
573a2a37 BS |
74 | struct list_head regions; |
75 | u32 memtype; | |
76 | u64 offset; | |
77 | u64 size; | |
78 | }; | |
79 | ||
a0af9add | 80 | struct nouveau_tile_reg { |
a0af9add | 81 | bool used; |
a5cf68b0 FJ |
82 | uint32_t addr; |
83 | uint32_t limit; | |
84 | uint32_t pitch; | |
87a326a3 FJ |
85 | uint32_t zcomp; |
86 | struct drm_mm_node *tag_mem; | |
a5cf68b0 | 87 | struct nouveau_fence *fence; |
a0af9add FJ |
88 | }; |
89 | ||
6ee73861 BS |
90 | struct nouveau_bo { |
91 | struct ttm_buffer_object bo; | |
92 | struct ttm_placement placement; | |
93 | u32 placements[3]; | |
78ad0f7b | 94 | u32 busy_placements[3]; |
6ee73861 BS |
95 | struct ttm_bo_kmap_obj kmap; |
96 | struct list_head head; | |
97 | ||
98 | /* protected by ttm_bo_reserve() */ | |
99 | struct drm_file *reserved_by; | |
100 | struct list_head entry; | |
101 | int pbbo_index; | |
a1606a95 | 102 | bool validate_mapped; |
6ee73861 BS |
103 | |
104 | struct nouveau_channel *channel; | |
105 | ||
4c136142 | 106 | struct nouveau_vma vma; |
6ee73861 BS |
107 | bool mappable; |
108 | bool no_vm; | |
109 | ||
110 | uint32_t tile_mode; | |
111 | uint32_t tile_flags; | |
a0af9add | 112 | struct nouveau_tile_reg *tile; |
6ee73861 BS |
113 | |
114 | struct drm_gem_object *gem; | |
6ee73861 BS |
115 | int pin_refcnt; |
116 | }; | |
117 | ||
f13b3263 FJ |
118 | #define nouveau_bo_tile_layout(nvbo) \ |
119 | ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) | |
120 | ||
6ee73861 BS |
121 | static inline struct nouveau_bo * |
122 | nouveau_bo(struct ttm_buffer_object *bo) | |
123 | { | |
124 | return container_of(bo, struct nouveau_bo, bo); | |
125 | } | |
126 | ||
127 | static inline struct nouveau_bo * | |
128 | nouveau_gem_object(struct drm_gem_object *gem) | |
129 | { | |
130 | return gem ? gem->driver_private : NULL; | |
131 | } | |
132 | ||
133 | /* TODO: submit equivalent to TTM generic API upstream? */ | |
134 | static inline void __iomem * | |
135 | nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) | |
136 | { | |
137 | bool is_iomem; | |
138 | void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( | |
139 | &nvbo->kmap, &is_iomem); | |
140 | WARN_ON_ONCE(ioptr && !is_iomem); | |
141 | return ioptr; | |
142 | } | |
143 | ||
6ee73861 BS |
144 | enum nouveau_flags { |
145 | NV_NFORCE = 0x10000000, | |
146 | NV_NFORCE2 = 0x20000000 | |
147 | }; | |
148 | ||
149 | #define NVOBJ_ENGINE_SW 0 | |
150 | #define NVOBJ_ENGINE_GR 1 | |
bd2e597d BS |
151 | #define NVOBJ_ENGINE_PPP 2 |
152 | #define NVOBJ_ENGINE_COPY 3 | |
153 | #define NVOBJ_ENGINE_VP 4 | |
154 | #define NVOBJ_ENGINE_CRYPT 5 | |
155 | #define NVOBJ_ENGINE_BSP 6 | |
50536946 | 156 | #define NVOBJ_ENGINE_DISPLAY 0xcafe0001 |
6ee73861 BS |
157 | #define NVOBJ_ENGINE_INT 0xdeadbeef |
158 | ||
a11c3198 | 159 | #define NVOBJ_FLAG_DONT_MAP (1 << 0) |
6ee73861 BS |
160 | #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) |
161 | #define NVOBJ_FLAG_ZERO_FREE (1 << 2) | |
34cf01bc | 162 | #define NVOBJ_FLAG_VM (1 << 3) |
c906ca0f | 163 | #define NVOBJ_FLAG_VM_USER (1 << 4) |
e41115d0 BS |
164 | |
165 | #define NVOBJ_CINST_GLOBAL 0xdeadbeef | |
166 | ||
6ee73861 | 167 | struct nouveau_gpuobj { |
b3beb167 | 168 | struct drm_device *dev; |
eb9bcbdc | 169 | struct kref refcount; |
6ee73861 BS |
170 | struct list_head list; |
171 | ||
e41115d0 | 172 | void *node; |
dc1e5c0d | 173 | u32 *suspend; |
6ee73861 BS |
174 | |
175 | uint32_t flags; | |
6ee73861 | 176 | |
43efc9ce | 177 | u32 size; |
de3a6c0a BS |
178 | u32 pinst; |
179 | u32 cinst; | |
180 | u64 vinst; | |
181 | ||
6ee73861 BS |
182 | uint32_t engine; |
183 | uint32_t class; | |
184 | ||
185 | void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); | |
186 | void *priv; | |
187 | }; | |
188 | ||
332b242f FJ |
189 | struct nouveau_page_flip_state { |
190 | struct list_head head; | |
191 | struct drm_pending_vblank_event *event; | |
192 | int crtc, bpp, pitch, x, y; | |
193 | uint64_t offset; | |
194 | }; | |
195 | ||
e419cf09 FJ |
196 | enum nouveau_channel_mutex_class { |
197 | NOUVEAU_UCHANNEL_MUTEX, | |
198 | NOUVEAU_KCHANNEL_MUTEX | |
199 | }; | |
200 | ||
6ee73861 BS |
201 | struct nouveau_channel { |
202 | struct drm_device *dev; | |
203 | int id; | |
204 | ||
f091a3d4 FJ |
205 | /* references to the channel data structure */ |
206 | struct kref ref; | |
207 | /* users of the hardware channel resources, the hardware | |
208 | * context will be kicked off when it reaches zero. */ | |
209 | atomic_t users; | |
6a6b73f2 BS |
210 | struct mutex mutex; |
211 | ||
6ee73861 BS |
212 | /* owner of this fifo */ |
213 | struct drm_file *file_priv; | |
214 | /* mapping of the fifo itself */ | |
215 | struct drm_local_map *map; | |
216 | ||
217 | /* mapping of the regs controling the fifo */ | |
218 | void __iomem *user; | |
219 | uint32_t user_get; | |
220 | uint32_t user_put; | |
221 | ||
222 | /* Fencing */ | |
223 | struct { | |
224 | /* lock protects the pending list only */ | |
225 | spinlock_t lock; | |
226 | struct list_head pending; | |
227 | uint32_t sequence; | |
228 | uint32_t sequence_ack; | |
047d1d3c | 229 | atomic_t last_sequence_irq; |
6ee73861 BS |
230 | } fence; |
231 | ||
232 | /* DMA push buffer */ | |
a8eaebc6 BS |
233 | struct nouveau_gpuobj *pushbuf; |
234 | struct nouveau_bo *pushbuf_bo; | |
235 | uint32_t pushbuf_base; | |
6ee73861 BS |
236 | |
237 | /* Notifier memory */ | |
238 | struct nouveau_bo *notifier_bo; | |
b833ac26 | 239 | struct drm_mm notifier_heap; |
6ee73861 BS |
240 | |
241 | /* PFIFO context */ | |
a8eaebc6 BS |
242 | struct nouveau_gpuobj *ramfc; |
243 | struct nouveau_gpuobj *cache; | |
b2b09938 | 244 | void *fifo_priv; |
6ee73861 BS |
245 | |
246 | /* PGRAPH context */ | |
247 | /* XXX may be merge 2 pointers as private data ??? */ | |
a8eaebc6 | 248 | struct nouveau_gpuobj *ramin_grctx; |
bd2e597d | 249 | struct nouveau_gpuobj *crypt_ctx; |
6ee73861 BS |
250 | void *pgraph_ctx; |
251 | ||
252 | /* NV50 VM */ | |
f869ef88 | 253 | struct nouveau_vm *vm; |
a8eaebc6 | 254 | struct nouveau_gpuobj *vm_pd; |
6ee73861 BS |
255 | |
256 | /* Objects */ | |
a8eaebc6 BS |
257 | struct nouveau_gpuobj *ramin; /* Private instmem */ |
258 | struct drm_mm ramin_heap; /* Private PRAMIN heap */ | |
259 | struct nouveau_ramht *ramht; /* Hash table */ | |
6ee73861 BS |
260 | |
261 | /* GPU object info for stuff used in-kernel (mm_enabled) */ | |
262 | uint32_t m2mf_ntfy; | |
263 | uint32_t vram_handle; | |
264 | uint32_t gart_handle; | |
265 | bool accel_done; | |
266 | ||
267 | /* Push buffer state (only for drm's channel on !mm_enabled) */ | |
268 | struct { | |
269 | int max; | |
270 | int free; | |
271 | int cur; | |
272 | int put; | |
273 | /* access via pushbuf_bo */ | |
9a391ad8 BS |
274 | |
275 | int ib_base; | |
276 | int ib_max; | |
277 | int ib_free; | |
278 | int ib_put; | |
6ee73861 BS |
279 | } dma; |
280 | ||
281 | uint32_t sw_subchannel[8]; | |
282 | ||
283 | struct { | |
284 | struct nouveau_gpuobj *vblsem; | |
1f6d2de2 | 285 | uint32_t vblsem_head; |
6ee73861 BS |
286 | uint32_t vblsem_offset; |
287 | uint32_t vblsem_rval; | |
288 | struct list_head vbl_wait; | |
332b242f | 289 | struct list_head flip; |
6ee73861 BS |
290 | } nvsw; |
291 | ||
292 | struct { | |
293 | bool active; | |
294 | char name[32]; | |
295 | struct drm_info_list info; | |
296 | } debugfs; | |
297 | }; | |
298 | ||
299 | struct nouveau_instmem_engine { | |
300 | void *priv; | |
301 | ||
302 | int (*init)(struct drm_device *dev); | |
303 | void (*takedown)(struct drm_device *dev); | |
304 | int (*suspend)(struct drm_device *dev); | |
305 | void (*resume)(struct drm_device *dev); | |
306 | ||
e41115d0 BS |
307 | int (*get)(struct nouveau_gpuobj *, u32 size, u32 align); |
308 | void (*put)(struct nouveau_gpuobj *); | |
309 | int (*map)(struct nouveau_gpuobj *); | |
310 | void (*unmap)(struct nouveau_gpuobj *); | |
311 | ||
f56cb86f | 312 | void (*flush)(struct drm_device *); |
6ee73861 BS |
313 | }; |
314 | ||
315 | struct nouveau_mc_engine { | |
316 | int (*init)(struct drm_device *dev); | |
317 | void (*takedown)(struct drm_device *dev); | |
318 | }; | |
319 | ||
320 | struct nouveau_timer_engine { | |
321 | int (*init)(struct drm_device *dev); | |
322 | void (*takedown)(struct drm_device *dev); | |
323 | uint64_t (*read)(struct drm_device *dev); | |
324 | }; | |
325 | ||
326 | struct nouveau_fb_engine { | |
cb00f7c1 | 327 | int num_tiles; |
87a326a3 | 328 | struct drm_mm tag_heap; |
20f63afe | 329 | void *priv; |
cb00f7c1 | 330 | |
6ee73861 BS |
331 | int (*init)(struct drm_device *dev); |
332 | void (*takedown)(struct drm_device *dev); | |
cb00f7c1 | 333 | |
a5cf68b0 FJ |
334 | void (*init_tile_region)(struct drm_device *dev, int i, |
335 | uint32_t addr, uint32_t size, | |
336 | uint32_t pitch, uint32_t flags); | |
337 | void (*set_tile_region)(struct drm_device *dev, int i); | |
338 | void (*free_tile_region)(struct drm_device *dev, int i); | |
6ee73861 BS |
339 | }; |
340 | ||
341 | struct nouveau_fifo_engine { | |
b2b09938 | 342 | void *priv; |
6ee73861 BS |
343 | int channels; |
344 | ||
a8eaebc6 | 345 | struct nouveau_gpuobj *playlist[2]; |
ac94a343 BS |
346 | int cur_playlist; |
347 | ||
6ee73861 BS |
348 | int (*init)(struct drm_device *); |
349 | void (*takedown)(struct drm_device *); | |
350 | ||
351 | void (*disable)(struct drm_device *); | |
352 | void (*enable)(struct drm_device *); | |
353 | bool (*reassign)(struct drm_device *, bool enable); | |
588d7d12 | 354 | bool (*cache_pull)(struct drm_device *dev, bool enable); |
6ee73861 BS |
355 | |
356 | int (*channel_id)(struct drm_device *); | |
357 | ||
358 | int (*create_context)(struct nouveau_channel *); | |
359 | void (*destroy_context)(struct nouveau_channel *); | |
360 | int (*load_context)(struct nouveau_channel *); | |
361 | int (*unload_context)(struct drm_device *); | |
56ac7475 | 362 | void (*tlb_flush)(struct drm_device *dev); |
6ee73861 BS |
363 | }; |
364 | ||
6ee73861 | 365 | struct nouveau_pgraph_engine { |
6ee73861 | 366 | bool accel_blocked; |
b8c157d3 | 367 | bool registered; |
054b93e4 | 368 | int grctx_size; |
966a5b7d | 369 | void *priv; |
6ee73861 | 370 | |
c50a5681 | 371 | /* NV2x/NV3x context table (0x400780) */ |
a8eaebc6 | 372 | struct nouveau_gpuobj *ctx_table; |
c50a5681 | 373 | |
6ee73861 BS |
374 | int (*init)(struct drm_device *); |
375 | void (*takedown)(struct drm_device *); | |
376 | ||
377 | void (*fifo_access)(struct drm_device *, bool); | |
378 | ||
379 | struct nouveau_channel *(*channel)(struct drm_device *); | |
380 | int (*create_context)(struct nouveau_channel *); | |
381 | void (*destroy_context)(struct nouveau_channel *); | |
382 | int (*load_context)(struct nouveau_channel *); | |
383 | int (*unload_context)(struct drm_device *); | |
56ac7475 | 384 | void (*tlb_flush)(struct drm_device *dev); |
cb00f7c1 | 385 | |
a5cf68b0 | 386 | void (*set_tile_region)(struct drm_device *dev, int i); |
6ee73861 BS |
387 | }; |
388 | ||
c88c2e06 FJ |
389 | struct nouveau_display_engine { |
390 | int (*early_init)(struct drm_device *); | |
391 | void (*late_takedown)(struct drm_device *); | |
392 | int (*create)(struct drm_device *); | |
393 | int (*init)(struct drm_device *); | |
394 | void (*destroy)(struct drm_device *); | |
395 | }; | |
396 | ||
ee2e0131 | 397 | struct nouveau_gpio_engine { |
fce2bad0 BS |
398 | void *priv; |
399 | ||
ee2e0131 BS |
400 | int (*init)(struct drm_device *); |
401 | void (*takedown)(struct drm_device *); | |
402 | ||
403 | int (*get)(struct drm_device *, enum dcb_gpio_tag); | |
404 | int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); | |
405 | ||
fce2bad0 BS |
406 | int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, |
407 | void (*)(void *, int), void *); | |
408 | void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, | |
409 | void (*)(void *, int), void *); | |
410 | bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); | |
ee2e0131 BS |
411 | }; |
412 | ||
330c5988 BS |
413 | struct nouveau_pm_voltage_level { |
414 | u8 voltage; | |
415 | u8 vid; | |
416 | }; | |
417 | ||
418 | struct nouveau_pm_voltage { | |
419 | bool supported; | |
420 | u8 vid_mask; | |
421 | ||
422 | struct nouveau_pm_voltage_level *level; | |
423 | int nr_level; | |
424 | }; | |
425 | ||
426 | #define NOUVEAU_PM_MAX_LEVEL 8 | |
427 | struct nouveau_pm_level { | |
428 | struct device_attribute dev_attr; | |
429 | char name[32]; | |
430 | int id; | |
431 | ||
432 | u32 core; | |
433 | u32 memory; | |
434 | u32 shader; | |
435 | u32 unk05; | |
436 | ||
437 | u8 voltage; | |
438 | u8 fanspeed; | |
aee582de BS |
439 | |
440 | u16 memscript; | |
330c5988 BS |
441 | }; |
442 | ||
34e9d85a MP |
443 | struct nouveau_pm_temp_sensor_constants { |
444 | u16 offset_constant; | |
445 | s16 offset_mult; | |
446 | u16 offset_div; | |
447 | u16 slope_mult; | |
448 | u16 slope_div; | |
449 | }; | |
450 | ||
451 | struct nouveau_pm_threshold_temp { | |
452 | s16 critical; | |
453 | s16 down_clock; | |
454 | s16 fan_boost; | |
455 | }; | |
456 | ||
7760fcb0 RS |
457 | struct nouveau_pm_memtiming { |
458 | u32 reg_100220; | |
459 | u32 reg_100224; | |
460 | u32 reg_100228; | |
461 | u32 reg_10022c; | |
462 | u32 reg_100230; | |
463 | u32 reg_100234; | |
464 | u32 reg_100238; | |
465 | u32 reg_10023c; | |
466 | }; | |
467 | ||
468 | struct nouveau_pm_memtimings { | |
469 | bool supported; | |
470 | struct nouveau_pm_memtiming *timing; | |
471 | int nr_timing; | |
472 | }; | |
473 | ||
330c5988 BS |
474 | struct nouveau_pm_engine { |
475 | struct nouveau_pm_voltage voltage; | |
476 | struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; | |
477 | int nr_perflvl; | |
7760fcb0 | 478 | struct nouveau_pm_memtimings memtimings; |
34e9d85a MP |
479 | struct nouveau_pm_temp_sensor_constants sensor_constants; |
480 | struct nouveau_pm_threshold_temp threshold_temp; | |
330c5988 BS |
481 | |
482 | struct nouveau_pm_level boot; | |
483 | struct nouveau_pm_level *cur; | |
484 | ||
8155cac4 | 485 | struct device *hwmon; |
6032649d | 486 | struct notifier_block acpi_nb; |
8155cac4 | 487 | |
330c5988 | 488 | int (*clock_get)(struct drm_device *, u32 id); |
5c6dc657 BS |
489 | void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, |
490 | u32 id, int khz); | |
330c5988 BS |
491 | void (*clock_set)(struct drm_device *, void *); |
492 | int (*voltage_get)(struct drm_device *); | |
493 | int (*voltage_set)(struct drm_device *, int voltage); | |
494 | int (*fanspeed_get)(struct drm_device *); | |
495 | int (*fanspeed_set)(struct drm_device *, int fanspeed); | |
8155cac4 | 496 | int (*temp_get)(struct drm_device *); |
330c5988 BS |
497 | }; |
498 | ||
bd2e597d BS |
499 | struct nouveau_crypt_engine { |
500 | bool registered; | |
501 | ||
502 | int (*init)(struct drm_device *); | |
503 | void (*takedown)(struct drm_device *); | |
504 | int (*create_context)(struct nouveau_channel *); | |
505 | void (*destroy_context)(struct nouveau_channel *); | |
506 | void (*tlb_flush)(struct drm_device *dev); | |
507 | }; | |
508 | ||
60d2a88a BS |
509 | struct nouveau_vram_engine { |
510 | int (*init)(struct drm_device *); | |
511 | int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, | |
512 | u32 type, struct nouveau_vram **); | |
513 | void (*put)(struct drm_device *, struct nouveau_vram **); | |
514 | ||
515 | bool (*flags_valid)(struct drm_device *, u32 tile_flags); | |
516 | }; | |
517 | ||
6ee73861 BS |
518 | struct nouveau_engine { |
519 | struct nouveau_instmem_engine instmem; | |
520 | struct nouveau_mc_engine mc; | |
521 | struct nouveau_timer_engine timer; | |
522 | struct nouveau_fb_engine fb; | |
523 | struct nouveau_pgraph_engine graph; | |
524 | struct nouveau_fifo_engine fifo; | |
c88c2e06 | 525 | struct nouveau_display_engine display; |
ee2e0131 | 526 | struct nouveau_gpio_engine gpio; |
330c5988 | 527 | struct nouveau_pm_engine pm; |
bd2e597d | 528 | struct nouveau_crypt_engine crypt; |
60d2a88a | 529 | struct nouveau_vram_engine vram; |
6ee73861 BS |
530 | }; |
531 | ||
532 | struct nouveau_pll_vals { | |
533 | union { | |
534 | struct { | |
535 | #ifdef __BIG_ENDIAN | |
536 | uint8_t N1, M1, N2, M2; | |
537 | #else | |
538 | uint8_t M1, N1, M2, N2; | |
539 | #endif | |
540 | }; | |
541 | struct { | |
542 | uint16_t NM1, NM2; | |
543 | } __attribute__((packed)); | |
544 | }; | |
545 | int log2P; | |
546 | ||
547 | int refclk; | |
548 | }; | |
549 | ||
550 | enum nv04_fp_display_regs { | |
551 | FP_DISPLAY_END, | |
552 | FP_TOTAL, | |
553 | FP_CRTC, | |
554 | FP_SYNC_START, | |
555 | FP_SYNC_END, | |
556 | FP_VALID_START, | |
557 | FP_VALID_END | |
558 | }; | |
559 | ||
560 | struct nv04_crtc_reg { | |
cbab95db | 561 | unsigned char MiscOutReg; |
4a9f822f | 562 | uint8_t CRTC[0xa0]; |
6ee73861 BS |
563 | uint8_t CR58[0x10]; |
564 | uint8_t Sequencer[5]; | |
565 | uint8_t Graphics[9]; | |
566 | uint8_t Attribute[21]; | |
cbab95db | 567 | unsigned char DAC[768]; |
6ee73861 BS |
568 | |
569 | /* PCRTC regs */ | |
570 | uint32_t fb_start; | |
571 | uint32_t crtc_cfg; | |
572 | uint32_t cursor_cfg; | |
573 | uint32_t gpio_ext; | |
574 | uint32_t crtc_830; | |
575 | uint32_t crtc_834; | |
576 | uint32_t crtc_850; | |
577 | uint32_t crtc_eng_ctrl; | |
578 | ||
579 | /* PRAMDAC regs */ | |
580 | uint32_t nv10_cursync; | |
581 | struct nouveau_pll_vals pllvals; | |
582 | uint32_t ramdac_gen_ctrl; | |
583 | uint32_t ramdac_630; | |
584 | uint32_t ramdac_634; | |
585 | uint32_t tv_setup; | |
586 | uint32_t tv_vtotal; | |
587 | uint32_t tv_vskew; | |
588 | uint32_t tv_vsync_delay; | |
589 | uint32_t tv_htotal; | |
590 | uint32_t tv_hskew; | |
591 | uint32_t tv_hsync_delay; | |
592 | uint32_t tv_hsync_delay2; | |
593 | uint32_t fp_horiz_regs[7]; | |
594 | uint32_t fp_vert_regs[7]; | |
595 | uint32_t dither; | |
596 | uint32_t fp_control; | |
597 | uint32_t dither_regs[6]; | |
598 | uint32_t fp_debug_0; | |
599 | uint32_t fp_debug_1; | |
600 | uint32_t fp_debug_2; | |
601 | uint32_t fp_margin_color; | |
602 | uint32_t ramdac_8c0; | |
603 | uint32_t ramdac_a20; | |
604 | uint32_t ramdac_a24; | |
605 | uint32_t ramdac_a34; | |
606 | uint32_t ctv_regs[38]; | |
607 | }; | |
608 | ||
609 | struct nv04_output_reg { | |
610 | uint32_t output; | |
611 | int head; | |
612 | }; | |
613 | ||
614 | struct nv04_mode_state { | |
cbab95db | 615 | struct nv04_crtc_reg crtc_reg[2]; |
6ee73861 BS |
616 | uint32_t pllsel; |
617 | uint32_t sel_clk; | |
6ee73861 BS |
618 | }; |
619 | ||
620 | enum nouveau_card_type { | |
621 | NV_04 = 0x00, | |
622 | NV_10 = 0x10, | |
623 | NV_20 = 0x20, | |
624 | NV_30 = 0x30, | |
625 | NV_40 = 0x40, | |
626 | NV_50 = 0x50, | |
4b223eef | 627 | NV_C0 = 0xc0, |
6ee73861 BS |
628 | }; |
629 | ||
630 | struct drm_nouveau_private { | |
631 | struct drm_device *dev; | |
6ee73861 BS |
632 | |
633 | /* the card type, takes NV_* as values */ | |
634 | enum nouveau_card_type card_type; | |
635 | /* exact chipset, derived from NV_PMC_BOOT_0 */ | |
636 | int chipset; | |
637 | int flags; | |
638 | ||
639 | void __iomem *mmio; | |
5125bfd8 | 640 | |
e05d7eae | 641 | spinlock_t ramin_lock; |
6ee73861 | 642 | void __iomem *ramin; |
5125bfd8 BS |
643 | u32 ramin_size; |
644 | u32 ramin_base; | |
645 | bool ramin_available; | |
e05d7eae BS |
646 | struct drm_mm ramin_heap; |
647 | struct list_head gpuobj_list; | |
b8c157d3 | 648 | struct list_head classes; |
6ee73861 | 649 | |
ac8fb975 BS |
650 | struct nouveau_bo *vga_ram; |
651 | ||
35fa2f2a | 652 | /* interrupt handling */ |
8f8a5448 | 653 | void (*irq_handler[32])(struct drm_device *); |
35fa2f2a | 654 | bool msi_enabled; |
6ee73861 BS |
655 | struct workqueue_struct *wq; |
656 | struct work_struct irq_work; | |
ab838338 | 657 | |
6ee73861 BS |
658 | struct list_head vbl_waiting; |
659 | ||
660 | struct { | |
ba4420c2 | 661 | struct drm_global_reference mem_global_ref; |
6ee73861 BS |
662 | struct ttm_bo_global_ref bo_global_ref; |
663 | struct ttm_bo_device bdev; | |
6ee73861 BS |
664 | atomic_t validate_sequence; |
665 | } ttm; | |
666 | ||
0c6c1c2f FJ |
667 | struct { |
668 | spinlock_t lock; | |
669 | struct drm_mm heap; | |
670 | struct nouveau_bo *bo; | |
671 | } fence; | |
672 | ||
cff5c133 BS |
673 | struct { |
674 | spinlock_t lock; | |
675 | struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; | |
676 | } channels; | |
6ee73861 BS |
677 | |
678 | struct nouveau_engine engine; | |
679 | struct nouveau_channel *channel; | |
680 | ||
ff9e5279 MM |
681 | /* For PFIFO and PGRAPH. */ |
682 | spinlock_t context_switch_lock; | |
683 | ||
6ee73861 | 684 | /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ |
e05c5a31 BS |
685 | struct nouveau_ramht *ramht; |
686 | struct nouveau_gpuobj *ramfc; | |
687 | struct nouveau_gpuobj *ramro; | |
688 | ||
6ee73861 | 689 | uint32_t ramin_rsvd_vram; |
6ee73861 | 690 | |
6ee73861 BS |
691 | struct { |
692 | enum { | |
693 | NOUVEAU_GART_NONE = 0, | |
694 | NOUVEAU_GART_AGP, | |
695 | NOUVEAU_GART_SGDMA | |
696 | } type; | |
697 | uint64_t aper_base; | |
698 | uint64_t aper_size; | |
699 | uint64_t aper_free; | |
700 | ||
701 | struct nouveau_gpuobj *sg_ctxdma; | |
b571fe21 | 702 | struct nouveau_vma vma; |
6ee73861 BS |
703 | } gart_info; |
704 | ||
a0af9add | 705 | /* nv10-nv40 tiling regions */ |
a5cf68b0 FJ |
706 | struct { |
707 | struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; | |
708 | spinlock_t lock; | |
709 | } tile; | |
a0af9add | 710 | |
a76fb4e8 BS |
711 | /* VRAM/fb configuration */ |
712 | uint64_t vram_size; | |
713 | uint64_t vram_sys_base; | |
6c3d7ef2 | 714 | u32 vram_rblock_size; |
a76fb4e8 BS |
715 | |
716 | uint64_t fb_phys; | |
717 | uint64_t fb_available_size; | |
718 | uint64_t fb_mappable_pages; | |
719 | uint64_t fb_aper_free; | |
720 | int fb_mtrr; | |
721 | ||
f869ef88 BS |
722 | /* BAR control (NV50-) */ |
723 | struct nouveau_vm *bar1_vm; | |
724 | struct nouveau_vm *bar3_vm; | |
725 | ||
6ee73861 | 726 | /* G8x/G9x virtual address space */ |
4c136142 | 727 | struct nouveau_vm *chan_vm; |
6ee73861 | 728 | |
04a39c57 | 729 | struct nvbios vbios; |
6ee73861 BS |
730 | |
731 | struct nv04_mode_state mode_reg; | |
732 | struct nv04_mode_state saved_reg; | |
733 | uint32_t saved_vga_font[4][16384]; | |
734 | uint32_t crtc_owner; | |
735 | uint32_t dac_users[4]; | |
736 | ||
737 | struct nouveau_suspend_resume { | |
6ee73861 | 738 | uint32_t *ramin_copy; |
6ee73861 BS |
739 | } susres; |
740 | ||
741 | struct backlight_device *backlight; | |
6ee73861 BS |
742 | |
743 | struct nouveau_channel *evo; | |
1e96268a | 744 | u32 evo_alloc; |
87c0e0e5 BS |
745 | struct { |
746 | struct dcb_entry *dcb; | |
747 | u16 script; | |
748 | u32 pclk; | |
749 | } evo_irq; | |
6ee73861 BS |
750 | |
751 | struct { | |
752 | struct dentry *channel_root; | |
753 | } debugfs; | |
38651674 | 754 | |
8be48d92 | 755 | struct nouveau_fbdev *nfbdev; |
06415c56 | 756 | struct apertures_struct *apertures; |
5bcf719b DA |
757 | |
758 | bool powered_down; | |
6ee73861 BS |
759 | }; |
760 | ||
2730723b FJ |
761 | static inline struct drm_nouveau_private * |
762 | nouveau_private(struct drm_device *dev) | |
763 | { | |
764 | return dev->dev_private; | |
765 | } | |
766 | ||
6ee73861 BS |
767 | static inline struct drm_nouveau_private * |
768 | nouveau_bdev(struct ttm_bo_device *bd) | |
769 | { | |
770 | return container_of(bd, struct drm_nouveau_private, ttm.bdev); | |
771 | } | |
772 | ||
773 | static inline int | |
774 | nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) | |
775 | { | |
776 | struct nouveau_bo *prev; | |
777 | ||
778 | if (!pnvbo) | |
779 | return -EINVAL; | |
780 | prev = *pnvbo; | |
781 | ||
782 | *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; | |
783 | if (prev) { | |
784 | struct ttm_buffer_object *bo = &prev->bo; | |
785 | ||
786 | ttm_bo_unref(&bo); | |
787 | } | |
788 | ||
789 | return 0; | |
790 | } | |
791 | ||
6ee73861 | 792 | /* nouveau_drv.c */ |
de5899bd | 793 | extern int nouveau_agpmode; |
6ee73861 BS |
794 | extern int nouveau_duallink; |
795 | extern int nouveau_uscript_lvds; | |
796 | extern int nouveau_uscript_tmds; | |
797 | extern int nouveau_vram_pushbuf; | |
798 | extern int nouveau_vram_notify; | |
799 | extern int nouveau_fbpercrtc; | |
f4053509 | 800 | extern int nouveau_tv_disable; |
6ee73861 BS |
801 | extern char *nouveau_tv_norm; |
802 | extern int nouveau_reg_debug; | |
803 | extern char *nouveau_vbios; | |
a1470890 | 804 | extern int nouveau_ignorelid; |
a32ed69d MK |
805 | extern int nouveau_nofbaccel; |
806 | extern int nouveau_noaccel; | |
0cba1b76 | 807 | extern int nouveau_force_post; |
da647d5b | 808 | extern int nouveau_override_conntype; |
6f876986 BS |
809 | extern char *nouveau_perflvl; |
810 | extern int nouveau_perflvl_wr; | |
35fa2f2a | 811 | extern int nouveau_msi; |
6ee73861 | 812 | |
6a9ee8af DA |
813 | extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); |
814 | extern int nouveau_pci_resume(struct pci_dev *pdev); | |
815 | ||
6ee73861 BS |
816 | /* nouveau_state.c */ |
817 | extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); | |
818 | extern int nouveau_load(struct drm_device *, unsigned long flags); | |
819 | extern int nouveau_firstopen(struct drm_device *); | |
820 | extern void nouveau_lastclose(struct drm_device *); | |
821 | extern int nouveau_unload(struct drm_device *); | |
822 | extern int nouveau_ioctl_getparam(struct drm_device *, void *data, | |
823 | struct drm_file *); | |
824 | extern int nouveau_ioctl_setparam(struct drm_device *, void *data, | |
825 | struct drm_file *); | |
12fb9525 BS |
826 | extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, |
827 | uint32_t reg, uint32_t mask, uint32_t val); | |
828 | extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, | |
829 | uint32_t reg, uint32_t mask, uint32_t val); | |
6ee73861 BS |
830 | extern bool nouveau_wait_for_idle(struct drm_device *); |
831 | extern int nouveau_card_init(struct drm_device *); | |
6ee73861 BS |
832 | |
833 | /* nouveau_mem.c */ | |
fbd2895e BS |
834 | extern int nouveau_mem_vram_init(struct drm_device *); |
835 | extern void nouveau_mem_vram_fini(struct drm_device *); | |
836 | extern int nouveau_mem_gart_init(struct drm_device *); | |
837 | extern void nouveau_mem_gart_fini(struct drm_device *); | |
6ee73861 | 838 | extern int nouveau_mem_init_agp(struct drm_device *); |
e04d8e82 | 839 | extern int nouveau_mem_reset_agp(struct drm_device *); |
6ee73861 | 840 | extern void nouveau_mem_close(struct drm_device *); |
60d2a88a BS |
841 | extern int nouveau_mem_detect(struct drm_device *); |
842 | extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); | |
a5cf68b0 FJ |
843 | extern struct nouveau_tile_reg *nv10_mem_set_tiling( |
844 | struct drm_device *dev, uint32_t addr, uint32_t size, | |
845 | uint32_t pitch, uint32_t flags); | |
846 | extern void nv10_mem_put_tile_region(struct drm_device *dev, | |
847 | struct nouveau_tile_reg *tile, | |
848 | struct nouveau_fence *fence); | |
573a2a37 | 849 | extern const struct ttm_mem_type_manager_func nouveau_vram_manager; |
6ee73861 BS |
850 | |
851 | /* nouveau_notifier.c */ | |
852 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); | |
853 | extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); | |
854 | extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, | |
855 | int cout, uint32_t *offset); | |
856 | extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); | |
857 | extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, | |
858 | struct drm_file *); | |
859 | extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, | |
860 | struct drm_file *); | |
861 | ||
862 | /* nouveau_channel.c */ | |
863 | extern struct drm_ioctl_desc nouveau_ioctls[]; | |
864 | extern int nouveau_max_ioctl; | |
865 | extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); | |
6ee73861 BS |
866 | extern int nouveau_channel_alloc(struct drm_device *dev, |
867 | struct nouveau_channel **chan, | |
868 | struct drm_file *file_priv, | |
869 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); | |
cff5c133 | 870 | extern struct nouveau_channel * |
feeb0aec FJ |
871 | nouveau_channel_get_unlocked(struct nouveau_channel *); |
872 | extern struct nouveau_channel * | |
cff5c133 | 873 | nouveau_channel_get(struct drm_device *, struct drm_file *, int id); |
feeb0aec | 874 | extern void nouveau_channel_put_unlocked(struct nouveau_channel **); |
cff5c133 | 875 | extern void nouveau_channel_put(struct nouveau_channel **); |
f091a3d4 FJ |
876 | extern void nouveau_channel_ref(struct nouveau_channel *chan, |
877 | struct nouveau_channel **pchan); | |
6dccd311 | 878 | extern void nouveau_channel_idle(struct nouveau_channel *chan); |
6ee73861 BS |
879 | |
880 | /* nouveau_object.c */ | |
b8c157d3 BS |
881 | #define NVOBJ_CLASS(d,c,e) do { \ |
882 | int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ | |
883 | if (ret) \ | |
884 | return ret; \ | |
885 | } while(0) | |
886 | ||
887 | #define NVOBJ_MTHD(d,c,m,e) do { \ | |
888 | int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ | |
889 | if (ret) \ | |
890 | return ret; \ | |
891 | } while(0) | |
892 | ||
6ee73861 BS |
893 | extern int nouveau_gpuobj_early_init(struct drm_device *); |
894 | extern int nouveau_gpuobj_init(struct drm_device *); | |
895 | extern void nouveau_gpuobj_takedown(struct drm_device *); | |
6ee73861 | 896 | extern int nouveau_gpuobj_suspend(struct drm_device *dev); |
6ee73861 | 897 | extern void nouveau_gpuobj_resume(struct drm_device *dev); |
b8c157d3 BS |
898 | extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); |
899 | extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, | |
900 | int (*exec)(struct nouveau_channel *, | |
901 | u32 class, u32 mthd, u32 data)); | |
902 | extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); | |
274fec93 | 903 | extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); |
6ee73861 BS |
904 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, |
905 | uint32_t vram_h, uint32_t tt_h); | |
906 | extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); | |
907 | extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, | |
908 | uint32_t size, int align, uint32_t flags, | |
909 | struct nouveau_gpuobj **); | |
a8eaebc6 BS |
910 | extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, |
911 | struct nouveau_gpuobj **); | |
43efc9ce BS |
912 | extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, |
913 | u32 size, u32 flags, | |
a8eaebc6 | 914 | struct nouveau_gpuobj **); |
6ee73861 BS |
915 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, |
916 | uint64_t offset, uint64_t size, int access, | |
917 | int target, struct nouveau_gpuobj **); | |
ceac3099 | 918 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); |
7f4a195f BS |
919 | extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, |
920 | u64 size, int target, int access, u32 type, | |
921 | u32 comp, struct nouveau_gpuobj **pobj); | |
922 | extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, | |
923 | int class, u64 base, u64 size, int target, | |
924 | int access, u32 type, u32 comp); | |
6ee73861 BS |
925 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, |
926 | struct drm_file *); | |
927 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, | |
928 | struct drm_file *); | |
929 | ||
930 | /* nouveau_irq.c */ | |
35fa2f2a BS |
931 | extern int nouveau_irq_init(struct drm_device *); |
932 | extern void nouveau_irq_fini(struct drm_device *); | |
6ee73861 | 933 | extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); |
8f8a5448 BS |
934 | extern void nouveau_irq_register(struct drm_device *, int status_bit, |
935 | void (*)(struct drm_device *)); | |
936 | extern void nouveau_irq_unregister(struct drm_device *, int status_bit); | |
6ee73861 BS |
937 | extern void nouveau_irq_preinstall(struct drm_device *); |
938 | extern int nouveau_irq_postinstall(struct drm_device *); | |
939 | extern void nouveau_irq_uninstall(struct drm_device *); | |
940 | ||
941 | /* nouveau_sgdma.c */ | |
942 | extern int nouveau_sgdma_init(struct drm_device *); | |
943 | extern void nouveau_sgdma_takedown(struct drm_device *); | |
fd70b6cd FJ |
944 | extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, |
945 | uint32_t offset); | |
6ee73861 BS |
946 | extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); |
947 | ||
948 | /* nouveau_debugfs.c */ | |
949 | #if defined(CONFIG_DRM_NOUVEAU_DEBUG) | |
950 | extern int nouveau_debugfs_init(struct drm_minor *); | |
951 | extern void nouveau_debugfs_takedown(struct drm_minor *); | |
952 | extern int nouveau_debugfs_channel_init(struct nouveau_channel *); | |
953 | extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); | |
954 | #else | |
955 | static inline int | |
956 | nouveau_debugfs_init(struct drm_minor *minor) | |
957 | { | |
958 | return 0; | |
959 | } | |
960 | ||
961 | static inline void nouveau_debugfs_takedown(struct drm_minor *minor) | |
962 | { | |
963 | } | |
964 | ||
965 | static inline int | |
966 | nouveau_debugfs_channel_init(struct nouveau_channel *chan) | |
967 | { | |
968 | return 0; | |
969 | } | |
970 | ||
971 | static inline void | |
972 | nouveau_debugfs_channel_fini(struct nouveau_channel *chan) | |
973 | { | |
974 | } | |
975 | #endif | |
976 | ||
977 | /* nouveau_dma.c */ | |
75c99da6 | 978 | extern void nouveau_dma_pre_init(struct nouveau_channel *); |
6ee73861 | 979 | extern int nouveau_dma_init(struct nouveau_channel *); |
9a391ad8 | 980 | extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); |
6ee73861 BS |
981 | |
982 | /* nouveau_acpi.c */ | |
afeb3e11 | 983 | #define ROM_BIOS_PAGE 4096 |
2f41a7f1 | 984 | #if defined(CONFIG_ACPI) |
6a9ee8af DA |
985 | void nouveau_register_dsm_handler(void); |
986 | void nouveau_unregister_dsm_handler(void); | |
afeb3e11 DA |
987 | int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); |
988 | bool nouveau_acpi_rom_supported(struct pci_dev *pdev); | |
a6ed76d7 | 989 | int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); |
8edb381d DA |
990 | #else |
991 | static inline void nouveau_register_dsm_handler(void) {} | |
992 | static inline void nouveau_unregister_dsm_handler(void) {} | |
afeb3e11 DA |
993 | static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } |
994 | static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } | |
5620ba46 | 995 | static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } |
8edb381d | 996 | #endif |
6ee73861 BS |
997 | |
998 | /* nouveau_backlight.c */ | |
999 | #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT | |
1000 | extern int nouveau_backlight_init(struct drm_device *); | |
1001 | extern void nouveau_backlight_exit(struct drm_device *); | |
1002 | #else | |
1003 | static inline int nouveau_backlight_init(struct drm_device *dev) | |
1004 | { | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static inline void nouveau_backlight_exit(struct drm_device *dev) { } | |
1009 | #endif | |
1010 | ||
1011 | /* nouveau_bios.c */ | |
1012 | extern int nouveau_bios_init(struct drm_device *); | |
1013 | extern void nouveau_bios_takedown(struct drm_device *dev); | |
1014 | extern int nouveau_run_vbios_init(struct drm_device *); | |
1015 | extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, | |
1016 | struct dcb_entry *); | |
1017 | extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, | |
1018 | enum dcb_gpio_tag); | |
1019 | extern struct dcb_connector_table_entry * | |
1020 | nouveau_bios_connector_entry(struct drm_device *, int index); | |
855a95e4 | 1021 | extern u32 get_pll_register(struct drm_device *, enum pll_types); |
6ee73861 BS |
1022 | extern int get_pll_limits(struct drm_device *, uint32_t limit_match, |
1023 | struct pll_lims *); | |
1024 | extern int nouveau_bios_run_display_table(struct drm_device *, | |
1025 | struct dcb_entry *, | |
1026 | uint32_t script, int pxclk); | |
1027 | extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, | |
1028 | int *length); | |
1029 | extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); | |
1030 | extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); | |
1031 | extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, | |
1032 | bool *dl, bool *if_is_24bit); | |
1033 | extern int run_tmds_table(struct drm_device *, struct dcb_entry *, | |
1034 | int head, int pxclk); | |
1035 | extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, | |
1036 | enum LVDS_script, int pxclk); | |
1037 | ||
1038 | /* nouveau_ttm.c */ | |
1039 | int nouveau_ttm_global_init(struct drm_nouveau_private *); | |
1040 | void nouveau_ttm_global_release(struct drm_nouveau_private *); | |
1041 | int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); | |
1042 | ||
1043 | /* nouveau_dp.c */ | |
1044 | int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, | |
1045 | uint8_t *data, int data_nr); | |
1046 | bool nouveau_dp_detect(struct drm_encoder *); | |
1047 | bool nouveau_dp_link_train(struct drm_encoder *); | |
1048 | ||
1049 | /* nv04_fb.c */ | |
1050 | extern int nv04_fb_init(struct drm_device *); | |
1051 | extern void nv04_fb_takedown(struct drm_device *); | |
1052 | ||
1053 | /* nv10_fb.c */ | |
1054 | extern int nv10_fb_init(struct drm_device *); | |
1055 | extern void nv10_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1056 | extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, |
1057 | uint32_t addr, uint32_t size, | |
1058 | uint32_t pitch, uint32_t flags); | |
1059 | extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); | |
1060 | extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); | |
6ee73861 | 1061 | |
8bded189 FJ |
1062 | /* nv30_fb.c */ |
1063 | extern int nv30_fb_init(struct drm_device *); | |
1064 | extern void nv30_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1065 | extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, |
1066 | uint32_t addr, uint32_t size, | |
1067 | uint32_t pitch, uint32_t flags); | |
1068 | extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); | |
8bded189 | 1069 | |
6ee73861 BS |
1070 | /* nv40_fb.c */ |
1071 | extern int nv40_fb_init(struct drm_device *); | |
1072 | extern void nv40_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1073 | extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); |
1074 | ||
304424e1 MK |
1075 | /* nv50_fb.c */ |
1076 | extern int nv50_fb_init(struct drm_device *); | |
1077 | extern void nv50_fb_takedown(struct drm_device *); | |
d96773e7 | 1078 | extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *); |
304424e1 | 1079 | |
4b223eef BS |
1080 | /* nvc0_fb.c */ |
1081 | extern int nvc0_fb_init(struct drm_device *); | |
1082 | extern void nvc0_fb_takedown(struct drm_device *); | |
1083 | ||
6ee73861 BS |
1084 | /* nv04_fifo.c */ |
1085 | extern int nv04_fifo_init(struct drm_device *); | |
5178d40d | 1086 | extern void nv04_fifo_fini(struct drm_device *); |
6ee73861 BS |
1087 | extern void nv04_fifo_disable(struct drm_device *); |
1088 | extern void nv04_fifo_enable(struct drm_device *); | |
1089 | extern bool nv04_fifo_reassign(struct drm_device *, bool); | |
588d7d12 | 1090 | extern bool nv04_fifo_cache_pull(struct drm_device *, bool); |
6ee73861 BS |
1091 | extern int nv04_fifo_channel_id(struct drm_device *); |
1092 | extern int nv04_fifo_create_context(struct nouveau_channel *); | |
1093 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); | |
1094 | extern int nv04_fifo_load_context(struct nouveau_channel *); | |
1095 | extern int nv04_fifo_unload_context(struct drm_device *); | |
5178d40d | 1096 | extern void nv04_fifo_isr(struct drm_device *); |
6ee73861 BS |
1097 | |
1098 | /* nv10_fifo.c */ | |
1099 | extern int nv10_fifo_init(struct drm_device *); | |
1100 | extern int nv10_fifo_channel_id(struct drm_device *); | |
1101 | extern int nv10_fifo_create_context(struct nouveau_channel *); | |
6ee73861 BS |
1102 | extern int nv10_fifo_load_context(struct nouveau_channel *); |
1103 | extern int nv10_fifo_unload_context(struct drm_device *); | |
1104 | ||
1105 | /* nv40_fifo.c */ | |
1106 | extern int nv40_fifo_init(struct drm_device *); | |
1107 | extern int nv40_fifo_create_context(struct nouveau_channel *); | |
6ee73861 BS |
1108 | extern int nv40_fifo_load_context(struct nouveau_channel *); |
1109 | extern int nv40_fifo_unload_context(struct drm_device *); | |
1110 | ||
1111 | /* nv50_fifo.c */ | |
1112 | extern int nv50_fifo_init(struct drm_device *); | |
1113 | extern void nv50_fifo_takedown(struct drm_device *); | |
1114 | extern int nv50_fifo_channel_id(struct drm_device *); | |
1115 | extern int nv50_fifo_create_context(struct nouveau_channel *); | |
1116 | extern void nv50_fifo_destroy_context(struct nouveau_channel *); | |
1117 | extern int nv50_fifo_load_context(struct nouveau_channel *); | |
1118 | extern int nv50_fifo_unload_context(struct drm_device *); | |
56ac7475 | 1119 | extern void nv50_fifo_tlb_flush(struct drm_device *dev); |
6ee73861 | 1120 | |
4b223eef BS |
1121 | /* nvc0_fifo.c */ |
1122 | extern int nvc0_fifo_init(struct drm_device *); | |
1123 | extern void nvc0_fifo_takedown(struct drm_device *); | |
1124 | extern void nvc0_fifo_disable(struct drm_device *); | |
1125 | extern void nvc0_fifo_enable(struct drm_device *); | |
1126 | extern bool nvc0_fifo_reassign(struct drm_device *, bool); | |
4b223eef BS |
1127 | extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); |
1128 | extern int nvc0_fifo_channel_id(struct drm_device *); | |
1129 | extern int nvc0_fifo_create_context(struct nouveau_channel *); | |
1130 | extern void nvc0_fifo_destroy_context(struct nouveau_channel *); | |
1131 | extern int nvc0_fifo_load_context(struct nouveau_channel *); | |
1132 | extern int nvc0_fifo_unload_context(struct drm_device *); | |
1133 | ||
6ee73861 | 1134 | /* nv04_graph.c */ |
6ee73861 BS |
1135 | extern int nv04_graph_init(struct drm_device *); |
1136 | extern void nv04_graph_takedown(struct drm_device *); | |
1137 | extern void nv04_graph_fifo_access(struct drm_device *, bool); | |
1138 | extern struct nouveau_channel *nv04_graph_channel(struct drm_device *); | |
1139 | extern int nv04_graph_create_context(struct nouveau_channel *); | |
1140 | extern void nv04_graph_destroy_context(struct nouveau_channel *); | |
1141 | extern int nv04_graph_load_context(struct nouveau_channel *); | |
1142 | extern int nv04_graph_unload_context(struct drm_device *); | |
332b242f FJ |
1143 | extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, |
1144 | u32 class, u32 mthd, u32 data); | |
274fec93 | 1145 | extern struct nouveau_bitfield nv04_graph_nsource[]; |
6ee73861 BS |
1146 | |
1147 | /* nv10_graph.c */ | |
6ee73861 BS |
1148 | extern int nv10_graph_init(struct drm_device *); |
1149 | extern void nv10_graph_takedown(struct drm_device *); | |
1150 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); | |
1151 | extern int nv10_graph_create_context(struct nouveau_channel *); | |
1152 | extern void nv10_graph_destroy_context(struct nouveau_channel *); | |
1153 | extern int nv10_graph_load_context(struct nouveau_channel *); | |
1154 | extern int nv10_graph_unload_context(struct drm_device *); | |
a5cf68b0 | 1155 | extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); |
274fec93 BS |
1156 | extern struct nouveau_bitfield nv10_graph_intr[]; |
1157 | extern struct nouveau_bitfield nv10_graph_nstatus[]; | |
6ee73861 BS |
1158 | |
1159 | /* nv20_graph.c */ | |
6ee73861 BS |
1160 | extern int nv20_graph_create_context(struct nouveau_channel *); |
1161 | extern void nv20_graph_destroy_context(struct nouveau_channel *); | |
1162 | extern int nv20_graph_load_context(struct nouveau_channel *); | |
1163 | extern int nv20_graph_unload_context(struct drm_device *); | |
1164 | extern int nv20_graph_init(struct drm_device *); | |
1165 | extern void nv20_graph_takedown(struct drm_device *); | |
1166 | extern int nv30_graph_init(struct drm_device *); | |
a5cf68b0 | 1167 | extern void nv20_graph_set_tile_region(struct drm_device *dev, int i); |
6ee73861 BS |
1168 | |
1169 | /* nv40_graph.c */ | |
6ee73861 BS |
1170 | extern int nv40_graph_init(struct drm_device *); |
1171 | extern void nv40_graph_takedown(struct drm_device *); | |
1172 | extern struct nouveau_channel *nv40_graph_channel(struct drm_device *); | |
1173 | extern int nv40_graph_create_context(struct nouveau_channel *); | |
1174 | extern void nv40_graph_destroy_context(struct nouveau_channel *); | |
1175 | extern int nv40_graph_load_context(struct nouveau_channel *); | |
1176 | extern int nv40_graph_unload_context(struct drm_device *); | |
054b93e4 | 1177 | extern void nv40_grctx_init(struct nouveau_grctx *); |
a5cf68b0 | 1178 | extern void nv40_graph_set_tile_region(struct drm_device *dev, int i); |
6ee73861 BS |
1179 | |
1180 | /* nv50_graph.c */ | |
6ee73861 BS |
1181 | extern int nv50_graph_init(struct drm_device *); |
1182 | extern void nv50_graph_takedown(struct drm_device *); | |
1183 | extern void nv50_graph_fifo_access(struct drm_device *, bool); | |
1184 | extern struct nouveau_channel *nv50_graph_channel(struct drm_device *); | |
1185 | extern int nv50_graph_create_context(struct nouveau_channel *); | |
1186 | extern void nv50_graph_destroy_context(struct nouveau_channel *); | |
1187 | extern int nv50_graph_load_context(struct nouveau_channel *); | |
1188 | extern int nv50_graph_unload_context(struct drm_device *); | |
d5f3c90d | 1189 | extern int nv50_grctx_init(struct nouveau_grctx *); |
56ac7475 BS |
1190 | extern void nv50_graph_tlb_flush(struct drm_device *dev); |
1191 | extern void nv86_graph_tlb_flush(struct drm_device *dev); | |
6effe393 | 1192 | extern struct nouveau_enum nv50_data_error_names[]; |
6ee73861 | 1193 | |
4b223eef BS |
1194 | /* nvc0_graph.c */ |
1195 | extern int nvc0_graph_init(struct drm_device *); | |
1196 | extern void nvc0_graph_takedown(struct drm_device *); | |
1197 | extern void nvc0_graph_fifo_access(struct drm_device *, bool); | |
1198 | extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *); | |
1199 | extern int nvc0_graph_create_context(struct nouveau_channel *); | |
1200 | extern void nvc0_graph_destroy_context(struct nouveau_channel *); | |
1201 | extern int nvc0_graph_load_context(struct nouveau_channel *); | |
1202 | extern int nvc0_graph_unload_context(struct drm_device *); | |
1203 | ||
bd2e597d BS |
1204 | /* nv84_crypt.c */ |
1205 | extern int nv84_crypt_init(struct drm_device *dev); | |
1206 | extern void nv84_crypt_fini(struct drm_device *dev); | |
1207 | extern int nv84_crypt_create_context(struct nouveau_channel *); | |
1208 | extern void nv84_crypt_destroy_context(struct nouveau_channel *); | |
1209 | extern void nv84_crypt_tlb_flush(struct drm_device *dev); | |
1210 | ||
6ee73861 BS |
1211 | /* nv04_instmem.c */ |
1212 | extern int nv04_instmem_init(struct drm_device *); | |
1213 | extern void nv04_instmem_takedown(struct drm_device *); | |
1214 | extern int nv04_instmem_suspend(struct drm_device *); | |
1215 | extern void nv04_instmem_resume(struct drm_device *); | |
e41115d0 BS |
1216 | extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); |
1217 | extern void nv04_instmem_put(struct nouveau_gpuobj *); | |
1218 | extern int nv04_instmem_map(struct nouveau_gpuobj *); | |
1219 | extern void nv04_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1220 | extern void nv04_instmem_flush(struct drm_device *); |
6ee73861 BS |
1221 | |
1222 | /* nv50_instmem.c */ | |
1223 | extern int nv50_instmem_init(struct drm_device *); | |
1224 | extern void nv50_instmem_takedown(struct drm_device *); | |
1225 | extern int nv50_instmem_suspend(struct drm_device *); | |
1226 | extern void nv50_instmem_resume(struct drm_device *); | |
e41115d0 BS |
1227 | extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align); |
1228 | extern void nv50_instmem_put(struct nouveau_gpuobj *); | |
1229 | extern int nv50_instmem_map(struct nouveau_gpuobj *); | |
1230 | extern void nv50_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1231 | extern void nv50_instmem_flush(struct drm_device *); |
734ee835 | 1232 | extern void nv84_instmem_flush(struct drm_device *); |
6ee73861 | 1233 | |
4b223eef BS |
1234 | /* nvc0_instmem.c */ |
1235 | extern int nvc0_instmem_init(struct drm_device *); | |
1236 | extern void nvc0_instmem_takedown(struct drm_device *); | |
1237 | extern int nvc0_instmem_suspend(struct drm_device *); | |
1238 | extern void nvc0_instmem_resume(struct drm_device *); | |
4b223eef | 1239 | |
6ee73861 BS |
1240 | /* nv04_mc.c */ |
1241 | extern int nv04_mc_init(struct drm_device *); | |
1242 | extern void nv04_mc_takedown(struct drm_device *); | |
1243 | ||
1244 | /* nv40_mc.c */ | |
1245 | extern int nv40_mc_init(struct drm_device *); | |
1246 | extern void nv40_mc_takedown(struct drm_device *); | |
1247 | ||
1248 | /* nv50_mc.c */ | |
1249 | extern int nv50_mc_init(struct drm_device *); | |
1250 | extern void nv50_mc_takedown(struct drm_device *); | |
1251 | ||
1252 | /* nv04_timer.c */ | |
1253 | extern int nv04_timer_init(struct drm_device *); | |
1254 | extern uint64_t nv04_timer_read(struct drm_device *); | |
1255 | extern void nv04_timer_takedown(struct drm_device *); | |
1256 | ||
1257 | extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, | |
1258 | unsigned long arg); | |
1259 | ||
1260 | /* nv04_dac.c */ | |
8f1a6086 | 1261 | extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); |
11d6eb2a | 1262 | extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); |
6ee73861 BS |
1263 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); |
1264 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); | |
8ccfe9e0 | 1265 | extern bool nv04_dac_in_use(struct drm_encoder *encoder); |
6ee73861 BS |
1266 | |
1267 | /* nv04_dfp.c */ | |
8f1a6086 | 1268 | extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1269 | extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); |
1270 | extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, | |
1271 | int head, bool dl); | |
1272 | extern void nv04_dfp_disable(struct drm_device *dev, int head); | |
1273 | extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); | |
1274 | ||
1275 | /* nv04_tv.c */ | |
1276 | extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); | |
8f1a6086 | 1277 | extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1278 | |
1279 | /* nv17_tv.c */ | |
8f1a6086 | 1280 | extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1281 | |
1282 | /* nv04_display.c */ | |
c88c2e06 FJ |
1283 | extern int nv04_display_early_init(struct drm_device *); |
1284 | extern void nv04_display_late_takedown(struct drm_device *); | |
6ee73861 | 1285 | extern int nv04_display_create(struct drm_device *); |
c88c2e06 | 1286 | extern int nv04_display_init(struct drm_device *); |
6ee73861 | 1287 | extern void nv04_display_destroy(struct drm_device *); |
6ee73861 BS |
1288 | |
1289 | /* nv04_crtc.c */ | |
1290 | extern int nv04_crtc_create(struct drm_device *, int index); | |
1291 | ||
1292 | /* nouveau_bo.c */ | |
1293 | extern struct ttm_bo_driver nouveau_bo_driver; | |
1294 | extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, | |
1295 | int size, int align, uint32_t flags, | |
1296 | uint32_t tile_mode, uint32_t tile_flags, | |
1297 | bool no_vm, bool mappable, struct nouveau_bo **); | |
1298 | extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); | |
1299 | extern int nouveau_bo_unpin(struct nouveau_bo *); | |
1300 | extern int nouveau_bo_map(struct nouveau_bo *); | |
1301 | extern void nouveau_bo_unmap(struct nouveau_bo *); | |
78ad0f7b FJ |
1302 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, |
1303 | uint32_t busy); | |
6ee73861 BS |
1304 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); |
1305 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); | |
1306 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); | |
1307 | extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); | |
332b242f | 1308 | extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); |
7a45d764 BS |
1309 | extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, |
1310 | bool no_wait_reserve, bool no_wait_gpu); | |
6ee73861 BS |
1311 | |
1312 | /* nouveau_fence.c */ | |
1313 | struct nouveau_fence; | |
0c6c1c2f FJ |
1314 | extern int nouveau_fence_init(struct drm_device *); |
1315 | extern void nouveau_fence_fini(struct drm_device *); | |
2730723b FJ |
1316 | extern int nouveau_fence_channel_init(struct nouveau_channel *); |
1317 | extern void nouveau_fence_channel_fini(struct nouveau_channel *); | |
6ee73861 BS |
1318 | extern void nouveau_fence_update(struct nouveau_channel *); |
1319 | extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, | |
1320 | bool emit); | |
1321 | extern int nouveau_fence_emit(struct nouveau_fence *); | |
8ac3891b FJ |
1322 | extern void nouveau_fence_work(struct nouveau_fence *fence, |
1323 | void (*work)(void *priv, bool signalled), | |
1324 | void *priv); | |
6ee73861 | 1325 | struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); |
382d62e5 MS |
1326 | |
1327 | extern bool __nouveau_fence_signalled(void *obj, void *arg); | |
1328 | extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); | |
1329 | extern int __nouveau_fence_flush(void *obj, void *arg); | |
1330 | extern void __nouveau_fence_unref(void **obj); | |
1331 | extern void *__nouveau_fence_ref(void *obj); | |
1332 | ||
1333 | static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) | |
1334 | { | |
1335 | return __nouveau_fence_signalled(obj, NULL); | |
1336 | } | |
1337 | static inline int | |
1338 | nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) | |
1339 | { | |
1340 | return __nouveau_fence_wait(obj, NULL, lazy, intr); | |
1341 | } | |
2730723b | 1342 | extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); |
382d62e5 MS |
1343 | static inline int nouveau_fence_flush(struct nouveau_fence *obj) |
1344 | { | |
1345 | return __nouveau_fence_flush(obj, NULL); | |
1346 | } | |
1347 | static inline void nouveau_fence_unref(struct nouveau_fence **obj) | |
1348 | { | |
1349 | __nouveau_fence_unref((void **)obj); | |
1350 | } | |
1351 | static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) | |
1352 | { | |
1353 | return __nouveau_fence_ref(obj); | |
1354 | } | |
6ee73861 BS |
1355 | |
1356 | /* nouveau_gem.c */ | |
1357 | extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *, | |
1358 | int size, int align, uint32_t flags, | |
1359 | uint32_t tile_mode, uint32_t tile_flags, | |
1360 | bool no_vm, bool mappable, struct nouveau_bo **); | |
1361 | extern int nouveau_gem_object_new(struct drm_gem_object *); | |
1362 | extern void nouveau_gem_object_del(struct drm_gem_object *); | |
1363 | extern int nouveau_gem_ioctl_new(struct drm_device *, void *, | |
1364 | struct drm_file *); | |
1365 | extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, | |
1366 | struct drm_file *); | |
6ee73861 BS |
1367 | extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, |
1368 | struct drm_file *); | |
1369 | extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, | |
1370 | struct drm_file *); | |
1371 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | |
1372 | struct drm_file *); | |
1373 | ||
042206c0 FJ |
1374 | /* nouveau_display.c */ |
1375 | int nouveau_vblank_enable(struct drm_device *dev, int crtc); | |
1376 | void nouveau_vblank_disable(struct drm_device *dev, int crtc); | |
332b242f FJ |
1377 | int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1378 | struct drm_pending_vblank_event *event); | |
1379 | int nouveau_finish_page_flip(struct nouveau_channel *, | |
1380 | struct nouveau_page_flip_state *); | |
042206c0 | 1381 | |
ee2e0131 BS |
1382 | /* nv10_gpio.c */ |
1383 | int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | |
1384 | int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
6ee73861 | 1385 | |
45284162 | 1386 | /* nv50_gpio.c */ |
ee2e0131 | 1387 | int nv50_gpio_init(struct drm_device *dev); |
2cbd4c81 | 1388 | void nv50_gpio_fini(struct drm_device *dev); |
45284162 BS |
1389 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1390 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
fce2bad0 BS |
1391 | int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, |
1392 | void (*)(void *, int), void *); | |
1393 | void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, | |
1394 | void (*)(void *, int), void *); | |
1395 | bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); | |
45284162 | 1396 | |
e9ebb68b BS |
1397 | /* nv50_calc. */ |
1398 | int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, | |
1399 | int *N1, int *M1, int *N2, int *M2, int *P); | |
1400 | int nv50_calc_pll2(struct drm_device *, struct pll_lims *, | |
1401 | int clk, int *N, int *fN, int *M, int *P); | |
1402 | ||
6ee73861 BS |
1403 | #ifndef ioread32_native |
1404 | #ifdef __BIG_ENDIAN | |
1405 | #define ioread16_native ioread16be | |
1406 | #define iowrite16_native iowrite16be | |
1407 | #define ioread32_native ioread32be | |
1408 | #define iowrite32_native iowrite32be | |
1409 | #else /* def __BIG_ENDIAN */ | |
1410 | #define ioread16_native ioread16 | |
1411 | #define iowrite16_native iowrite16 | |
1412 | #define ioread32_native ioread32 | |
1413 | #define iowrite32_native iowrite32 | |
1414 | #endif /* def __BIG_ENDIAN else */ | |
1415 | #endif /* !ioread32_native */ | |
1416 | ||
1417 | /* channel control reg access */ | |
1418 | static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) | |
1419 | { | |
1420 | return ioread32_native(chan->user + reg); | |
1421 | } | |
1422 | ||
1423 | static inline void nvchan_wr32(struct nouveau_channel *chan, | |
1424 | unsigned reg, u32 val) | |
1425 | { | |
1426 | iowrite32_native(val, chan->user + reg); | |
1427 | } | |
1428 | ||
1429 | /* register access */ | |
1430 | static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) | |
1431 | { | |
1432 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1433 | return ioread32_native(dev_priv->mmio + reg); | |
1434 | } | |
1435 | ||
1436 | static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) | |
1437 | { | |
1438 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1439 | iowrite32_native(val, dev_priv->mmio + reg); | |
1440 | } | |
1441 | ||
2a7fdb2b | 1442 | static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) |
49eed80a BS |
1443 | { |
1444 | u32 tmp = nv_rd32(dev, reg); | |
2a7fdb2b BS |
1445 | nv_wr32(dev, reg, (tmp & ~mask) | val); |
1446 | return tmp; | |
49eed80a BS |
1447 | } |
1448 | ||
6ee73861 BS |
1449 | static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) |
1450 | { | |
1451 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1452 | return ioread8(dev_priv->mmio + reg); | |
1453 | } | |
1454 | ||
1455 | static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) | |
1456 | { | |
1457 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1458 | iowrite8(val, dev_priv->mmio + reg); | |
1459 | } | |
1460 | ||
4b5c152a | 1461 | #define nv_wait(dev, reg, mask, val) \ |
12fb9525 BS |
1462 | nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) |
1463 | #define nv_wait_ne(dev, reg, mask, val) \ | |
1464 | nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) | |
6ee73861 BS |
1465 | |
1466 | /* PRAMIN access */ | |
1467 | static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) | |
1468 | { | |
1469 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1470 | return ioread32_native(dev_priv->ramin + offset); | |
1471 | } | |
1472 | ||
1473 | static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) | |
1474 | { | |
1475 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1476 | iowrite32_native(val, dev_priv->ramin + offset); | |
1477 | } | |
1478 | ||
1479 | /* object access */ | |
b3beb167 BS |
1480 | extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); |
1481 | extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); | |
6ee73861 BS |
1482 | |
1483 | /* | |
1484 | * Logging | |
1485 | * Argument d is (struct drm_device *). | |
1486 | */ | |
1487 | #define NV_PRINTK(level, d, fmt, arg...) \ | |
1488 | printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ | |
1489 | pci_name(d->pdev), ##arg) | |
1490 | #ifndef NV_DEBUG_NOTRACE | |
1491 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1492 | if (drm_debug & DRM_UT_DRIVER) { \ |
1493 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ | |
1494 | __LINE__, ##arg); \ | |
1495 | } \ | |
1496 | } while (0) | |
1497 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1498 | if (drm_debug & DRM_UT_KMS) { \ | |
6ee73861 BS |
1499 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ |
1500 | __LINE__, ##arg); \ | |
1501 | } \ | |
1502 | } while (0) | |
1503 | #else | |
1504 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1505 | if (drm_debug & DRM_UT_DRIVER) \ |
1506 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ | |
1507 | } while (0) | |
1508 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1509 | if (drm_debug & DRM_UT_KMS) \ | |
6ee73861 BS |
1510 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ |
1511 | } while (0) | |
1512 | #endif | |
1513 | #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) | |
1514 | #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1515 | #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) | |
1516 | #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1517 | #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) | |
1518 | ||
1519 | /* nouveau_reg_debug bitmask */ | |
1520 | enum { | |
1521 | NOUVEAU_REG_DEBUG_MC = 0x1, | |
1522 | NOUVEAU_REG_DEBUG_VIDEO = 0x2, | |
1523 | NOUVEAU_REG_DEBUG_FB = 0x4, | |
1524 | NOUVEAU_REG_DEBUG_EXTDEV = 0x8, | |
1525 | NOUVEAU_REG_DEBUG_CRTC = 0x10, | |
1526 | NOUVEAU_REG_DEBUG_RAMDAC = 0x20, | |
1527 | NOUVEAU_REG_DEBUG_VGACRTC = 0x40, | |
1528 | NOUVEAU_REG_DEBUG_RMVIO = 0x80, | |
1529 | NOUVEAU_REG_DEBUG_VGAATTR = 0x100, | |
1530 | NOUVEAU_REG_DEBUG_EVO = 0x200, | |
1531 | }; | |
1532 | ||
1533 | #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ | |
1534 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ | |
1535 | NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ | |
1536 | } while (0) | |
1537 | ||
1538 | static inline bool | |
1539 | nv_two_heads(struct drm_device *dev) | |
1540 | { | |
1541 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1542 | const int impl = dev->pci_device & 0x0ff0; | |
1543 | ||
1544 | if (dev_priv->card_type >= NV_10 && impl != 0x0100 && | |
1545 | impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) | |
1546 | return true; | |
1547 | ||
1548 | return false; | |
1549 | } | |
1550 | ||
1551 | static inline bool | |
1552 | nv_gf4_disp_arch(struct drm_device *dev) | |
1553 | { | |
1554 | return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; | |
1555 | } | |
1556 | ||
1557 | static inline bool | |
1558 | nv_two_reg_pll(struct drm_device *dev) | |
1559 | { | |
1560 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1561 | const int impl = dev->pci_device & 0x0ff0; | |
1562 | ||
1563 | if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) | |
1564 | return true; | |
1565 | return false; | |
1566 | } | |
1567 | ||
acae116c FJ |
1568 | static inline bool |
1569 | nv_match_device(struct drm_device *dev, unsigned device, | |
1570 | unsigned sub_vendor, unsigned sub_device) | |
1571 | { | |
1572 | return dev->pdev->device == device && | |
1573 | dev->pdev->subsystem_vendor == sub_vendor && | |
1574 | dev->pdev->subsystem_device == sub_device; | |
1575 | } | |
1576 | ||
c693931d BS |
1577 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, |
1578 | * helpful to determine a number of other hardware features | |
1579 | */ | |
1580 | static inline int | |
1581 | nv44_graph_class(struct drm_device *dev) | |
1582 | { | |
1583 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1584 | ||
1585 | if ((dev_priv->chipset & 0xf0) == 0x60) | |
1586 | return 1; | |
1587 | ||
1588 | return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); | |
1589 | } | |
1590 | ||
7f4a195f | 1591 | /* memory type/access flags, do not match hardware values */ |
a11c3198 BS |
1592 | #define NV_MEM_ACCESS_RO 1 |
1593 | #define NV_MEM_ACCESS_WO 2 | |
7f4a195f | 1594 | #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) |
a11c3198 BS |
1595 | #define NV_MEM_ACCESS_SYS 4 |
1596 | #define NV_MEM_ACCESS_VM 8 | |
7f4a195f BS |
1597 | |
1598 | #define NV_MEM_TARGET_VRAM 0 | |
1599 | #define NV_MEM_TARGET_PCI 1 | |
1600 | #define NV_MEM_TARGET_PCI_NOSNOOP 2 | |
1601 | #define NV_MEM_TARGET_VM 3 | |
1602 | #define NV_MEM_TARGET_GART 4 | |
1603 | ||
1604 | #define NV_MEM_TYPE_VM 0x7f | |
1605 | #define NV_MEM_COMP_VM 0x03 | |
1606 | ||
1607 | /* NV_SW object class */ | |
f03a314b FJ |
1608 | #define NV_SW 0x0000506e |
1609 | #define NV_SW_DMA_SEMAPHORE 0x00000060 | |
1610 | #define NV_SW_SEMAPHORE_OFFSET 0x00000064 | |
1611 | #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 | |
1612 | #define NV_SW_SEMAPHORE_RELEASE 0x0000006c | |
8af29ccd | 1613 | #define NV_SW_YIELD 0x00000080 |
f03a314b FJ |
1614 | #define NV_SW_DMA_VBLSEM 0x0000018c |
1615 | #define NV_SW_VBLSEM_OFFSET 0x00000400 | |
1616 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 | |
1617 | #define NV_SW_VBLSEM_RELEASE 0x00000408 | |
332b242f | 1618 | #define NV_SW_PAGE_FLIP 0x00000500 |
6ee73861 BS |
1619 | |
1620 | #endif /* __NOUVEAU_DRV_H__ */ |