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drm/nouveau: rework gpu-specific instmem interfaces
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
274fec93 57#include "nouveau_util.h"
054b93e4 58struct nouveau_grctx;
6ee73861
BS		 59
60#define MAX_NUM_DCB_ENTRIES 16
61
62#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 63#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 64
65#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
66#define NV50_VM_BLOCK (512*1024*1024ULL)
67#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
68
a0af9add 69struct nouveau_tile_reg {
a0af9add 70 bool used;
a5cf68b0
FJ		 71 uint32_t addr;
72 uint32_t limit;
73 uint32_t pitch;
87a326a3
FJ		 74 uint32_t zcomp;
75 struct drm_mm_node *tag_mem;
a5cf68b0 76 struct nouveau_fence *fence;
a0af9add
FJ		 77};
78
6ee73861
BS		 79struct nouveau_bo {
80 struct ttm_buffer_object bo;
81 struct ttm_placement placement;
82 u32 placements[3];
78ad0f7b 83 u32 busy_placements[3];
6ee73861
BS		 84 struct ttm_bo_kmap_obj kmap;
85 struct list_head head;
86
87 /* protected by ttm_bo_reserve() */
88 struct drm_file *reserved_by;
89 struct list_head entry;
90 int pbbo_index;
a1606a95 91 bool validate_mapped;
6ee73861
BS		 92
93 struct nouveau_channel *channel;
94
95 bool mappable;
96 bool no_vm;
97
98 uint32_t tile_mode;
99 uint32_t tile_flags;
a0af9add 100 struct nouveau_tile_reg *tile;
6ee73861
BS		 101
102 struct drm_gem_object *gem;
6ee73861
BS		 103 int pin_refcnt;
104};
105
f13b3263
FJ		 106#define nouveau_bo_tile_layout(nvbo) \
107 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
108
6ee73861
BS		 109static inline struct nouveau_bo *
110nouveau_bo(struct ttm_buffer_object *bo)
111{
112 return container_of(bo, struct nouveau_bo, bo);
113}
114
115static inline struct nouveau_bo *
116nouveau_gem_object(struct drm_gem_object *gem)
117{
118 return gem ? gem->driver_private : NULL;
119}
120
121/* TODO: submit equivalent to TTM generic API upstream? */
122static inline void __iomem *
123nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
124{
125 bool is_iomem;
126 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
127 &nvbo->kmap, &is_iomem);
128 WARN_ON_ONCE(ioptr && !is_iomem);
129 return ioptr;
130}
131
6ee73861
BS		 132enum nouveau_flags {
133 NV_NFORCE = 0x10000000,
134 NV_NFORCE2 = 0x20000000
135};
136
137#define NVOBJ_ENGINE_SW 0
138#define NVOBJ_ENGINE_GR 1
bd2e597d
BS		 139#define NVOBJ_ENGINE_PPP 2
140#define NVOBJ_ENGINE_COPY 3
141#define NVOBJ_ENGINE_VP 4
142#define NVOBJ_ENGINE_CRYPT 5
143#define NVOBJ_ENGINE_BSP 6
50536946 144#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
6ee73861
BS		 145#define NVOBJ_ENGINE_INT 0xdeadbeef
146
6ee73861
BS		 147#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
148#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
e41115d0
BS		 149
150#define NVOBJ_CINST_GLOBAL 0xdeadbeef
151
6ee73861 152struct nouveau_gpuobj {
b3beb167 153 struct drm_device *dev;
eb9bcbdc 154 struct kref refcount;
6ee73861
BS		 155 struct list_head list;
156
e41115d0 157 void *node;
dc1e5c0d 158 u32 *suspend;
6ee73861
BS		 159
160 uint32_t flags;
6ee73861 161
43efc9ce 162 u32 size;
de3a6c0a
BS		 163 u32 pinst;
164 u32 cinst;
165 u64 vinst;
166
6ee73861
BS		 167 uint32_t engine;
168 uint32_t class;
169
170 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
171 void *priv;
172};
173
332b242f
FJ		 174struct nouveau_page_flip_state {
175 struct list_head head;
176 struct drm_pending_vblank_event *event;
177 int crtc, bpp, pitch, x, y;
178 uint64_t offset;
179};
180
e419cf09
FJ		 181enum nouveau_channel_mutex_class {
182 NOUVEAU_UCHANNEL_MUTEX,
183 NOUVEAU_KCHANNEL_MUTEX
184};
185
6ee73861
BS		 186struct nouveau_channel {
187 struct drm_device *dev;
188 int id;
189
f091a3d4
FJ		 190 /* references to the channel data structure */
191 struct kref ref;
192 /* users of the hardware channel resources, the hardware
193 * context will be kicked off when it reaches zero. */
194 atomic_t users;
6a6b73f2
BS		 195 struct mutex mutex;
196
6ee73861
BS		 197 /* owner of this fifo */
198 struct drm_file *file_priv;
199 /* mapping of the fifo itself */
200 struct drm_local_map *map;
201
202 /* mapping of the regs controling the fifo */
203 void __iomem *user;
204 uint32_t user_get;
205 uint32_t user_put;
206
207 /* Fencing */
208 struct {
209 /* lock protects the pending list only */
210 spinlock_t lock;
211 struct list_head pending;
212 uint32_t sequence;
213 uint32_t sequence_ack;
047d1d3c 214 atomic_t last_sequence_irq;
6ee73861
BS		 215 } fence;
216
217 /* DMA push buffer */
a8eaebc6
BS		 218 struct nouveau_gpuobj *pushbuf;
219 struct nouveau_bo *pushbuf_bo;
220 uint32_t pushbuf_base;
6ee73861
BS		 221
222 /* Notifier memory */
223 struct nouveau_bo *notifier_bo;
b833ac26 224 struct drm_mm notifier_heap;
6ee73861
BS		 225
226 /* PFIFO context */
a8eaebc6
BS		 227 struct nouveau_gpuobj *ramfc;
228 struct nouveau_gpuobj *cache;
6ee73861
BS		 229
230 /* PGRAPH context */
231 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 232 struct nouveau_gpuobj *ramin_grctx;
bd2e597d 233 struct nouveau_gpuobj *crypt_ctx;
6ee73861
BS		 234 void *pgraph_ctx;
235
236 /* NV50 VM */
a8eaebc6
BS		 237 struct nouveau_gpuobj *vm_pd;
238 struct nouveau_gpuobj *vm_gart_pt;
239 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 240
241 /* Objects */
a8eaebc6
BS		 242 struct nouveau_gpuobj *ramin; /* Private instmem */
243 struct drm_mm ramin_heap; /* Private PRAMIN heap */
244 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 245
246 /* GPU object info for stuff used in-kernel (mm_enabled) */
247 uint32_t m2mf_ntfy;
248 uint32_t vram_handle;
249 uint32_t gart_handle;
250 bool accel_done;
251
252 /* Push buffer state (only for drm's channel on !mm_enabled) */
253 struct {
254 int max;
255 int free;
256 int cur;
257 int put;
258 /* access via pushbuf_bo */
9a391ad8
BS		 259
260 int ib_base;
261 int ib_max;
262 int ib_free;
263 int ib_put;
6ee73861
BS		 264 } dma;
265
266 uint32_t sw_subchannel[8];
267
268 struct {
269 struct nouveau_gpuobj *vblsem;
1f6d2de2 270 uint32_t vblsem_head;
6ee73861
BS		 271 uint32_t vblsem_offset;
272 uint32_t vblsem_rval;
273 struct list_head vbl_wait;
332b242f 274 struct list_head flip;
6ee73861
BS		 275 } nvsw;
276
277 struct {
278 bool active;
279 char name[32];
280 struct drm_info_list info;
281 } debugfs;
282};
283
284struct nouveau_instmem_engine {
285 void *priv;
286
287 int (*init)(struct drm_device *dev);
288 void (*takedown)(struct drm_device *dev);
289 int (*suspend)(struct drm_device *dev);
290 void (*resume)(struct drm_device *dev);
291
e41115d0
BS		 292 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
293 void (*put)(struct nouveau_gpuobj *);
294 int (*map)(struct nouveau_gpuobj *);
295 void (*unmap)(struct nouveau_gpuobj *);
296
f56cb86f 297 void (*flush)(struct drm_device *);
6ee73861
BS		 298};
299
300struct nouveau_mc_engine {
301 int (*init)(struct drm_device *dev);
302 void (*takedown)(struct drm_device *dev);
303};
304
305struct nouveau_timer_engine {
306 int (*init)(struct drm_device *dev);
307 void (*takedown)(struct drm_device *dev);
308 uint64_t (*read)(struct drm_device *dev);
309};
310
311struct nouveau_fb_engine {
cb00f7c1 312 int num_tiles;
87a326a3 313 struct drm_mm tag_heap;
cb00f7c1 314
6ee73861
BS		 315 int (*init)(struct drm_device *dev);
316 void (*takedown)(struct drm_device *dev);
cb00f7c1 317
a5cf68b0
FJ		 318 void (*init_tile_region)(struct drm_device *dev, int i,
319 uint32_t addr, uint32_t size,
320 uint32_t pitch, uint32_t flags);
321 void (*set_tile_region)(struct drm_device *dev, int i);
322 void (*free_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 323};
324
325struct nouveau_fifo_engine {
6ee73861
BS		 326 int channels;
327
a8eaebc6 328 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 329 int cur_playlist;
330
6ee73861
BS		 331 int (*init)(struct drm_device *);
332 void (*takedown)(struct drm_device *);
333
334 void (*disable)(struct drm_device *);
335 void (*enable)(struct drm_device *);
336 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 337 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 338
339 int (*channel_id)(struct drm_device *);
340
341 int (*create_context)(struct nouveau_channel *);
342 void (*destroy_context)(struct nouveau_channel *);
343 int (*load_context)(struct nouveau_channel *);
344 int (*unload_context)(struct drm_device *);
56ac7475 345 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 346};
347
6ee73861 348struct nouveau_pgraph_engine {
6ee73861 349 bool accel_blocked;
b8c157d3 350 bool registered;
054b93e4 351 int grctx_size;
6ee73861 352
c50a5681 353 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 354 struct nouveau_gpuobj *ctx_table;
c50a5681 355
6ee73861
BS		 356 int (*init)(struct drm_device *);
357 void (*takedown)(struct drm_device *);
358
359 void (*fifo_access)(struct drm_device *, bool);
360
361 struct nouveau_channel *(*channel)(struct drm_device *);
362 int (*create_context)(struct nouveau_channel *);
363 void (*destroy_context)(struct nouveau_channel *);
364 int (*load_context)(struct nouveau_channel *);
365 int (*unload_context)(struct drm_device *);
56ac7475 366 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1 367
a5cf68b0 368 void (*set_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 369};
370
c88c2e06
FJ		 371struct nouveau_display_engine {
372 int (*early_init)(struct drm_device *);
373 void (*late_takedown)(struct drm_device *);
374 int (*create)(struct drm_device *);
375 int (*init)(struct drm_device *);
376 void (*destroy)(struct drm_device *);
377};
378
ee2e0131 379struct nouveau_gpio_engine {
fce2bad0
BS		 380 void *priv;
381
ee2e0131
BS		 382 int (*init)(struct drm_device *);
383 void (*takedown)(struct drm_device *);
384
385 int (*get)(struct drm_device *, enum dcb_gpio_tag);
386 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
387
fce2bad0
BS		 388 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
389 void (*)(void *, int), void *);
390 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
391 void (*)(void *, int), void *);
392 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
ee2e0131
BS		 393};
394
330c5988
BS		 395struct nouveau_pm_voltage_level {
396 u8 voltage;
397 u8 vid;
398};
399
400struct nouveau_pm_voltage {
401 bool supported;
402 u8 vid_mask;
403
404 struct nouveau_pm_voltage_level *level;
405 int nr_level;
406};
407
408#define NOUVEAU_PM_MAX_LEVEL 8
409struct nouveau_pm_level {
410 struct device_attribute dev_attr;
411 char name[32];
412 int id;
413
414 u32 core;
415 u32 memory;
416 u32 shader;
417 u32 unk05;
418
419 u8 voltage;
420 u8 fanspeed;
aee582de
BS		 421
422 u16 memscript;
330c5988
BS		 423};
424
34e9d85a
MP		 425struct nouveau_pm_temp_sensor_constants {
426 u16 offset_constant;
427 s16 offset_mult;
428 u16 offset_div;
429 u16 slope_mult;
430 u16 slope_div;
431};
432
433struct nouveau_pm_threshold_temp {
434 s16 critical;
435 s16 down_clock;
436 s16 fan_boost;
437};
438
7760fcb0
RS		 439struct nouveau_pm_memtiming {
440 u32 reg_100220;
441 u32 reg_100224;
442 u32 reg_100228;
443 u32 reg_10022c;
444 u32 reg_100230;
445 u32 reg_100234;
446 u32 reg_100238;
447 u32 reg_10023c;
448};
449
450struct nouveau_pm_memtimings {
451 bool supported;
452 struct nouveau_pm_memtiming *timing;
453 int nr_timing;
454};
455
330c5988
BS		 456struct nouveau_pm_engine {
457 struct nouveau_pm_voltage voltage;
458 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
459 int nr_perflvl;
7760fcb0 460 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 461 struct nouveau_pm_temp_sensor_constants sensor_constants;
462 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 463
464 struct nouveau_pm_level boot;
465 struct nouveau_pm_level *cur;
466
8155cac4 467 struct device *hwmon;
6032649d 468 struct notifier_block acpi_nb;
8155cac4 469
330c5988 470 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 471 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
472 u32 id, int khz);
330c5988
BS		 473 void (*clock_set)(struct drm_device *, void *);
474 int (*voltage_get)(struct drm_device *);
475 int (*voltage_set)(struct drm_device *, int voltage);
476 int (*fanspeed_get)(struct drm_device *);
477 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 478 int (*temp_get)(struct drm_device *);
330c5988
BS		 479};
480
bd2e597d
BS		 481struct nouveau_crypt_engine {
482 bool registered;
483
484 int (*init)(struct drm_device *);
485 void (*takedown)(struct drm_device *);
486 int (*create_context)(struct nouveau_channel *);
487 void (*destroy_context)(struct nouveau_channel *);
488 void (*tlb_flush)(struct drm_device *dev);
489};
490
6ee73861
BS		 491struct nouveau_engine {
492 struct nouveau_instmem_engine instmem;
493 struct nouveau_mc_engine mc;
494 struct nouveau_timer_engine timer;
495 struct nouveau_fb_engine fb;
496 struct nouveau_pgraph_engine graph;
497 struct nouveau_fifo_engine fifo;
c88c2e06 498 struct nouveau_display_engine display;
ee2e0131 499 struct nouveau_gpio_engine gpio;
330c5988 500 struct nouveau_pm_engine pm;
bd2e597d 501 struct nouveau_crypt_engine crypt;
6ee73861
BS		 502};
503
504struct nouveau_pll_vals {
505 union {
506 struct {
507#ifdef __BIG_ENDIAN
508 uint8_t N1, M1, N2, M2;
509#else
510 uint8_t M1, N1, M2, N2;
511#endif
512 };
513 struct {
514 uint16_t NM1, NM2;
515 } __attribute__((packed));
516 };
517 int log2P;
518
519 int refclk;
520};
521
522enum nv04_fp_display_regs {
523 FP_DISPLAY_END,
524 FP_TOTAL,
525 FP_CRTC,
526 FP_SYNC_START,
527 FP_SYNC_END,
528 FP_VALID_START,
529 FP_VALID_END
530};
531
532struct nv04_crtc_reg {
cbab95db 533 unsigned char MiscOutReg;
4a9f822f 534 uint8_t CRTC[0xa0];
6ee73861
BS		 535 uint8_t CR58[0x10];
536 uint8_t Sequencer[5];
537 uint8_t Graphics[9];
538 uint8_t Attribute[21];
cbab95db 539 unsigned char DAC[768];
6ee73861
BS		 540
541 /* PCRTC regs */
542 uint32_t fb_start;
543 uint32_t crtc_cfg;
544 uint32_t cursor_cfg;
545 uint32_t gpio_ext;
546 uint32_t crtc_830;
547 uint32_t crtc_834;
548 uint32_t crtc_850;
549 uint32_t crtc_eng_ctrl;
550
551 /* PRAMDAC regs */
552 uint32_t nv10_cursync;
553 struct nouveau_pll_vals pllvals;
554 uint32_t ramdac_gen_ctrl;
555 uint32_t ramdac_630;
556 uint32_t ramdac_634;
557 uint32_t tv_setup;
558 uint32_t tv_vtotal;
559 uint32_t tv_vskew;
560 uint32_t tv_vsync_delay;
561 uint32_t tv_htotal;
562 uint32_t tv_hskew;
563 uint32_t tv_hsync_delay;
564 uint32_t tv_hsync_delay2;
565 uint32_t fp_horiz_regs[7];
566 uint32_t fp_vert_regs[7];
567 uint32_t dither;
568 uint32_t fp_control;
569 uint32_t dither_regs[6];
570 uint32_t fp_debug_0;
571 uint32_t fp_debug_1;
572 uint32_t fp_debug_2;
573 uint32_t fp_margin_color;
574 uint32_t ramdac_8c0;
575 uint32_t ramdac_a20;
576 uint32_t ramdac_a24;
577 uint32_t ramdac_a34;
578 uint32_t ctv_regs[38];
579};
580
581struct nv04_output_reg {
582 uint32_t output;
583 int head;
584};
585
586struct nv04_mode_state {
cbab95db 587 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 588 uint32_t pllsel;
589 uint32_t sel_clk;
6ee73861
BS		 590};
591
592enum nouveau_card_type {
593 NV_04 = 0x00,
594 NV_10 = 0x10,
595 NV_20 = 0x20,
596 NV_30 = 0x30,
597 NV_40 = 0x40,
598 NV_50 = 0x50,
4b223eef 599 NV_C0 = 0xc0,
6ee73861
BS		 600};
601
602struct drm_nouveau_private {
603 struct drm_device *dev;
6ee73861
BS		 604
605 /* the card type, takes NV_* as values */
606 enum nouveau_card_type card_type;
607 /* exact chipset, derived from NV_PMC_BOOT_0 */
608 int chipset;
609 int flags;
610
611 void __iomem *mmio;
5125bfd8 612
e05d7eae 613 spinlock_t ramin_lock;
6ee73861 614 void __iomem *ramin;
5125bfd8
BS		 615 u32 ramin_size;
616 u32 ramin_base;
617 bool ramin_available;
e05d7eae
BS		 618 struct drm_mm ramin_heap;
619 struct list_head gpuobj_list;
b8c157d3 620 struct list_head classes;
6ee73861 621
ac8fb975
BS		 622 struct nouveau_bo *vga_ram;
623
35fa2f2a 624 /* interrupt handling */
8f8a5448 625 void (*irq_handler[32])(struct drm_device *);
35fa2f2a 626 bool msi_enabled;
6ee73861
BS		 627 struct workqueue_struct *wq;
628 struct work_struct irq_work;
ab838338 629
6ee73861
BS		 630 struct list_head vbl_waiting;
631
632 struct {
ba4420c2 633 struct drm_global_reference mem_global_ref;
6ee73861
BS		 634 struct ttm_bo_global_ref bo_global_ref;
635 struct ttm_bo_device bdev;
6ee73861
BS		 636 atomic_t validate_sequence;
637 } ttm;
638
0c6c1c2f
FJ		 639 struct {
640 spinlock_t lock;
641 struct drm_mm heap;
642 struct nouveau_bo *bo;
643 } fence;
644
cff5c133
BS		 645 struct {
646 spinlock_t lock;
647 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
648 } channels;
6ee73861
BS		 649
650 struct nouveau_engine engine;
651 struct nouveau_channel *channel;
652
ff9e5279
MM		 653 /* For PFIFO and PGRAPH. */
654 spinlock_t context_switch_lock;
655
6ee73861 656 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 657 struct nouveau_ramht *ramht;
658 struct nouveau_gpuobj *ramfc;
659 struct nouveau_gpuobj *ramro;
660
6ee73861 661 uint32_t ramin_rsvd_vram;
6ee73861 662
6ee73861
BS		 663 struct {
664 enum {
665 NOUVEAU_GART_NONE = 0,
666 NOUVEAU_GART_AGP,
667 NOUVEAU_GART_SGDMA
668 } type;
669 uint64_t aper_base;
670 uint64_t aper_size;
671 uint64_t aper_free;
672
673 struct nouveau_gpuobj *sg_ctxdma;
674 struct page *sg_dummy_page;
675 dma_addr_t sg_dummy_bus;
6ee73861
BS		 676 } gart_info;
677
a0af9add 678 /* nv10-nv40 tiling regions */
a5cf68b0
FJ		 679 struct {
680 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
681 spinlock_t lock;
682 } tile;
a0af9add 683
a76fb4e8
BS		 684 /* VRAM/fb configuration */
685 uint64_t vram_size;
686 uint64_t vram_sys_base;
6c3d7ef2 687 u32 vram_rblock_size;
a76fb4e8
BS		 688
689 uint64_t fb_phys;
690 uint64_t fb_available_size;
691 uint64_t fb_mappable_pages;
692 uint64_t fb_aper_free;
693 int fb_mtrr;
694
6ee73861
BS		 695 /* G8x/G9x virtual address space */
696 uint64_t vm_gart_base;
697 uint64_t vm_gart_size;
698 uint64_t vm_vram_base;
699 uint64_t vm_vram_size;
700 uint64_t vm_end;
701 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
702 int vm_vram_pt_nr;
6ee73861 703
04a39c57 704 struct nvbios vbios;
6ee73861
BS		 705
706 struct nv04_mode_state mode_reg;
707 struct nv04_mode_state saved_reg;
708 uint32_t saved_vga_font[4][16384];
709 uint32_t crtc_owner;
710 uint32_t dac_users[4];
711
712 struct nouveau_suspend_resume {
6ee73861 713 uint32_t *ramin_copy;
6ee73861
BS		 714 } susres;
715
716 struct backlight_device *backlight;
6ee73861
BS		 717
718 struct nouveau_channel *evo;
1e96268a 719 u32 evo_alloc;
87c0e0e5
BS		 720 struct {
721 struct dcb_entry *dcb;
722 u16 script;
723 u32 pclk;
724 } evo_irq;
6ee73861
BS		 725
726 struct {
727 struct dentry *channel_root;
728 } debugfs;
38651674 729
8be48d92 730 struct nouveau_fbdev *nfbdev;
06415c56 731 struct apertures_struct *apertures;
6ee73861
BS		 732};
733
2730723b
FJ		 734static inline struct drm_nouveau_private *
735nouveau_private(struct drm_device *dev)
736{
737 return dev->dev_private;
738}
739
6ee73861
BS		 740static inline struct drm_nouveau_private *
741nouveau_bdev(struct ttm_bo_device *bd)
742{
743 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
744}
745
746static inline int
747nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
748{
749 struct nouveau_bo *prev;
750
751 if (!pnvbo)
752 return -EINVAL;
753 prev = *pnvbo;
754
755 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
756 if (prev) {
757 struct ttm_buffer_object *bo = &prev->bo;
758
759 ttm_bo_unref(&bo);
760 }
761
762 return 0;
763}
764
6ee73861 765/* nouveau_drv.c */
de5899bd 766extern int nouveau_agpmode;
6ee73861
BS		 767extern int nouveau_duallink;
768extern int nouveau_uscript_lvds;
769extern int nouveau_uscript_tmds;
770extern int nouveau_vram_pushbuf;
771extern int nouveau_vram_notify;
772extern int nouveau_fbpercrtc;
f4053509 773extern int nouveau_tv_disable;
6ee73861
BS		 774extern char *nouveau_tv_norm;
775extern int nouveau_reg_debug;
776extern char *nouveau_vbios;
a1470890 777extern int nouveau_ignorelid;
a32ed69d
MK		 778extern int nouveau_nofbaccel;
779extern int nouveau_noaccel;
0cba1b76 780extern int nouveau_force_post;
da647d5b 781extern int nouveau_override_conntype;
6f876986
BS		 782extern char *nouveau_perflvl;
783extern int nouveau_perflvl_wr;
35fa2f2a 784extern int nouveau_msi;
6ee73861 785
6a9ee8af
DA		 786extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
787extern int nouveau_pci_resume(struct pci_dev *pdev);
788
6ee73861
BS		 789/* nouveau_state.c */
790extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
791extern int nouveau_load(struct drm_device *, unsigned long flags);
792extern int nouveau_firstopen(struct drm_device *);
793extern void nouveau_lastclose(struct drm_device *);
794extern int nouveau_unload(struct drm_device *);
795extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
796 struct drm_file *);
797extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
798 struct drm_file *);
799extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
800 uint32_t reg, uint32_t mask, uint32_t val);
801extern bool nouveau_wait_for_idle(struct drm_device *);
802extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 803
804/* nouveau_mem.c */
fbd2895e
BS		 805extern int nouveau_mem_vram_init(struct drm_device *);
806extern void nouveau_mem_vram_fini(struct drm_device *);
807extern int nouveau_mem_gart_init(struct drm_device *);
808extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 809extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 810extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 811extern void nouveau_mem_close(struct drm_device *);
a5cf68b0
FJ		 812extern struct nouveau_tile_reg *nv10_mem_set_tiling(
813 struct drm_device *dev, uint32_t addr, uint32_t size,
814 uint32_t pitch, uint32_t flags);
815extern void nv10_mem_put_tile_region(struct drm_device *dev,
816 struct nouveau_tile_reg *tile,
817 struct nouveau_fence *fence);
6ee73861
BS		 818extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
819 uint32_t size, uint32_t flags,
820 uint64_t phys);
821extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
822 uint32_t size);
823
824/* nouveau_notifier.c */
825extern int nouveau_notifier_init_channel(struct nouveau_channel *);
826extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
827extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
828 int cout, uint32_t *offset);
829extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
830extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
831 struct drm_file *);
832extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
833 struct drm_file *);
834
835/* nouveau_channel.c */
836extern struct drm_ioctl_desc nouveau_ioctls[];
837extern int nouveau_max_ioctl;
838extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 839extern int nouveau_channel_alloc(struct drm_device *dev,
840 struct nouveau_channel **chan,
841 struct drm_file *file_priv,
842 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 843extern struct nouveau_channel *
feeb0aec
FJ		 844nouveau_channel_get_unlocked(struct nouveau_channel *);
845extern struct nouveau_channel *
cff5c133 846nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 847extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 848extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 849extern void nouveau_channel_ref(struct nouveau_channel *chan,
850 struct nouveau_channel **pchan);
6ee73861
BS		 851
852/* nouveau_object.c */
b8c157d3
BS		 853#define NVOBJ_CLASS(d,c,e) do { \
854 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
855 if (ret) \
856 return ret; \
857} while(0)
858
859#define NVOBJ_MTHD(d,c,m,e) do { \
860 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
861 if (ret) \
862 return ret; \
863} while(0)
864
6ee73861
BS		 865extern int nouveau_gpuobj_early_init(struct drm_device *);
866extern int nouveau_gpuobj_init(struct drm_device *);
867extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861 868extern int nouveau_gpuobj_suspend(struct drm_device *dev);
6ee73861 869extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS		 870extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
871extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
872 int (*exec)(struct nouveau_channel *,
873 u32 class, u32 mthd, u32 data));
874extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
274fec93 875extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
6ee73861
BS		 876extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
877 uint32_t vram_h, uint32_t tt_h);
878extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
879extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
880 uint32_t size, int align, uint32_t flags,
881 struct nouveau_gpuobj **);
a8eaebc6
BS		 882extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
883 struct nouveau_gpuobj **);
43efc9ce
BS		 884extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
885 u32 size, u32 flags,
a8eaebc6 886 struct nouveau_gpuobj **);
6ee73861
BS		 887extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
888 uint64_t offset, uint64_t size, int access,
889 int target, struct nouveau_gpuobj **);
890extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
891 uint64_t offset, uint64_t size,
892 int access, struct nouveau_gpuobj **,
893 uint32_t *o_ret);
894extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
895 struct nouveau_gpuobj **);
896extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
897 struct drm_file *);
898extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
899 struct drm_file *);
900
901/* nouveau_irq.c */
35fa2f2a
BS		 902extern int nouveau_irq_init(struct drm_device *);
903extern void nouveau_irq_fini(struct drm_device *);
6ee73861 904extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
8f8a5448
BS		 905extern void nouveau_irq_register(struct drm_device *, int status_bit,
906 void (*)(struct drm_device *));
907extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
6ee73861
BS		 908extern void nouveau_irq_preinstall(struct drm_device *);
909extern int nouveau_irq_postinstall(struct drm_device *);
910extern void nouveau_irq_uninstall(struct drm_device *);
911
912/* nouveau_sgdma.c */
913extern int nouveau_sgdma_init(struct drm_device *);
914extern void nouveau_sgdma_takedown(struct drm_device *);
915extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
916 uint32_t *page);
917extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
918
919/* nouveau_debugfs.c */
920#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
921extern int nouveau_debugfs_init(struct drm_minor *);
922extern void nouveau_debugfs_takedown(struct drm_minor *);
923extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
924extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
925#else
926static inline int
927nouveau_debugfs_init(struct drm_minor *minor)
928{
929 return 0;
930}
931
932static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
933{
934}
935
936static inline int
937nouveau_debugfs_channel_init(struct nouveau_channel *chan)
938{
939 return 0;
940}
941
942static inline void
943nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
944{
945}
946#endif
947
948/* nouveau_dma.c */
75c99da6 949extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 950extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 951extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 952
953/* nouveau_acpi.c */
afeb3e11 954#define ROM_BIOS_PAGE 4096
2f41a7f1 955#if defined(CONFIG_ACPI)
6a9ee8af
DA		 956void nouveau_register_dsm_handler(void);
957void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 958int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
959bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 960int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 961#else
962static inline void nouveau_register_dsm_handler(void) {}
963static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 964static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
965static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 966static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 967#endif
6ee73861
BS		 968
969/* nouveau_backlight.c */
970#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
971extern int nouveau_backlight_init(struct drm_device *);
972extern void nouveau_backlight_exit(struct drm_device *);
973#else
974static inline int nouveau_backlight_init(struct drm_device *dev)
975{
976 return 0;
977}
978
979static inline void nouveau_backlight_exit(struct drm_device *dev) { }
980#endif
981
982/* nouveau_bios.c */
983extern int nouveau_bios_init(struct drm_device *);
984extern void nouveau_bios_takedown(struct drm_device *dev);
985extern int nouveau_run_vbios_init(struct drm_device *);
986extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
987 struct dcb_entry *);
988extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
989 enum dcb_gpio_tag);
990extern struct dcb_connector_table_entry *
991nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 992extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 993extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
994 struct pll_lims *);
995extern int nouveau_bios_run_display_table(struct drm_device *,
996 struct dcb_entry *,
997 uint32_t script, int pxclk);
998extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
999 int *length);
1000extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1001extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1002extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1003 bool *dl, bool *if_is_24bit);
1004extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1005 int head, int pxclk);
1006extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1007 enum LVDS_script, int pxclk);
1008
1009/* nouveau_ttm.c */
1010int nouveau_ttm_global_init(struct drm_nouveau_private *);
1011void nouveau_ttm_global_release(struct drm_nouveau_private *);
1012int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1013
1014/* nouveau_dp.c */
1015int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1016 uint8_t *data, int data_nr);
1017bool nouveau_dp_detect(struct drm_encoder *);
1018bool nouveau_dp_link_train(struct drm_encoder *);
1019
1020/* nv04_fb.c */
1021extern int nv04_fb_init(struct drm_device *);
1022extern void nv04_fb_takedown(struct drm_device *);
1023
1024/* nv10_fb.c */
1025extern int nv10_fb_init(struct drm_device *);
1026extern void nv10_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1027extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1028 uint32_t addr, uint32_t size,
1029 uint32_t pitch, uint32_t flags);
1030extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1031extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
6ee73861 1032
8bded189
FJ		 1033/* nv30_fb.c */
1034extern int nv30_fb_init(struct drm_device *);
1035extern void nv30_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1036extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1037 uint32_t addr, uint32_t size,
1038 uint32_t pitch, uint32_t flags);
1039extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
8bded189 1040
6ee73861
BS		 1041/* nv40_fb.c */
1042extern int nv40_fb_init(struct drm_device *);
1043extern void nv40_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1044extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1045
304424e1
MK		 1046/* nv50_fb.c */
1047extern int nv50_fb_init(struct drm_device *);
1048extern void nv50_fb_takedown(struct drm_device *);
d96773e7 1049extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 1050
4b223eef
BS		 1051/* nvc0_fb.c */
1052extern int nvc0_fb_init(struct drm_device *);
1053extern void nvc0_fb_takedown(struct drm_device *);
1054
6ee73861
BS		 1055/* nv04_fifo.c */
1056extern int nv04_fifo_init(struct drm_device *);
5178d40d 1057extern void nv04_fifo_fini(struct drm_device *);
6ee73861
BS		 1058extern void nv04_fifo_disable(struct drm_device *);
1059extern void nv04_fifo_enable(struct drm_device *);
1060extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1061extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1062extern int nv04_fifo_channel_id(struct drm_device *);
1063extern int nv04_fifo_create_context(struct nouveau_channel *);
1064extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1065extern int nv04_fifo_load_context(struct nouveau_channel *);
1066extern int nv04_fifo_unload_context(struct drm_device *);
5178d40d 1067extern void nv04_fifo_isr(struct drm_device *);
6ee73861
BS		 1068
1069/* nv10_fifo.c */
1070extern int nv10_fifo_init(struct drm_device *);
1071extern int nv10_fifo_channel_id(struct drm_device *);
1072extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1073extern int nv10_fifo_load_context(struct nouveau_channel *);
1074extern int nv10_fifo_unload_context(struct drm_device *);
1075
1076/* nv40_fifo.c */
1077extern int nv40_fifo_init(struct drm_device *);
1078extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1079extern int nv40_fifo_load_context(struct nouveau_channel *);
1080extern int nv40_fifo_unload_context(struct drm_device *);
1081
1082/* nv50_fifo.c */
1083extern int nv50_fifo_init(struct drm_device *);
1084extern void nv50_fifo_takedown(struct drm_device *);
1085extern int nv50_fifo_channel_id(struct drm_device *);
1086extern int nv50_fifo_create_context(struct nouveau_channel *);
1087extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1088extern int nv50_fifo_load_context(struct nouveau_channel *);
1089extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1090extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1091
4b223eef
BS		 1092/* nvc0_fifo.c */
1093extern int nvc0_fifo_init(struct drm_device *);
1094extern void nvc0_fifo_takedown(struct drm_device *);
1095extern void nvc0_fifo_disable(struct drm_device *);
1096extern void nvc0_fifo_enable(struct drm_device *);
1097extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1098extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1099extern int nvc0_fifo_channel_id(struct drm_device *);
1100extern int nvc0_fifo_create_context(struct nouveau_channel *);
1101extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1102extern int nvc0_fifo_load_context(struct nouveau_channel *);
1103extern int nvc0_fifo_unload_context(struct drm_device *);
1104
6ee73861 1105/* nv04_graph.c */
6ee73861
BS		 1106extern int nv04_graph_init(struct drm_device *);
1107extern void nv04_graph_takedown(struct drm_device *);
1108extern void nv04_graph_fifo_access(struct drm_device *, bool);
1109extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1110extern int nv04_graph_create_context(struct nouveau_channel *);
1111extern void nv04_graph_destroy_context(struct nouveau_channel *);
1112extern int nv04_graph_load_context(struct nouveau_channel *);
1113extern int nv04_graph_unload_context(struct drm_device *);
332b242f
FJ		 1114extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1115 u32 class, u32 mthd, u32 data);
274fec93 1116extern struct nouveau_bitfield nv04_graph_nsource[];
6ee73861
BS		 1117
1118/* nv10_graph.c */
6ee73861
BS		 1119extern int nv10_graph_init(struct drm_device *);
1120extern void nv10_graph_takedown(struct drm_device *);
1121extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1122extern int nv10_graph_create_context(struct nouveau_channel *);
1123extern void nv10_graph_destroy_context(struct nouveau_channel *);
1124extern int nv10_graph_load_context(struct nouveau_channel *);
1125extern int nv10_graph_unload_context(struct drm_device *);
a5cf68b0 1126extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
274fec93
BS		 1127extern struct nouveau_bitfield nv10_graph_intr[];
1128extern struct nouveau_bitfield nv10_graph_nstatus[];
6ee73861
BS		 1129
1130/* nv20_graph.c */
6ee73861
BS		 1131extern int nv20_graph_create_context(struct nouveau_channel *);
1132extern void nv20_graph_destroy_context(struct nouveau_channel *);
1133extern int nv20_graph_load_context(struct nouveau_channel *);
1134extern int nv20_graph_unload_context(struct drm_device *);
1135extern int nv20_graph_init(struct drm_device *);
1136extern void nv20_graph_takedown(struct drm_device *);
1137extern int nv30_graph_init(struct drm_device *);
a5cf68b0 1138extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1139
1140/* nv40_graph.c */
6ee73861
BS		 1141extern int nv40_graph_init(struct drm_device *);
1142extern void nv40_graph_takedown(struct drm_device *);
1143extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1144extern int nv40_graph_create_context(struct nouveau_channel *);
1145extern void nv40_graph_destroy_context(struct nouveau_channel *);
1146extern int nv40_graph_load_context(struct nouveau_channel *);
1147extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1148extern void nv40_grctx_init(struct nouveau_grctx *);
a5cf68b0 1149extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1150
1151/* nv50_graph.c */
6ee73861
BS		 1152extern int nv50_graph_init(struct drm_device *);
1153extern void nv50_graph_takedown(struct drm_device *);
1154extern void nv50_graph_fifo_access(struct drm_device *, bool);
1155extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1156extern int nv50_graph_create_context(struct nouveau_channel *);
1157extern void nv50_graph_destroy_context(struct nouveau_channel *);
1158extern int nv50_graph_load_context(struct nouveau_channel *);
1159extern int nv50_graph_unload_context(struct drm_device *);
d5f3c90d 1160extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1161extern void nv50_graph_tlb_flush(struct drm_device *dev);
1162extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1163
4b223eef
BS		 1164/* nvc0_graph.c */
1165extern int nvc0_graph_init(struct drm_device *);
1166extern void nvc0_graph_takedown(struct drm_device *);
1167extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1168extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1169extern int nvc0_graph_create_context(struct nouveau_channel *);
1170extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1171extern int nvc0_graph_load_context(struct nouveau_channel *);
1172extern int nvc0_graph_unload_context(struct drm_device *);
1173
bd2e597d
BS		 1174/* nv84_crypt.c */
1175extern int nv84_crypt_init(struct drm_device *dev);
1176extern void nv84_crypt_fini(struct drm_device *dev);
1177extern int nv84_crypt_create_context(struct nouveau_channel *);
1178extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1179extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1180
6ee73861
BS		 1181/* nv04_instmem.c */
1182extern int nv04_instmem_init(struct drm_device *);
1183extern void nv04_instmem_takedown(struct drm_device *);
1184extern int nv04_instmem_suspend(struct drm_device *);
1185extern void nv04_instmem_resume(struct drm_device *);
e41115d0
BS		 1186extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1187extern void nv04_instmem_put(struct nouveau_gpuobj *);
1188extern int nv04_instmem_map(struct nouveau_gpuobj *);
1189extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1190extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1191
1192/* nv50_instmem.c */
1193extern int nv50_instmem_init(struct drm_device *);
1194extern void nv50_instmem_takedown(struct drm_device *);
1195extern int nv50_instmem_suspend(struct drm_device *);
1196extern void nv50_instmem_resume(struct drm_device *);
e41115d0
BS		 1197extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1198extern void nv50_instmem_put(struct nouveau_gpuobj *);
1199extern int nv50_instmem_map(struct nouveau_gpuobj *);
1200extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1201extern void nv50_instmem_flush(struct drm_device *);
734ee835 1202extern void nv84_instmem_flush(struct drm_device *);
63187215 1203extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1204
4b223eef
BS		 1205/* nvc0_instmem.c */
1206extern int nvc0_instmem_init(struct drm_device *);
1207extern void nvc0_instmem_takedown(struct drm_device *);
1208extern int nvc0_instmem_suspend(struct drm_device *);
1209extern void nvc0_instmem_resume(struct drm_device *);
e41115d0
BS		 1210extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1211extern void nvc0_instmem_put(struct nouveau_gpuobj *);
1212extern int nvc0_instmem_map(struct nouveau_gpuobj *);
1213extern void nvc0_instmem_unmap(struct nouveau_gpuobj *);
4b223eef
BS		 1214extern void nvc0_instmem_flush(struct drm_device *);
1215
6ee73861
BS		 1216/* nv04_mc.c */
1217extern int nv04_mc_init(struct drm_device *);
1218extern void nv04_mc_takedown(struct drm_device *);
1219
1220/* nv40_mc.c */
1221extern int nv40_mc_init(struct drm_device *);
1222extern void nv40_mc_takedown(struct drm_device *);
1223
1224/* nv50_mc.c */
1225extern int nv50_mc_init(struct drm_device *);
1226extern void nv50_mc_takedown(struct drm_device *);
1227
1228/* nv04_timer.c */
1229extern int nv04_timer_init(struct drm_device *);
1230extern uint64_t nv04_timer_read(struct drm_device *);
1231extern void nv04_timer_takedown(struct drm_device *);
1232
1233extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1234 unsigned long arg);
1235
1236/* nv04_dac.c */
8f1a6086 1237extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1238extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1239extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1240extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1241extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1242
1243/* nv04_dfp.c */
8f1a6086 1244extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1245extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1246extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1247 int head, bool dl);
1248extern void nv04_dfp_disable(struct drm_device *dev, int head);
1249extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1250
1251/* nv04_tv.c */
1252extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1253extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1254
1255/* nv17_tv.c */
8f1a6086 1256extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1257
1258/* nv04_display.c */
c88c2e06
FJ		 1259extern int nv04_display_early_init(struct drm_device *);
1260extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1261extern int nv04_display_create(struct drm_device *);
c88c2e06 1262extern int nv04_display_init(struct drm_device *);
6ee73861 1263extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1264
1265/* nv04_crtc.c */
1266extern int nv04_crtc_create(struct drm_device *, int index);
1267
1268/* nouveau_bo.c */
1269extern struct ttm_bo_driver nouveau_bo_driver;
1270extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1271 int size, int align, uint32_t flags,
1272 uint32_t tile_mode, uint32_t tile_flags,
1273 bool no_vm, bool mappable, struct nouveau_bo **);
1274extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1275extern int nouveau_bo_unpin(struct nouveau_bo *);
1276extern int nouveau_bo_map(struct nouveau_bo *);
1277extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1278extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1279 uint32_t busy);
6ee73861
BS		 1280extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1281extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1282extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1283extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1284extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
6ee73861
BS		 1285
1286/* nouveau_fence.c */
1287struct nouveau_fence;
0c6c1c2f
FJ		 1288extern int nouveau_fence_init(struct drm_device *);
1289extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1290extern int nouveau_fence_channel_init(struct nouveau_channel *);
1291extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1292extern void nouveau_fence_update(struct nouveau_channel *);
1293extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1294 bool emit);
1295extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1296extern void nouveau_fence_work(struct nouveau_fence *fence,
1297 void (*work)(void *priv, bool signalled),
1298 void *priv);
6ee73861 1299struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
382d62e5
MS		 1300
1301extern bool __nouveau_fence_signalled(void *obj, void *arg);
1302extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1303extern int __nouveau_fence_flush(void *obj, void *arg);
1304extern void __nouveau_fence_unref(void **obj);
1305extern void *__nouveau_fence_ref(void *obj);
1306
1307static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1308{
1309 return __nouveau_fence_signalled(obj, NULL);
1310}
1311static inline int
1312nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1313{
1314 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1315}
2730723b 1316extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
382d62e5
MS		 1317static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1318{
1319 return __nouveau_fence_flush(obj, NULL);
1320}
1321static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1322{
1323 __nouveau_fence_unref((void **)obj);
1324}
1325static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1326{
1327 return __nouveau_fence_ref(obj);
1328}
6ee73861
BS		 1329
1330/* nouveau_gem.c */
1331extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1332 int size, int align, uint32_t flags,
1333 uint32_t tile_mode, uint32_t tile_flags,
1334 bool no_vm, bool mappable, struct nouveau_bo **);
1335extern int nouveau_gem_object_new(struct drm_gem_object *);
1336extern void nouveau_gem_object_del(struct drm_gem_object *);
1337extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1338 struct drm_file *);
1339extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1340 struct drm_file *);
6ee73861
BS		 1341extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1342 struct drm_file *);
1343extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1344 struct drm_file *);
1345extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1346 struct drm_file *);
1347
042206c0
FJ		 1348/* nouveau_display.c */
1349int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1350void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 1351int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1352 struct drm_pending_vblank_event *event);
1353int nouveau_finish_page_flip(struct nouveau_channel *,
1354 struct nouveau_page_flip_state *);
042206c0 1355
ee2e0131
BS		 1356/* nv10_gpio.c */
1357int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1358int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1359
45284162 1360/* nv50_gpio.c */
ee2e0131 1361int nv50_gpio_init(struct drm_device *dev);
2cbd4c81 1362void nv50_gpio_fini(struct drm_device *dev);
45284162
BS		 1363int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1364int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
fce2bad0
BS		 1365int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1366 void (*)(void *, int), void *);
1367void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1368 void (*)(void *, int), void *);
1369bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1370
e9ebb68b
BS		 1371/* nv50_calc. */
1372int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1373 int *N1, int *M1, int *N2, int *M2, int *P);
1374int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1375 int clk, int *N, int *fN, int *M, int *P);
1376
6ee73861
BS		 1377#ifndef ioread32_native
1378#ifdef __BIG_ENDIAN
1379#define ioread16_native ioread16be
1380#define iowrite16_native iowrite16be
1381#define ioread32_native ioread32be
1382#define iowrite32_native iowrite32be
1383#else /* def __BIG_ENDIAN */
1384#define ioread16_native ioread16
1385#define iowrite16_native iowrite16
1386#define ioread32_native ioread32
1387#define iowrite32_native iowrite32
1388#endif /* def __BIG_ENDIAN else */
1389#endif /* !ioread32_native */
1390
1391/* channel control reg access */
1392static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1393{
1394 return ioread32_native(chan->user + reg);
1395}
1396
1397static inline void nvchan_wr32(struct nouveau_channel *chan,
1398 unsigned reg, u32 val)
1399{
1400 iowrite32_native(val, chan->user + reg);
1401}
1402
1403/* register access */
1404static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1405{
1406 struct drm_nouveau_private *dev_priv = dev->dev_private;
1407 return ioread32_native(dev_priv->mmio + reg);
1408}
1409
1410static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1411{
1412 struct drm_nouveau_private *dev_priv = dev->dev_private;
1413 iowrite32_native(val, dev_priv->mmio + reg);
1414}
1415
2a7fdb2b 1416static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1417{
1418 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1419 nv_wr32(dev, reg, (tmp & ~mask) | val);
1420 return tmp;
49eed80a
BS		 1421}
1422
6ee73861
BS		 1423static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1424{
1425 struct drm_nouveau_private *dev_priv = dev->dev_private;
1426 return ioread8(dev_priv->mmio + reg);
1427}
1428
1429static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1430{
1431 struct drm_nouveau_private *dev_priv = dev->dev_private;
1432 iowrite8(val, dev_priv->mmio + reg);
1433}
1434
4b5c152a 1435#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1436 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1437
1438/* PRAMIN access */
1439static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1440{
1441 struct drm_nouveau_private *dev_priv = dev->dev_private;
1442 return ioread32_native(dev_priv->ramin + offset);
1443}
1444
1445static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1446{
1447 struct drm_nouveau_private *dev_priv = dev->dev_private;
1448 iowrite32_native(val, dev_priv->ramin + offset);
1449}
1450
1451/* object access */
b3beb167
BS		 1452extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1453extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1454
1455/*
1456 * Logging
1457 * Argument d is (struct drm_device *).
1458 */
1459#define NV_PRINTK(level, d, fmt, arg...) \
1460 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1461 pci_name(d->pdev), ##arg)
1462#ifndef NV_DEBUG_NOTRACE
1463#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1464 if (drm_debug & DRM_UT_DRIVER) { \
1465 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1466 __LINE__, ##arg); \
1467 } \
1468} while (0)
1469#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1470 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1471 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1472 __LINE__, ##arg); \
1473 } \
1474} while (0)
1475#else
1476#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1477 if (drm_debug & DRM_UT_DRIVER) \
1478 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1479} while (0)
1480#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1481 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1482 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1483} while (0)
1484#endif
1485#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1486#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1487#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1488#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1489#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1490
1491/* nouveau_reg_debug bitmask */
1492enum {
1493 NOUVEAU_REG_DEBUG_MC = 0x1,
1494 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1495 NOUVEAU_REG_DEBUG_FB = 0x4,
1496 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1497 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1498 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1499 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1500 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1501 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1502 NOUVEAU_REG_DEBUG_EVO = 0x200,
1503};
1504
1505#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1506 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1507 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1508} while (0)
1509
1510static inline bool
1511nv_two_heads(struct drm_device *dev)
1512{
1513 struct drm_nouveau_private *dev_priv = dev->dev_private;
1514 const int impl = dev->pci_device & 0x0ff0;
1515
1516 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1517 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1518 return true;
1519
1520 return false;
1521}
1522
1523static inline bool
1524nv_gf4_disp_arch(struct drm_device *dev)
1525{
1526 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1527}
1528
1529static inline bool
1530nv_two_reg_pll(struct drm_device *dev)
1531{
1532 struct drm_nouveau_private *dev_priv = dev->dev_private;
1533 const int impl = dev->pci_device & 0x0ff0;
1534
1535 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1536 return true;
1537 return false;
1538}
1539
acae116c
FJ		 1540static inline bool
1541nv_match_device(struct drm_device *dev, unsigned device,
1542 unsigned sub_vendor, unsigned sub_device)
1543{
1544 return dev->pdev->device == device &&
1545 dev->pdev->subsystem_vendor == sub_vendor &&
1546 dev->pdev->subsystem_device == sub_device;
1547}
1548
f03a314b
FJ		 1549#define NV_SW 0x0000506e
1550#define NV_SW_DMA_SEMAPHORE 0x00000060
1551#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1552#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1553#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1554#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1555#define NV_SW_DMA_VBLSEM 0x0000018c
1556#define NV_SW_VBLSEM_OFFSET 0x00000400
1557#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1558#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1559#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 1560
1561#endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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