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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef __NOUVEAU_DRV_H__ | |
26 | #define __NOUVEAU_DRV_H__ | |
27 | ||
28 | #define DRIVER_AUTHOR "Stephane Marchesin" | |
29 | #define DRIVER_EMAIL "dri-devel@lists.sourceforge.net" | |
30 | ||
31 | #define DRIVER_NAME "nouveau" | |
32 | #define DRIVER_DESC "nVidia Riva/TNT/GeForce" | |
33 | #define DRIVER_DATE "20090420" | |
34 | ||
35 | #define DRIVER_MAJOR 0 | |
36 | #define DRIVER_MINOR 0 | |
a1606a95 | 37 | #define DRIVER_PATCHLEVEL 16 |
6ee73861 BS |
38 | |
39 | #define NOUVEAU_FAMILY 0x0000FFFF | |
40 | #define NOUVEAU_FLAGS 0xFFFF0000 | |
41 | ||
42 | #include "ttm/ttm_bo_api.h" | |
43 | #include "ttm/ttm_bo_driver.h" | |
44 | #include "ttm/ttm_placement.h" | |
45 | #include "ttm/ttm_memory.h" | |
46 | #include "ttm/ttm_module.h" | |
47 | ||
48 | struct nouveau_fpriv { | |
3f0a68d8 | 49 | spinlock_t lock; |
e8a863c1 | 50 | struct list_head channels; |
fe32b16e | 51 | struct nouveau_vm *vm; |
6ee73861 BS |
52 | }; |
53 | ||
3f0a68d8 BS |
54 | static inline struct nouveau_fpriv * |
55 | nouveau_fpriv(struct drm_file *file_priv) | |
56 | { | |
57 | return file_priv ? file_priv->driver_priv : NULL; | |
58 | } | |
59 | ||
6ee73861 BS |
60 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
61 | ||
62 | #include "nouveau_drm.h" | |
63 | #include "nouveau_reg.h" | |
64 | #include "nouveau_bios.h" | |
274fec93 | 65 | #include "nouveau_util.h" |
f869ef88 | 66 | |
054b93e4 | 67 | struct nouveau_grctx; |
d5f42394 | 68 | struct nouveau_mem; |
f869ef88 | 69 | #include "nouveau_vm.h" |
6ee73861 BS |
70 | |
71 | #define MAX_NUM_DCB_ENTRIES 16 | |
72 | ||
73 | #define NOUVEAU_MAX_CHANNEL_NR 128 | |
a0af9add | 74 | #define NOUVEAU_MAX_TILE_NR 15 |
6ee73861 | 75 | |
d5f42394 | 76 | struct nouveau_mem { |
573a2a37 BS |
77 | struct drm_device *dev; |
78 | ||
f869ef88 | 79 | struct nouveau_vma bar_vma; |
3425df48 | 80 | struct nouveau_vma tmp_vma; |
4c74eb7f | 81 | u8 page_shift; |
f869ef88 | 82 | |
8f7286f8 | 83 | struct drm_mm_node *tag; |
573a2a37 | 84 | struct list_head regions; |
26c0c9e3 | 85 | dma_addr_t *pages; |
573a2a37 BS |
86 | u32 memtype; |
87 | u64 offset; | |
88 | u64 size; | |
89 | }; | |
90 | ||
a0af9add | 91 | struct nouveau_tile_reg { |
a0af9add | 92 | bool used; |
a5cf68b0 FJ |
93 | uint32_t addr; |
94 | uint32_t limit; | |
95 | uint32_t pitch; | |
87a326a3 FJ |
96 | uint32_t zcomp; |
97 | struct drm_mm_node *tag_mem; | |
a5cf68b0 | 98 | struct nouveau_fence *fence; |
a0af9add FJ |
99 | }; |
100 | ||
6ee73861 BS |
101 | struct nouveau_bo { |
102 | struct ttm_buffer_object bo; | |
103 | struct ttm_placement placement; | |
db5c8e29 | 104 | u32 valid_domains; |
6ee73861 | 105 | u32 placements[3]; |
78ad0f7b | 106 | u32 busy_placements[3]; |
6ee73861 BS |
107 | struct ttm_bo_kmap_obj kmap; |
108 | struct list_head head; | |
109 | ||
110 | /* protected by ttm_bo_reserve() */ | |
111 | struct drm_file *reserved_by; | |
112 | struct list_head entry; | |
113 | int pbbo_index; | |
a1606a95 | 114 | bool validate_mapped; |
6ee73861 BS |
115 | |
116 | struct nouveau_channel *channel; | |
117 | ||
4c136142 | 118 | struct nouveau_vma vma; |
f91bac5b | 119 | unsigned page_shift; |
6ee73861 BS |
120 | |
121 | uint32_t tile_mode; | |
122 | uint32_t tile_flags; | |
a0af9add | 123 | struct nouveau_tile_reg *tile; |
6ee73861 BS |
124 | |
125 | struct drm_gem_object *gem; | |
6ee73861 BS |
126 | int pin_refcnt; |
127 | }; | |
128 | ||
f13b3263 FJ |
129 | #define nouveau_bo_tile_layout(nvbo) \ |
130 | ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) | |
131 | ||
6ee73861 BS |
132 | static inline struct nouveau_bo * |
133 | nouveau_bo(struct ttm_buffer_object *bo) | |
134 | { | |
135 | return container_of(bo, struct nouveau_bo, bo); | |
136 | } | |
137 | ||
138 | static inline struct nouveau_bo * | |
139 | nouveau_gem_object(struct drm_gem_object *gem) | |
140 | { | |
141 | return gem ? gem->driver_private : NULL; | |
142 | } | |
143 | ||
144 | /* TODO: submit equivalent to TTM generic API upstream? */ | |
145 | static inline void __iomem * | |
146 | nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) | |
147 | { | |
148 | bool is_iomem; | |
149 | void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( | |
150 | &nvbo->kmap, &is_iomem); | |
151 | WARN_ON_ONCE(ioptr && !is_iomem); | |
152 | return ioptr; | |
153 | } | |
154 | ||
6ee73861 BS |
155 | enum nouveau_flags { |
156 | NV_NFORCE = 0x10000000, | |
157 | NV_NFORCE2 = 0x20000000 | |
158 | }; | |
159 | ||
160 | #define NVOBJ_ENGINE_SW 0 | |
161 | #define NVOBJ_ENGINE_GR 1 | |
6dfdd7a6 | 162 | #define NVOBJ_ENGINE_CRYPT 2 |
7ff5441e BS |
163 | #define NVOBJ_ENGINE_COPY0 3 |
164 | #define NVOBJ_ENGINE_COPY1 4 | |
a02ccc7f | 165 | #define NVOBJ_ENGINE_MPEG 5 |
6dfdd7a6 BS |
166 | #define NVOBJ_ENGINE_DISPLAY 15 |
167 | #define NVOBJ_ENGINE_NR 16 | |
6ee73861 | 168 | |
a11c3198 | 169 | #define NVOBJ_FLAG_DONT_MAP (1 << 0) |
6ee73861 BS |
170 | #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) |
171 | #define NVOBJ_FLAG_ZERO_FREE (1 << 2) | |
34cf01bc | 172 | #define NVOBJ_FLAG_VM (1 << 3) |
c906ca0f | 173 | #define NVOBJ_FLAG_VM_USER (1 << 4) |
e41115d0 BS |
174 | |
175 | #define NVOBJ_CINST_GLOBAL 0xdeadbeef | |
176 | ||
6ee73861 | 177 | struct nouveau_gpuobj { |
b3beb167 | 178 | struct drm_device *dev; |
eb9bcbdc | 179 | struct kref refcount; |
6ee73861 BS |
180 | struct list_head list; |
181 | ||
e41115d0 | 182 | void *node; |
dc1e5c0d | 183 | u32 *suspend; |
6ee73861 BS |
184 | |
185 | uint32_t flags; | |
6ee73861 | 186 | |
43efc9ce | 187 | u32 size; |
f8522fc8 BS |
188 | u32 pinst; /* PRAMIN BAR offset */ |
189 | u32 cinst; /* Channel offset */ | |
190 | u64 vinst; /* VRAM address */ | |
191 | u64 linst; /* VM address */ | |
de3a6c0a | 192 | |
6ee73861 BS |
193 | uint32_t engine; |
194 | uint32_t class; | |
195 | ||
196 | void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); | |
197 | void *priv; | |
198 | }; | |
199 | ||
332b242f FJ |
200 | struct nouveau_page_flip_state { |
201 | struct list_head head; | |
202 | struct drm_pending_vblank_event *event; | |
203 | int crtc, bpp, pitch, x, y; | |
204 | uint64_t offset; | |
205 | }; | |
206 | ||
e419cf09 FJ |
207 | enum nouveau_channel_mutex_class { |
208 | NOUVEAU_UCHANNEL_MUTEX, | |
209 | NOUVEAU_KCHANNEL_MUTEX | |
210 | }; | |
211 | ||
6ee73861 BS |
212 | struct nouveau_channel { |
213 | struct drm_device *dev; | |
e8a863c1 | 214 | struct list_head list; |
6ee73861 BS |
215 | int id; |
216 | ||
f091a3d4 FJ |
217 | /* references to the channel data structure */ |
218 | struct kref ref; | |
219 | /* users of the hardware channel resources, the hardware | |
220 | * context will be kicked off when it reaches zero. */ | |
221 | atomic_t users; | |
6a6b73f2 BS |
222 | struct mutex mutex; |
223 | ||
6ee73861 BS |
224 | /* owner of this fifo */ |
225 | struct drm_file *file_priv; | |
226 | /* mapping of the fifo itself */ | |
227 | struct drm_local_map *map; | |
228 | ||
25985edc | 229 | /* mapping of the regs controlling the fifo */ |
6ee73861 BS |
230 | void __iomem *user; |
231 | uint32_t user_get; | |
232 | uint32_t user_put; | |
233 | ||
234 | /* Fencing */ | |
235 | struct { | |
236 | /* lock protects the pending list only */ | |
237 | spinlock_t lock; | |
238 | struct list_head pending; | |
239 | uint32_t sequence; | |
240 | uint32_t sequence_ack; | |
047d1d3c | 241 | atomic_t last_sequence_irq; |
6ee73861 BS |
242 | } fence; |
243 | ||
244 | /* DMA push buffer */ | |
a8eaebc6 BS |
245 | struct nouveau_gpuobj *pushbuf; |
246 | struct nouveau_bo *pushbuf_bo; | |
247 | uint32_t pushbuf_base; | |
6ee73861 BS |
248 | |
249 | /* Notifier memory */ | |
250 | struct nouveau_bo *notifier_bo; | |
b833ac26 | 251 | struct drm_mm notifier_heap; |
6ee73861 BS |
252 | |
253 | /* PFIFO context */ | |
a8eaebc6 BS |
254 | struct nouveau_gpuobj *ramfc; |
255 | struct nouveau_gpuobj *cache; | |
b2b09938 | 256 | void *fifo_priv; |
6ee73861 | 257 | |
a82dd49f | 258 | /* Execution engine contexts */ |
6dfdd7a6 | 259 | void *engctx[NVOBJ_ENGINE_NR]; |
6ee73861 BS |
260 | |
261 | /* NV50 VM */ | |
f869ef88 | 262 | struct nouveau_vm *vm; |
a8eaebc6 | 263 | struct nouveau_gpuobj *vm_pd; |
6ee73861 BS |
264 | |
265 | /* Objects */ | |
a8eaebc6 BS |
266 | struct nouveau_gpuobj *ramin; /* Private instmem */ |
267 | struct drm_mm ramin_heap; /* Private PRAMIN heap */ | |
268 | struct nouveau_ramht *ramht; /* Hash table */ | |
6ee73861 BS |
269 | |
270 | /* GPU object info for stuff used in-kernel (mm_enabled) */ | |
271 | uint32_t m2mf_ntfy; | |
272 | uint32_t vram_handle; | |
273 | uint32_t gart_handle; | |
274 | bool accel_done; | |
275 | ||
276 | /* Push buffer state (only for drm's channel on !mm_enabled) */ | |
277 | struct { | |
278 | int max; | |
279 | int free; | |
280 | int cur; | |
281 | int put; | |
282 | /* access via pushbuf_bo */ | |
9a391ad8 BS |
283 | |
284 | int ib_base; | |
285 | int ib_max; | |
286 | int ib_free; | |
287 | int ib_put; | |
6ee73861 BS |
288 | } dma; |
289 | ||
290 | uint32_t sw_subchannel[8]; | |
291 | ||
292 | struct { | |
293 | struct nouveau_gpuobj *vblsem; | |
1f6d2de2 | 294 | uint32_t vblsem_head; |
6ee73861 BS |
295 | uint32_t vblsem_offset; |
296 | uint32_t vblsem_rval; | |
297 | struct list_head vbl_wait; | |
332b242f | 298 | struct list_head flip; |
6ee73861 BS |
299 | } nvsw; |
300 | ||
301 | struct { | |
302 | bool active; | |
303 | char name[32]; | |
304 | struct drm_info_list info; | |
305 | } debugfs; | |
306 | }; | |
307 | ||
6dfdd7a6 BS |
308 | struct nouveau_exec_engine { |
309 | void (*destroy)(struct drm_device *, int engine); | |
310 | int (*init)(struct drm_device *, int engine); | |
311 | int (*fini)(struct drm_device *, int engine); | |
312 | int (*context_new)(struct nouveau_channel *, int engine); | |
313 | void (*context_del)(struct nouveau_channel *, int engine); | |
314 | int (*object_new)(struct nouveau_channel *, int engine, | |
315 | u32 handle, u16 class); | |
96c50082 | 316 | void (*set_tile_region)(struct drm_device *dev, int i); |
6dfdd7a6 BS |
317 | void (*tlb_flush)(struct drm_device *, int engine); |
318 | }; | |
319 | ||
6ee73861 BS |
320 | struct nouveau_instmem_engine { |
321 | void *priv; | |
322 | ||
323 | int (*init)(struct drm_device *dev); | |
324 | void (*takedown)(struct drm_device *dev); | |
325 | int (*suspend)(struct drm_device *dev); | |
326 | void (*resume)(struct drm_device *dev); | |
327 | ||
6e32fedc BS |
328 | int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, |
329 | u32 size, u32 align); | |
e41115d0 BS |
330 | void (*put)(struct nouveau_gpuobj *); |
331 | int (*map)(struct nouveau_gpuobj *); | |
332 | void (*unmap)(struct nouveau_gpuobj *); | |
333 | ||
f56cb86f | 334 | void (*flush)(struct drm_device *); |
6ee73861 BS |
335 | }; |
336 | ||
337 | struct nouveau_mc_engine { | |
338 | int (*init)(struct drm_device *dev); | |
339 | void (*takedown)(struct drm_device *dev); | |
340 | }; | |
341 | ||
342 | struct nouveau_timer_engine { | |
343 | int (*init)(struct drm_device *dev); | |
344 | void (*takedown)(struct drm_device *dev); | |
345 | uint64_t (*read)(struct drm_device *dev); | |
346 | }; | |
347 | ||
348 | struct nouveau_fb_engine { | |
cb00f7c1 | 349 | int num_tiles; |
87a326a3 | 350 | struct drm_mm tag_heap; |
20f63afe | 351 | void *priv; |
cb00f7c1 | 352 | |
6ee73861 BS |
353 | int (*init)(struct drm_device *dev); |
354 | void (*takedown)(struct drm_device *dev); | |
cb00f7c1 | 355 | |
a5cf68b0 FJ |
356 | void (*init_tile_region)(struct drm_device *dev, int i, |
357 | uint32_t addr, uint32_t size, | |
358 | uint32_t pitch, uint32_t flags); | |
359 | void (*set_tile_region)(struct drm_device *dev, int i); | |
360 | void (*free_tile_region)(struct drm_device *dev, int i); | |
6ee73861 BS |
361 | }; |
362 | ||
363 | struct nouveau_fifo_engine { | |
b2b09938 | 364 | void *priv; |
6ee73861 BS |
365 | int channels; |
366 | ||
a8eaebc6 | 367 | struct nouveau_gpuobj *playlist[2]; |
ac94a343 BS |
368 | int cur_playlist; |
369 | ||
6ee73861 BS |
370 | int (*init)(struct drm_device *); |
371 | void (*takedown)(struct drm_device *); | |
372 | ||
373 | void (*disable)(struct drm_device *); | |
374 | void (*enable)(struct drm_device *); | |
375 | bool (*reassign)(struct drm_device *, bool enable); | |
588d7d12 | 376 | bool (*cache_pull)(struct drm_device *dev, bool enable); |
6ee73861 BS |
377 | |
378 | int (*channel_id)(struct drm_device *); | |
379 | ||
380 | int (*create_context)(struct nouveau_channel *); | |
381 | void (*destroy_context)(struct nouveau_channel *); | |
382 | int (*load_context)(struct nouveau_channel *); | |
383 | int (*unload_context)(struct drm_device *); | |
56ac7475 | 384 | void (*tlb_flush)(struct drm_device *dev); |
6ee73861 BS |
385 | }; |
386 | ||
c88c2e06 | 387 | struct nouveau_display_engine { |
ef8389a8 | 388 | void *priv; |
c88c2e06 FJ |
389 | int (*early_init)(struct drm_device *); |
390 | void (*late_takedown)(struct drm_device *); | |
391 | int (*create)(struct drm_device *); | |
392 | int (*init)(struct drm_device *); | |
393 | void (*destroy)(struct drm_device *); | |
394 | }; | |
395 | ||
ee2e0131 | 396 | struct nouveau_gpio_engine { |
fce2bad0 BS |
397 | void *priv; |
398 | ||
ee2e0131 BS |
399 | int (*init)(struct drm_device *); |
400 | void (*takedown)(struct drm_device *); | |
401 | ||
402 | int (*get)(struct drm_device *, enum dcb_gpio_tag); | |
403 | int (*set)(struct drm_device *, enum dcb_gpio_tag, int state); | |
404 | ||
fce2bad0 BS |
405 | int (*irq_register)(struct drm_device *, enum dcb_gpio_tag, |
406 | void (*)(void *, int), void *); | |
407 | void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag, | |
408 | void (*)(void *, int), void *); | |
409 | bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on); | |
ee2e0131 BS |
410 | }; |
411 | ||
330c5988 BS |
412 | struct nouveau_pm_voltage_level { |
413 | u8 voltage; | |
414 | u8 vid; | |
415 | }; | |
416 | ||
417 | struct nouveau_pm_voltage { | |
418 | bool supported; | |
419 | u8 vid_mask; | |
420 | ||
421 | struct nouveau_pm_voltage_level *level; | |
422 | int nr_level; | |
423 | }; | |
424 | ||
e614b2e7 MP |
425 | struct nouveau_pm_memtiming { |
426 | int id; | |
427 | u32 reg_100220; | |
428 | u32 reg_100224; | |
429 | u32 reg_100228; | |
430 | u32 reg_10022c; | |
431 | u32 reg_100230; | |
432 | u32 reg_100234; | |
433 | u32 reg_100238; | |
434 | u32 reg_10023c; | |
435 | u32 reg_100240; | |
436 | }; | |
437 | ||
330c5988 BS |
438 | #define NOUVEAU_PM_MAX_LEVEL 8 |
439 | struct nouveau_pm_level { | |
440 | struct device_attribute dev_attr; | |
441 | char name[32]; | |
442 | int id; | |
443 | ||
444 | u32 core; | |
445 | u32 memory; | |
446 | u32 shader; | |
447 | u32 unk05; | |
047d2df5 | 448 | u32 unk0a; |
330c5988 BS |
449 | |
450 | u8 voltage; | |
451 | u8 fanspeed; | |
aee582de BS |
452 | |
453 | u16 memscript; | |
e614b2e7 | 454 | struct nouveau_pm_memtiming *timing; |
330c5988 BS |
455 | }; |
456 | ||
34e9d85a MP |
457 | struct nouveau_pm_temp_sensor_constants { |
458 | u16 offset_constant; | |
459 | s16 offset_mult; | |
460 | u16 offset_div; | |
461 | u16 slope_mult; | |
462 | u16 slope_div; | |
463 | }; | |
464 | ||
465 | struct nouveau_pm_threshold_temp { | |
466 | s16 critical; | |
467 | s16 down_clock; | |
468 | s16 fan_boost; | |
469 | }; | |
470 | ||
7760fcb0 RS |
471 | struct nouveau_pm_memtimings { |
472 | bool supported; | |
473 | struct nouveau_pm_memtiming *timing; | |
474 | int nr_timing; | |
475 | }; | |
476 | ||
330c5988 BS |
477 | struct nouveau_pm_engine { |
478 | struct nouveau_pm_voltage voltage; | |
479 | struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; | |
480 | int nr_perflvl; | |
7760fcb0 | 481 | struct nouveau_pm_memtimings memtimings; |
34e9d85a MP |
482 | struct nouveau_pm_temp_sensor_constants sensor_constants; |
483 | struct nouveau_pm_threshold_temp threshold_temp; | |
330c5988 BS |
484 | |
485 | struct nouveau_pm_level boot; | |
486 | struct nouveau_pm_level *cur; | |
487 | ||
8155cac4 | 488 | struct device *hwmon; |
6032649d | 489 | struct notifier_block acpi_nb; |
8155cac4 | 490 | |
330c5988 | 491 | int (*clock_get)(struct drm_device *, u32 id); |
5c6dc657 BS |
492 | void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *, |
493 | u32 id, int khz); | |
330c5988 BS |
494 | void (*clock_set)(struct drm_device *, void *); |
495 | int (*voltage_get)(struct drm_device *); | |
496 | int (*voltage_set)(struct drm_device *, int voltage); | |
497 | int (*fanspeed_get)(struct drm_device *); | |
498 | int (*fanspeed_set)(struct drm_device *, int fanspeed); | |
8155cac4 | 499 | int (*temp_get)(struct drm_device *); |
330c5988 BS |
500 | }; |
501 | ||
60d2a88a BS |
502 | struct nouveau_vram_engine { |
503 | int (*init)(struct drm_device *); | |
504 | int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, | |
d5f42394 BS |
505 | u32 type, struct nouveau_mem **); |
506 | void (*put)(struct drm_device *, struct nouveau_mem **); | |
60d2a88a BS |
507 | |
508 | bool (*flags_valid)(struct drm_device *, u32 tile_flags); | |
509 | }; | |
510 | ||
6ee73861 BS |
511 | struct nouveau_engine { |
512 | struct nouveau_instmem_engine instmem; | |
513 | struct nouveau_mc_engine mc; | |
514 | struct nouveau_timer_engine timer; | |
515 | struct nouveau_fb_engine fb; | |
6ee73861 | 516 | struct nouveau_fifo_engine fifo; |
c88c2e06 | 517 | struct nouveau_display_engine display; |
ee2e0131 | 518 | struct nouveau_gpio_engine gpio; |
330c5988 | 519 | struct nouveau_pm_engine pm; |
60d2a88a | 520 | struct nouveau_vram_engine vram; |
6ee73861 BS |
521 | }; |
522 | ||
523 | struct nouveau_pll_vals { | |
524 | union { | |
525 | struct { | |
526 | #ifdef __BIG_ENDIAN | |
527 | uint8_t N1, M1, N2, M2; | |
528 | #else | |
529 | uint8_t M1, N1, M2, N2; | |
530 | #endif | |
531 | }; | |
532 | struct { | |
533 | uint16_t NM1, NM2; | |
534 | } __attribute__((packed)); | |
535 | }; | |
536 | int log2P; | |
537 | ||
538 | int refclk; | |
539 | }; | |
540 | ||
541 | enum nv04_fp_display_regs { | |
542 | FP_DISPLAY_END, | |
543 | FP_TOTAL, | |
544 | FP_CRTC, | |
545 | FP_SYNC_START, | |
546 | FP_SYNC_END, | |
547 | FP_VALID_START, | |
548 | FP_VALID_END | |
549 | }; | |
550 | ||
551 | struct nv04_crtc_reg { | |
cbab95db | 552 | unsigned char MiscOutReg; |
4a9f822f | 553 | uint8_t CRTC[0xa0]; |
6ee73861 BS |
554 | uint8_t CR58[0x10]; |
555 | uint8_t Sequencer[5]; | |
556 | uint8_t Graphics[9]; | |
557 | uint8_t Attribute[21]; | |
cbab95db | 558 | unsigned char DAC[768]; |
6ee73861 BS |
559 | |
560 | /* PCRTC regs */ | |
561 | uint32_t fb_start; | |
562 | uint32_t crtc_cfg; | |
563 | uint32_t cursor_cfg; | |
564 | uint32_t gpio_ext; | |
565 | uint32_t crtc_830; | |
566 | uint32_t crtc_834; | |
567 | uint32_t crtc_850; | |
568 | uint32_t crtc_eng_ctrl; | |
569 | ||
570 | /* PRAMDAC regs */ | |
571 | uint32_t nv10_cursync; | |
572 | struct nouveau_pll_vals pllvals; | |
573 | uint32_t ramdac_gen_ctrl; | |
574 | uint32_t ramdac_630; | |
575 | uint32_t ramdac_634; | |
576 | uint32_t tv_setup; | |
577 | uint32_t tv_vtotal; | |
578 | uint32_t tv_vskew; | |
579 | uint32_t tv_vsync_delay; | |
580 | uint32_t tv_htotal; | |
581 | uint32_t tv_hskew; | |
582 | uint32_t tv_hsync_delay; | |
583 | uint32_t tv_hsync_delay2; | |
584 | uint32_t fp_horiz_regs[7]; | |
585 | uint32_t fp_vert_regs[7]; | |
586 | uint32_t dither; | |
587 | uint32_t fp_control; | |
588 | uint32_t dither_regs[6]; | |
589 | uint32_t fp_debug_0; | |
590 | uint32_t fp_debug_1; | |
591 | uint32_t fp_debug_2; | |
592 | uint32_t fp_margin_color; | |
593 | uint32_t ramdac_8c0; | |
594 | uint32_t ramdac_a20; | |
595 | uint32_t ramdac_a24; | |
596 | uint32_t ramdac_a34; | |
597 | uint32_t ctv_regs[38]; | |
598 | }; | |
599 | ||
600 | struct nv04_output_reg { | |
601 | uint32_t output; | |
602 | int head; | |
603 | }; | |
604 | ||
605 | struct nv04_mode_state { | |
cbab95db | 606 | struct nv04_crtc_reg crtc_reg[2]; |
6ee73861 BS |
607 | uint32_t pllsel; |
608 | uint32_t sel_clk; | |
6ee73861 BS |
609 | }; |
610 | ||
611 | enum nouveau_card_type { | |
612 | NV_04 = 0x00, | |
613 | NV_10 = 0x10, | |
614 | NV_20 = 0x20, | |
615 | NV_30 = 0x30, | |
616 | NV_40 = 0x40, | |
617 | NV_50 = 0x50, | |
4b223eef | 618 | NV_C0 = 0xc0, |
6ee73861 BS |
619 | }; |
620 | ||
621 | struct drm_nouveau_private { | |
622 | struct drm_device *dev; | |
aba99a84 | 623 | bool noaccel; |
6ee73861 BS |
624 | |
625 | /* the card type, takes NV_* as values */ | |
626 | enum nouveau_card_type card_type; | |
627 | /* exact chipset, derived from NV_PMC_BOOT_0 */ | |
628 | int chipset; | |
50066f81 | 629 | int stepping; |
6ee73861 BS |
630 | int flags; |
631 | ||
632 | void __iomem *mmio; | |
5125bfd8 | 633 | |
e05d7eae | 634 | spinlock_t ramin_lock; |
6ee73861 | 635 | void __iomem *ramin; |
5125bfd8 BS |
636 | u32 ramin_size; |
637 | u32 ramin_base; | |
638 | bool ramin_available; | |
e05d7eae | 639 | struct drm_mm ramin_heap; |
6dfdd7a6 | 640 | struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; |
e05d7eae | 641 | struct list_head gpuobj_list; |
b8c157d3 | 642 | struct list_head classes; |
6ee73861 | 643 | |
ac8fb975 BS |
644 | struct nouveau_bo *vga_ram; |
645 | ||
35fa2f2a | 646 | /* interrupt handling */ |
8f8a5448 | 647 | void (*irq_handler[32])(struct drm_device *); |
35fa2f2a | 648 | bool msi_enabled; |
ab838338 | 649 | |
6ee73861 BS |
650 | struct list_head vbl_waiting; |
651 | ||
652 | struct { | |
ba4420c2 | 653 | struct drm_global_reference mem_global_ref; |
6ee73861 BS |
654 | struct ttm_bo_global_ref bo_global_ref; |
655 | struct ttm_bo_device bdev; | |
6ee73861 BS |
656 | atomic_t validate_sequence; |
657 | } ttm; | |
658 | ||
0c6c1c2f FJ |
659 | struct { |
660 | spinlock_t lock; | |
661 | struct drm_mm heap; | |
662 | struct nouveau_bo *bo; | |
663 | } fence; | |
664 | ||
cff5c133 BS |
665 | struct { |
666 | spinlock_t lock; | |
667 | struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; | |
668 | } channels; | |
6ee73861 BS |
669 | |
670 | struct nouveau_engine engine; | |
671 | struct nouveau_channel *channel; | |
672 | ||
ff9e5279 MM |
673 | /* For PFIFO and PGRAPH. */ |
674 | spinlock_t context_switch_lock; | |
675 | ||
04eb34a4 BS |
676 | /* VM/PRAMIN flush, legacy PRAMIN aperture */ |
677 | spinlock_t vm_lock; | |
678 | ||
6ee73861 | 679 | /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ |
e05c5a31 BS |
680 | struct nouveau_ramht *ramht; |
681 | struct nouveau_gpuobj *ramfc; | |
682 | struct nouveau_gpuobj *ramro; | |
683 | ||
6ee73861 | 684 | uint32_t ramin_rsvd_vram; |
6ee73861 | 685 | |
6ee73861 BS |
686 | struct { |
687 | enum { | |
688 | NOUVEAU_GART_NONE = 0, | |
58e6c7a9 BS |
689 | NOUVEAU_GART_AGP, /* AGP */ |
690 | NOUVEAU_GART_PDMA, /* paged dma object */ | |
691 | NOUVEAU_GART_HW /* on-chip gart/vm */ | |
6ee73861 BS |
692 | } type; |
693 | uint64_t aper_base; | |
694 | uint64_t aper_size; | |
695 | uint64_t aper_free; | |
696 | ||
7948758d BS |
697 | struct ttm_backend_func *func; |
698 | ||
699 | struct { | |
700 | struct page *page; | |
701 | dma_addr_t addr; | |
702 | } dummy; | |
703 | ||
6ee73861 | 704 | struct nouveau_gpuobj *sg_ctxdma; |
6ee73861 BS |
705 | } gart_info; |
706 | ||
a0af9add | 707 | /* nv10-nv40 tiling regions */ |
a5cf68b0 FJ |
708 | struct { |
709 | struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; | |
710 | spinlock_t lock; | |
711 | } tile; | |
a0af9add | 712 | |
a76fb4e8 BS |
713 | /* VRAM/fb configuration */ |
714 | uint64_t vram_size; | |
715 | uint64_t vram_sys_base; | |
6c3d7ef2 | 716 | u32 vram_rblock_size; |
a76fb4e8 BS |
717 | |
718 | uint64_t fb_phys; | |
719 | uint64_t fb_available_size; | |
720 | uint64_t fb_mappable_pages; | |
721 | uint64_t fb_aper_free; | |
722 | int fb_mtrr; | |
723 | ||
f869ef88 BS |
724 | /* BAR control (NV50-) */ |
725 | struct nouveau_vm *bar1_vm; | |
726 | struct nouveau_vm *bar3_vm; | |
727 | ||
6ee73861 | 728 | /* G8x/G9x virtual address space */ |
4c136142 | 729 | struct nouveau_vm *chan_vm; |
6ee73861 | 730 | |
04a39c57 | 731 | struct nvbios vbios; |
6ee73861 BS |
732 | |
733 | struct nv04_mode_state mode_reg; | |
734 | struct nv04_mode_state saved_reg; | |
735 | uint32_t saved_vga_font[4][16384]; | |
736 | uint32_t crtc_owner; | |
737 | uint32_t dac_users[4]; | |
738 | ||
6ee73861 | 739 | struct backlight_device *backlight; |
6ee73861 | 740 | |
6ee73861 BS |
741 | struct { |
742 | struct dentry *channel_root; | |
743 | } debugfs; | |
38651674 | 744 | |
8be48d92 | 745 | struct nouveau_fbdev *nfbdev; |
06415c56 | 746 | struct apertures_struct *apertures; |
6ee73861 BS |
747 | }; |
748 | ||
2730723b FJ |
749 | static inline struct drm_nouveau_private * |
750 | nouveau_private(struct drm_device *dev) | |
751 | { | |
752 | return dev->dev_private; | |
753 | } | |
754 | ||
6ee73861 BS |
755 | static inline struct drm_nouveau_private * |
756 | nouveau_bdev(struct ttm_bo_device *bd) | |
757 | { | |
758 | return container_of(bd, struct drm_nouveau_private, ttm.bdev); | |
759 | } | |
760 | ||
761 | static inline int | |
762 | nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) | |
763 | { | |
764 | struct nouveau_bo *prev; | |
765 | ||
766 | if (!pnvbo) | |
767 | return -EINVAL; | |
768 | prev = *pnvbo; | |
769 | ||
770 | *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; | |
771 | if (prev) { | |
772 | struct ttm_buffer_object *bo = &prev->bo; | |
773 | ||
774 | ttm_bo_unref(&bo); | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
6ee73861 | 780 | /* nouveau_drv.c */ |
de5899bd | 781 | extern int nouveau_agpmode; |
6ee73861 BS |
782 | extern int nouveau_duallink; |
783 | extern int nouveau_uscript_lvds; | |
784 | extern int nouveau_uscript_tmds; | |
785 | extern int nouveau_vram_pushbuf; | |
786 | extern int nouveau_vram_notify; | |
787 | extern int nouveau_fbpercrtc; | |
f4053509 | 788 | extern int nouveau_tv_disable; |
6ee73861 BS |
789 | extern char *nouveau_tv_norm; |
790 | extern int nouveau_reg_debug; | |
791 | extern char *nouveau_vbios; | |
a1470890 | 792 | extern int nouveau_ignorelid; |
a32ed69d MK |
793 | extern int nouveau_nofbaccel; |
794 | extern int nouveau_noaccel; | |
0cba1b76 | 795 | extern int nouveau_force_post; |
da647d5b | 796 | extern int nouveau_override_conntype; |
6f876986 BS |
797 | extern char *nouveau_perflvl; |
798 | extern int nouveau_perflvl_wr; | |
35fa2f2a | 799 | extern int nouveau_msi; |
0411de85 | 800 | extern int nouveau_ctxfw; |
6ee73861 | 801 | |
6a9ee8af DA |
802 | extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); |
803 | extern int nouveau_pci_resume(struct pci_dev *pdev); | |
804 | ||
6ee73861 | 805 | /* nouveau_state.c */ |
3f0a68d8 | 806 | extern int nouveau_open(struct drm_device *, struct drm_file *); |
6ee73861 | 807 | extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); |
3f0a68d8 | 808 | extern void nouveau_postclose(struct drm_device *, struct drm_file *); |
6ee73861 BS |
809 | extern int nouveau_load(struct drm_device *, unsigned long flags); |
810 | extern int nouveau_firstopen(struct drm_device *); | |
811 | extern void nouveau_lastclose(struct drm_device *); | |
812 | extern int nouveau_unload(struct drm_device *); | |
813 | extern int nouveau_ioctl_getparam(struct drm_device *, void *data, | |
814 | struct drm_file *); | |
815 | extern int nouveau_ioctl_setparam(struct drm_device *, void *data, | |
816 | struct drm_file *); | |
12fb9525 BS |
817 | extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, |
818 | uint32_t reg, uint32_t mask, uint32_t val); | |
819 | extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, | |
820 | uint32_t reg, uint32_t mask, uint32_t val); | |
6ee73861 BS |
821 | extern bool nouveau_wait_for_idle(struct drm_device *); |
822 | extern int nouveau_card_init(struct drm_device *); | |
6ee73861 BS |
823 | |
824 | /* nouveau_mem.c */ | |
fbd2895e BS |
825 | extern int nouveau_mem_vram_init(struct drm_device *); |
826 | extern void nouveau_mem_vram_fini(struct drm_device *); | |
827 | extern int nouveau_mem_gart_init(struct drm_device *); | |
828 | extern void nouveau_mem_gart_fini(struct drm_device *); | |
6ee73861 | 829 | extern int nouveau_mem_init_agp(struct drm_device *); |
e04d8e82 | 830 | extern int nouveau_mem_reset_agp(struct drm_device *); |
6ee73861 | 831 | extern void nouveau_mem_close(struct drm_device *); |
60d2a88a BS |
832 | extern int nouveau_mem_detect(struct drm_device *); |
833 | extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); | |
a5cf68b0 FJ |
834 | extern struct nouveau_tile_reg *nv10_mem_set_tiling( |
835 | struct drm_device *dev, uint32_t addr, uint32_t size, | |
836 | uint32_t pitch, uint32_t flags); | |
837 | extern void nv10_mem_put_tile_region(struct drm_device *dev, | |
838 | struct nouveau_tile_reg *tile, | |
839 | struct nouveau_fence *fence); | |
573a2a37 | 840 | extern const struct ttm_mem_type_manager_func nouveau_vram_manager; |
26c0c9e3 | 841 | extern const struct ttm_mem_type_manager_func nouveau_gart_manager; |
6ee73861 BS |
842 | |
843 | /* nouveau_notifier.c */ | |
844 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); | |
845 | extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); | |
846 | extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, | |
73412c38 BS |
847 | int cout, uint32_t start, uint32_t end, |
848 | uint32_t *offset); | |
6ee73861 BS |
849 | extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); |
850 | extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, | |
851 | struct drm_file *); | |
852 | extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, | |
853 | struct drm_file *); | |
854 | ||
855 | /* nouveau_channel.c */ | |
856 | extern struct drm_ioctl_desc nouveau_ioctls[]; | |
857 | extern int nouveau_max_ioctl; | |
858 | extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); | |
6ee73861 BS |
859 | extern int nouveau_channel_alloc(struct drm_device *dev, |
860 | struct nouveau_channel **chan, | |
861 | struct drm_file *file_priv, | |
862 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); | |
cff5c133 | 863 | extern struct nouveau_channel * |
feeb0aec FJ |
864 | nouveau_channel_get_unlocked(struct nouveau_channel *); |
865 | extern struct nouveau_channel * | |
e8a863c1 | 866 | nouveau_channel_get(struct drm_file *, int id); |
feeb0aec | 867 | extern void nouveau_channel_put_unlocked(struct nouveau_channel **); |
cff5c133 | 868 | extern void nouveau_channel_put(struct nouveau_channel **); |
f091a3d4 FJ |
869 | extern void nouveau_channel_ref(struct nouveau_channel *chan, |
870 | struct nouveau_channel **pchan); | |
6dccd311 | 871 | extern void nouveau_channel_idle(struct nouveau_channel *chan); |
6ee73861 BS |
872 | |
873 | /* nouveau_object.c */ | |
6dfdd7a6 BS |
874 | #define NVOBJ_ENGINE_ADD(d, e, p) do { \ |
875 | struct drm_nouveau_private *dev_priv = (d)->dev_private; \ | |
876 | dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ | |
877 | } while (0) | |
878 | ||
879 | #define NVOBJ_ENGINE_DEL(d, e) do { \ | |
880 | struct drm_nouveau_private *dev_priv = (d)->dev_private; \ | |
881 | dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ | |
882 | } while (0) | |
883 | ||
0b89a072 | 884 | #define NVOBJ_CLASS(d, c, e) do { \ |
b8c157d3 BS |
885 | int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ |
886 | if (ret) \ | |
887 | return ret; \ | |
71298e2f | 888 | } while (0) |
b8c157d3 | 889 | |
0b89a072 | 890 | #define NVOBJ_MTHD(d, c, m, e) do { \ |
b8c157d3 BS |
891 | int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ |
892 | if (ret) \ | |
893 | return ret; \ | |
71298e2f | 894 | } while (0) |
b8c157d3 | 895 | |
6ee73861 BS |
896 | extern int nouveau_gpuobj_early_init(struct drm_device *); |
897 | extern int nouveau_gpuobj_init(struct drm_device *); | |
898 | extern void nouveau_gpuobj_takedown(struct drm_device *); | |
6ee73861 | 899 | extern int nouveau_gpuobj_suspend(struct drm_device *dev); |
6ee73861 | 900 | extern void nouveau_gpuobj_resume(struct drm_device *dev); |
b8c157d3 BS |
901 | extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); |
902 | extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, | |
903 | int (*exec)(struct nouveau_channel *, | |
71298e2f | 904 | u32 class, u32 mthd, u32 data)); |
b8c157d3 | 905 | extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); |
274fec93 | 906 | extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); |
6ee73861 BS |
907 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, |
908 | uint32_t vram_h, uint32_t tt_h); | |
909 | extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); | |
910 | extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, | |
911 | uint32_t size, int align, uint32_t flags, | |
912 | struct nouveau_gpuobj **); | |
a8eaebc6 BS |
913 | extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, |
914 | struct nouveau_gpuobj **); | |
43efc9ce BS |
915 | extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, |
916 | u32 size, u32 flags, | |
a8eaebc6 | 917 | struct nouveau_gpuobj **); |
6ee73861 BS |
918 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, |
919 | uint64_t offset, uint64_t size, int access, | |
920 | int target, struct nouveau_gpuobj **); | |
ceac3099 | 921 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); |
7f4a195f BS |
922 | extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, |
923 | u64 size, int target, int access, u32 type, | |
924 | u32 comp, struct nouveau_gpuobj **pobj); | |
925 | extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, | |
926 | int class, u64 base, u64 size, int target, | |
927 | int access, u32 type, u32 comp); | |
6ee73861 BS |
928 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, |
929 | struct drm_file *); | |
930 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, | |
931 | struct drm_file *); | |
932 | ||
933 | /* nouveau_irq.c */ | |
35fa2f2a BS |
934 | extern int nouveau_irq_init(struct drm_device *); |
935 | extern void nouveau_irq_fini(struct drm_device *); | |
6ee73861 | 936 | extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); |
8f8a5448 BS |
937 | extern void nouveau_irq_register(struct drm_device *, int status_bit, |
938 | void (*)(struct drm_device *)); | |
939 | extern void nouveau_irq_unregister(struct drm_device *, int status_bit); | |
6ee73861 BS |
940 | extern void nouveau_irq_preinstall(struct drm_device *); |
941 | extern int nouveau_irq_postinstall(struct drm_device *); | |
942 | extern void nouveau_irq_uninstall(struct drm_device *); | |
943 | ||
944 | /* nouveau_sgdma.c */ | |
945 | extern int nouveau_sgdma_init(struct drm_device *); | |
946 | extern void nouveau_sgdma_takedown(struct drm_device *); | |
fd70b6cd FJ |
947 | extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, |
948 | uint32_t offset); | |
6ee73861 BS |
949 | extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *); |
950 | ||
951 | /* nouveau_debugfs.c */ | |
952 | #if defined(CONFIG_DRM_NOUVEAU_DEBUG) | |
953 | extern int nouveau_debugfs_init(struct drm_minor *); | |
954 | extern void nouveau_debugfs_takedown(struct drm_minor *); | |
955 | extern int nouveau_debugfs_channel_init(struct nouveau_channel *); | |
956 | extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); | |
957 | #else | |
958 | static inline int | |
959 | nouveau_debugfs_init(struct drm_minor *minor) | |
960 | { | |
961 | return 0; | |
962 | } | |
963 | ||
964 | static inline void nouveau_debugfs_takedown(struct drm_minor *minor) | |
965 | { | |
966 | } | |
967 | ||
968 | static inline int | |
969 | nouveau_debugfs_channel_init(struct nouveau_channel *chan) | |
970 | { | |
971 | return 0; | |
972 | } | |
973 | ||
974 | static inline void | |
975 | nouveau_debugfs_channel_fini(struct nouveau_channel *chan) | |
976 | { | |
977 | } | |
978 | #endif | |
979 | ||
980 | /* nouveau_dma.c */ | |
75c99da6 | 981 | extern void nouveau_dma_pre_init(struct nouveau_channel *); |
6ee73861 | 982 | extern int nouveau_dma_init(struct nouveau_channel *); |
9a391ad8 | 983 | extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); |
6ee73861 BS |
984 | |
985 | /* nouveau_acpi.c */ | |
afeb3e11 | 986 | #define ROM_BIOS_PAGE 4096 |
2f41a7f1 | 987 | #if defined(CONFIG_ACPI) |
6a9ee8af DA |
988 | void nouveau_register_dsm_handler(void); |
989 | void nouveau_unregister_dsm_handler(void); | |
afeb3e11 DA |
990 | int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); |
991 | bool nouveau_acpi_rom_supported(struct pci_dev *pdev); | |
a6ed76d7 | 992 | int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); |
8edb381d DA |
993 | #else |
994 | static inline void nouveau_register_dsm_handler(void) {} | |
995 | static inline void nouveau_unregister_dsm_handler(void) {} | |
afeb3e11 DA |
996 | static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } |
997 | static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } | |
5620ba46 | 998 | static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } |
8edb381d | 999 | #endif |
6ee73861 BS |
1000 | |
1001 | /* nouveau_backlight.c */ | |
1002 | #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT | |
7eae3efa MG |
1003 | extern int nouveau_backlight_init(struct drm_connector *); |
1004 | extern void nouveau_backlight_exit(struct drm_connector *); | |
6ee73861 | 1005 | #else |
7eae3efa | 1006 | static inline int nouveau_backlight_init(struct drm_connector *dev) |
6ee73861 BS |
1007 | { |
1008 | return 0; | |
1009 | } | |
1010 | ||
7eae3efa | 1011 | static inline void nouveau_backlight_exit(struct drm_connector *dev) { } |
6ee73861 BS |
1012 | #endif |
1013 | ||
1014 | /* nouveau_bios.c */ | |
1015 | extern int nouveau_bios_init(struct drm_device *); | |
1016 | extern void nouveau_bios_takedown(struct drm_device *dev); | |
1017 | extern int nouveau_run_vbios_init(struct drm_device *); | |
1018 | extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, | |
1019 | struct dcb_entry *); | |
1020 | extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *, | |
1021 | enum dcb_gpio_tag); | |
1022 | extern struct dcb_connector_table_entry * | |
1023 | nouveau_bios_connector_entry(struct drm_device *, int index); | |
855a95e4 | 1024 | extern u32 get_pll_register(struct drm_device *, enum pll_types); |
6ee73861 BS |
1025 | extern int get_pll_limits(struct drm_device *, uint32_t limit_match, |
1026 | struct pll_lims *); | |
1027 | extern int nouveau_bios_run_display_table(struct drm_device *, | |
1028 | struct dcb_entry *, | |
1029 | uint32_t script, int pxclk); | |
1030 | extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *, | |
1031 | int *length); | |
1032 | extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); | |
1033 | extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); | |
1034 | extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, | |
1035 | bool *dl, bool *if_is_24bit); | |
1036 | extern int run_tmds_table(struct drm_device *, struct dcb_entry *, | |
1037 | int head, int pxclk); | |
1038 | extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, | |
1039 | enum LVDS_script, int pxclk); | |
1040 | ||
1041 | /* nouveau_ttm.c */ | |
1042 | int nouveau_ttm_global_init(struct drm_nouveau_private *); | |
1043 | void nouveau_ttm_global_release(struct drm_nouveau_private *); | |
1044 | int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); | |
1045 | ||
1046 | /* nouveau_dp.c */ | |
1047 | int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, | |
1048 | uint8_t *data, int data_nr); | |
1049 | bool nouveau_dp_detect(struct drm_encoder *); | |
1050 | bool nouveau_dp_link_train(struct drm_encoder *); | |
1051 | ||
1052 | /* nv04_fb.c */ | |
1053 | extern int nv04_fb_init(struct drm_device *); | |
1054 | extern void nv04_fb_takedown(struct drm_device *); | |
1055 | ||
1056 | /* nv10_fb.c */ | |
1057 | extern int nv10_fb_init(struct drm_device *); | |
1058 | extern void nv10_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1059 | extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, |
1060 | uint32_t addr, uint32_t size, | |
1061 | uint32_t pitch, uint32_t flags); | |
1062 | extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); | |
1063 | extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); | |
6ee73861 | 1064 | |
8bded189 FJ |
1065 | /* nv30_fb.c */ |
1066 | extern int nv30_fb_init(struct drm_device *); | |
1067 | extern void nv30_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1068 | extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, |
1069 | uint32_t addr, uint32_t size, | |
1070 | uint32_t pitch, uint32_t flags); | |
1071 | extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); | |
8bded189 | 1072 | |
6ee73861 BS |
1073 | /* nv40_fb.c */ |
1074 | extern int nv40_fb_init(struct drm_device *); | |
1075 | extern void nv40_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1076 | extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); |
1077 | ||
304424e1 MK |
1078 | /* nv50_fb.c */ |
1079 | extern int nv50_fb_init(struct drm_device *); | |
1080 | extern void nv50_fb_takedown(struct drm_device *); | |
6fdb383e | 1081 | extern void nv50_fb_vm_trap(struct drm_device *, int display); |
304424e1 | 1082 | |
4b223eef BS |
1083 | /* nvc0_fb.c */ |
1084 | extern int nvc0_fb_init(struct drm_device *); | |
1085 | extern void nvc0_fb_takedown(struct drm_device *); | |
1086 | ||
6ee73861 BS |
1087 | /* nv04_fifo.c */ |
1088 | extern int nv04_fifo_init(struct drm_device *); | |
5178d40d | 1089 | extern void nv04_fifo_fini(struct drm_device *); |
6ee73861 BS |
1090 | extern void nv04_fifo_disable(struct drm_device *); |
1091 | extern void nv04_fifo_enable(struct drm_device *); | |
1092 | extern bool nv04_fifo_reassign(struct drm_device *, bool); | |
588d7d12 | 1093 | extern bool nv04_fifo_cache_pull(struct drm_device *, bool); |
6ee73861 BS |
1094 | extern int nv04_fifo_channel_id(struct drm_device *); |
1095 | extern int nv04_fifo_create_context(struct nouveau_channel *); | |
1096 | extern void nv04_fifo_destroy_context(struct nouveau_channel *); | |
1097 | extern int nv04_fifo_load_context(struct nouveau_channel *); | |
1098 | extern int nv04_fifo_unload_context(struct drm_device *); | |
5178d40d | 1099 | extern void nv04_fifo_isr(struct drm_device *); |
6ee73861 BS |
1100 | |
1101 | /* nv10_fifo.c */ | |
1102 | extern int nv10_fifo_init(struct drm_device *); | |
1103 | extern int nv10_fifo_channel_id(struct drm_device *); | |
1104 | extern int nv10_fifo_create_context(struct nouveau_channel *); | |
6ee73861 BS |
1105 | extern int nv10_fifo_load_context(struct nouveau_channel *); |
1106 | extern int nv10_fifo_unload_context(struct drm_device *); | |
1107 | ||
1108 | /* nv40_fifo.c */ | |
1109 | extern int nv40_fifo_init(struct drm_device *); | |
1110 | extern int nv40_fifo_create_context(struct nouveau_channel *); | |
6ee73861 BS |
1111 | extern int nv40_fifo_load_context(struct nouveau_channel *); |
1112 | extern int nv40_fifo_unload_context(struct drm_device *); | |
1113 | ||
1114 | /* nv50_fifo.c */ | |
1115 | extern int nv50_fifo_init(struct drm_device *); | |
1116 | extern void nv50_fifo_takedown(struct drm_device *); | |
1117 | extern int nv50_fifo_channel_id(struct drm_device *); | |
1118 | extern int nv50_fifo_create_context(struct nouveau_channel *); | |
1119 | extern void nv50_fifo_destroy_context(struct nouveau_channel *); | |
1120 | extern int nv50_fifo_load_context(struct nouveau_channel *); | |
1121 | extern int nv50_fifo_unload_context(struct drm_device *); | |
56ac7475 | 1122 | extern void nv50_fifo_tlb_flush(struct drm_device *dev); |
6ee73861 | 1123 | |
4b223eef BS |
1124 | /* nvc0_fifo.c */ |
1125 | extern int nvc0_fifo_init(struct drm_device *); | |
1126 | extern void nvc0_fifo_takedown(struct drm_device *); | |
1127 | extern void nvc0_fifo_disable(struct drm_device *); | |
1128 | extern void nvc0_fifo_enable(struct drm_device *); | |
1129 | extern bool nvc0_fifo_reassign(struct drm_device *, bool); | |
4b223eef BS |
1130 | extern bool nvc0_fifo_cache_pull(struct drm_device *, bool); |
1131 | extern int nvc0_fifo_channel_id(struct drm_device *); | |
1132 | extern int nvc0_fifo_create_context(struct nouveau_channel *); | |
1133 | extern void nvc0_fifo_destroy_context(struct nouveau_channel *); | |
1134 | extern int nvc0_fifo_load_context(struct nouveau_channel *); | |
1135 | extern int nvc0_fifo_unload_context(struct drm_device *); | |
1136 | ||
6ee73861 | 1137 | /* nv04_graph.c */ |
4976986b | 1138 | extern int nv04_graph_create(struct drm_device *); |
6ee73861 | 1139 | extern void nv04_graph_fifo_access(struct drm_device *, bool); |
4976986b | 1140 | extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); |
332b242f FJ |
1141 | extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, |
1142 | u32 class, u32 mthd, u32 data); | |
274fec93 | 1143 | extern struct nouveau_bitfield nv04_graph_nsource[]; |
6ee73861 BS |
1144 | |
1145 | /* nv10_graph.c */ | |
d11db279 | 1146 | extern int nv10_graph_create(struct drm_device *); |
6ee73861 | 1147 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); |
274fec93 BS |
1148 | extern struct nouveau_bitfield nv10_graph_intr[]; |
1149 | extern struct nouveau_bitfield nv10_graph_nstatus[]; | |
6ee73861 BS |
1150 | |
1151 | /* nv20_graph.c */ | |
a0b1de84 | 1152 | extern int nv20_graph_create(struct drm_device *); |
6ee73861 BS |
1153 | |
1154 | /* nv40_graph.c */ | |
39c8d368 | 1155 | extern int nv40_graph_create(struct drm_device *); |
054b93e4 | 1156 | extern void nv40_grctx_init(struct nouveau_grctx *); |
6ee73861 BS |
1157 | |
1158 | /* nv50_graph.c */ | |
2703c21a | 1159 | extern int nv50_graph_create(struct drm_device *); |
d5f3c90d | 1160 | extern int nv50_grctx_init(struct nouveau_grctx *); |
6effe393 | 1161 | extern struct nouveau_enum nv50_data_error_names[]; |
7ff5441e | 1162 | extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); |
6ee73861 | 1163 | |
4b223eef | 1164 | /* nvc0_graph.c */ |
7a45cd19 | 1165 | extern int nvc0_graph_create(struct drm_device *); |
d5a27370 | 1166 | extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); |
4b223eef | 1167 | |
bd2e597d | 1168 | /* nv84_crypt.c */ |
6dfdd7a6 | 1169 | extern int nv84_crypt_create(struct drm_device *); |
bd2e597d | 1170 | |
7ff5441e BS |
1171 | /* nva3_copy.c */ |
1172 | extern int nva3_copy_create(struct drm_device *dev); | |
1173 | ||
1174 | /* nvc0_copy.c */ | |
1175 | extern int nvc0_copy_create(struct drm_device *dev, int engine); | |
1176 | ||
a02ccc7f BS |
1177 | /* nv40_mpeg.c */ |
1178 | extern int nv40_mpeg_create(struct drm_device *dev); | |
1179 | ||
93187450 BS |
1180 | /* nv50_mpeg.c */ |
1181 | extern int nv50_mpeg_create(struct drm_device *dev); | |
c0924326 | 1182 | |
6ee73861 BS |
1183 | /* nv04_instmem.c */ |
1184 | extern int nv04_instmem_init(struct drm_device *); | |
1185 | extern void nv04_instmem_takedown(struct drm_device *); | |
1186 | extern int nv04_instmem_suspend(struct drm_device *); | |
1187 | extern void nv04_instmem_resume(struct drm_device *); | |
6e32fedc BS |
1188 | extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, |
1189 | u32 size, u32 align); | |
e41115d0 BS |
1190 | extern void nv04_instmem_put(struct nouveau_gpuobj *); |
1191 | extern int nv04_instmem_map(struct nouveau_gpuobj *); | |
1192 | extern void nv04_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1193 | extern void nv04_instmem_flush(struct drm_device *); |
6ee73861 BS |
1194 | |
1195 | /* nv50_instmem.c */ | |
1196 | extern int nv50_instmem_init(struct drm_device *); | |
1197 | extern void nv50_instmem_takedown(struct drm_device *); | |
1198 | extern int nv50_instmem_suspend(struct drm_device *); | |
1199 | extern void nv50_instmem_resume(struct drm_device *); | |
6e32fedc BS |
1200 | extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, |
1201 | u32 size, u32 align); | |
e41115d0 BS |
1202 | extern void nv50_instmem_put(struct nouveau_gpuobj *); |
1203 | extern int nv50_instmem_map(struct nouveau_gpuobj *); | |
1204 | extern void nv50_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1205 | extern void nv50_instmem_flush(struct drm_device *); |
734ee835 | 1206 | extern void nv84_instmem_flush(struct drm_device *); |
6ee73861 | 1207 | |
4b223eef BS |
1208 | /* nvc0_instmem.c */ |
1209 | extern int nvc0_instmem_init(struct drm_device *); | |
1210 | extern void nvc0_instmem_takedown(struct drm_device *); | |
1211 | extern int nvc0_instmem_suspend(struct drm_device *); | |
1212 | extern void nvc0_instmem_resume(struct drm_device *); | |
4b223eef | 1213 | |
6ee73861 BS |
1214 | /* nv04_mc.c */ |
1215 | extern int nv04_mc_init(struct drm_device *); | |
1216 | extern void nv04_mc_takedown(struct drm_device *); | |
1217 | ||
1218 | /* nv40_mc.c */ | |
1219 | extern int nv40_mc_init(struct drm_device *); | |
1220 | extern void nv40_mc_takedown(struct drm_device *); | |
1221 | ||
1222 | /* nv50_mc.c */ | |
1223 | extern int nv50_mc_init(struct drm_device *); | |
1224 | extern void nv50_mc_takedown(struct drm_device *); | |
1225 | ||
1226 | /* nv04_timer.c */ | |
1227 | extern int nv04_timer_init(struct drm_device *); | |
1228 | extern uint64_t nv04_timer_read(struct drm_device *); | |
1229 | extern void nv04_timer_takedown(struct drm_device *); | |
1230 | ||
1231 | extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, | |
1232 | unsigned long arg); | |
1233 | ||
1234 | /* nv04_dac.c */ | |
8f1a6086 | 1235 | extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); |
11d6eb2a | 1236 | extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); |
6ee73861 BS |
1237 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); |
1238 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); | |
8ccfe9e0 | 1239 | extern bool nv04_dac_in_use(struct drm_encoder *encoder); |
6ee73861 BS |
1240 | |
1241 | /* nv04_dfp.c */ | |
8f1a6086 | 1242 | extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1243 | extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); |
1244 | extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, | |
1245 | int head, bool dl); | |
1246 | extern void nv04_dfp_disable(struct drm_device *dev, int head); | |
1247 | extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); | |
1248 | ||
1249 | /* nv04_tv.c */ | |
1250 | extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); | |
8f1a6086 | 1251 | extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1252 | |
1253 | /* nv17_tv.c */ | |
8f1a6086 | 1254 | extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1255 | |
1256 | /* nv04_display.c */ | |
c88c2e06 FJ |
1257 | extern int nv04_display_early_init(struct drm_device *); |
1258 | extern void nv04_display_late_takedown(struct drm_device *); | |
6ee73861 | 1259 | extern int nv04_display_create(struct drm_device *); |
c88c2e06 | 1260 | extern int nv04_display_init(struct drm_device *); |
6ee73861 | 1261 | extern void nv04_display_destroy(struct drm_device *); |
6ee73861 BS |
1262 | |
1263 | /* nv04_crtc.c */ | |
1264 | extern int nv04_crtc_create(struct drm_device *, int index); | |
1265 | ||
1266 | /* nouveau_bo.c */ | |
1267 | extern struct ttm_bo_driver nouveau_bo_driver; | |
1268 | extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *, | |
1269 | int size, int align, uint32_t flags, | |
1270 | uint32_t tile_mode, uint32_t tile_flags, | |
d550c41e | 1271 | struct nouveau_bo **); |
6ee73861 BS |
1272 | extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); |
1273 | extern int nouveau_bo_unpin(struct nouveau_bo *); | |
1274 | extern int nouveau_bo_map(struct nouveau_bo *); | |
1275 | extern void nouveau_bo_unmap(struct nouveau_bo *); | |
78ad0f7b FJ |
1276 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, |
1277 | uint32_t busy); | |
6ee73861 BS |
1278 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); |
1279 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); | |
1280 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); | |
1281 | extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); | |
332b242f | 1282 | extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); |
7a45d764 BS |
1283 | extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, |
1284 | bool no_wait_reserve, bool no_wait_gpu); | |
6ee73861 BS |
1285 | |
1286 | /* nouveau_fence.c */ | |
1287 | struct nouveau_fence; | |
0c6c1c2f FJ |
1288 | extern int nouveau_fence_init(struct drm_device *); |
1289 | extern void nouveau_fence_fini(struct drm_device *); | |
2730723b FJ |
1290 | extern int nouveau_fence_channel_init(struct nouveau_channel *); |
1291 | extern void nouveau_fence_channel_fini(struct nouveau_channel *); | |
6ee73861 BS |
1292 | extern void nouveau_fence_update(struct nouveau_channel *); |
1293 | extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **, | |
1294 | bool emit); | |
1295 | extern int nouveau_fence_emit(struct nouveau_fence *); | |
8ac3891b FJ |
1296 | extern void nouveau_fence_work(struct nouveau_fence *fence, |
1297 | void (*work)(void *priv, bool signalled), | |
1298 | void *priv); | |
6ee73861 | 1299 | struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *); |
382d62e5 MS |
1300 | |
1301 | extern bool __nouveau_fence_signalled(void *obj, void *arg); | |
1302 | extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr); | |
1303 | extern int __nouveau_fence_flush(void *obj, void *arg); | |
1304 | extern void __nouveau_fence_unref(void **obj); | |
1305 | extern void *__nouveau_fence_ref(void *obj); | |
1306 | ||
1307 | static inline bool nouveau_fence_signalled(struct nouveau_fence *obj) | |
1308 | { | |
1309 | return __nouveau_fence_signalled(obj, NULL); | |
1310 | } | |
1311 | static inline int | |
1312 | nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr) | |
1313 | { | |
1314 | return __nouveau_fence_wait(obj, NULL, lazy, intr); | |
1315 | } | |
2730723b | 1316 | extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *); |
382d62e5 MS |
1317 | static inline int nouveau_fence_flush(struct nouveau_fence *obj) |
1318 | { | |
1319 | return __nouveau_fence_flush(obj, NULL); | |
1320 | } | |
1321 | static inline void nouveau_fence_unref(struct nouveau_fence **obj) | |
1322 | { | |
1323 | __nouveau_fence_unref((void **)obj); | |
1324 | } | |
1325 | static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj) | |
1326 | { | |
1327 | return __nouveau_fence_ref(obj); | |
1328 | } | |
6ee73861 BS |
1329 | |
1330 | /* nouveau_gem.c */ | |
f6d4e621 BS |
1331 | extern int nouveau_gem_new(struct drm_device *, int size, int align, |
1332 | uint32_t domain, uint32_t tile_mode, | |
1333 | uint32_t tile_flags, struct nouveau_bo **); | |
6ee73861 BS |
1334 | extern int nouveau_gem_object_new(struct drm_gem_object *); |
1335 | extern void nouveau_gem_object_del(struct drm_gem_object *); | |
639212d0 BS |
1336 | extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); |
1337 | extern void nouveau_gem_object_close(struct drm_gem_object *, | |
1338 | struct drm_file *); | |
6ee73861 BS |
1339 | extern int nouveau_gem_ioctl_new(struct drm_device *, void *, |
1340 | struct drm_file *); | |
1341 | extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, | |
1342 | struct drm_file *); | |
6ee73861 BS |
1343 | extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, |
1344 | struct drm_file *); | |
1345 | extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, | |
1346 | struct drm_file *); | |
1347 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | |
1348 | struct drm_file *); | |
1349 | ||
042206c0 FJ |
1350 | /* nouveau_display.c */ |
1351 | int nouveau_vblank_enable(struct drm_device *dev, int crtc); | |
1352 | void nouveau_vblank_disable(struct drm_device *dev, int crtc); | |
332b242f FJ |
1353 | int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1354 | struct drm_pending_vblank_event *event); | |
1355 | int nouveau_finish_page_flip(struct nouveau_channel *, | |
1356 | struct nouveau_page_flip_state *); | |
042206c0 | 1357 | |
ee2e0131 BS |
1358 | /* nv10_gpio.c */ |
1359 | int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); | |
1360 | int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
6ee73861 | 1361 | |
45284162 | 1362 | /* nv50_gpio.c */ |
ee2e0131 | 1363 | int nv50_gpio_init(struct drm_device *dev); |
2cbd4c81 | 1364 | void nv50_gpio_fini(struct drm_device *dev); |
45284162 BS |
1365 | int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag); |
1366 | int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state); | |
fce2bad0 BS |
1367 | int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag, |
1368 | void (*)(void *, int), void *); | |
1369 | void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, | |
1370 | void (*)(void *, int), void *); | |
1371 | bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); | |
45284162 | 1372 | |
e9ebb68b BS |
1373 | /* nv50_calc. */ |
1374 | int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, | |
1375 | int *N1, int *M1, int *N2, int *M2, int *P); | |
52eba8dd BS |
1376 | int nva3_calc_pll(struct drm_device *, struct pll_lims *, |
1377 | int clk, int *N, int *fN, int *M, int *P); | |
e9ebb68b | 1378 | |
6ee73861 BS |
1379 | #ifndef ioread32_native |
1380 | #ifdef __BIG_ENDIAN | |
1381 | #define ioread16_native ioread16be | |
1382 | #define iowrite16_native iowrite16be | |
1383 | #define ioread32_native ioread32be | |
1384 | #define iowrite32_native iowrite32be | |
1385 | #else /* def __BIG_ENDIAN */ | |
1386 | #define ioread16_native ioread16 | |
1387 | #define iowrite16_native iowrite16 | |
1388 | #define ioread32_native ioread32 | |
1389 | #define iowrite32_native iowrite32 | |
1390 | #endif /* def __BIG_ENDIAN else */ | |
1391 | #endif /* !ioread32_native */ | |
1392 | ||
1393 | /* channel control reg access */ | |
1394 | static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) | |
1395 | { | |
1396 | return ioread32_native(chan->user + reg); | |
1397 | } | |
1398 | ||
1399 | static inline void nvchan_wr32(struct nouveau_channel *chan, | |
1400 | unsigned reg, u32 val) | |
1401 | { | |
1402 | iowrite32_native(val, chan->user + reg); | |
1403 | } | |
1404 | ||
1405 | /* register access */ | |
1406 | static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) | |
1407 | { | |
1408 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1409 | return ioread32_native(dev_priv->mmio + reg); | |
1410 | } | |
1411 | ||
1412 | static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) | |
1413 | { | |
1414 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1415 | iowrite32_native(val, dev_priv->mmio + reg); | |
1416 | } | |
1417 | ||
2a7fdb2b | 1418 | static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) |
49eed80a BS |
1419 | { |
1420 | u32 tmp = nv_rd32(dev, reg); | |
2a7fdb2b BS |
1421 | nv_wr32(dev, reg, (tmp & ~mask) | val); |
1422 | return tmp; | |
49eed80a BS |
1423 | } |
1424 | ||
6ee73861 BS |
1425 | static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) |
1426 | { | |
1427 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1428 | return ioread8(dev_priv->mmio + reg); | |
1429 | } | |
1430 | ||
1431 | static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) | |
1432 | { | |
1433 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1434 | iowrite8(val, dev_priv->mmio + reg); | |
1435 | } | |
1436 | ||
4b5c152a | 1437 | #define nv_wait(dev, reg, mask, val) \ |
12fb9525 BS |
1438 | nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) |
1439 | #define nv_wait_ne(dev, reg, mask, val) \ | |
1440 | nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) | |
6ee73861 BS |
1441 | |
1442 | /* PRAMIN access */ | |
1443 | static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) | |
1444 | { | |
1445 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1446 | return ioread32_native(dev_priv->ramin + offset); | |
1447 | } | |
1448 | ||
1449 | static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) | |
1450 | { | |
1451 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1452 | iowrite32_native(val, dev_priv->ramin + offset); | |
1453 | } | |
1454 | ||
1455 | /* object access */ | |
b3beb167 BS |
1456 | extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); |
1457 | extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); | |
6ee73861 BS |
1458 | |
1459 | /* | |
1460 | * Logging | |
1461 | * Argument d is (struct drm_device *). | |
1462 | */ | |
1463 | #define NV_PRINTK(level, d, fmt, arg...) \ | |
1464 | printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ | |
1465 | pci_name(d->pdev), ##arg) | |
1466 | #ifndef NV_DEBUG_NOTRACE | |
1467 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1468 | if (drm_debug & DRM_UT_DRIVER) { \ |
1469 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ | |
1470 | __LINE__, ##arg); \ | |
1471 | } \ | |
1472 | } while (0) | |
1473 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1474 | if (drm_debug & DRM_UT_KMS) { \ | |
6ee73861 BS |
1475 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ |
1476 | __LINE__, ##arg); \ | |
1477 | } \ | |
1478 | } while (0) | |
1479 | #else | |
1480 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1481 | if (drm_debug & DRM_UT_DRIVER) \ |
1482 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ | |
1483 | } while (0) | |
1484 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1485 | if (drm_debug & DRM_UT_KMS) \ | |
6ee73861 BS |
1486 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ |
1487 | } while (0) | |
1488 | #endif | |
1489 | #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) | |
1490 | #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1491 | #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) | |
1492 | #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1493 | #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) | |
1494 | ||
1495 | /* nouveau_reg_debug bitmask */ | |
1496 | enum { | |
1497 | NOUVEAU_REG_DEBUG_MC = 0x1, | |
1498 | NOUVEAU_REG_DEBUG_VIDEO = 0x2, | |
1499 | NOUVEAU_REG_DEBUG_FB = 0x4, | |
1500 | NOUVEAU_REG_DEBUG_EXTDEV = 0x8, | |
1501 | NOUVEAU_REG_DEBUG_CRTC = 0x10, | |
1502 | NOUVEAU_REG_DEBUG_RAMDAC = 0x20, | |
1503 | NOUVEAU_REG_DEBUG_VGACRTC = 0x40, | |
1504 | NOUVEAU_REG_DEBUG_RMVIO = 0x80, | |
1505 | NOUVEAU_REG_DEBUG_VGAATTR = 0x100, | |
1506 | NOUVEAU_REG_DEBUG_EVO = 0x200, | |
1507 | }; | |
1508 | ||
1509 | #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ | |
1510 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ | |
1511 | NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ | |
1512 | } while (0) | |
1513 | ||
1514 | static inline bool | |
1515 | nv_two_heads(struct drm_device *dev) | |
1516 | { | |
1517 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1518 | const int impl = dev->pci_device & 0x0ff0; | |
1519 | ||
1520 | if (dev_priv->card_type >= NV_10 && impl != 0x0100 && | |
1521 | impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) | |
1522 | return true; | |
1523 | ||
1524 | return false; | |
1525 | } | |
1526 | ||
1527 | static inline bool | |
1528 | nv_gf4_disp_arch(struct drm_device *dev) | |
1529 | { | |
1530 | return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; | |
1531 | } | |
1532 | ||
1533 | static inline bool | |
1534 | nv_two_reg_pll(struct drm_device *dev) | |
1535 | { | |
1536 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1537 | const int impl = dev->pci_device & 0x0ff0; | |
1538 | ||
1539 | if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) | |
1540 | return true; | |
1541 | return false; | |
1542 | } | |
1543 | ||
acae116c FJ |
1544 | static inline bool |
1545 | nv_match_device(struct drm_device *dev, unsigned device, | |
1546 | unsigned sub_vendor, unsigned sub_device) | |
1547 | { | |
1548 | return dev->pdev->device == device && | |
1549 | dev->pdev->subsystem_vendor == sub_vendor && | |
1550 | dev->pdev->subsystem_device == sub_device; | |
1551 | } | |
1552 | ||
6dfdd7a6 BS |
1553 | static inline void * |
1554 | nv_engine(struct drm_device *dev, int engine) | |
1555 | { | |
1556 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1557 | return (void *)dev_priv->eng[engine]; | |
1558 | } | |
1559 | ||
c693931d BS |
1560 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, |
1561 | * helpful to determine a number of other hardware features | |
1562 | */ | |
1563 | static inline int | |
1564 | nv44_graph_class(struct drm_device *dev) | |
1565 | { | |
1566 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1567 | ||
1568 | if ((dev_priv->chipset & 0xf0) == 0x60) | |
1569 | return 1; | |
1570 | ||
1571 | return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); | |
1572 | } | |
1573 | ||
7f4a195f | 1574 | /* memory type/access flags, do not match hardware values */ |
a11c3198 BS |
1575 | #define NV_MEM_ACCESS_RO 1 |
1576 | #define NV_MEM_ACCESS_WO 2 | |
7f4a195f | 1577 | #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) |
a11c3198 BS |
1578 | #define NV_MEM_ACCESS_SYS 4 |
1579 | #define NV_MEM_ACCESS_VM 8 | |
7f4a195f BS |
1580 | |
1581 | #define NV_MEM_TARGET_VRAM 0 | |
1582 | #define NV_MEM_TARGET_PCI 1 | |
1583 | #define NV_MEM_TARGET_PCI_NOSNOOP 2 | |
1584 | #define NV_MEM_TARGET_VM 3 | |
1585 | #define NV_MEM_TARGET_GART 4 | |
1586 | ||
1587 | #define NV_MEM_TYPE_VM 0x7f | |
1588 | #define NV_MEM_COMP_VM 0x03 | |
1589 | ||
1590 | /* NV_SW object class */ | |
f03a314b FJ |
1591 | #define NV_SW 0x0000506e |
1592 | #define NV_SW_DMA_SEMAPHORE 0x00000060 | |
1593 | #define NV_SW_SEMAPHORE_OFFSET 0x00000064 | |
1594 | #define NV_SW_SEMAPHORE_ACQUIRE 0x00000068 | |
1595 | #define NV_SW_SEMAPHORE_RELEASE 0x0000006c | |
8af29ccd | 1596 | #define NV_SW_YIELD 0x00000080 |
f03a314b FJ |
1597 | #define NV_SW_DMA_VBLSEM 0x0000018c |
1598 | #define NV_SW_VBLSEM_OFFSET 0x00000400 | |
1599 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 | |
1600 | #define NV_SW_VBLSEM_RELEASE 0x00000408 | |
332b242f | 1601 | #define NV_SW_PAGE_FLIP 0x00000500 |
6ee73861 BS |
1602 | |
1603 | #endif /* __NOUVEAU_DRV_H__ */ |