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drm/edid: Split mode lists out to their own header for readability
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv04_crtc.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 1993-2003 NVIDIA, Corporation
3 * Copyright 2006 Dave Airlie
4 * Copyright 2007 Maarten Maathuis
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include "drmP.h"
27#include "drm_crtc_helper.h"
28
29#include "nouveau_drv.h"
30#include "nouveau_encoder.h"
31#include "nouveau_connector.h"
32#include "nouveau_crtc.h"
33#include "nouveau_fb.h"
34#include "nouveau_hw.h"
35#include "nvreg.h"
36
37static int
38nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
39 struct drm_framebuffer *old_fb);
40
41static void
42crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
43{
44 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
45 crtcstate->CRTC[index]);
46}
47
48static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level)
49{
50 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
51 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
52 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
53
54 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level;
55 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) {
56 regp->CRTC[NV_CIO_CRE_CSB] = 0x80;
57 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2;
58 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B);
59 }
60 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB);
61}
62
63static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level)
64{
65 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
66 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
67 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
68
69 nv_crtc->sharpness = level;
70 if (level < 0) /* blur is in hw range 0x3f -> 0x20 */
71 level += 0x40;
72 regp->ramdac_634 = level;
73 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
74}
75
76#define PLLSEL_VPLL1_MASK \
77 (NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_VPLL \
78 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK_RATIO_DB2)
79#define PLLSEL_VPLL2_MASK \
80 (NV_PRAMDAC_PLL_COEFF_SELECT_PLL_SOURCE_VPLL2 \
81 | NV_PRAMDAC_PLL_COEFF_SELECT_VCLK2_RATIO_DB2)
82#define PLLSEL_TV_MASK \
83 (NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK1 \
84 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK1 \
85 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_VSCLK2 \
86 | NV_PRAMDAC_PLL_COEFF_SELECT_TV_PCLK2)
87
88/* NV4x 0x40.. pll notes:
89 * gpu pll: 0x4000 + 0x4004
90 * ?gpu? pll: 0x4008 + 0x400c
91 * vpll1: 0x4010 + 0x4014
92 * vpll2: 0x4018 + 0x401c
93 * mpll: 0x4020 + 0x4024
94 * mpll: 0x4038 + 0x403c
95 *
96 * the first register of each pair has some unknown details:
97 * bits 0-7: redirected values from elsewhere? (similar to PLL_SETUP_CONTROL?)
98 * bits 20-23: (mpll) something to do with post divider?
99 * bits 28-31: related to single stage mode? (bit 8/12)
100 */
101
102static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
103{
104 struct drm_device *dev = crtc->dev;
105 struct drm_nouveau_private *dev_priv = dev->dev_private;
106 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
107 struct nv04_mode_state *state = &dev_priv->mode_reg;
108 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
109 struct nouveau_pll_vals *pv = &regp->pllvals;
110 struct pll_lims pll_lim;
111
112 if (get_pll_limits(dev, nv_crtc->index ? VPLL2 : VPLL1, &pll_lim))
113 return;
114
115 /* NM2 == 0 is used to determine single stage mode on two stage plls */
116 pv->NM2 = 0;
117
118 /* for newer nv4x the blob uses only the first stage of the vpll below a
119 * certain clock. for a certain nv4b this is 150MHz. since the max
120 * output frequency of the first stage for this card is 300MHz, it is
121 * assumed the threshold is given by vco1 maxfreq/2
122 */
123 /* for early nv4x, specifically nv40 and *some* nv43 (devids 0 and 6,
124 * not 8, others unknown), the blob always uses both plls. no problem
125 * has yet been observed in allowing the use a single stage pll on all
126 * nv43 however. the behaviour of single stage use is untested on nv40
127 */
128 if (dev_priv->chipset > 0x40 && dot_clock <= (pll_lim.vco1.maxfreq / 2))
129 memset(&pll_lim.vco2, 0, sizeof(pll_lim.vco2));
130
131 if (!nouveau_calc_pll_mnp(dev, &pll_lim, dot_clock, pv))
132 return;
133
134 state->pllsel &= PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK;
135
136 /* The blob uses this always, so let's do the same */
137 if (dev_priv->card_type == NV_40)
138 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_USE_VPLL2_TRUE;
139 /* again nv40 and some nv43 act more like nv3x as described above */
140 if (dev_priv->chipset < 0x41)
141 state->pllsel |= NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_MPLL |
142 NV_PRAMDAC_PLL_COEFF_SELECT_SOURCE_PROG_NVPLL;
143 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
144
145 if (pv->NM2)
ef2bb506 146 NV_DEBUG_KMS(dev, "vpll: n1 %d n2 %d m1 %d m2 %d log2p %d\n",
6ee73861
BS		 147 pv->N1, pv->N2, pv->M1, pv->M2, pv->log2P);
148 else
ef2bb506 149 NV_DEBUG_KMS(dev, "vpll: n %d m %d log2p %d\n",
6ee73861
BS		 150 pv->N1, pv->M1, pv->log2P);
151
152 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
153}
154
155static void
156nv_crtc_dpms(struct drm_crtc *crtc, int mode)
157{
158 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
159 struct drm_device *dev = crtc->dev;
2ed06b7d 160 struct drm_connector *connector;
6ee73861
BS		 161 unsigned char seq1 = 0, crtc17 = 0;
162 unsigned char crtc1A;
163
ef2bb506 164 NV_DEBUG_KMS(dev, "Setting dpms mode %d on CRTC %d\n", mode,
6ee73861
BS		 165 nv_crtc->index);
166
167 if (nv_crtc->last_dpms == mode) /* Don't do unnecesary mode changes. */
168 return;
169
170 nv_crtc->last_dpms = mode;
171
172 if (nv_two_heads(dev))
173 NVSetOwner(dev, nv_crtc->index);
174
175 /* nv4ref indicates these two RPC1 bits inhibit h/v sync */
176 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
177 NV_CIO_CRE_RPC1_INDEX) & ~0xC0;
178 switch (mode) {
179 case DRM_MODE_DPMS_STANDBY:
180 /* Screen: Off; HSync: Off, VSync: On -- Not Supported */
181 seq1 = 0x20;
182 crtc17 = 0x80;
183 crtc1A |= 0x80;
184 break;
185 case DRM_MODE_DPMS_SUSPEND:
186 /* Screen: Off; HSync: On, VSync: Off -- Not Supported */
187 seq1 = 0x20;
188 crtc17 = 0x80;
189 crtc1A |= 0x40;
190 break;
191 case DRM_MODE_DPMS_OFF:
192 /* Screen: Off; HSync: Off, VSync: Off */
193 seq1 = 0x20;
194 crtc17 = 0x00;
195 crtc1A |= 0xC0;
196 break;
197 case DRM_MODE_DPMS_ON:
198 default:
199 /* Screen: On; HSync: On, VSync: On */
200 seq1 = 0x00;
201 crtc17 = 0x80;
202 break;
203 }
204
205 NVVgaSeqReset(dev, nv_crtc->index, true);
206 /* Each head has it's own sequencer, so we can turn it off when we want */
207 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
208 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
209 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
210 mdelay(10);
211 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
212 NVVgaSeqReset(dev, nv_crtc->index, false);
213
214 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
2ed06b7d
FJ		 215
216 /* Update connector polling modes */
217 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
218 nouveau_connector_set_polling(connector);
6ee73861
BS		 219}
220
221static bool
222nv_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
223 struct drm_display_mode *adjusted_mode)
224{
225 return true;
226}
227
228static void
229nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
230{
231 struct drm_device *dev = crtc->dev;
232 struct drm_nouveau_private *dev_priv = dev->dev_private;
233 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
234 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
235 struct drm_framebuffer *fb = crtc->fb;
236
237 /* Calculate our timings */
e5ec882c
FJ		 238 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
239 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
240 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
6ee73861
BS		 241 int horizTotal = (mode->crtc_htotal >> 3) - 5;
242 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
243 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
244 int vertDisplay = mode->crtc_vdisplay - 1;
245 int vertStart = mode->crtc_vsync_start - 1;
246 int vertEnd = mode->crtc_vsync_end - 1;
247 int vertTotal = mode->crtc_vtotal - 2;
248 int vertBlankStart = mode->crtc_vdisplay - 1;
249 int vertBlankEnd = mode->crtc_vtotal - 1;
250
251 struct drm_encoder *encoder;
252 bool fp_output = false;
253
254 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
255 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
256
257 if (encoder->crtc == crtc &&
258 (nv_encoder->dcb->type == OUTPUT_LVDS ||
259 nv_encoder->dcb->type == OUTPUT_TMDS))
260 fp_output = true;
261 }
262
263 if (fp_output) {
264 vertStart = vertTotal - 3;
265 vertEnd = vertTotal - 2;
266 vertBlankStart = vertStart;
267 horizStart = horizTotal - 5;
268 horizEnd = horizTotal - 2;
269 horizBlankEnd = horizTotal + 4;
270#if 0
271 if (dev->overlayAdaptor && dev_priv->card_type >= NV_10)
272 /* This reportedly works around some video overlay bandwidth problems */
273 horizTotal += 2;
274#endif
275 }
276
277 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
278 vertTotal |= 1;
279
280#if 0
281 ErrorF("horizDisplay: 0x%X \n", horizDisplay);
282 ErrorF("horizStart: 0x%X \n", horizStart);
283 ErrorF("horizEnd: 0x%X \n", horizEnd);
284 ErrorF("horizTotal: 0x%X \n", horizTotal);
285 ErrorF("horizBlankStart: 0x%X \n", horizBlankStart);
286 ErrorF("horizBlankEnd: 0x%X \n", horizBlankEnd);
287 ErrorF("vertDisplay: 0x%X \n", vertDisplay);
288 ErrorF("vertStart: 0x%X \n", vertStart);
289 ErrorF("vertEnd: 0x%X \n", vertEnd);
290 ErrorF("vertTotal: 0x%X \n", vertTotal);
291 ErrorF("vertBlankStart: 0x%X \n", vertBlankStart);
292 ErrorF("vertBlankEnd: 0x%X \n", vertBlankEnd);
293#endif
294
295 /*
296 * compute correct Hsync & Vsync polarity
297 */
298 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
299 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
300
301 regp->MiscOutReg = 0x23;
302 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
303 regp->MiscOutReg |= 0x40;
304 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
305 regp->MiscOutReg |= 0x80;
306 } else {
307 int vdisplay = mode->vdisplay;
308 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
309 vdisplay *= 2;
310 if (mode->vscan > 1)
311 vdisplay *= mode->vscan;
312 if (vdisplay < 400)
313 regp->MiscOutReg = 0xA3; /* +hsync -vsync */
314 else if (vdisplay < 480)
315 regp->MiscOutReg = 0x63; /* -hsync +vsync */
316 else if (vdisplay < 768)
317 regp->MiscOutReg = 0xE3; /* -hsync -vsync */
318 else
319 regp->MiscOutReg = 0x23; /* +hsync +vsync */
320 }
321
322 regp->MiscOutReg |= (mode->clock_index & 0x03) << 2;
323
324 /*
325 * Time Sequencer
326 */
327 regp->Sequencer[NV_VIO_SR_RESET_INDEX] = 0x00;
328 /* 0x20 disables the sequencer */
329 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
330 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x29;
331 else
332 regp->Sequencer[NV_VIO_SR_CLOCK_INDEX] = 0x21;
333 regp->Sequencer[NV_VIO_SR_PLANE_MASK_INDEX] = 0x0F;
334 regp->Sequencer[NV_VIO_SR_CHAR_MAP_INDEX] = 0x00;
335 regp->Sequencer[NV_VIO_SR_MEM_MODE_INDEX] = 0x0E;
336
337 /*
338 * CRTC
339 */
340 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal;
341 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay;
342 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart;
343 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) |
344 XLATE(horizBlankEnd, 0, NV_CIO_CR_HBE_4_0);
345 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart;
346 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) |
347 XLATE(horizEnd, 0, NV_CIO_CR_HRE_4_0);
348 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal;
349 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) |
350 XLATE(vertDisplay, 9, NV_CIO_CR_OVL_VDE_9) |
351 XLATE(vertTotal, 9, NV_CIO_CR_OVL_VDT_9) |
352 (1 << 4) |
353 XLATE(vertBlankStart, 8, NV_CIO_CR_OVL_VBS_8) |
354 XLATE(vertStart, 8, NV_CIO_CR_OVL_VRS_8) |
355 XLATE(vertDisplay, 8, NV_CIO_CR_OVL_VDE_8) |
356 XLATE(vertTotal, 8, NV_CIO_CR_OVL_VDT_8);
357 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00;
358 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
359 1 << 6 |
360 XLATE(vertBlankStart, 9, NV_CIO_CR_CELL_HT_VBS_9);
361 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00;
362 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00;
363 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00;
364 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00;
365 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00;
366 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00;
367 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart;
368 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0);
369 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay;
370 /* framebuffer can be larger than crtc scanout area. */
371 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitch / 8;
372 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00;
373 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart;
374 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd;
375 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43;
376 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff;
377
378 /*
379 * Some extended CRTC registers (they are not saved with the rest of the vga regs).
380 */
381
382 /* framebuffer can be larger than crtc scanout area. */
383 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
384 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
385 MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
386 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
387 XLATE(vertBlankStart, 10, NV_CIO_CRE_LSR_VBS_10) |
388 XLATE(vertStart, 10, NV_CIO_CRE_LSR_VRS_10) |
389 XLATE(vertDisplay, 10, NV_CIO_CRE_LSR_VDE_10) |
390 XLATE(vertTotal, 10, NV_CIO_CRE_LSR_VDT_10);
391 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) |
392 XLATE(horizBlankStart, 8, NV_CIO_CRE_HEB_HBS_8) |
393 XLATE(horizDisplay, 8, NV_CIO_CRE_HEB_HDE_8) |
394 XLATE(horizTotal, 8, NV_CIO_CRE_HEB_HDT_8);
395 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) |
396 XLATE(vertStart, 11, NV_CIO_CRE_EBR_VRS_11) |
397 XLATE(vertDisplay, 11, NV_CIO_CRE_EBR_VDE_11) |
398 XLATE(vertTotal, 11, NV_CIO_CRE_EBR_VDT_11);
399
400 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
401 horizTotal = (horizTotal >> 1) & ~1;
402 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal;
403 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8);
404 } else
405 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */
406
407 /*
408 * Graphics Display Controller
409 */
410 regp->Graphics[NV_VIO_GX_SR_INDEX] = 0x00;
411 regp->Graphics[NV_VIO_GX_SREN_INDEX] = 0x00;
412 regp->Graphics[NV_VIO_GX_CCOMP_INDEX] = 0x00;
413 regp->Graphics[NV_VIO_GX_ROP_INDEX] = 0x00;
414 regp->Graphics[NV_VIO_GX_READ_MAP_INDEX] = 0x00;
415 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
416 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
417 regp->Graphics[NV_VIO_GX_DONT_CARE_INDEX] = 0x0F;
418 regp->Graphics[NV_VIO_GX_BIT_MASK_INDEX] = 0xFF;
419
420 regp->Attribute[0] = 0x00; /* standard colormap translation */
421 regp->Attribute[1] = 0x01;
422 regp->Attribute[2] = 0x02;
423 regp->Attribute[3] = 0x03;
424 regp->Attribute[4] = 0x04;
425 regp->Attribute[5] = 0x05;
426 regp->Attribute[6] = 0x06;
427 regp->Attribute[7] = 0x07;
428 regp->Attribute[8] = 0x08;
429 regp->Attribute[9] = 0x09;
430 regp->Attribute[10] = 0x0A;
431 regp->Attribute[11] = 0x0B;
432 regp->Attribute[12] = 0x0C;
433 regp->Attribute[13] = 0x0D;
434 regp->Attribute[14] = 0x0E;
435 regp->Attribute[15] = 0x0F;
436 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
437 /* Non-vga */
438 regp->Attribute[NV_CIO_AR_OSCAN_INDEX] = 0x00;
439 regp->Attribute[NV_CIO_AR_PLANE_INDEX] = 0x0F; /* enable all color planes */
440 regp->Attribute[NV_CIO_AR_HPP_INDEX] = 0x00;
441 regp->Attribute[NV_CIO_AR_CSEL_INDEX] = 0x00;
442}
443
444/**
445 * Sets up registers for the given mode/adjusted_mode pair.
446 *
447 * The clocks, CRTCs and outputs attached to this CRTC must be off.
448 *
449 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
450 * be easily turned on/off after this.
451 */
452static void
453nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
454{
455 struct drm_device *dev = crtc->dev;
456 struct drm_nouveau_private *dev_priv = dev->dev_private;
457 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
458 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
459 struct nv04_crtc_reg *savep = &dev_priv->saved_reg.crtc_reg[nv_crtc->index];
460 struct drm_encoder *encoder;
461 bool lvds_output = false, tmds_output = false, tv_output = false,
462 off_chip_digital = false;
463
464 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
465 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
466 bool digital = false;
467
468 if (encoder->crtc != crtc)
469 continue;
470
471 if (nv_encoder->dcb->type == OUTPUT_LVDS)
472 digital = lvds_output = true;
473 if (nv_encoder->dcb->type == OUTPUT_TV)
474 tv_output = true;
475 if (nv_encoder->dcb->type == OUTPUT_TMDS)
476 digital = tmds_output = true;
477 if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital)
478 off_chip_digital = true;
479 }
480
481 /* Registers not directly related to the (s)vga mode */
482
483 /* What is the meaning of this register? */
484 /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
485 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5);
486
487 regp->crtc_eng_ctrl = 0;
488 /* Except for rare conditions I2C is enabled on the primary crtc */
489 if (nv_crtc->index == 0)
490 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
491#if 0
492 /* Set overlay to desired crtc. */
493 if (dev->overlayAdaptor) {
494 NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
495 if (pPriv->overlayCRTC == nv_crtc->index)
496 regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
497 }
498#endif
499
500 /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
501 regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 |
502 NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 |
503 NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
504 if (dev_priv->chipset >= 0x11)
505 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
506 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
507 regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
508
509 /* Unblock some timings */
510 regp->CRTC[NV_CIO_CRE_53] = 0;
511 regp->CRTC[NV_CIO_CRE_54] = 0;
512
513 /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
514 if (lvds_output)
515 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
516 else if (tmds_output)
517 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
518 else
519 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
520
521 /* These values seem to vary */
522 /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
523 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
524
525 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
526
527 /* probably a scratch reg, but kept for cargo-cult purposes:
528 * bit0: crtc0?, head A
529 * bit6: lvds, head A
530 * bit7: (only in X), head A
531 */
532 if (nv_crtc->index == 0)
533 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
534
535 /* The blob seems to take the current value from crtc 0, add 4 to that
536 * and reuse the old value for crtc 1 */
537 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = dev_priv->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
538 if (!nv_crtc->index)
539 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
540
541 /* the blob sometimes sets |= 0x10 (which is the same as setting |=
542 * 1 << 30 on 0x60.830), for no apparent reason */
543 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
544
4a9f822f
FJ		 545 if (dev_priv->card_type >= NV_30)
546 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
547
6ee73861
BS		 548 regp->crtc_830 = mode->crtc_vdisplay - 3;
549 regp->crtc_834 = mode->crtc_vdisplay - 1;
550
551 if (dev_priv->card_type == NV_40)
552 /* This is what the blob does */
553 regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
554
555 if (dev_priv->card_type >= NV_30)
556 regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
557
558 regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
559
560 /* Some misc regs */
561 if (dev_priv->card_type == NV_40) {
562 regp->CRTC[NV_CIO_CRE_85] = 0xFF;
563 regp->CRTC[NV_CIO_CRE_86] = 0x1;
564 }
565
566 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (crtc->fb->depth + 1) / 8;
567 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
568 if (lvds_output || tmds_output || tv_output)
569 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
570
571 /* Generic PRAMDAC regs */
572
573 if (dev_priv->card_type >= NV_10)
574 /* Only bit that bios and blob set. */
575 regp->nv10_cursync = (1 << 25);
576
577 regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS |
578 NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL |
579 NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
580 if (crtc->fb->depth == 16)
581 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
582 if (dev_priv->chipset >= 0x11)
583 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
584
585 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
586 regp->tv_setup = 0;
587
588 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
589
590 /* Some values the blob sets */
591 regp->ramdac_8c0 = 0x100;
592 regp->ramdac_a20 = 0x0;
593 regp->ramdac_a24 = 0xfffff;
594 regp->ramdac_a34 = 0x1;
595}
596
597/**
598 * Sets up registers for the given mode/adjusted_mode pair.
599 *
600 * The clocks, CRTCs and outputs attached to this CRTC must be off.
601 *
602 * This shouldn't enable any clocks, CRTCs, or outputs, but they should
603 * be easily turned on/off after this.
604 */
605static int
606nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
607 struct drm_display_mode *adjusted_mode,
608 int x, int y, struct drm_framebuffer *old_fb)
609{
610 struct drm_device *dev = crtc->dev;
611 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
612 struct drm_nouveau_private *dev_priv = dev->dev_private;
613
ef2bb506 614 NV_DEBUG_KMS(dev, "CTRC mode on CRTC %d:\n", nv_crtc->index);
6ee73861
BS		 615 drm_mode_debug_printmodeline(adjusted_mode);
616
617 /* unlock must come after turning off FP_TG_CONTROL in output_prepare */
618 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
619
620 nv_crtc_mode_set_vga(crtc, adjusted_mode);
621 /* calculated in nv04_dfp_prepare, nv40 needs it written before calculating PLLs */
622 if (dev_priv->card_type == NV_40)
623 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, dev_priv->mode_reg.sel_clk);
624 nv_crtc_mode_set_regs(crtc, adjusted_mode);
625 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
626 return 0;
627}
628
629static void nv_crtc_save(struct drm_crtc *crtc)
630{
631 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
632 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
633 struct nv04_mode_state *state = &dev_priv->mode_reg;
634 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
635 struct nv04_mode_state *saved = &dev_priv->saved_reg;
636 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
637
638 if (nv_two_heads(crtc->dev))
639 NVSetOwner(crtc->dev, nv_crtc->index);
640
641 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
642
643 /* init some state to saved value */
644 state->sel_clk = saved->sel_clk & ~(0x5 << 16);
645 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX];
646 state->pllsel = saved->pllsel & ~(PLLSEL_VPLL1_MASK | PLLSEL_VPLL2_MASK | PLLSEL_TV_MASK);
647 crtc_state->gpio_ext = crtc_saved->gpio_ext;
648}
649
650static void nv_crtc_restore(struct drm_crtc *crtc)
651{
652 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
653 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
654 int head = nv_crtc->index;
655 uint8_t saved_cr21 = dev_priv->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21];
656
657 if (nv_two_heads(crtc->dev))
658 NVSetOwner(crtc->dev, head);
659
660 nouveau_hw_load_state(crtc->dev, head, &dev_priv->saved_reg);
661 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21);
662
663 nv_crtc->last_dpms = NV_DPMS_CLEARED;
664}
665
666static void nv_crtc_prepare(struct drm_crtc *crtc)
667{
668 struct drm_device *dev = crtc->dev;
669 struct drm_nouveau_private *dev_priv = dev->dev_private;
670 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
671 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
672
673 if (nv_two_heads(dev))
674 NVSetOwner(dev, nv_crtc->index);
675
676 funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
677
678 NVBlankScreen(dev, nv_crtc->index, true);
679
680 /* Some more preperation. */
681 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
682 if (dev_priv->card_type == NV_40) {
683 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
684 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
685 }
686}
687
688static void nv_crtc_commit(struct drm_crtc *crtc)
689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_crtc_helper_funcs *funcs = crtc->helper_private;
692 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
693 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
694
695 nouveau_hw_load_state(dev, nv_crtc->index, &dev_priv->mode_reg);
696 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL);
697
698#ifdef __BIG_ENDIAN
699 /* turn on LFB swapping */
700 {
701 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
702 tmp |= MASK(NV_CIO_CRE_RCR_ENDIAN_BIG);
703 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
704 }
705#endif
706
707 funcs->dpms(crtc, DRM_MODE_DPMS_ON);
708}
709
710static void nv_crtc_destroy(struct drm_crtc *crtc)
711{
712 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
713
ef2bb506 714 NV_DEBUG_KMS(crtc->dev, "\n");
6ee73861
BS		 715
716 if (!nv_crtc)
717 return;
718
719 drm_crtc_cleanup(crtc);
720
721 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
722 kfree(nv_crtc);
723}
724
725static void
726nv_crtc_gamma_load(struct drm_crtc *crtc)
727{
728 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
729 struct drm_device *dev = nv_crtc->base.dev;
730 struct drm_nouveau_private *dev_priv = dev->dev_private;
731 struct rgb { uint8_t r, g, b; } __attribute__((packed)) *rgbs;
732 int i;
733
734 rgbs = (struct rgb *)dev_priv->mode_reg.crtc_reg[nv_crtc->index].DAC;
735 for (i = 0; i < 256; i++) {
736 rgbs[i].r = nv_crtc->lut.r[i] >> 8;
737 rgbs[i].g = nv_crtc->lut.g[i] >> 8;
738 rgbs[i].b = nv_crtc->lut.b[i] >> 8;
739 }
740
741 nouveau_hw_load_state_palette(dev, nv_crtc->index, &dev_priv->mode_reg);
742}
743
744static void
745nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, uint32_t size)
746{
747 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
748 int i;
749
750 if (size != 256)
751 return;
752
753 for (i = 0; i < 256; i++) {
754 nv_crtc->lut.r[i] = r[i];
755 nv_crtc->lut.g[i] = g[i];
756 nv_crtc->lut.b[i] = b[i];
757 }
758
759 /* We need to know the depth before we upload, but it's possible to
760 * get called before a framebuffer is bound. If this is the case,
761 * mark the lut values as dirty by setting depth==0, and it'll be
762 * uploaded on the first mode_set_base()
763 */
764 if (!nv_crtc->base.fb) {
765 nv_crtc->lut.depth = 0;
766 return;
767 }
768
769 nv_crtc_gamma_load(crtc);
770}
771
772static int
773nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
774 struct drm_framebuffer *old_fb)
775{
776 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
777 struct drm_device *dev = crtc->dev;
778 struct drm_nouveau_private *dev_priv = dev->dev_private;
779 struct nv04_crtc_reg *regp = &dev_priv->mode_reg.crtc_reg[nv_crtc->index];
780 struct drm_framebuffer *drm_fb = nv_crtc->base.fb;
781 struct nouveau_framebuffer *fb = nouveau_framebuffer(drm_fb);
782 int arb_burst, arb_lwm;
783 int ret;
784
785 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
786 if (ret)
787 return ret;
788
789 if (old_fb) {
790 struct nouveau_framebuffer *ofb = nouveau_framebuffer(old_fb);
791 nouveau_bo_unpin(ofb->nvbo);
792 }
793
794 nv_crtc->fb.offset = fb->nvbo->bo.offset;
795
796 if (nv_crtc->lut.depth != drm_fb->depth) {
797 nv_crtc->lut.depth = drm_fb->depth;
798 nv_crtc_gamma_load(crtc);
799 }
800
801 /* Update the framebuffer format. */
802 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3;
803 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (crtc->fb->depth + 1) / 8;
804 regp->ramdac_gen_ctrl &= ~NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
805 if (crtc->fb->depth == 16)
806 regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
807 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX);
808 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
809 regp->ramdac_gen_ctrl);
810
811 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
812 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
813 XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
814 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
815 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
816
817 /* Update the framebuffer location. */
818 regp->fb_start = nv_crtc->fb.offset & ~3;
819 regp->fb_start += (y * drm_fb->pitch) + (x * drm_fb->bits_per_pixel / 8);
820 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_START, regp->fb_start);
821
822 /* Update the arbitration parameters. */
823 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->bits_per_pixel,
824 &arb_burst, &arb_lwm);
825
826 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst;
827 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff;
828 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX);
829 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX);
830
831 if (dev_priv->card_type >= NV_30) {
832 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8;
833 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47);
834 }
835
836 return 0;
837}
838
839static void nv04_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
840 struct nouveau_bo *dst)
841{
842 int width = nv_cursor_width(dev);
843 uint32_t pixel;
844 int i, j;
845
846 for (i = 0; i < width; i++) {
847 for (j = 0; j < width; j++) {
848 pixel = nouveau_bo_rd32(src, i*64 + j);
849
850 nouveau_bo_wr16(dst, i*width + j, (pixel & 0x80000000) >> 16
851 | (pixel & 0xf80000) >> 9
852 | (pixel & 0xf800) >> 6
853 | (pixel & 0xf8) >> 3);
854 }
855 }
856}
857
858static void nv11_cursor_upload(struct drm_device *dev, struct nouveau_bo *src,
859 struct nouveau_bo *dst)
860{
861 uint32_t pixel;
862 int alpha, i;
863
864 /* nv11+ supports premultiplied (PM), or non-premultiplied (NPM) alpha
865 * cursors (though NPM in combination with fp dithering may not work on
866 * nv11, from "nv" driver history)
867 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
868 * blob uses, however we get given PM cursors so we use PM mode
869 */
870 for (i = 0; i < 64 * 64; i++) {
871 pixel = nouveau_bo_rd32(src, i);
872
873 /* hw gets unhappy if alpha <= rgb values. for a PM image "less
874 * than" shouldn't happen; fix "equal to" case by adding one to
875 * alpha channel (slightly inaccurate, but so is attempting to
876 * get back to NPM images, due to limits of integer precision)
877 */
878 alpha = pixel >> 24;
879 if (alpha > 0 && alpha < 255)
880 pixel = (pixel & 0x00ffffff) | ((alpha + 1) << 24);
881
882#ifdef __BIG_ENDIAN
883 {
884 struct drm_nouveau_private *dev_priv = dev->dev_private;
885
886 if (dev_priv->chipset == 0x11) {
887 pixel = ((pixel & 0x000000ff) << 24) |
888 ((pixel & 0x0000ff00) << 8) |
889 ((pixel & 0x00ff0000) >> 8) |
890 ((pixel & 0xff000000) >> 24);
891 }
892 }
893#endif
894
895 nouveau_bo_wr32(dst, i, pixel);
896 }
897}
898
899static int
900nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
901 uint32_t buffer_handle, uint32_t width, uint32_t height)
902{
903 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
904 struct drm_device *dev = dev_priv->dev;
905 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
906 struct nouveau_bo *cursor = NULL;
907 struct drm_gem_object *gem;
908 int ret = 0;
909
910 if (width != 64 || height != 64)
911 return -EINVAL;
912
913 if (!buffer_handle) {
914 nv_crtc->cursor.hide(nv_crtc, true);
915 return 0;
916 }
917
918 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
919 if (!gem)
bf79cb91 920 return -ENOENT;
6ee73861
BS		 921 cursor = nouveau_gem_object(gem);
922
923 ret = nouveau_bo_map(cursor);
924 if (ret)
925 goto out;
926
927 if (dev_priv->chipset >= 0x11)
928 nv11_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
929 else
930 nv04_cursor_upload(dev, cursor, nv_crtc->cursor.nvbo);
931
932 nouveau_bo_unmap(cursor);
933 nv_crtc->cursor.offset = nv_crtc->cursor.nvbo->bo.offset;
934 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.offset);
935 nv_crtc->cursor.show(nv_crtc, true);
936out:
bc9025bd 937 drm_gem_object_unreference_unlocked(gem);
6ee73861
BS		 938 return ret;
939}
940
941static int
942nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
943{
944 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
945
946 nv_crtc->cursor.set_pos(nv_crtc, x, y);
947 return 0;
948}
949
950static const struct drm_crtc_funcs nv04_crtc_funcs = {
951 .save = nv_crtc_save,
952 .restore = nv_crtc_restore,
953 .cursor_set = nv04_crtc_cursor_set,
954 .cursor_move = nv04_crtc_cursor_move,
955 .gamma_set = nv_crtc_gamma_set,
956 .set_config = drm_crtc_helper_set_config,
957 .destroy = nv_crtc_destroy,
958};
959
960static const struct drm_crtc_helper_funcs nv04_crtc_helper_funcs = {
961 .dpms = nv_crtc_dpms,
962 .prepare = nv_crtc_prepare,
963 .commit = nv_crtc_commit,
964 .mode_fixup = nv_crtc_mode_fixup,
965 .mode_set = nv_crtc_mode_set,
966 .mode_set_base = nv04_crtc_mode_set_base,
967 .load_lut = nv_crtc_gamma_load,
968};
969
970int
971nv04_crtc_create(struct drm_device *dev, int crtc_num)
972{
973 struct nouveau_crtc *nv_crtc;
974 int ret, i;
975
976 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
977 if (!nv_crtc)
978 return -ENOMEM;
979
980 for (i = 0; i < 256; i++) {
981 nv_crtc->lut.r[i] = i << 8;
982 nv_crtc->lut.g[i] = i << 8;
983 nv_crtc->lut.b[i] = i << 8;
984 }
985 nv_crtc->lut.depth = 0;
986
987 nv_crtc->index = crtc_num;
988 nv_crtc->last_dpms = NV_DPMS_CLEARED;
989
990 drm_crtc_init(dev, &nv_crtc->base, &nv04_crtc_funcs);
991 drm_crtc_helper_add(&nv_crtc->base, &nv04_crtc_helper_funcs);
992 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
993
994 ret = nouveau_bo_new(dev, NULL, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
995 0, 0x0000, false, true, &nv_crtc->cursor.nvbo);
996 if (!ret) {
997 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
998 if (!ret)
999 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
1000 if (ret)
1001 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1002 }
1003
1004 nv04_cursor_init(nv_crtc);
1005
1006 return 0;
1007}
1008
Linux kernel - Deliverables
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