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1262a206 BS |
1 | /* |
2 | * Copyright 2011 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
760285e7 | 25 | #include <drm/drmP.h> |
1262a206 BS |
26 | #include "nouveau_drv.h" |
27 | #include "nouveau_bios.h" | |
28 | #include "nouveau_pm.h" | |
29 | #include "nouveau_hw.h" | |
c420b2dc | 30 | #include "nouveau_fifo.h" |
1262a206 BS |
31 | |
32 | #define min2(a,b) ((a) < (b) ? (a) : (b)) | |
33 | ||
34 | static u32 | |
35 | read_pll_1(struct drm_device *dev, u32 reg) | |
36 | { | |
37 | u32 ctrl = nv_rd32(dev, reg + 0x00); | |
38 | int P = (ctrl & 0x00070000) >> 16; | |
39 | int N = (ctrl & 0x0000ff00) >> 8; | |
40 | int M = (ctrl & 0x000000ff) >> 0; | |
41 | u32 ref = 27000, clk = 0; | |
42 | ||
43 | if (ctrl & 0x80000000) | |
44 | clk = ref * N / M; | |
45 | ||
46 | return clk >> P; | |
47 | } | |
48 | ||
49 | static u32 | |
50 | read_pll_2(struct drm_device *dev, u32 reg) | |
51 | { | |
52 | u32 ctrl = nv_rd32(dev, reg + 0x00); | |
53 | u32 coef = nv_rd32(dev, reg + 0x04); | |
54 | int N2 = (coef & 0xff000000) >> 24; | |
55 | int M2 = (coef & 0x00ff0000) >> 16; | |
56 | int N1 = (coef & 0x0000ff00) >> 8; | |
57 | int M1 = (coef & 0x000000ff) >> 0; | |
58 | int P = (ctrl & 0x00070000) >> 16; | |
59 | u32 ref = 27000, clk = 0; | |
60 | ||
2bfa7482 | 61 | if ((ctrl & 0x80000000) && M1) { |
1262a206 | 62 | clk = ref * N1 / M1; |
2bfa7482 BS |
63 | if ((ctrl & 0x40000100) == 0x40000000) { |
64 | if (M2) | |
65 | clk = clk * N2 / M2; | |
66 | else | |
67 | clk = 0; | |
68 | } | |
1262a206 BS |
69 | } |
70 | ||
71 | return clk >> P; | |
72 | } | |
73 | ||
74 | static u32 | |
75 | read_clk(struct drm_device *dev, u32 src) | |
76 | { | |
77 | switch (src) { | |
78 | case 3: | |
79 | return read_pll_2(dev, 0x004000); | |
80 | case 2: | |
81 | return read_pll_1(dev, 0x004008); | |
82 | default: | |
83 | break; | |
84 | } | |
85 | ||
86 | return 0; | |
87 | } | |
88 | ||
89 | int | |
90 | nv40_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) | |
91 | { | |
92 | u32 ctrl = nv_rd32(dev, 0x00c040); | |
93 | ||
94 | perflvl->core = read_clk(dev, (ctrl & 0x00000003) >> 0); | |
95 | perflvl->shader = read_clk(dev, (ctrl & 0x00000030) >> 4); | |
96 | perflvl->memory = read_pll_2(dev, 0x4020); | |
97 | return 0; | |
98 | } | |
99 | ||
100 | struct nv40_pm_state { | |
101 | u32 ctrl; | |
102 | u32 npll_ctrl; | |
103 | u32 npll_coef; | |
104 | u32 spll; | |
105 | u32 mpll_ctrl; | |
106 | u32 mpll_coef; | |
107 | }; | |
108 | ||
109 | static int | |
110 | nv40_calc_pll(struct drm_device *dev, u32 reg, struct pll_lims *pll, | |
111 | u32 clk, int *N1, int *M1, int *N2, int *M2, int *log2P) | |
112 | { | |
113 | struct nouveau_pll_vals coef; | |
114 | int ret; | |
115 | ||
116 | ret = get_pll_limits(dev, reg, pll); | |
117 | if (ret) | |
118 | return ret; | |
119 | ||
120 | if (clk < pll->vco1.maxfreq) | |
121 | pll->vco2.maxfreq = 0; | |
122 | ||
123 | ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); | |
124 | if (ret == 0) | |
125 | return -ERANGE; | |
126 | ||
127 | *N1 = coef.N1; | |
128 | *M1 = coef.M1; | |
129 | if (N2 && M2) { | |
130 | if (pll->vco2.maxfreq) { | |
131 | *N2 = coef.N2; | |
132 | *M2 = coef.M2; | |
133 | } else { | |
134 | *N2 = 1; | |
135 | *M2 = 1; | |
136 | } | |
137 | } | |
138 | *log2P = coef.log2P; | |
139 | return 0; | |
140 | } | |
141 | ||
142 | void * | |
143 | nv40_pm_clocks_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl) | |
144 | { | |
145 | struct nv40_pm_state *info; | |
146 | struct pll_lims pll; | |
147 | int N1, N2, M1, M2, log2P; | |
148 | int ret; | |
149 | ||
150 | info = kmalloc(sizeof(*info), GFP_KERNEL); | |
151 | if (!info) | |
152 | return ERR_PTR(-ENOMEM); | |
153 | ||
154 | /* core/geometric clock */ | |
155 | ret = nv40_calc_pll(dev, 0x004000, &pll, perflvl->core, | |
156 | &N1, &M1, &N2, &M2, &log2P); | |
157 | if (ret < 0) | |
158 | goto out; | |
159 | ||
160 | if (N2 == M2) { | |
161 | info->npll_ctrl = 0x80000100 | (log2P << 16); | |
162 | info->npll_coef = (N1 << 8) | M1; | |
163 | } else { | |
164 | info->npll_ctrl = 0xc0000000 | (log2P << 16); | |
165 | info->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; | |
166 | } | |
167 | ||
168 | /* use the second PLL for shader/rop clock, if it differs from core */ | |
169 | if (perflvl->shader && perflvl->shader != perflvl->core) { | |
170 | ret = nv40_calc_pll(dev, 0x004008, &pll, perflvl->shader, | |
171 | &N1, &M1, NULL, NULL, &log2P); | |
172 | if (ret < 0) | |
173 | goto out; | |
174 | ||
175 | info->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; | |
176 | info->ctrl = 0x00000223; | |
177 | } else { | |
178 | info->spll = 0x00000000; | |
179 | info->ctrl = 0x00000333; | |
180 | } | |
181 | ||
182 | /* memory clock */ | |
2bfa7482 BS |
183 | if (!perflvl->memory) { |
184 | info->mpll_ctrl = 0x00000000; | |
185 | goto out; | |
186 | } | |
187 | ||
1262a206 BS |
188 | ret = nv40_calc_pll(dev, 0x004020, &pll, perflvl->memory, |
189 | &N1, &M1, &N2, &M2, &log2P); | |
190 | if (ret < 0) | |
191 | goto out; | |
192 | ||
193 | info->mpll_ctrl = 0x80000000 | (log2P << 16); | |
194 | info->mpll_ctrl |= min2(pll.log2p_bias + log2P, pll.max_log2p) << 20; | |
195 | if (N2 == M2) { | |
196 | info->mpll_ctrl |= 0x00000100; | |
197 | info->mpll_coef = (N1 << 8) | M1; | |
198 | } else { | |
199 | info->mpll_ctrl |= 0x40000000; | |
200 | info->mpll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; | |
201 | } | |
202 | ||
203 | out: | |
204 | if (ret < 0) { | |
205 | kfree(info); | |
206 | info = ERR_PTR(ret); | |
207 | } | |
208 | return info; | |
209 | } | |
210 | ||
211 | static bool | |
212 | nv40_pm_gr_idle(void *data) | |
213 | { | |
214 | struct drm_device *dev = data; | |
215 | ||
216 | if ((nv_rd32(dev, 0x400760) & 0x000000f0) >> 4 != | |
217 | (nv_rd32(dev, 0x400760) & 0x0000000f)) | |
218 | return false; | |
219 | ||
220 | if (nv_rd32(dev, 0x400700)) | |
221 | return false; | |
222 | ||
223 | return true; | |
224 | } | |
225 | ||
dd1da8de | 226 | int |
1262a206 BS |
227 | nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) |
228 | { | |
229 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
230 | struct nv40_pm_state *info = pre_state; | |
231 | unsigned long flags; | |
59ef9742 | 232 | struct bit_entry M; |
1262a206 BS |
233 | u32 crtc_mask = 0; |
234 | u8 sr1[2]; | |
dd1da8de | 235 | int i, ret = -EAGAIN; |
1262a206 BS |
236 | |
237 | /* determine which CRTCs are active, fetch VGA_SR1 for each */ | |
238 | for (i = 0; i < 2; i++) { | |
239 | u32 vbl = nv_rd32(dev, 0x600808 + (i * 0x2000)); | |
240 | u32 cnt = 0; | |
241 | do { | |
242 | if (vbl != nv_rd32(dev, 0x600808 + (i * 0x2000))) { | |
243 | nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01); | |
244 | sr1[i] = nv_rd08(dev, 0x0c03c5 + (i * 0x2000)); | |
245 | if (!(sr1[i] & 0x20)) | |
246 | crtc_mask |= (1 << i); | |
247 | break; | |
248 | } | |
249 | udelay(1); | |
250 | } while (cnt++ < 32); | |
251 | } | |
252 | ||
253 | /* halt and idle engines */ | |
254 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); | |
255 | nv_mask(dev, 0x002500, 0x00000001, 0x00000000); | |
256 | if (!nv_wait(dev, 0x002500, 0x00000010, 0x00000000)) | |
257 | goto resume; | |
258 | nv_mask(dev, 0x003220, 0x00000001, 0x00000000); | |
259 | if (!nv_wait(dev, 0x003220, 0x00000010, 0x00000000)) | |
260 | goto resume; | |
261 | nv_mask(dev, 0x003200, 0x00000001, 0x00000000); | |
262 | nv04_fifo_cache_pull(dev, false); | |
263 | ||
264 | if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev)) | |
265 | goto resume; | |
266 | ||
dd1da8de MP |
267 | ret = 0; |
268 | ||
1262a206 BS |
269 | /* set engine clocks */ |
270 | nv_mask(dev, 0x00c040, 0x00000333, 0x00000000); | |
271 | nv_wr32(dev, 0x004004, info->npll_coef); | |
272 | nv_mask(dev, 0x004000, 0xc0070100, info->npll_ctrl); | |
273 | nv_mask(dev, 0x004008, 0xc007ffff, info->spll); | |
274 | mdelay(5); | |
275 | nv_mask(dev, 0x00c040, 0x00000333, info->ctrl); | |
276 | ||
2bfa7482 BS |
277 | if (!info->mpll_ctrl) |
278 | goto resume; | |
279 | ||
1262a206 BS |
280 | /* wait for vblank start on active crtcs, disable memory access */ |
281 | for (i = 0; i < 2; i++) { | |
282 | if (!(crtc_mask & (1 << i))) | |
283 | continue; | |
284 | nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000); | |
285 | nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); | |
286 | nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01); | |
287 | nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20); | |
288 | } | |
289 | ||
290 | /* prepare ram for reclocking */ | |
291 | nv_wr32(dev, 0x1002d4, 0x00000001); /* precharge */ | |
292 | nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */ | |
293 | nv_wr32(dev, 0x1002d0, 0x00000001); /* refresh */ | |
294 | nv_mask(dev, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */ | |
295 | nv_wr32(dev, 0x1002dc, 0x00000001); /* enable self-refresh */ | |
296 | ||
297 | /* change the PLL of each memory partition */ | |
298 | nv_mask(dev, 0x00c040, 0x0000c000, 0x00000000); | |
299 | switch (dev_priv->chipset) { | |
300 | case 0x40: | |
301 | case 0x45: | |
302 | case 0x41: | |
303 | case 0x42: | |
304 | case 0x47: | |
305 | nv_mask(dev, 0x004044, 0xc0771100, info->mpll_ctrl); | |
306 | nv_mask(dev, 0x00402c, 0xc0771100, info->mpll_ctrl); | |
307 | nv_wr32(dev, 0x004048, info->mpll_coef); | |
308 | nv_wr32(dev, 0x004030, info->mpll_coef); | |
309 | case 0x43: | |
310 | case 0x49: | |
311 | case 0x4b: | |
312 | nv_mask(dev, 0x004038, 0xc0771100, info->mpll_ctrl); | |
313 | nv_wr32(dev, 0x00403c, info->mpll_coef); | |
314 | default: | |
315 | nv_mask(dev, 0x004020, 0xc0771100, info->mpll_ctrl); | |
316 | nv_wr32(dev, 0x004024, info->mpll_coef); | |
317 | break; | |
318 | } | |
319 | udelay(100); | |
320 | nv_mask(dev, 0x00c040, 0x0000c000, 0x0000c000); | |
321 | ||
322 | /* re-enable normal operation of memory controller */ | |
323 | nv_wr32(dev, 0x1002dc, 0x00000000); | |
324 | nv_mask(dev, 0x100210, 0x80000000, 0x80000000); | |
325 | udelay(100); | |
326 | ||
59ef9742 BS |
327 | /* execute memory reset script from vbios */ |
328 | if (!bit_table(dev, 'M', &M)) | |
329 | nouveau_bios_init_exec(dev, ROM16(M.data[0])); | |
330 | ||
1262a206 BS |
331 | /* make sure we're in vblank (hopefully the same one as before), and |
332 | * then re-enable crtc memory access | |
333 | */ | |
334 | for (i = 0; i < 2; i++) { | |
335 | if (!(crtc_mask & (1 << i))) | |
336 | continue; | |
337 | nv_wait(dev, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000); | |
338 | nv_wr08(dev, 0x0c03c4 + (i * 0x2000), 0x01); | |
339 | nv_wr08(dev, 0x0c03c5 + (i * 0x2000), sr1[i]); | |
340 | } | |
341 | ||
342 | /* resume engines */ | |
343 | resume: | |
344 | nv_wr32(dev, 0x003250, 0x00000001); | |
345 | nv_mask(dev, 0x003220, 0x00000001, 0x00000001); | |
346 | nv_wr32(dev, 0x003200, 0x00000001); | |
347 | nv_wr32(dev, 0x002500, 0x00000001); | |
348 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); | |
349 | ||
350 | kfree(info); | |
dd1da8de | 351 | return ret; |
1262a206 | 352 | } |
9232969e BS |
353 | |
354 | int | |
675aac03 | 355 | nv40_pm_pwm_get(struct drm_device *dev, int line, u32 *divs, u32 *duty) |
9232969e | 356 | { |
675aac03 | 357 | if (line == 2) { |
69346180 BS |
358 | u32 reg = nv_rd32(dev, 0x0010f0); |
359 | if (reg & 0x80000000) { | |
360 | *duty = (reg & 0x7fff0000) >> 16; | |
361 | *divs = (reg & 0x00007fff); | |
362 | return 0; | |
363 | } | |
364 | } else | |
675aac03 | 365 | if (line == 9) { |
69346180 BS |
366 | u32 reg = nv_rd32(dev, 0x0015f4); |
367 | if (reg & 0x80000000) { | |
368 | *divs = nv_rd32(dev, 0x0015f8); | |
369 | *duty = (reg & 0x7fffffff); | |
370 | return 0; | |
371 | } | |
372 | } else { | |
675aac03 | 373 | NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", line); |
69346180 | 374 | return -ENODEV; |
9232969e BS |
375 | } |
376 | ||
69346180 | 377 | return -EINVAL; |
9232969e BS |
378 | } |
379 | ||
380 | int | |
675aac03 | 381 | nv40_pm_pwm_set(struct drm_device *dev, int line, u32 divs, u32 duty) |
9232969e | 382 | { |
675aac03 | 383 | if (line == 2) { |
69346180 BS |
384 | nv_wr32(dev, 0x0010f0, 0x80000000 | (duty << 16) | divs); |
385 | } else | |
675aac03 | 386 | if (line == 9) { |
69346180 BS |
387 | nv_wr32(dev, 0x0015f8, divs); |
388 | nv_wr32(dev, 0x0015f4, duty | 0x80000000); | |
389 | } else { | |
675aac03 | 390 | NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", line); |
69346180 | 391 | return -ENODEV; |
04de6a04 BS |
392 | } |
393 | ||
04de6a04 BS |
394 | return 0; |
395 | } |