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drm: Move drm_crtc_init from drm_crtc.h to drm_plane_helper.h
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_display.c
CommitLineData
56d237d2 1/*
26f6d88b
BS		 2 * Copyright 2011 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
51beb428 25#include <linux/dma-mapping.h>
83fc083c 26
760285e7
DH		 27#include <drm/drmP.h>
28#include <drm/drm_crtc_helper.h>
3cb9ae4f 29#include <drm/drm_plane_helper.h>
4874322e 30#include <drm/drm_dp_helper.h>
26f6d88b 31
fdb751ef
BS		 32#include <nvif/class.h>
33
77145f1c
BS		 34#include "nouveau_drm.h"
35#include "nouveau_dma.h"
36#include "nouveau_gem.h"
26f6d88b
BS		 37#include "nouveau_connector.h"
38#include "nouveau_encoder.h"
39#include "nouveau_crtc.h"
f589be88 40#include "nouveau_fence.h"
3a89cd02 41#include "nv50_display.h"
26f6d88b 42
8a46438a
BS		 43#define EVO_DMA_NR 9
44
bdb8c212 45#define EVO_MASTER (0x00)
a63a97eb 46#define EVO_FLIP(c) (0x01 + (c))
8a46438a
BS		 47#define EVO_OVLY(c) (0x05 + (c))
48#define EVO_OIMM(c) (0x09 + (c))
bdb8c212
BS		 49#define EVO_CURS(c) (0x0d + (c))
50
816af2f2
BS		 51/* offsets in shared sync bo of various structures */
52#define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
9f9bdaaf
BS		 53#define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
54#define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
55#define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
816af2f2 56
b5a794b0
BS		 57/******************************************************************************
58 * EVO channel
59 *****************************************************************************/
60
e225f446 61struct nv50_chan {
0ad72863 62 struct nvif_object user;
b5a794b0
BS		 63};
64
65static int
410f3ec6 66nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
e225f446 67 void *data, u32 size, struct nv50_chan *chan)
b5a794b0 68{
410f3ec6
BS		 69 while (oclass[0]) {
70 int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,
71 oclass[0], data, size,
72 &chan->user);
b76f1529
BS		 73 if (oclass++, ret == 0) {
74 nvif_object_map(&chan->user);
410f3ec6 75 return ret;
b76f1529 76 }
410f3ec6
BS		 77 }
78 return -ENOSYS;
b5a794b0
BS		 79}
80
81static void
0ad72863 82nv50_chan_destroy(struct nv50_chan *chan)
b5a794b0 83{
0ad72863 84 nvif_object_fini(&chan->user);
b5a794b0
BS		 85}
86
87/******************************************************************************
88 * PIO EVO channel
89 *****************************************************************************/
90
e225f446
BS		 91struct nv50_pioc {
92 struct nv50_chan base;
b5a794b0
BS		 93};
94
95static void
0ad72863 96nv50_pioc_destroy(struct nv50_pioc *pioc)
b5a794b0 97{
0ad72863 98 nv50_chan_destroy(&pioc->base);
b5a794b0
BS		 99}
100
101static int
410f3ec6 102nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
e225f446 103 void *data, u32 size, struct nv50_pioc *pioc)
b5a794b0 104{
410f3ec6
BS		 105 return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
106}
107
108/******************************************************************************
109 * Cursor Immediate
110 *****************************************************************************/
111
112struct nv50_curs {
113 struct nv50_pioc base;
114};
115
116static int
117nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
118{
648d4dfd 119 struct nv50_disp_cursor_v0 args = {
410f3ec6
BS		 120 .head = head,
121 };
122 static const u32 oclass[] = {
648d4dfd
BS		 123 GK104_DISP_CURSOR,
124 GF110_DISP_CURSOR,
125 GT214_DISP_CURSOR,
126 G82_DISP_CURSOR,
127 NV50_DISP_CURSOR,
410f3ec6
BS		 128 0
129 };
130
131 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
132 &curs->base);
133}
134
135/******************************************************************************
136 * Overlay Immediate
137 *****************************************************************************/
138
139struct nv50_oimm {
140 struct nv50_pioc base;
141};
142
143static int
144nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
145{
648d4dfd 146 struct nv50_disp_cursor_v0 args = {
410f3ec6
BS		 147 .head = head,
148 };
149 static const u32 oclass[] = {
648d4dfd
BS		 150 GK104_DISP_OVERLAY,
151 GF110_DISP_OVERLAY,
152 GT214_DISP_OVERLAY,
153 G82_DISP_OVERLAY,
154 NV50_DISP_OVERLAY,
410f3ec6
BS		 155 0
156 };
157
158 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
159 &oimm->base);
b5a794b0
BS		 160}
161
162/******************************************************************************
163 * DMA EVO channel
164 *****************************************************************************/
165
e225f446
BS		 166struct nv50_dmac {
167 struct nv50_chan base;
3376ee37
BS		 168 dma_addr_t handle;
169 u32 *ptr;
59ad1465 170
0ad72863
BS		 171 struct nvif_object sync;
172 struct nvif_object vram;
173
59ad1465
DV		 174 /* Protects against concurrent pushbuf access to this channel, lock is
175 * grabbed by evo_wait (if the pushbuf reservation is successful) and
176 * dropped again by evo_kick. */
177 struct mutex lock;
b5a794b0
BS		 178};
179
180static void
0ad72863 181nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
b5a794b0 182{
0ad72863
BS		 183 nvif_object_fini(&dmac->vram);
184 nvif_object_fini(&dmac->sync);
185
186 nv50_chan_destroy(&dmac->base);
187
b5a794b0 188 if (dmac->ptr) {
0ad72863 189 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
b5a794b0
BS		 190 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
191 }
b5a794b0
BS		 192}
193
47057302 194static int
410f3ec6 195nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
47057302 196 void *data, u32 size, u64 syncbuf,
e225f446 197 struct nv50_dmac *dmac)
47057302 198{
f392ec4b 199 struct nvif_device *device = nvif_device(disp);
648d4dfd 200 struct nv50_disp_core_channel_dma_v0 *args = data;
0ad72863 201 struct nvif_object pushbuf;
47057302
BS		 202 int ret;
203
59ad1465
DV		 204 mutex_init(&dmac->lock);
205
f392ec4b 206 dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
0ad72863 207 PAGE_SIZE, &dmac->handle);
47057302
BS		 208 if (!dmac->ptr)
209 return -ENOMEM;
210
f392ec4b 211 ret = nvif_object_init(nvif_object(device), NULL,
648d4dfd 212 args->pushbuf, NV_DMA_FROM_MEMORY,
4acfd707
BS		 213 &(struct nv_dma_v0) {
214 .target = NV_DMA_V0_TARGET_PCI_US,
215 .access = NV_DMA_V0_ACCESS_RD,
47057302
BS		 216 .start = dmac->handle + 0x0000,
217 .limit = dmac->handle + 0x0fff,
4acfd707 218 }, sizeof(struct nv_dma_v0), &pushbuf);
b5a794b0 219 if (ret)
47057302 220 return ret;
b5a794b0 221
410f3ec6 222 ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
0ad72863 223 nvif_object_fini(&pushbuf);
47057302
BS		 224 if (ret)
225 return ret;
226
f45f55c4 227 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
4acfd707
BS		 228 NV_DMA_IN_MEMORY,
229 &(struct nv_dma_v0) {
230 .target = NV_DMA_V0_TARGET_VRAM,
231 .access = NV_DMA_V0_ACCESS_RDWR,
47057302
BS		 232 .start = syncbuf + 0x0000,
233 .limit = syncbuf + 0x0fff,
4acfd707 234 }, sizeof(struct nv_dma_v0),
0ad72863 235 &dmac->sync);
47057302
BS		 236 if (ret)
237 return ret;
238
f45f55c4 239 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
4acfd707
BS		 240 NV_DMA_IN_MEMORY,
241 &(struct nv_dma_v0) {
242 .target = NV_DMA_V0_TARGET_VRAM,
243 .access = NV_DMA_V0_ACCESS_RDWR,
b5a794b0 244 .start = 0,
f392ec4b 245 .limit = device->info.ram_user - 1,
4acfd707 246 }, sizeof(struct nv_dma_v0),
0ad72863 247 &dmac->vram);
b5a794b0 248 if (ret)
47057302
BS		 249 return ret;
250
b5a794b0
BS		 251 return ret;
252}
253
410f3ec6
BS		 254/******************************************************************************
255 * Core
256 *****************************************************************************/
257
e225f446
BS		 258struct nv50_mast {
259 struct nv50_dmac base;
b5a794b0
BS		 260};
261
410f3ec6
BS		 262static int
263nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
264{
648d4dfd
BS		 265 struct nv50_disp_core_channel_dma_v0 args = {
266 .pushbuf = 0xb0007d00,
410f3ec6
BS		 267 };
268 static const u32 oclass[] = {
648d4dfd
BS		 269 GM107_DISP_CORE_CHANNEL_DMA,
270 GK110_DISP_CORE_CHANNEL_DMA,
271 GK104_DISP_CORE_CHANNEL_DMA,
272 GF110_DISP_CORE_CHANNEL_DMA,
273 GT214_DISP_CORE_CHANNEL_DMA,
274 GT206_DISP_CORE_CHANNEL_DMA,
275 GT200_DISP_CORE_CHANNEL_DMA,
276 G82_DISP_CORE_CHANNEL_DMA,
277 NV50_DISP_CORE_CHANNEL_DMA,
410f3ec6
BS		 278 0
279 };
280
281 return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
282 &core->base);
283}
284
285/******************************************************************************
286 * Base
287 *****************************************************************************/
b5a794b0 288
e225f446
BS		 289struct nv50_sync {
290 struct nv50_dmac base;
9f9bdaaf
BS		 291 u32 addr;
292 u32 data;
3376ee37
BS		 293};
294
410f3ec6
BS		 295static int
296nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
297 struct nv50_sync *base)
298{
648d4dfd
BS		 299 struct nv50_disp_base_channel_dma_v0 args = {
300 .pushbuf = 0xb0007c00 | head,
410f3ec6
BS		 301 .head = head,
302 };
303 static const u32 oclass[] = {
648d4dfd
BS		 304 GK110_DISP_BASE_CHANNEL_DMA,
305 GK104_DISP_BASE_CHANNEL_DMA,
306 GF110_DISP_BASE_CHANNEL_DMA,
307 GT214_DISP_BASE_CHANNEL_DMA,
308 GT200_DISP_BASE_CHANNEL_DMA,
309 G82_DISP_BASE_CHANNEL_DMA,
310 NV50_DISP_BASE_CHANNEL_DMA,
410f3ec6
BS		 311 0
312 };
313
314 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
315 syncbuf, &base->base);
316}
317
318/******************************************************************************
319 * Overlay
320 *****************************************************************************/
321
e225f446
BS		 322struct nv50_ovly {
323 struct nv50_dmac base;
b5a794b0 324};
f20ce962 325
410f3ec6
BS		 326static int
327nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
328 struct nv50_ovly *ovly)
329{
648d4dfd
BS		 330 struct nv50_disp_overlay_channel_dma_v0 args = {
331 .pushbuf = 0xb0007e00 | head,
410f3ec6
BS		 332 .head = head,
333 };
334 static const u32 oclass[] = {
648d4dfd
BS		 335 GK104_DISP_OVERLAY_CONTROL_DMA,
336 GF110_DISP_OVERLAY_CONTROL_DMA,
337 GT214_DISP_OVERLAY_CHANNEL_DMA,
338 GT200_DISP_OVERLAY_CHANNEL_DMA,
339 G82_DISP_OVERLAY_CHANNEL_DMA,
340 NV50_DISP_OVERLAY_CHANNEL_DMA,
410f3ec6
BS		 341 0
342 };
343
344 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
345 syncbuf, &ovly->base);
346}
26f6d88b 347
e225f446 348struct nv50_head {
dd0e3d53 349 struct nouveau_crtc base;
8dda53fc 350 struct nouveau_bo *image;
e225f446
BS		 351 struct nv50_curs curs;
352 struct nv50_sync sync;
353 struct nv50_ovly ovly;
354 struct nv50_oimm oimm;
b5a794b0
BS		 355};
356
e225f446
BS		 357#define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
358#define nv50_curs(c) (&nv50_head(c)->curs)
359#define nv50_sync(c) (&nv50_head(c)->sync)
360#define nv50_ovly(c) (&nv50_head(c)->ovly)
361#define nv50_oimm(c) (&nv50_head(c)->oimm)
362#define nv50_chan(c) (&(c)->base.base)
0ad72863
BS		 363#define nv50_vers(c) nv50_chan(c)->user.oclass
364
365struct nv50_fbdma {
366 struct list_head head;
367 struct nvif_object core;
368 struct nvif_object base[4];
369};
b5a794b0 370
e225f446 371struct nv50_disp {
0ad72863 372 struct nvif_object *disp;
e225f446 373 struct nv50_mast mast;
b5a794b0 374
8a423647 375 struct list_head fbdma;
b5a794b0
BS		 376
377 struct nouveau_bo *sync;
dd0e3d53
BS		 378};
379
e225f446
BS		 380static struct nv50_disp *
381nv50_disp(struct drm_device *dev)
26f6d88b 382{
77145f1c 383 return nouveau_display(dev)->priv;
26f6d88b
BS		 384}
385
e225f446 386#define nv50_mast(d) (&nv50_disp(d)->mast)
b5a794b0 387
bdb8c212 388static struct drm_crtc *
e225f446 389nv50_display_crtc_get(struct drm_encoder *encoder)
bdb8c212
BS		 390{
391 return nouveau_encoder(encoder)->crtc;
392}
393
394/******************************************************************************
395 * EVO channel helpers
396 *****************************************************************************/
51beb428 397static u32 *
b5a794b0 398evo_wait(void *evoc, int nr)
51beb428 399{
e225f446 400 struct nv50_dmac *dmac = evoc;
0ad72863 401 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
51beb428 402
59ad1465 403 mutex_lock(&dmac->lock);
de8268c5 404 if (put + nr >= (PAGE_SIZE / 4) - 8) {
b5a794b0 405 dmac->ptr[put] = 0x20000000;
51beb428 406
0ad72863
BS		 407 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
408 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
59ad1465 409 mutex_unlock(&dmac->lock);
0ad72863 410 nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
51beb428
BS		 411 return NULL;
412 }
413
414 put = 0;
415 }
416
b5a794b0 417 return dmac->ptr + put;
51beb428
BS		 418}
419
420static void
b5a794b0 421evo_kick(u32 *push, void *evoc)
51beb428 422{
e225f446 423 struct nv50_dmac *dmac = evoc;
0ad72863 424 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
59ad1465 425 mutex_unlock(&dmac->lock);
51beb428
BS		 426}
427
428#define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
429#define evo_data(p,d) *((p)++) = (d)
430
3376ee37
BS		 431static bool
432evo_sync_wait(void *data)
433{
5cc027f6
BS		 434 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
435 return true;
436 usleep_range(1, 2);
437 return false;
3376ee37
BS		 438}
439
440static int
b5a794b0 441evo_sync(struct drm_device *dev)
3376ee37 442{
967e7bde 443 struct nvif_device *device = &nouveau_drm(dev)->device;
e225f446
BS		 444 struct nv50_disp *disp = nv50_disp(dev);
445 struct nv50_mast *mast = nv50_mast(dev);
b5a794b0 446 u32 *push = evo_wait(mast, 8);
3376ee37 447 if (push) {
816af2f2 448 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
3376ee37 449 evo_mthd(push, 0x0084, 1);
816af2f2 450 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
3376ee37
BS		 451 evo_mthd(push, 0x0080, 2);
452 evo_data(push, 0x00000000);
453 evo_data(push, 0x00000000);
b5a794b0 454 evo_kick(push, mast);
967e7bde 455 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
3376ee37
BS		 456 return 0;
457 }
458
459 return -EBUSY;
460}
461
462/******************************************************************************
a63a97eb 463 * Page flipping channel
3376ee37
BS		 464 *****************************************************************************/
465struct nouveau_bo *
e225f446 466nv50_display_crtc_sema(struct drm_device *dev, int crtc)
3376ee37 467{
e225f446 468 return nv50_disp(dev)->sync;
3376ee37
BS		 469}
470
9f9bdaaf
BS		 471struct nv50_display_flip {
472 struct nv50_disp *disp;
473 struct nv50_sync *chan;
474};
475
476static bool
477nv50_display_flip_wait(void *data)
478{
479 struct nv50_display_flip *flip = data;
480 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
b1ea3e6e 481 flip->chan->data)
9f9bdaaf
BS		 482 return true;
483 usleep_range(1, 2);
484 return false;
485}
486
3376ee37 487void
e225f446 488nv50_display_flip_stop(struct drm_crtc *crtc)
3376ee37 489{
967e7bde 490 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
9f9bdaaf
BS		 491 struct nv50_display_flip flip = {
492 .disp = nv50_disp(crtc->dev),
493 .chan = nv50_sync(crtc),
494 };
3376ee37
BS		 495 u32 *push;
496
9f9bdaaf 497 push = evo_wait(flip.chan, 8);
3376ee37
BS		 498 if (push) {
499 evo_mthd(push, 0x0084, 1);
500 evo_data(push, 0x00000000);
501 evo_mthd(push, 0x0094, 1);
502 evo_data(push, 0x00000000);
503 evo_mthd(push, 0x00c0, 1);
504 evo_data(push, 0x00000000);
505 evo_mthd(push, 0x0080, 1);
506 evo_data(push, 0x00000000);
9f9bdaaf 507 evo_kick(push, flip.chan);
3376ee37 508 }
9f9bdaaf 509
967e7bde 510 nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
3376ee37
BS		 511}
512
513int
e225f446 514nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3376ee37
BS		 515 struct nouveau_channel *chan, u32 swap_interval)
516{
517 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
3376ee37 518 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
8dda53fc 519 struct nv50_head *head = nv50_head(crtc);
e225f446 520 struct nv50_sync *sync = nv50_sync(crtc);
3376ee37 521 u32 *push;
8dda53fc 522 int ret;
3376ee37
BS		 523
524 swap_interval <<= 4;
525 if (swap_interval == 0)
526 swap_interval |= 0x100;
f60b6e7a
BS		 527 if (chan == NULL)
528 evo_sync(crtc->dev);
3376ee37 529
b5a794b0 530 push = evo_wait(sync, 128);
3376ee37
BS		 531 if (unlikely(push == NULL))
532 return -EBUSY;
533
bbf8906b 534 if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
9f9bdaaf
BS		 535 ret = RING_SPACE(chan, 8);
536 if (ret)
537 return ret;
538
539 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
8dda53fc 540 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
9f9bdaaf
BS		 541 OUT_RING (chan, sync->addr ^ 0x10);
542 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
543 OUT_RING (chan, sync->data + 1);
544 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
545 OUT_RING (chan, sync->addr);
546 OUT_RING (chan, sync->data);
547 } else
bbf8906b 548 if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
8dda53fc 549 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 550 ret = RING_SPACE(chan, 12);
551 if (ret)
552 return ret;
553
554 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
0ad72863 555 OUT_RING (chan, chan->vram.handle);
9f9bdaaf
BS		 556 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
557 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
558 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
559 OUT_RING (chan, sync->data + 1);
560 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
561 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
562 OUT_RING (chan, upper_32_bits(addr));
563 OUT_RING (chan, lower_32_bits(addr));
564 OUT_RING (chan, sync->data);
565 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
566 } else
567 if (chan) {
8dda53fc 568 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
9f9bdaaf
BS		 569 ret = RING_SPACE(chan, 10);
570 if (ret)
571 return ret;
572
573 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
574 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
575 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
576 OUT_RING (chan, sync->data + 1);
577 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
578 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
579 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
580 OUT_RING (chan, upper_32_bits(addr));
581 OUT_RING (chan, lower_32_bits(addr));
582 OUT_RING (chan, sync->data);
583 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
584 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
585 }
35bcf5d5 586
9f9bdaaf
BS		 587 if (chan) {
588 sync->addr ^= 0x10;
589 sync->data++;
3376ee37 590 FIRE_RING (chan);
3376ee37
BS		 591 }
592
593 /* queue the flip */
594 evo_mthd(push, 0x0100, 1);
595 evo_data(push, 0xfffe0000);
596 evo_mthd(push, 0x0084, 1);
597 evo_data(push, swap_interval);
598 if (!(swap_interval & 0x00000100)) {
599 evo_mthd(push, 0x00e0, 1);
600 evo_data(push, 0x40000000);
601 }
602 evo_mthd(push, 0x0088, 4);
9f9bdaaf
BS		 603 evo_data(push, sync->addr);
604 evo_data(push, sync->data++);
605 evo_data(push, sync->data);
f45f55c4 606 evo_data(push, sync->base.sync.handle);
3376ee37
BS		 607 evo_mthd(push, 0x00a0, 2);
608 evo_data(push, 0x00000000);
609 evo_data(push, 0x00000000);
610 evo_mthd(push, 0x00c0, 1);
8a423647 611 evo_data(push, nv_fb->r_handle);
3376ee37
BS		 612 evo_mthd(push, 0x0110, 2);
613 evo_data(push, 0x00000000);
614 evo_data(push, 0x00000000);
648d4dfd 615 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
ed5085a5
BS		 616 evo_mthd(push, 0x0800, 5);
617 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
618 evo_data(push, 0);
619 evo_data(push, (fb->height << 16) | fb->width);
620 evo_data(push, nv_fb->r_pitch);
621 evo_data(push, nv_fb->r_format);
622 } else {
623 evo_mthd(push, 0x0400, 5);
624 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
625 evo_data(push, 0);
626 evo_data(push, (fb->height << 16) | fb->width);
627 evo_data(push, nv_fb->r_pitch);
628 evo_data(push, nv_fb->r_format);
629 }
3376ee37
BS		 630 evo_mthd(push, 0x0080, 1);
631 evo_data(push, 0x00000000);
b5a794b0 632 evo_kick(push, sync);
8dda53fc
BS		 633
634 nouveau_bo_ref(nv_fb->nvbo, &head->image);
3376ee37
BS		 635 return 0;
636}
637
438d99e3
BS		 638/******************************************************************************
639 * CRTC
640 *****************************************************************************/
641static int
e225f446 642nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 643{
e225f446 644 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de691855
BS		 645 struct nouveau_connector *nv_connector;
646 struct drm_connector *connector;
647 u32 *push, mode = 0x00;
438d99e3 648
488ff207 649 nv_connector = nouveau_crtc_connector_get(nv_crtc);
de691855
BS		 650 connector = &nv_connector->base;
651 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
f4510a27 652 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
de691855
BS		 653 mode = DITHERING_MODE_DYNAMIC2X2;
654 } else {
655 mode = nv_connector->dithering_mode;
656 }
657
658 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
659 if (connector->display_info.bpc >= 8)
660 mode |= DITHERING_DEPTH_8BPC;
661 } else {
662 mode |= nv_connector->dithering_depth;
438d99e3
BS		 663 }
664
de8268c5 665 push = evo_wait(mast, 4);
438d99e3 666 if (push) {
648d4dfd 667 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 668 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
669 evo_data(push, mode);
670 } else
648d4dfd 671 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 672 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
673 evo_data(push, mode);
674 } else {
675 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
676 evo_data(push, mode);
677 }
678
438d99e3
BS		 679 if (update) {
680 evo_mthd(push, 0x0080, 1);
681 evo_data(push, 0x00000000);
682 }
de8268c5 683 evo_kick(push, mast);
438d99e3
BS		 684 }
685
686 return 0;
687}
688
689static int
e225f446 690nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
438d99e3 691{
e225f446 692 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
92854622 693 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
3376ee37 694 struct drm_crtc *crtc = &nv_crtc->base;
f3fdc52d 695 struct nouveau_connector *nv_connector;
92854622
BS		 696 int mode = DRM_MODE_SCALE_NONE;
697 u32 oX, oY, *push;
f3fdc52d 698
92854622
BS		 699 /* start off at the resolution we programmed the crtc for, this
700 * effectively handles NONE/FULL scaling
701 */
f3fdc52d 702 nv_connector = nouveau_crtc_connector_get(nv_crtc);
92854622
BS		 703 if (nv_connector && nv_connector->native_mode)
704 mode = nv_connector->scaling_mode;
705
706 if (mode != DRM_MODE_SCALE_NONE)
707 omode = nv_connector->native_mode;
708 else
709 omode = umode;
710
711 oX = omode->hdisplay;
712 oY = omode->vdisplay;
713 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
714 oY *= 2;
715
716 /* add overscan compensation if necessary, will keep the aspect
717 * ratio the same as the backend mode unless overridden by the
718 * user setting both hborder and vborder properties.
719 */
720 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
721 (nv_connector->underscan == UNDERSCAN_AUTO &&
722 nv_connector->edid &&
723 drm_detect_hdmi_monitor(nv_connector->edid)))) {
724 u32 bX = nv_connector->underscan_hborder;
725 u32 bY = nv_connector->underscan_vborder;
726 u32 aspect = (oY << 19) / oX;
727
728 if (bX) {
729 oX -= (bX * 2);
730 if (bY) oY -= (bY * 2);
731 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
732 } else {
733 oX -= (oX >> 4) + 32;
734 if (bY) oY -= (bY * 2);
735 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
736 }
737 }
738
739 /* handle CENTER/ASPECT scaling, taking into account the areas
740 * removed already for overscan compensation
741 */
742 switch (mode) {
743 case DRM_MODE_SCALE_CENTER:
744 oX = min((u32)umode->hdisplay, oX);
745 oY = min((u32)umode->vdisplay, oY);
746 /* fall-through */
747 case DRM_MODE_SCALE_ASPECT:
748 if (oY < oX) {
749 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
750 oX = ((oY * aspect) + (aspect / 2)) >> 19;
751 } else {
752 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
753 oY = ((oX * aspect) + (aspect / 2)) >> 19;
f3fdc52d 754 }
92854622
BS		 755 break;
756 default:
757 break;
f3fdc52d 758 }
438d99e3 759
de8268c5 760 push = evo_wait(mast, 8);
438d99e3 761 if (push) {
648d4dfd 762 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 763 /*XXX: SCALE_CTRL_ACTIVE??? */
764 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
765 evo_data(push, (oY << 16) | oX);
766 evo_data(push, (oY << 16) | oX);
767 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
768 evo_data(push, 0x00000000);
769 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
770 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
771 } else {
772 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
773 evo_data(push, (oY << 16) | oX);
774 evo_data(push, (oY << 16) | oX);
775 evo_data(push, (oY << 16) | oX);
776 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
777 evo_data(push, 0x00000000);
778 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
779 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
780 }
781
782 evo_kick(push, mast);
783
438d99e3 784 if (update) {
e225f446 785 nv50_display_flip_stop(crtc);
f4510a27
MR		 786 nv50_display_flip_next(crtc, crtc->primary->fb,
787 NULL, 1);
438d99e3 788 }
438d99e3
BS		 789 }
790
791 return 0;
792}
793
f9887d09 794static int
e225f446 795nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
f9887d09 796{
e225f446 797 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
f9887d09
BS		 798 u32 *push, hue, vib;
799 int adj;
800
801 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
802 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
803 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
804
805 push = evo_wait(mast, 16);
806 if (push) {
648d4dfd 807 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
f9887d09
BS		 808 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
809 evo_data(push, (hue << 20) | (vib << 8));
810 } else {
811 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
812 evo_data(push, (hue << 20) | (vib << 8));
813 }
814
815 if (update) {
816 evo_mthd(push, 0x0080, 1);
817 evo_data(push, 0x00000000);
818 }
819 evo_kick(push, mast);
820 }
821
822 return 0;
823}
824
438d99e3 825static int
e225f446 826nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
438d99e3
BS		 827 int x, int y, bool update)
828{
829 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
e225f446 830 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
438d99e3
BS		 831 u32 *push;
832
de8268c5 833 push = evo_wait(mast, 16);
438d99e3 834 if (push) {
648d4dfd 835 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 836 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
837 evo_data(push, nvfb->nvbo->bo.offset >> 8);
838 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
839 evo_data(push, (fb->height << 16) | fb->width);
840 evo_data(push, nvfb->r_pitch);
841 evo_data(push, nvfb->r_format);
842 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
843 evo_data(push, (y << 16) | x);
648d4dfd 844 if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
de8268c5 845 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 846 evo_data(push, nvfb->r_handle);
de8268c5
BS		 847 }
848 } else {
849 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
850 evo_data(push, nvfb->nvbo->bo.offset >> 8);
851 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
852 evo_data(push, (fb->height << 16) | fb->width);
853 evo_data(push, nvfb->r_pitch);
854 evo_data(push, nvfb->r_format);
8a423647 855 evo_data(push, nvfb->r_handle);
de8268c5
BS		 856 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
857 evo_data(push, (y << 16) | x);
858 }
859
a46232ee
BS		 860 if (update) {
861 evo_mthd(push, 0x0080, 1);
862 evo_data(push, 0x00000000);
863 }
de8268c5 864 evo_kick(push, mast);
438d99e3
BS		 865 }
866
8a423647 867 nv_crtc->fb.handle = nvfb->r_handle;
438d99e3
BS		 868 return 0;
869}
870
871static void
e225f446 872nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
438d99e3 873{
e225f446 874 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5 875 u32 *push = evo_wait(mast, 16);
438d99e3 876 if (push) {
648d4dfd 877 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 878 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
879 evo_data(push, 0x85000000);
880 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
881 } else
648d4dfd 882 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 883 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
884 evo_data(push, 0x85000000);
885 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
886 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
f45f55c4 887 evo_data(push, mast->base.vram.handle);
de8268c5 888 } else {
438d99e3
BS		 889 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
890 evo_data(push, 0x85000000);
891 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
892 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
f45f55c4 893 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 894 }
895 evo_kick(push, mast);
896 }
897}
898
899static void
e225f446 900nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
de8268c5 901{
e225f446 902 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 903 u32 *push = evo_wait(mast, 16);
904 if (push) {
648d4dfd 905 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 906 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
907 evo_data(push, 0x05000000);
908 } else
648d4dfd 909 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 910 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
911 evo_data(push, 0x05000000);
912 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
913 evo_data(push, 0x00000000);
438d99e3
BS		 914 } else {
915 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
916 evo_data(push, 0x05000000);
917 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
918 evo_data(push, 0x00000000);
919 }
de8268c5
BS		 920 evo_kick(push, mast);
921 }
922}
438d99e3 923
de8268c5 924static void
e225f446 925nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
de8268c5 926{
e225f446 927 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
de8268c5
BS		 928
929 if (show)
e225f446 930 nv50_crtc_cursor_show(nv_crtc);
de8268c5 931 else
e225f446 932 nv50_crtc_cursor_hide(nv_crtc);
de8268c5
BS		 933
934 if (update) {
935 u32 *push = evo_wait(mast, 2);
936 if (push) {
438d99e3
BS		 937 evo_mthd(push, 0x0080, 1);
938 evo_data(push, 0x00000000);
de8268c5 939 evo_kick(push, mast);
438d99e3 940 }
438d99e3
BS		 941 }
942}
943
944static void
e225f446 945nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
438d99e3
BS		 946{
947}
948
949static void
e225f446 950nv50_crtc_prepare(struct drm_crtc *crtc)
438d99e3
BS		 951{
952 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 953 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 954 u32 *push;
955
e225f446 956 nv50_display_flip_stop(crtc);
3376ee37 957
56d237d2 958 push = evo_wait(mast, 6);
438d99e3 959 if (push) {
648d4dfd 960 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 961 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
962 evo_data(push, 0x00000000);
963 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
964 evo_data(push, 0x40000000);
965 } else
648d4dfd 966 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 967 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
968 evo_data(push, 0x00000000);
969 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
970 evo_data(push, 0x40000000);
971 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
972 evo_data(push, 0x00000000);
973 } else {
974 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
975 evo_data(push, 0x00000000);
976 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
977 evo_data(push, 0x03000000);
978 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
979 evo_data(push, 0x00000000);
980 }
981
982 evo_kick(push, mast);
438d99e3
BS		 983 }
984
e225f446 985 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
438d99e3
BS		 986}
987
988static void
e225f446 989nv50_crtc_commit(struct drm_crtc *crtc)
438d99e3
BS		 990{
991 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446 992 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 993 u32 *push;
994
de8268c5 995 push = evo_wait(mast, 32);
438d99e3 996 if (push) {
648d4dfd 997 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
de8268c5 998 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 999 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1000 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1001 evo_data(push, 0xc0000000);
1002 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1003 } else
648d4dfd 1004 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5 1005 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
8a423647 1006 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1007 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1008 evo_data(push, 0xc0000000);
1009 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1010 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
f45f55c4 1011 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 1012 } else {
1013 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
8a423647 1014 evo_data(push, nv_crtc->fb.handle);
de8268c5
BS		 1015 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1016 evo_data(push, 0x83000000);
1017 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1018 evo_data(push, 0x00000000);
1019 evo_data(push, 0x00000000);
1020 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
f45f55c4 1021 evo_data(push, mast->base.vram.handle);
de8268c5
BS		 1022 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1023 evo_data(push, 0xffffff00);
1024 }
1025
1026 evo_kick(push, mast);
438d99e3
BS		 1027 }
1028
e225f446 1029 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
f4510a27 1030 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
438d99e3
BS		 1031}
1032
1033static bool
e225f446 1034nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
438d99e3
BS		 1035 struct drm_display_mode *adjusted_mode)
1036{
eb2e9686 1037 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
438d99e3
BS		 1038 return true;
1039}
1040
1041static int
e225f446 1042nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
438d99e3 1043{
f4510a27 1044 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
8dda53fc 1045 struct nv50_head *head = nv50_head(crtc);
438d99e3
BS		 1046 int ret;
1047
1048 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
8dda53fc
BS		 1049 if (ret == 0) {
1050 if (head->image)
1051 nouveau_bo_unpin(head->image);
1052 nouveau_bo_ref(nvfb->nvbo, &head->image);
438d99e3
BS		 1053 }
1054
8dda53fc 1055 return ret;
438d99e3
BS		 1056}
1057
1058static int
e225f446 1059nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
438d99e3
BS		 1060 struct drm_display_mode *mode, int x, int y,
1061 struct drm_framebuffer *old_fb)
1062{
e225f446 1063 struct nv50_mast *mast = nv50_mast(crtc->dev);
438d99e3
BS		 1064 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1065 struct nouveau_connector *nv_connector;
2d1d898b
BS		 1066 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1067 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1068 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1069 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1dce6264 1070 u32 vblan2e = 0, vblan2s = 1, vblankus = 0;
3488c57b 1071 u32 *push;
438d99e3
BS		 1072 int ret;
1073
2d1d898b
BS		 1074 hactive = mode->htotal;
1075 hsynce = mode->hsync_end - mode->hsync_start - 1;
1076 hbackp = mode->htotal - mode->hsync_end;
1077 hblanke = hsynce + hbackp;
1078 hfrontp = mode->hsync_start - mode->hdisplay;
1079 hblanks = mode->htotal - hfrontp - 1;
1080
1081 vactive = mode->vtotal * vscan / ilace;
1082 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1083 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1084 vblanke = vsynce + vbackp;
1085 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1086 vblanks = vactive - vfrontp - 1;
1dce6264
RS		 1087 /* XXX: Safe underestimate, even "0" works */
1088 vblankus = (vactive - mode->vdisplay - 2) * hactive;
1089 vblankus *= 1000;
1090 vblankus /= mode->clock;
1091
2d1d898b
BS		 1092 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1093 vblan2e = vactive + vsynce + vbackp;
1094 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1095 vactive = (vactive * 2) + 1;
2d1d898b
BS		 1096 }
1097
e225f446 1098 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1099 if (ret)
1100 return ret;
1101
de8268c5 1102 push = evo_wait(mast, 64);
438d99e3 1103 if (push) {
648d4dfd 1104 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
de8268c5
BS		 1105 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1106 evo_data(push, 0x00800000 | mode->clock);
1107 evo_data(push, (ilace == 2) ? 2 : 0);
1dce6264 1108 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 8);
de8268c5
BS		 1109 evo_data(push, 0x00000000);
1110 evo_data(push, (vactive << 16) | hactive);
1111 evo_data(push, ( vsynce << 16) | hsynce);
1112 evo_data(push, (vblanke << 16) | hblanke);
1113 evo_data(push, (vblanks << 16) | hblanks);
1114 evo_data(push, (vblan2e << 16) | vblan2s);
1dce6264 1115 evo_data(push, vblankus);
de8268c5
BS		 1116 evo_data(push, 0x00000000);
1117 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1118 evo_data(push, 0x00000311);
1119 evo_data(push, 0x00000100);
1120 } else {
1121 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1122 evo_data(push, 0x00000000);
1123 evo_data(push, (vactive << 16) | hactive);
1124 evo_data(push, ( vsynce << 16) | hsynce);
1125 evo_data(push, (vblanke << 16) | hblanke);
1126 evo_data(push, (vblanks << 16) | hblanks);
1127 evo_data(push, (vblan2e << 16) | vblan2s);
1128 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1129 evo_data(push, 0x00000000); /* ??? */
1130 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1131 evo_data(push, mode->clock * 1000);
1132 evo_data(push, 0x00200000); /* ??? */
1133 evo_data(push, mode->clock * 1000);
1134 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1135 evo_data(push, 0x00000311);
1136 evo_data(push, 0x00000100);
1137 }
1138
1139 evo_kick(push, mast);
438d99e3
BS		 1140 }
1141
1142 nv_connector = nouveau_crtc_connector_get(nv_crtc);
e225f446
BS		 1143 nv50_crtc_set_dither(nv_crtc, false);
1144 nv50_crtc_set_scale(nv_crtc, false);
1145 nv50_crtc_set_color_vibrance(nv_crtc, false);
f4510a27 1146 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
438d99e3
BS		 1147 return 0;
1148}
1149
1150static int
e225f446 1151nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
438d99e3
BS		 1152 struct drm_framebuffer *old_fb)
1153{
77145f1c 1154 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
438d99e3
BS		 1155 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1156 int ret;
1157
f4510a27 1158 if (!crtc->primary->fb) {
77145f1c 1159 NV_DEBUG(drm, "No FB bound\n");
84e2ad8b
BS		 1160 return 0;
1161 }
1162
e225f446 1163 ret = nv50_crtc_swap_fbs(crtc, old_fb);
438d99e3
BS		 1164 if (ret)
1165 return ret;
1166
e225f446 1167 nv50_display_flip_stop(crtc);
f4510a27
MR		 1168 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1169 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
438d99e3
BS		 1170 return 0;
1171}
1172
1173static int
e225f446 1174nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
438d99e3
BS		 1175 struct drm_framebuffer *fb, int x, int y,
1176 enum mode_set_atomic state)
1177{
1178 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1179 nv50_display_flip_stop(crtc);
1180 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
438d99e3
BS		 1181 return 0;
1182}
1183
1184static void
e225f446 1185nv50_crtc_lut_load(struct drm_crtc *crtc)
438d99e3 1186{
e225f446 1187 struct nv50_disp *disp = nv50_disp(crtc->dev);
438d99e3
BS		 1188 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1189 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1190 int i;
1191
1192 for (i = 0; i < 256; i++) {
de8268c5
BS		 1193 u16 r = nv_crtc->lut.r[i] >> 2;
1194 u16 g = nv_crtc->lut.g[i] >> 2;
1195 u16 b = nv_crtc->lut.b[i] >> 2;
1196
648d4dfd 1197 if (disp->disp->oclass < GF110_DISP) {
de8268c5
BS		 1198 writew(r + 0x0000, lut + (i * 0x08) + 0);
1199 writew(g + 0x0000, lut + (i * 0x08) + 2);
1200 writew(b + 0x0000, lut + (i * 0x08) + 4);
1201 } else {
1202 writew(r + 0x6000, lut + (i * 0x20) + 0);
1203 writew(g + 0x6000, lut + (i * 0x20) + 2);
1204 writew(b + 0x6000, lut + (i * 0x20) + 4);
1205 }
438d99e3
BS		 1206 }
1207}
1208
8dda53fc
BS		 1209static void
1210nv50_crtc_disable(struct drm_crtc *crtc)
1211{
1212 struct nv50_head *head = nv50_head(crtc);
efa366fd 1213 evo_sync(crtc->dev);
8dda53fc
BS		 1214 if (head->image)
1215 nouveau_bo_unpin(head->image);
1216 nouveau_bo_ref(NULL, &head->image);
1217}
1218
438d99e3 1219static int
e225f446 1220nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
438d99e3
BS		 1221 uint32_t handle, uint32_t width, uint32_t height)
1222{
1223 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1224 struct drm_device *dev = crtc->dev;
1225 struct drm_gem_object *gem;
1226 struct nouveau_bo *nvbo;
1227 bool visible = (handle != 0);
1228 int i, ret = 0;
1229
1230 if (visible) {
1231 if (width != 64 || height != 64)
1232 return -EINVAL;
1233
1234 gem = drm_gem_object_lookup(dev, file_priv, handle);
1235 if (unlikely(!gem))
1236 return -ENOENT;
1237 nvbo = nouveau_gem_object(gem);
1238
1239 ret = nouveau_bo_map(nvbo);
1240 if (ret == 0) {
1241 for (i = 0; i < 64 * 64; i++) {
1242 u32 v = nouveau_bo_rd32(nvbo, i);
1243 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1244 }
1245 nouveau_bo_unmap(nvbo);
1246 }
1247
1248 drm_gem_object_unreference_unlocked(gem);
1249 }
1250
1251 if (visible != nv_crtc->cursor.visible) {
e225f446 1252 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
438d99e3
BS		 1253 nv_crtc->cursor.visible = visible;
1254 }
1255
1256 return ret;
1257}
1258
1259static int
e225f446 1260nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
438d99e3 1261{
e225f446
BS		 1262 struct nv50_curs *curs = nv50_curs(crtc);
1263 struct nv50_chan *chan = nv50_chan(curs);
0ad72863
BS		 1264 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1265 nvif_wr32(&chan->user, 0x0080, 0x00000000);
438d99e3
BS		 1266 return 0;
1267}
1268
1269static void
e225f446 1270nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
438d99e3
BS		 1271 uint32_t start, uint32_t size)
1272{
1273 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
bdefc8cb 1274 u32 end = min_t(u32, start + size, 256);
438d99e3
BS		 1275 u32 i;
1276
1277 for (i = start; i < end; i++) {
1278 nv_crtc->lut.r[i] = r[i];
1279 nv_crtc->lut.g[i] = g[i];
1280 nv_crtc->lut.b[i] = b[i];
1281 }
1282
e225f446 1283 nv50_crtc_lut_load(crtc);
438d99e3
BS		 1284}
1285
1286static void
e225f446 1287nv50_crtc_destroy(struct drm_crtc *crtc)
438d99e3
BS		 1288{
1289 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
e225f446
BS		 1290 struct nv50_disp *disp = nv50_disp(crtc->dev);
1291 struct nv50_head *head = nv50_head(crtc);
0ad72863 1292 struct nv50_fbdma *fbdma;
8dda53fc 1293
0ad72863
BS		 1294 list_for_each_entry(fbdma, &disp->fbdma, head) {
1295 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1296 }
1297
1298 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1299 nv50_pioc_destroy(&head->oimm.base);
1300 nv50_dmac_destroy(&head->sync.base, disp->disp);
1301 nv50_pioc_destroy(&head->curs.base);
8dda53fc
BS		 1302
1303 /*XXX: this shouldn't be necessary, but the core doesn't call
1304 * disconnect() during the cleanup paths
1305 */
1306 if (head->image)
1307 nouveau_bo_unpin(head->image);
1308 nouveau_bo_ref(NULL, &head->image);
1309
438d99e3 1310 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
04c8c210
MS		 1311 if (nv_crtc->cursor.nvbo)
1312 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
438d99e3 1313 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
8dda53fc 1314
438d99e3 1315 nouveau_bo_unmap(nv_crtc->lut.nvbo);
04c8c210
MS		 1316 if (nv_crtc->lut.nvbo)
1317 nouveau_bo_unpin(nv_crtc->lut.nvbo);
438d99e3 1318 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
8dda53fc 1319
438d99e3
BS		 1320 drm_crtc_cleanup(crtc);
1321 kfree(crtc);
1322}
1323
e225f446
BS		 1324static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1325 .dpms = nv50_crtc_dpms,
1326 .prepare = nv50_crtc_prepare,
1327 .commit = nv50_crtc_commit,
1328 .mode_fixup = nv50_crtc_mode_fixup,
1329 .mode_set = nv50_crtc_mode_set,
1330 .mode_set_base = nv50_crtc_mode_set_base,
1331 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1332 .load_lut = nv50_crtc_lut_load,
8dda53fc 1333 .disable = nv50_crtc_disable,
438d99e3
BS		 1334};
1335
e225f446
BS		 1336static const struct drm_crtc_funcs nv50_crtc_func = {
1337 .cursor_set = nv50_crtc_cursor_set,
1338 .cursor_move = nv50_crtc_cursor_move,
1339 .gamma_set = nv50_crtc_gamma_set,
5addcf0a 1340 .set_config = nouveau_crtc_set_config,
e225f446 1341 .destroy = nv50_crtc_destroy,
3376ee37 1342 .page_flip = nouveau_crtc_page_flip,
438d99e3
BS		 1343};
1344
c20ab3e1 1345static void
e225f446 1346nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
c20ab3e1
BS		 1347{
1348}
1349
1350static void
e225f446 1351nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
c20ab3e1
BS		 1352{
1353}
1354
438d99e3 1355static int
0ad72863 1356nv50_crtc_create(struct drm_device *dev, int index)
438d99e3 1357{
e225f446
BS		 1358 struct nv50_disp *disp = nv50_disp(dev);
1359 struct nv50_head *head;
438d99e3
BS		 1360 struct drm_crtc *crtc;
1361 int ret, i;
1362
dd0e3d53
BS		 1363 head = kzalloc(sizeof(*head), GFP_KERNEL);
1364 if (!head)
438d99e3
BS		 1365 return -ENOMEM;
1366
dd0e3d53 1367 head->base.index = index;
e225f446
BS		 1368 head->base.set_dither = nv50_crtc_set_dither;
1369 head->base.set_scale = nv50_crtc_set_scale;
1370 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
f9887d09
BS		 1371 head->base.color_vibrance = 50;
1372 head->base.vibrant_hue = 0;
e225f446
BS		 1373 head->base.cursor.set_offset = nv50_cursor_set_offset;
1374 head->base.cursor.set_pos = nv50_cursor_set_pos;
438d99e3 1375 for (i = 0; i < 256; i++) {
dd0e3d53
BS		 1376 head->base.lut.r[i] = i << 8;
1377 head->base.lut.g[i] = i << 8;
1378 head->base.lut.b[i] = i << 8;
438d99e3
BS		 1379 }
1380
dd0e3d53 1381 crtc = &head->base.base;
e225f446
BS		 1382 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1383 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
438d99e3
BS		 1384 drm_mode_crtc_set_gamma_size(crtc, 256);
1385
b5a794b0 1386 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
bb6178b0 1387 0, 0x0000, NULL, NULL, &head->base.lut.nvbo);
b5a794b0
BS		 1388 if (!ret) {
1389 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1390 if (!ret) {
b5a794b0 1391 ret = nouveau_bo_map(head->base.lut.nvbo);
04c8c210
MS		 1392 if (ret)
1393 nouveau_bo_unpin(head->base.lut.nvbo);
1394 }
b5a794b0
BS		 1395 if (ret)
1396 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1397 }
1398
1399 if (ret)
1400 goto out;
1401
e225f446 1402 nv50_crtc_lut_load(crtc);
b5a794b0
BS		 1403
1404 /* allocate cursor resources */
410f3ec6 1405 ret = nv50_curs_create(disp->disp, index, &head->curs);
b5a794b0
BS		 1406 if (ret)
1407 goto out;
1408
438d99e3 1409 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
bb6178b0 1410 0, 0x0000, NULL, NULL, &head->base.cursor.nvbo);
438d99e3 1411 if (!ret) {
dd0e3d53 1412 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
04c8c210 1413 if (!ret) {
dd0e3d53 1414 ret = nouveau_bo_map(head->base.cursor.nvbo);
04c8c210
MS		 1415 if (ret)
1416 nouveau_bo_unpin(head->base.lut.nvbo);
1417 }
438d99e3 1418 if (ret)
dd0e3d53 1419 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
438d99e3
BS		 1420 }
1421
1422 if (ret)
1423 goto out;
1424
b5a794b0 1425 /* allocate page flip / sync resources */
410f3ec6
BS		 1426 ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1427 &head->sync);
b5a794b0
BS		 1428 if (ret)
1429 goto out;
1430
9f9bdaaf
BS		 1431 head->sync.addr = EVO_FLIP_SEM0(index);
1432 head->sync.data = 0x00000000;
438d99e3 1433
b5a794b0 1434 /* allocate overlay resources */
410f3ec6 1435 ret = nv50_oimm_create(disp->disp, index, &head->oimm);
438d99e3
BS		 1436 if (ret)
1437 goto out;
1438
410f3ec6
BS		 1439 ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1440 &head->ovly);
b5a794b0
BS		 1441 if (ret)
1442 goto out;
438d99e3
BS		 1443
1444out:
1445 if (ret)
e225f446 1446 nv50_crtc_destroy(crtc);
438d99e3
BS		 1447 return ret;
1448}
1449
26f6d88b
BS		 1450/******************************************************************************
1451 * DAC
1452 *****************************************************************************/
8eaa9669 1453static void
e225f446 1454nv50_dac_dpms(struct drm_encoder *encoder, int mode)
8eaa9669
BS		 1455{
1456 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1457 struct nv50_disp *disp = nv50_disp(encoder->dev);
bf0eb898
BS		 1458 struct {
1459 struct nv50_disp_mthd_v1 base;
1460 struct nv50_disp_dac_pwr_v0 pwr;
1461 } args = {
1462 .base.version = 1,
1463 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1464 .base.hasht = nv_encoder->dcb->hasht,
1465 .base.hashm = nv_encoder->dcb->hashm,
1466 .pwr.state = 1,
1467 .pwr.data = 1,
1468 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1469 mode != DRM_MODE_DPMS_OFF),
1470 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1471 mode != DRM_MODE_DPMS_OFF),
1472 };
8eaa9669 1473
bf0eb898 1474 nvif_mthd(disp->disp, 0, &args, sizeof(args));
8eaa9669
BS		 1475}
1476
1477static bool
e225f446 1478nv50_dac_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1479 const struct drm_display_mode *mode,
8eaa9669
BS		 1480 struct drm_display_mode *adjusted_mode)
1481{
1482 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1483 struct nouveau_connector *nv_connector;
1484
1485 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1486 if (nv_connector && nv_connector->native_mode) {
1487 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1488 int id = adjusted_mode->base.id;
1489 *adjusted_mode = *nv_connector->native_mode;
1490 adjusted_mode->base.id = id;
1491 }
1492 }
1493
1494 return true;
1495}
1496
8eaa9669 1497static void
e225f446 1498nv50_dac_commit(struct drm_encoder *encoder)
8eaa9669
BS		 1499{
1500}
1501
1502static void
e225f446 1503nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
8eaa9669
BS		 1504 struct drm_display_mode *adjusted_mode)
1505{
e225f446 1506 struct nv50_mast *mast = nv50_mast(encoder->dev);
8eaa9669
BS		 1507 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1508 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
97b19b5c 1509 u32 *push;
8eaa9669 1510
e225f446 1511 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
8eaa9669 1512
97b19b5c 1513 push = evo_wait(mast, 8);
8eaa9669 1514 if (push) {
648d4dfd 1515 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
97b19b5c
BS		 1516 u32 syncs = 0x00000000;
1517
1518 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1519 syncs |= 0x00000001;
1520 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1521 syncs |= 0x00000002;
1522
1523 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1524 evo_data(push, 1 << nv_crtc->index);
1525 evo_data(push, syncs);
1526 } else {
1527 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1528 u32 syncs = 0x00000001;
1529
1530 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1531 syncs |= 0x00000008;
1532 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1533 syncs |= 0x00000010;
1534
1535 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1536 magic |= 0x00000001;
1537
1538 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1539 evo_data(push, syncs);
1540 evo_data(push, magic);
1541 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1542 evo_data(push, 1 << nv_crtc->index);
1543 }
1544
1545 evo_kick(push, mast);
8eaa9669
BS		 1546 }
1547
1548 nv_encoder->crtc = encoder->crtc;
1549}
1550
1551static void
e225f446 1552nv50_dac_disconnect(struct drm_encoder *encoder)
8eaa9669
BS		 1553{
1554 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1555 struct nv50_mast *mast = nv50_mast(encoder->dev);
97b19b5c 1556 const int or = nv_encoder->or;
8eaa9669
BS		 1557 u32 *push;
1558
1559 if (nv_encoder->crtc) {
e225f446 1560 nv50_crtc_prepare(nv_encoder->crtc);
8eaa9669 1561
97b19b5c 1562 push = evo_wait(mast, 4);
8eaa9669 1563 if (push) {
648d4dfd 1564 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
97b19b5c
BS		 1565 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1566 evo_data(push, 0x00000000);
1567 } else {
1568 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1569 evo_data(push, 0x00000000);
1570 }
97b19b5c 1571 evo_kick(push, mast);
8eaa9669 1572 }
8eaa9669 1573 }
97b19b5c
BS		 1574
1575 nv_encoder->crtc = NULL;
8eaa9669
BS		 1576}
1577
b6d8e7ec 1578static enum drm_connector_status
e225f446 1579nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
b6d8e7ec 1580{
c4abd317 1581 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1582 struct nv50_disp *disp = nv50_disp(encoder->dev);
c4abd317
BS		 1583 struct {
1584 struct nv50_disp_mthd_v1 base;
1585 struct nv50_disp_dac_load_v0 load;
1586 } args = {
1587 .base.version = 1,
1588 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1589 .base.hasht = nv_encoder->dcb->hasht,
1590 .base.hashm = nv_encoder->dcb->hashm,
1591 };
1592 int ret;
1593
1594 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1595 if (args.load.data == 0)
1596 args.load.data = 340;
b681993f 1597
c4abd317
BS		 1598 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1599 if (ret || !args.load.load)
35b21d39 1600 return connector_status_disconnected;
b681993f 1601
35b21d39 1602 return connector_status_connected;
b6d8e7ec
BS		 1603}
1604
8eaa9669 1605static void
e225f446 1606nv50_dac_destroy(struct drm_encoder *encoder)
8eaa9669
BS		 1607{
1608 drm_encoder_cleanup(encoder);
1609 kfree(encoder);
1610}
1611
e225f446
BS		 1612static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1613 .dpms = nv50_dac_dpms,
1614 .mode_fixup = nv50_dac_mode_fixup,
1615 .prepare = nv50_dac_disconnect,
1616 .commit = nv50_dac_commit,
1617 .mode_set = nv50_dac_mode_set,
1618 .disable = nv50_dac_disconnect,
1619 .get_crtc = nv50_display_crtc_get,
1620 .detect = nv50_dac_detect
8eaa9669
BS		 1621};
1622
e225f446
BS		 1623static const struct drm_encoder_funcs nv50_dac_func = {
1624 .destroy = nv50_dac_destroy,
8eaa9669
BS		 1625};
1626
1627static int
e225f446 1628nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
8eaa9669 1629{
5ed50209 1630 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 1631 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
8eaa9669
BS		 1632 struct nouveau_encoder *nv_encoder;
1633 struct drm_encoder *encoder;
5ed50209 1634 int type = DRM_MODE_ENCODER_DAC;
8eaa9669
BS		 1635
1636 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1637 if (!nv_encoder)
1638 return -ENOMEM;
1639 nv_encoder->dcb = dcbe;
1640 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 1641 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
8eaa9669
BS		 1642
1643 encoder = to_drm_encoder(nv_encoder);
1644 encoder->possible_crtcs = dcbe->heads;
1645 encoder->possible_clones = 0;
5ed50209 1646 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
e225f446 1647 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
8eaa9669
BS		 1648
1649 drm_mode_connector_attach_encoder(connector, encoder);
1650 return 0;
1651}
26f6d88b 1652
78951d22
BS		 1653/******************************************************************************
1654 * Audio
1655 *****************************************************************************/
1656static void
e225f446 1657nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22
BS		 1658{
1659 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
cc2a9071 1660 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
78951d22 1661 struct nouveau_connector *nv_connector;
e225f446 1662 struct nv50_disp *disp = nv50_disp(encoder->dev);
d889c524
BS		 1663 struct __packed {
1664 struct {
1665 struct nv50_disp_mthd_v1 mthd;
1666 struct nv50_disp_sor_hda_eld_v0 eld;
1667 } base;
120b0c39
BS		 1668 u8 data[sizeof(nv_connector->base.eld)];
1669 } args = {
d889c524
BS		 1670 .base.mthd.version = 1,
1671 .base.mthd.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1672 .base.mthd.hasht = nv_encoder->dcb->hasht,
cc2a9071
BS		 1673 .base.mthd.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1674 (0x0100 << nv_crtc->index),
120b0c39 1675 };
78951d22
BS		 1676
1677 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1678 if (!drm_detect_monitor_audio(nv_connector->edid))
1679 return;
1680
78951d22 1681 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
120b0c39 1682 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
78951d22 1683
d889c524 1684 nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4);
78951d22
BS		 1685}
1686
1687static void
cc2a9071 1688nv50_audio_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
78951d22
BS		 1689{
1690 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1691 struct nv50_disp *disp = nv50_disp(encoder->dev);
120b0c39
BS		 1692 struct {
1693 struct nv50_disp_mthd_v1 base;
1694 struct nv50_disp_sor_hda_eld_v0 eld;
1695 } args = {
1696 .base.version = 1,
1697 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1698 .base.hasht = nv_encoder->dcb->hasht,
cc2a9071
BS		 1699 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1700 (0x0100 << nv_crtc->index),
120b0c39 1701 };
78951d22 1702
120b0c39 1703 nvif_mthd(disp->disp, 0, &args, sizeof(args));
78951d22
BS		 1704}
1705
1706/******************************************************************************
1707 * HDMI
1708 *****************************************************************************/
1709static void
e225f446 1710nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
78951d22 1711{
64d9cc04
BS		 1712 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1713 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
e225f446 1714 struct nv50_disp *disp = nv50_disp(encoder->dev);
e00f2235
BS		 1715 struct {
1716 struct nv50_disp_mthd_v1 base;
1717 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1718 } args = {
1719 .base.version = 1,
1720 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1721 .base.hasht = nv_encoder->dcb->hasht,
1722 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1723 (0x0100 << nv_crtc->index),
1724 .pwr.state = 1,
1725 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1726 };
1727 struct nouveau_connector *nv_connector;
64d9cc04
BS		 1728 u32 max_ac_packet;
1729
1730 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1731 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1732 return;
1733
1734 max_ac_packet = mode->htotal - mode->hdisplay;
e00f2235 1735 max_ac_packet -= args.pwr.rekey;
64d9cc04 1736 max_ac_packet -= 18; /* constant from tegra */
e00f2235 1737 args.pwr.max_ac_packet = max_ac_packet / 32;
091e40cd 1738
e00f2235 1739 nvif_mthd(disp->disp, 0, &args, sizeof(args));
e225f446 1740 nv50_audio_mode_set(encoder, mode);
78951d22
BS		 1741}
1742
1743static void
e84a35a8 1744nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
78951d22 1745{
64d9cc04 1746 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
e225f446 1747 struct nv50_disp *disp = nv50_disp(encoder->dev);
e00f2235
BS		 1748 struct {
1749 struct nv50_disp_mthd_v1 base;
1750 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1751 } args = {
1752 .base.version = 1,
1753 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1754 .base.hasht = nv_encoder->dcb->hasht,
1755 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1756 (0x0100 << nv_crtc->index),
1757 };
64d9cc04 1758
e00f2235 1759 nvif_mthd(disp->disp, 0, &args, sizeof(args));
78951d22
BS		 1760}
1761
26f6d88b
BS		 1762/******************************************************************************
1763 * SOR
1764 *****************************************************************************/
83fc083c 1765static void
e225f446 1766nv50_sor_dpms(struct drm_encoder *encoder, int mode)
83fc083c
BS		 1767{
1768 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
d55b4af9
BS		 1769 struct nv50_disp *disp = nv50_disp(encoder->dev);
1770 struct {
1771 struct nv50_disp_mthd_v1 base;
1772 struct nv50_disp_sor_pwr_v0 pwr;
1773 } args = {
1774 .base.version = 1,
1775 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1776 .base.hasht = nv_encoder->dcb->hasht,
1777 .base.hashm = nv_encoder->dcb->hashm,
1778 .pwr.state = mode == DRM_MODE_DPMS_ON,
1779 };
c02ed2bf
BS		 1780 struct {
1781 struct nv50_disp_mthd_v1 base;
1782 struct nv50_disp_sor_dp_pwr_v0 pwr;
1783 } link = {
1784 .base.version = 1,
1785 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1786 .base.hasht = nv_encoder->dcb->hasht,
1787 .base.hashm = nv_encoder->dcb->hashm,
1788 .pwr.state = mode == DRM_MODE_DPMS_ON,
1789 };
83fc083c
BS		 1790 struct drm_device *dev = encoder->dev;
1791 struct drm_encoder *partner;
83fc083c
BS		 1792
1793 nv_encoder->last_dpms = mode;
1794
1795 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1796 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1797
1798 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1799 continue;
1800
1801 if (nv_partner != nv_encoder &&
26cfa813 1802 nv_partner->dcb->or == nv_encoder->dcb->or) {
83fc083c
BS		 1803 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1804 return;
1805 break;
1806 }
1807 }
1808
4874322e 1809 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
d55b4af9
BS		 1810 args.pwr.state = 1;
1811 nvif_mthd(disp->disp, 0, &args, sizeof(args));
c02ed2bf 1812 nvif_mthd(disp->disp, 0, &link, sizeof(link));
4874322e 1813 } else {
d55b4af9 1814 nvif_mthd(disp->disp, 0, &args, sizeof(args));
4874322e 1815 }
83fc083c
BS		 1816}
1817
1818static bool
e225f446 1819nv50_sor_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1820 const struct drm_display_mode *mode,
83fc083c
BS		 1821 struct drm_display_mode *adjusted_mode)
1822{
1823 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1824 struct nouveau_connector *nv_connector;
1825
1826 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1827 if (nv_connector && nv_connector->native_mode) {
1828 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1829 int id = adjusted_mode->base.id;
1830 *adjusted_mode = *nv_connector->native_mode;
1831 adjusted_mode->base.id = id;
1832 }
1833 }
1834
1835 return true;
1836}
1837
4cbb0f8d 1838static void
e84a35a8 1839nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
4cbb0f8d 1840{
e84a35a8
BS		 1841 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1842 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1843 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
648d4dfd 1844 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
e84a35a8
BS		 1845 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1846 evo_data(push, (nv_encoder->ctrl = temp));
1847 } else {
1848 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1849 evo_data(push, (nv_encoder->ctrl = temp));
4cbb0f8d 1850 }
e84a35a8 1851 evo_kick(push, mast);
4cbb0f8d 1852 }
e84a35a8
BS		 1853}
1854
1855static void
1856nv50_sor_disconnect(struct drm_encoder *encoder)
1857{
1858 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1859 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
419e8dc0
BS		 1860
1861 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1862 nv_encoder->crtc = NULL;
e84a35a8
BS		 1863
1864 if (nv_crtc) {
1865 nv50_crtc_prepare(&nv_crtc->base);
1866 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
cc2a9071 1867 nv50_audio_disconnect(encoder, nv_crtc);
e84a35a8
BS		 1868 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1869 }
4cbb0f8d
BS		 1870}
1871
83fc083c 1872static void
e225f446 1873nv50_sor_commit(struct drm_encoder *encoder)
83fc083c
BS		 1874{
1875}
1876
1877static void
e225f446 1878nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
3b6d83d1 1879 struct drm_display_mode *mode)
83fc083c 1880{
a3761fa2
BS		 1881 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1882 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1883 struct {
1884 struct nv50_disp_mthd_v1 base;
1885 struct nv50_disp_sor_lvds_script_v0 lvds;
1886 } lvds = {
1887 .base.version = 1,
1888 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1889 .base.hasht = nv_encoder->dcb->hasht,
1890 .base.hashm = nv_encoder->dcb->hashm,
1891 };
e225f446
BS		 1892 struct nv50_disp *disp = nv50_disp(encoder->dev);
1893 struct nv50_mast *mast = nv50_mast(encoder->dev);
78951d22 1894 struct drm_device *dev = encoder->dev;
77145f1c 1895 struct nouveau_drm *drm = nouveau_drm(dev);
3b6d83d1 1896 struct nouveau_connector *nv_connector;
77145f1c 1897 struct nvbios *bios = &drm->vbios;
a3761fa2 1898 u32 mask, ctrl;
419e8dc0
BS		 1899 u8 owner = 1 << nv_crtc->index;
1900 u8 proto = 0xf;
1901 u8 depth = 0x0;
83fc083c 1902
3b6d83d1 1903 nv_connector = nouveau_encoder_connector_get(nv_encoder);
e84a35a8
BS		 1904 nv_encoder->crtc = encoder->crtc;
1905
3b6d83d1 1906 switch (nv_encoder->dcb->type) {
cb75d97e 1907 case DCB_OUTPUT_TMDS:
3b6d83d1
BS		 1908 if (nv_encoder->dcb->sorconf.link & 1) {
1909 if (mode->clock < 165000)
419e8dc0 1910 proto = 0x1;
3b6d83d1 1911 else
419e8dc0 1912 proto = 0x5;
3b6d83d1 1913 } else {
419e8dc0 1914 proto = 0x2;
3b6d83d1
BS		 1915 }
1916
e84a35a8 1917 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
3b6d83d1 1918 break;
cb75d97e 1919 case DCB_OUTPUT_LVDS:
419e8dc0
BS		 1920 proto = 0x0;
1921
3b6d83d1
BS		 1922 if (bios->fp_no_ddc) {
1923 if (bios->fp.dual_link)
a3761fa2 1924 lvds.lvds.script |= 0x0100;
3b6d83d1 1925 if (bios->fp.if_is_24bit)
a3761fa2 1926 lvds.lvds.script |= 0x0200;
3b6d83d1 1927 } else {
befb51e9 1928 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
3b6d83d1 1929 if (((u8 *)nv_connector->edid)[121] == 2)
a3761fa2 1930 lvds.lvds.script |= 0x0100;
3b6d83d1
BS		 1931 } else
1932 if (mode->clock >= bios->fp.duallink_transition_clk) {
a3761fa2 1933 lvds.lvds.script |= 0x0100;
3b6d83d1 1934 }
83fc083c 1935
a3761fa2 1936 if (lvds.lvds.script & 0x0100) {
3b6d83d1 1937 if (bios->fp.strapless_is_24bit & 2)
a3761fa2 1938 lvds.lvds.script |= 0x0200;
3b6d83d1
BS		 1939 } else {
1940 if (bios->fp.strapless_is_24bit & 1)
a3761fa2 1941 lvds.lvds.script |= 0x0200;
3b6d83d1
BS		 1942 }
1943
1944 if (nv_connector->base.display_info.bpc == 8)
a3761fa2 1945 lvds.lvds.script |= 0x0200;
3b6d83d1 1946 }
4a230fa6 1947
a3761fa2 1948 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
3b6d83d1 1949 break;
cb75d97e 1950 case DCB_OUTPUT_DP:
3488c57b 1951 if (nv_connector->base.display_info.bpc == 6) {
6e83fda2 1952 nv_encoder->dp.datarate = mode->clock * 18 / 8;
419e8dc0 1953 depth = 0x2;
bf2c886a
BS		 1954 } else
1955 if (nv_connector->base.display_info.bpc == 8) {
6e83fda2 1956 nv_encoder->dp.datarate = mode->clock * 24 / 8;
419e8dc0 1957 depth = 0x5;
bf2c886a
BS		 1958 } else {
1959 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1960 depth = 0x6;
3488c57b 1961 }
6e83fda2
BS		 1962
1963 if (nv_encoder->dcb->sorconf.link & 1)
419e8dc0 1964 proto = 0x8;
6e83fda2 1965 else
419e8dc0 1966 proto = 0x9;
3eee8646 1967 nv50_audio_mode_set(encoder, mode);
6e83fda2 1968 break;
3b6d83d1
BS		 1969 default:
1970 BUG_ON(1);
1971 break;
1972 }
ff8ff503 1973
e84a35a8 1974 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
83fc083c 1975
648d4dfd 1976 if (nv50_vers(mast) >= GF110_DISP) {
e84a35a8
BS		 1977 u32 *push = evo_wait(mast, 3);
1978 if (push) {
419e8dc0
BS		 1979 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1980 u32 syncs = 0x00000001;
1981
1982 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1983 syncs |= 0x00000008;
1984 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1985 syncs |= 0x00000010;
1986
1987 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1988 magic |= 0x00000001;
1989
1990 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1991 evo_data(push, syncs | (depth << 6));
1992 evo_data(push, magic);
e84a35a8 1993 evo_kick(push, mast);
419e8dc0
BS		 1994 }
1995
e84a35a8
BS		 1996 ctrl = proto << 8;
1997 mask = 0x00000f00;
1998 } else {
1999 ctrl = (depth << 16) | (proto << 8);
2000 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2001 ctrl |= 0x00001000;
2002 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2003 ctrl |= 0x00002000;
2004 mask = 0x000f3f00;
83fc083c
BS		 2005 }
2006
e84a35a8 2007 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
83fc083c
BS		 2008}
2009
83fc083c 2010static void
e225f446 2011nv50_sor_destroy(struct drm_encoder *encoder)
83fc083c
BS		 2012{
2013 drm_encoder_cleanup(encoder);
2014 kfree(encoder);
2015}
2016
e225f446
BS		 2017static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2018 .dpms = nv50_sor_dpms,
2019 .mode_fixup = nv50_sor_mode_fixup,
5a885f0b 2020 .prepare = nv50_sor_disconnect,
e225f446
BS		 2021 .commit = nv50_sor_commit,
2022 .mode_set = nv50_sor_mode_set,
2023 .disable = nv50_sor_disconnect,
2024 .get_crtc = nv50_display_crtc_get,
83fc083c
BS		 2025};
2026
e225f446
BS		 2027static const struct drm_encoder_funcs nv50_sor_func = {
2028 .destroy = nv50_sor_destroy,
83fc083c
BS		 2029};
2030
2031static int
e225f446 2032nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
83fc083c 2033{
5ed50209 2034 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 2035 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
83fc083c
BS		 2036 struct nouveau_encoder *nv_encoder;
2037 struct drm_encoder *encoder;
5ed50209
BS		 2038 int type;
2039
2040 switch (dcbe->type) {
2041 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2042 case DCB_OUTPUT_TMDS:
2043 case DCB_OUTPUT_DP:
2044 default:
2045 type = DRM_MODE_ENCODER_TMDS;
2046 break;
2047 }
83fc083c
BS		 2048
2049 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2050 if (!nv_encoder)
2051 return -ENOMEM;
2052 nv_encoder->dcb = dcbe;
2053 nv_encoder->or = ffs(dcbe->or) - 1;
5ed50209 2054 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
83fc083c
BS		 2055 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2056
2057 encoder = to_drm_encoder(nv_encoder);
2058 encoder->possible_crtcs = dcbe->heads;
2059 encoder->possible_clones = 0;
5ed50209 2060 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
e225f446 2061 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
83fc083c
BS		 2062
2063 drm_mode_connector_attach_encoder(connector, encoder);
2064 return 0;
2065}
26f6d88b 2066
eb6313ad
BS		 2067/******************************************************************************
2068 * PIOR
2069 *****************************************************************************/
2070
2071static void
2072nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2073{
2074 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2075 struct nv50_disp *disp = nv50_disp(encoder->dev);
67cb49c4
BS		 2076 struct {
2077 struct nv50_disp_mthd_v1 base;
2078 struct nv50_disp_pior_pwr_v0 pwr;
2079 } args = {
2080 .base.version = 1,
2081 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2082 .base.hasht = nv_encoder->dcb->hasht,
2083 .base.hashm = nv_encoder->dcb->hashm,
2084 .pwr.state = mode == DRM_MODE_DPMS_ON,
2085 .pwr.type = nv_encoder->dcb->type,
2086 };
2087
2088 nvif_mthd(disp->disp, 0, &args, sizeof(args));
eb6313ad
BS		 2089}
2090
2091static bool
2092nv50_pior_mode_fixup(struct drm_encoder *encoder,
2093 const struct drm_display_mode *mode,
2094 struct drm_display_mode *adjusted_mode)
2095{
2096 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2097 struct nouveau_connector *nv_connector;
2098
2099 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2100 if (nv_connector && nv_connector->native_mode) {
2101 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2102 int id = adjusted_mode->base.id;
2103 *adjusted_mode = *nv_connector->native_mode;
2104 adjusted_mode->base.id = id;
2105 }
2106 }
2107
2108 adjusted_mode->clock *= 2;
2109 return true;
2110}
2111
2112static void
2113nv50_pior_commit(struct drm_encoder *encoder)
2114{
2115}
2116
2117static void
2118nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2119 struct drm_display_mode *adjusted_mode)
2120{
2121 struct nv50_mast *mast = nv50_mast(encoder->dev);
2122 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2123 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2124 struct nouveau_connector *nv_connector;
2125 u8 owner = 1 << nv_crtc->index;
2126 u8 proto, depth;
2127 u32 *push;
2128
2129 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2130 switch (nv_connector->base.display_info.bpc) {
2131 case 10: depth = 0x6; break;
2132 case 8: depth = 0x5; break;
2133 case 6: depth = 0x2; break;
2134 default: depth = 0x0; break;
2135 }
2136
2137 switch (nv_encoder->dcb->type) {
2138 case DCB_OUTPUT_TMDS:
2139 case DCB_OUTPUT_DP:
2140 proto = 0x0;
2141 break;
2142 default:
2143 BUG_ON(1);
2144 break;
2145 }
2146
2147 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2148
2149 push = evo_wait(mast, 8);
2150 if (push) {
648d4dfd 2151 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
eb6313ad
BS		 2152 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2153 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2154 ctrl |= 0x00001000;
2155 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2156 ctrl |= 0x00002000;
2157 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2158 evo_data(push, ctrl);
2159 }
2160
2161 evo_kick(push, mast);
2162 }
2163
2164 nv_encoder->crtc = encoder->crtc;
2165}
2166
2167static void
2168nv50_pior_disconnect(struct drm_encoder *encoder)
2169{
2170 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2171 struct nv50_mast *mast = nv50_mast(encoder->dev);
2172 const int or = nv_encoder->or;
2173 u32 *push;
2174
2175 if (nv_encoder->crtc) {
2176 nv50_crtc_prepare(nv_encoder->crtc);
2177
2178 push = evo_wait(mast, 4);
2179 if (push) {
648d4dfd 2180 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
eb6313ad
BS		 2181 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2182 evo_data(push, 0x00000000);
2183 }
eb6313ad
BS		 2184 evo_kick(push, mast);
2185 }
2186 }
2187
2188 nv_encoder->crtc = NULL;
2189}
2190
2191static void
2192nv50_pior_destroy(struct drm_encoder *encoder)
2193{
2194 drm_encoder_cleanup(encoder);
2195 kfree(encoder);
2196}
2197
2198static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2199 .dpms = nv50_pior_dpms,
2200 .mode_fixup = nv50_pior_mode_fixup,
2201 .prepare = nv50_pior_disconnect,
2202 .commit = nv50_pior_commit,
2203 .mode_set = nv50_pior_mode_set,
2204 .disable = nv50_pior_disconnect,
2205 .get_crtc = nv50_display_crtc_get,
2206};
2207
2208static const struct drm_encoder_funcs nv50_pior_func = {
2209 .destroy = nv50_pior_destroy,
2210};
2211
2212static int
2213nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2214{
2215 struct nouveau_drm *drm = nouveau_drm(connector->dev);
967e7bde 2216 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
eb6313ad
BS		 2217 struct nouveau_i2c_port *ddc = NULL;
2218 struct nouveau_encoder *nv_encoder;
2219 struct drm_encoder *encoder;
2220 int type;
2221
2222 switch (dcbe->type) {
2223 case DCB_OUTPUT_TMDS:
2224 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2225 type = DRM_MODE_ENCODER_TMDS;
2226 break;
2227 case DCB_OUTPUT_DP:
2228 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2229 type = DRM_MODE_ENCODER_TMDS;
2230 break;
2231 default:
2232 return -ENODEV;
2233 }
2234
2235 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2236 if (!nv_encoder)
2237 return -ENOMEM;
2238 nv_encoder->dcb = dcbe;
2239 nv_encoder->or = ffs(dcbe->or) - 1;
2240 nv_encoder->i2c = ddc;
2241
2242 encoder = to_drm_encoder(nv_encoder);
2243 encoder->possible_crtcs = dcbe->heads;
2244 encoder->possible_clones = 0;
2245 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2246 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2247
2248 drm_mode_connector_attach_encoder(connector, encoder);
2249 return 0;
2250}
2251
ab0af559
BS		 2252/******************************************************************************
2253 * Framebuffer
2254 *****************************************************************************/
2255
8a423647 2256static void
0ad72863 2257nv50_fbdma_fini(struct nv50_fbdma *fbdma)
8a423647 2258{
0ad72863
BS		 2259 int i;
2260 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2261 nvif_object_fini(&fbdma->base[i]);
2262 nvif_object_fini(&fbdma->core);
8a423647
BS		 2263 list_del(&fbdma->head);
2264 kfree(fbdma);
2265}
2266
2267static int
2268nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2269{
2270 struct nouveau_drm *drm = nouveau_drm(dev);
2271 struct nv50_disp *disp = nv50_disp(dev);
2272 struct nv50_mast *mast = nv50_mast(dev);
4acfd707
BS		 2273 struct __attribute__ ((packed)) {
2274 struct nv_dma_v0 base;
2275 union {
2276 struct nv50_dma_v0 nv50;
2277 struct gf100_dma_v0 gf100;
2278 struct gf110_dma_v0 gf110;
2279 };
2280 } args = {};
8a423647
BS		 2281 struct nv50_fbdma *fbdma;
2282 struct drm_crtc *crtc;
4acfd707 2283 u32 size = sizeof(args.base);
8a423647
BS		 2284 int ret;
2285
2286 list_for_each_entry(fbdma, &disp->fbdma, head) {
0ad72863 2287 if (fbdma->core.handle == name)
8a423647
BS		 2288 return 0;
2289 }
2290
2291 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2292 if (!fbdma)
2293 return -ENOMEM;
2294 list_add(&fbdma->head, &disp->fbdma);
8a423647 2295
4acfd707
BS		 2296 args.base.target = NV_DMA_V0_TARGET_VRAM;
2297 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2298 args.base.start = offset;
2299 args.base.limit = offset + length - 1;
8a423647 2300
967e7bde 2301 if (drm->device.info.chipset < 0x80) {
4acfd707
BS		 2302 args.nv50.part = NV50_DMA_V0_PART_256;
2303 size += sizeof(args.nv50);
8a423647 2304 } else
967e7bde 2305 if (drm->device.info.chipset < 0xc0) {
4acfd707
BS		 2306 args.nv50.part = NV50_DMA_V0_PART_256;
2307 args.nv50.kind = kind;
2308 size += sizeof(args.nv50);
8a423647 2309 } else
967e7bde 2310 if (drm->device.info.chipset < 0xd0) {
4acfd707
BS		 2311 args.gf100.kind = kind;
2312 size += sizeof(args.gf100);
8a423647 2313 } else {
4acfd707
BS		 2314 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2315 args.gf110.kind = kind;
2316 size += sizeof(args.gf110);
8a423647
BS		 2317 }
2318
2319 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
0ad72863
BS		 2320 struct nv50_head *head = nv50_head(crtc);
2321 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
4acfd707 2322 name, NV_DMA_IN_MEMORY, &args, size,
0ad72863 2323 &fbdma->base[head->base.index]);
8a423647 2324 if (ret) {
0ad72863 2325 nv50_fbdma_fini(fbdma);
8a423647
BS		 2326 return ret;
2327 }
2328 }
2329
0ad72863 2330 ret = nvif_object_init(&mast->base.base.user, NULL, name,
4acfd707 2331 NV_DMA_IN_MEMORY, &args, size,
0ad72863 2332 &fbdma->core);
8a423647 2333 if (ret) {
0ad72863 2334 nv50_fbdma_fini(fbdma);
8a423647
BS		 2335 return ret;
2336 }
2337
2338 return 0;
2339}
2340
ab0af559
BS		 2341static void
2342nv50_fb_dtor(struct drm_framebuffer *fb)
2343{
2344}
2345
2346static int
2347nv50_fb_ctor(struct drm_framebuffer *fb)
2348{
2349 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2350 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2351 struct nouveau_bo *nvbo = nv_fb->nvbo;
8a423647 2352 struct nv50_disp *disp = nv50_disp(fb->dev);
8a423647
BS		 2353 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2354 u8 tile = nvbo->tile_mode;
ab0af559
BS		 2355
2356 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
2357 NV_ERROR(drm, "framebuffer requires contiguous bo\n");
2358 return -EINVAL;
2359 }
2360
967e7bde 2361 if (drm->device.info.chipset >= 0xc0)
8a423647
BS		 2362 tile >>= 4; /* yep.. */
2363
ab0af559
BS		 2364 switch (fb->depth) {
2365 case 8: nv_fb->r_format = 0x1e00; break;
2366 case 15: nv_fb->r_format = 0xe900; break;
2367 case 16: nv_fb->r_format = 0xe800; break;
2368 case 24:
2369 case 32: nv_fb->r_format = 0xcf00; break;
2370 case 30: nv_fb->r_format = 0xd100; break;
2371 default:
2372 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2373 return -EINVAL;
2374 }
2375
648d4dfd 2376 if (disp->disp->oclass < G82_DISP) {
8a423647
BS		 2377 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2378 (fb->pitches[0] | 0x00100000);
2379 nv_fb->r_format |= kind << 16;
2380 } else
648d4dfd 2381 if (disp->disp->oclass < GF110_DISP) {
8a423647
BS		 2382 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2383 (fb->pitches[0] | 0x00100000);
ab0af559 2384 } else {
8a423647
BS		 2385 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2386 (fb->pitches[0] | 0x01000000);
ab0af559 2387 }
8a423647 2388 nv_fb->r_handle = 0xffff0000 | kind;
ab0af559 2389
f392ec4b
BS		 2390 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2391 drm->device.info.ram_user, kind);
ab0af559
BS		 2392}
2393
26f6d88b
BS		 2394/******************************************************************************
2395 * Init
2396 *****************************************************************************/
ab0af559 2397
2a44e499 2398void
e225f446 2399nv50_display_fini(struct drm_device *dev)
26f6d88b 2400{
26f6d88b
BS		 2401}
2402
2403int
e225f446 2404nv50_display_init(struct drm_device *dev)
26f6d88b 2405{
9f9bdaaf
BS		 2406 struct nv50_disp *disp = nv50_disp(dev);
2407 struct drm_crtc *crtc;
2408 u32 *push;
2409
2410 push = evo_wait(nv50_mast(dev), 32);
2411 if (!push)
2412 return -EBUSY;
2413
2414 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2415 struct nv50_sync *sync = nv50_sync(crtc);
2416 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
bdb8c212 2417 }
efd272a7 2418
9f9bdaaf 2419 evo_mthd(push, 0x0088, 1);
f45f55c4 2420 evo_data(push, nv50_mast(dev)->base.sync.handle);
9f9bdaaf
BS		 2421 evo_kick(push, nv50_mast(dev));
2422 return 0;
26f6d88b
BS		 2423}
2424
2425void
e225f446 2426nv50_display_destroy(struct drm_device *dev)
26f6d88b 2427{
e225f446 2428 struct nv50_disp *disp = nv50_disp(dev);
8a423647
BS		 2429 struct nv50_fbdma *fbdma, *fbtmp;
2430
2431 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
0ad72863 2432 nv50_fbdma_fini(fbdma);
8a423647 2433 }
bdb8c212 2434
0ad72863 2435 nv50_dmac_destroy(&disp->mast.base, disp->disp);
26f6d88b 2436
816af2f2 2437 nouveau_bo_unmap(disp->sync);
04c8c210
MS		 2438 if (disp->sync)
2439 nouveau_bo_unpin(disp->sync);
816af2f2 2440 nouveau_bo_ref(NULL, &disp->sync);
51beb428 2441
77145f1c 2442 nouveau_display(dev)->priv = NULL;
26f6d88b
BS		 2443 kfree(disp);
2444}
2445
2446int
e225f446 2447nv50_display_create(struct drm_device *dev)
26f6d88b 2448{
967e7bde 2449 struct nvif_device *device = &nouveau_drm(dev)->device;
77145f1c 2450 struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c 2451 struct dcb_table *dcb = &drm->vbios.dcb;
83fc083c 2452 struct drm_connector *connector, *tmp;
e225f446 2453 struct nv50_disp *disp;
cb75d97e 2454 struct dcb_output *dcbe;
7c5f6a87 2455 int crtcs, ret, i;
26f6d88b
BS		 2456
2457 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2458 if (!disp)
2459 return -ENOMEM;
8a423647 2460 INIT_LIST_HEAD(&disp->fbdma);
77145f1c
BS		 2461
2462 nouveau_display(dev)->priv = disp;
e225f446
BS		 2463 nouveau_display(dev)->dtor = nv50_display_destroy;
2464 nouveau_display(dev)->init = nv50_display_init;
2465 nouveau_display(dev)->fini = nv50_display_fini;
ab0af559
BS		 2466 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2467 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
0ad72863 2468 disp->disp = &nouveau_display(dev)->disp;
26f6d88b 2469
b5a794b0
BS		 2470 /* small shared memory area we use for notifiers and semaphores */
2471 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
bb6178b0 2472 0, 0x0000, NULL, NULL, &disp->sync);
b5a794b0
BS		 2473 if (!ret) {
2474 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
04c8c210 2475 if (!ret) {
b5a794b0 2476 ret = nouveau_bo_map(disp->sync);
04c8c210
MS		 2477 if (ret)
2478 nouveau_bo_unpin(disp->sync);
2479 }
b5a794b0
BS		 2480 if (ret)
2481 nouveau_bo_ref(NULL, &disp->sync);
2482 }
2483
b5a794b0
BS		 2484 if (ret)
2485 goto out;
2486
2487 /* allocate master evo channel */
410f3ec6
BS		 2488 ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2489 &disp->mast);
b5a794b0
BS		 2490 if (ret)
2491 goto out;
2492
438d99e3 2493 /* create crtc objects to represent the hw heads */
648d4dfd 2494 if (disp->disp->oclass >= GF110_DISP)
db2bec18 2495 crtcs = nvif_rd32(device, 0x022448);
63718a07
BS		 2496 else
2497 crtcs = 2;
2498
7c5f6a87 2499 for (i = 0; i < crtcs; i++) {
0ad72863 2500 ret = nv50_crtc_create(dev, i);
438d99e3
BS		 2501 if (ret)
2502 goto out;
2503 }
2504
83fc083c
BS		 2505 /* create encoder/connector objects based on VBIOS DCB table */
2506 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2507 connector = nouveau_connector_create(dev, dcbe->connector);
2508 if (IS_ERR(connector))
2509 continue;
2510
eb6313ad
BS		 2511 if (dcbe->location == DCB_LOC_ON_CHIP) {
2512 switch (dcbe->type) {
2513 case DCB_OUTPUT_TMDS:
2514 case DCB_OUTPUT_LVDS:
2515 case DCB_OUTPUT_DP:
2516 ret = nv50_sor_create(connector, dcbe);
2517 break;
2518 case DCB_OUTPUT_ANALOG:
2519 ret = nv50_dac_create(connector, dcbe);
2520 break;
2521 default:
2522 ret = -ENODEV;
2523 break;
2524 }
2525 } else {
2526 ret = nv50_pior_create(connector, dcbe);
83fc083c
BS		 2527 }
2528
eb6313ad
BS		 2529 if (ret) {
2530 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2531 dcbe->location, dcbe->type,
2532 ffs(dcbe->or) - 1, ret);
94f54f53 2533 ret = 0;
83fc083c
BS		 2534 }
2535 }
2536
2537 /* cull any connectors we created that don't have an encoder */
2538 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2539 if (connector->encoder_ids[0])
2540 continue;
2541
77145f1c 2542 NV_WARN(drm, "%s has no encoders, removing\n",
8c6c361a 2543 connector->name);
83fc083c
BS		 2544 connector->funcs->destroy(connector);
2545 }
2546
26f6d88b
BS		 2547out:
2548 if (ret)
e225f446 2549 nv50_display_destroy(dev);
26f6d88b
BS		 2550 return ret;
2551}
Linux kernel - Deliverables
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