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1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
26 | #include "nouveau_drv.h" | |
27 | #include "nouveau_mm.h" | |
28 | ||
29 | static int types[0x80] = { | |
30 | 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
31 | 1, 1, 1, 1, 0, 0, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0, | |
32 | 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 2, 2, 2, 2, 2, 0, | |
33 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
34 | 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 0, 0, | |
35 | 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
36 | 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 2, 2, 2, 2, | |
37 | 1, 0, 2, 0, 1, 0, 2, 0, 1, 1, 2, 2, 1, 1, 0, 0 | |
38 | }; | |
39 | ||
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40 | bool |
41 | nv50_vram_flags_valid(struct drm_device *dev, u32 tile_flags) | |
42 | { | |
43 | int type = (tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) >> 8; | |
44 | ||
d095e232 | 45 | if (likely(type < ARRAY_SIZE(types) && types[type])) |
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46 | return true; |
47 | return false; | |
48 | } | |
49 | ||
573a2a37 | 50 | void |
d5f42394 | 51 | nv50_vram_del(struct drm_device *dev, struct nouveau_mem **pmem) |
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52 | { |
53 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
54 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
55 | struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM]; | |
56 | struct nouveau_mm *mm = man->priv; | |
57 | struct nouveau_mm_node *this; | |
d5f42394 | 58 | struct nouveau_mem *mem; |
573a2a37 | 59 | |
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60 | mem = *pmem; |
61 | *pmem = NULL; | |
62 | if (unlikely(mem == NULL)) | |
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63 | return; |
64 | ||
65 | mutex_lock(&mm->mutex); | |
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66 | while (!list_empty(&mem->regions)) { |
67 | this = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); | |
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68 | |
69 | list_del(&this->rl_entry); | |
70 | nouveau_mm_put(mm, this); | |
71 | } | |
72 | mutex_unlock(&mm->mutex); | |
73 | ||
d5f42394 | 74 | kfree(mem); |
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75 | } |
76 | ||
77 | int | |
78 | nv50_vram_new(struct drm_device *dev, u64 size, u32 align, u32 size_nc, | |
d5f42394 | 79 | u32 type, struct nouveau_mem **pmem) |
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80 | { |
81 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
82 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
83 | struct ttm_mem_type_manager *man = &bdev->man[TTM_PL_VRAM]; | |
84 | struct nouveau_mm *mm = man->priv; | |
85 | struct nouveau_mm_node *r; | |
d5f42394 | 86 | struct nouveau_mem *mem; |
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87 | int ret; |
88 | ||
89 | if (!types[type]) | |
90 | return -EINVAL; | |
91 | size >>= 12; | |
92 | align >>= 12; | |
93 | size_nc >>= 12; | |
94 | ||
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95 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
96 | if (!mem) | |
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97 | return -ENOMEM; |
98 | ||
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99 | INIT_LIST_HEAD(&mem->regions); |
100 | mem->dev = dev_priv->dev; | |
101 | mem->memtype = type; | |
102 | mem->size = size; | |
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103 | |
104 | mutex_lock(&mm->mutex); | |
105 | do { | |
106 | ret = nouveau_mm_get(mm, types[type], size, size_nc, align, &r); | |
107 | if (ret) { | |
108 | mutex_unlock(&mm->mutex); | |
d5f42394 | 109 | nv50_vram_del(dev, &mem); |
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110 | return ret; |
111 | } | |
112 | ||
d5f42394 | 113 | list_add_tail(&r->rl_entry, &mem->regions); |
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114 | size -= r->length; |
115 | } while (size); | |
116 | mutex_unlock(&mm->mutex); | |
117 | ||
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118 | r = list_first_entry(&mem->regions, struct nouveau_mm_node, rl_entry); |
119 | mem->offset = (u64)r->offset << 12; | |
120 | *pmem = mem; | |
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121 | return 0; |
122 | } | |
123 | ||
124 | static u32 | |
125 | nv50_vram_rblock(struct drm_device *dev) | |
126 | { | |
127 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
128 | int i, parts, colbits, rowbitsa, rowbitsb, banks; | |
129 | u64 rowsize, predicted; | |
130 | u32 r0, r4, rt, ru, rblock_size; | |
131 | ||
132 | r0 = nv_rd32(dev, 0x100200); | |
133 | r4 = nv_rd32(dev, 0x100204); | |
134 | rt = nv_rd32(dev, 0x100250); | |
135 | ru = nv_rd32(dev, 0x001540); | |
136 | NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru); | |
137 | ||
138 | for (i = 0, parts = 0; i < 8; i++) { | |
139 | if (ru & (0x00010000 << i)) | |
140 | parts++; | |
141 | } | |
142 | ||
143 | colbits = (r4 & 0x0000f000) >> 12; | |
144 | rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; | |
145 | rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; | |
146 | banks = ((r4 & 0x01000000) ? 8 : 4); | |
147 | ||
148 | rowsize = parts * banks * (1 << colbits) * 8; | |
149 | predicted = rowsize << rowbitsa; | |
150 | if (r0 & 0x00000004) | |
151 | predicted += rowsize << rowbitsb; | |
152 | ||
153 | if (predicted != dev_priv->vram_size) { | |
154 | NV_WARN(dev, "memory controller reports %dMiB VRAM\n", | |
155 | (u32)(dev_priv->vram_size >> 20)); | |
156 | NV_WARN(dev, "we calculated %dMiB VRAM\n", | |
157 | (u32)(predicted >> 20)); | |
158 | } | |
159 | ||
160 | rblock_size = rowsize; | |
161 | if (rt & 1) | |
162 | rblock_size *= 3; | |
163 | ||
164 | NV_DEBUG(dev, "rblock %d bytes\n", rblock_size); | |
165 | return rblock_size; | |
166 | } | |
167 | ||
168 | int | |
169 | nv50_vram_init(struct drm_device *dev) | |
170 | { | |
171 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
172 | ||
173 | dev_priv->vram_size = nv_rd32(dev, 0x10020c); | |
174 | dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; | |
175 | dev_priv->vram_size &= 0xffffffff00ULL; | |
176 | ||
177 | switch (dev_priv->chipset) { | |
178 | case 0xaa: | |
179 | case 0xac: | |
180 | case 0xaf: | |
181 | dev_priv->vram_sys_base = (u64)nv_rd32(dev, 0x100e10) << 12; | |
182 | dev_priv->vram_rblock_size = 4096; | |
183 | break; | |
184 | default: | |
185 | dev_priv->vram_rblock_size = nv50_vram_rblock(dev); | |
186 | break; | |
187 | } | |
188 | ||
189 | return 0; | |
190 | } |