[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvc0_vm.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>

#include "nouveau_drv.h"
#include "nouveau_vm.h"

void
nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
		struct nouveau_gpuobj *pgt[2])
{
	u32 pde[2] = { 0, 0 };

	if (pgt[0])
		pde[1] = 0x00000001 | (pgt[0]->vinst >> 8);
	if (pgt[1])
		pde[0] = 0x00000001 | (pgt[1]->vinst >> 8);

	nv_wo32(pgd, (index * 8) + 0, pde[0]);
	nv_wo32(pgd, (index * 8) + 4, pde[1]);
}

static inline u64
nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
{
	phys >>= 8;

	phys |= 0x00000001; /* present */
	if (vma->access & NV_MEM_ACCESS_SYS)
		phys |= 0x00000002;

	phys |= ((u64)target  << 32);
	phys |= ((u64)memtype << 36);

	return phys;
}

void
nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	    struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
	u32 next = 1 << (vma->node->type - 8);

	phys  = nvc0_vm_addr(vma, phys, mem->memtype, 0);
	pte <<= 3;
	while (cnt--) {
		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
		phys += next;
		pte  += 8;
	}
}

void
nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;

	pte <<= 3;
	while (cnt--) {
		u64 phys = nvc0_vm_addr(vma, *list++, mem->memtype, target);
		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
		pte += 8;
	}
}

void
nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
{
	pte <<= 3;
	while (cnt--) {
		nv_wo32(pgt, pte + 0, 0x00000000);
		nv_wo32(pgt, pte + 4, 0x00000000);
		pte += 8;
	}
}

void
nvc0_vm_flush(struct nouveau_vm *vm)
{
	struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct drm_device *dev = vm->dev;
	struct nouveau_vm_pgd *vpgd;
	unsigned long flags;
	u32 engine;

	engine = 1;
	if (vm == dev_priv->bar1_vm || vm == dev_priv->bar3_vm)
		engine |= 4;

	pinstmem->flush(vm->dev);

	spin_lock_irqsave(&dev_priv->vm_lock, flags);
	list_for_each_entry(vpgd, &vm->pgd_list, head) {
		/* looks like maybe a "free flush slots" counter, the
		 * faster you write to 0x100cbc to more it decreases
		 */
		if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
			NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
				 nv_rd32(dev, 0x100c80), engine);
		}
		nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
		nv_wr32(dev, 0x100cbc, 0x80000000 | engine);
		/* wait for flush to be queued? */
		if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
			NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
				 nv_rd32(dev, 0x100c80), engine);
		}
	}
	spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
}
Commit	Line	Data
4c74eb7f BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
4c74eb7f BS	26
	27	#include "nouveau_drv.h"
	28	#include "nouveau_vm.h"
	29
	30	void
	31	nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index,
	32	struct nouveau_gpuobj *pgt[2])
	33	{
	34	u32 pde[2] = { 0, 0 };
	35
	36	if (pgt[0])
	37	pde[1] = 0x00000001 \| (pgt[0]->vinst >> 8);
	38	if (pgt[1])
	39	pde[0] = 0x00000001 \| (pgt[1]->vinst >> 8);
	40
	41	nv_wo32(pgd, (index * 8) + 0, pde[0]);
	42	nv_wo32(pgd, (index * 8) + 4, pde[1]);
	43	}
	44
	45	static inline u64
	46	nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
	47	{
	48	phys >>= 8;
	49
	50	phys \|= 0x00000001; /* present */
c906ca0f BS	51	if (vma->access & NV_MEM_ACCESS_SYS)
c906ca0f BS	52	phys \|= 0x00000002;
4c74eb7f BS	53
	54	phys \|= ((u64)target << 32);
	55	phys \|= ((u64)memtype << 36);
	56
	57	return phys;
	58	}
	59
	60	void
	61	nvc0_vm_map(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
8f7286f8	62	struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
4c74eb7f BS	63	{
	64	u32 next = 1 << (vma->node->type - 8);
	65
	66	phys = nvc0_vm_addr(vma, phys, mem->memtype, 0);
	67	pte <<= 3;
	68	while (cnt--) {
	69	nv_wo32(pgt, pte + 0, lower_32_bits(phys));
	70	nv_wo32(pgt, pte + 4, upper_32_bits(phys));
	71	phys += next;
	72	pte += 8;
	73	}
	74	}
	75
	76	void
	77	nvc0_vm_map_sg(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
26c0c9e3	78	struct nouveau_mem mem, u32 pte, u32 cnt, dma_addr_t list)
4c74eb7f	79	{
990449c7 BS	80	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;
990449c7 BS	81
4c74eb7f BS	82	pte <<= 3;
4c74eb7f BS	83	while (cnt--) {
990449c7	84	u64 phys = nvc0_vm_addr(vma, *list++, mem->memtype, target);
4c74eb7f BS	85	nv_wo32(pgt, pte + 0, lower_32_bits(phys));
	86	nv_wo32(pgt, pte + 4, upper_32_bits(phys));
	87	pte += 8;
	88	}
	89	}
	90
	91	void
	92	nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
	93	{
	94	pte <<= 3;
	95	while (cnt--) {
	96	nv_wo32(pgt, pte + 0, 0x00000000);
	97	nv_wo32(pgt, pte + 4, 0x00000000);
	98	pte += 8;
	99	}
	100	}
	101
	102	void
	103	nvc0_vm_flush(struct nouveau_vm *vm)
	104	{
	105	struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
	106	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	107	struct drm_device *dev = vm->dev;
	108	struct nouveau_vm_pgd *vpgd;
04eb34a4	109	unsigned long flags;
b79181cb BS	110	u32 engine;
	111
	112	engine = 1;
	113	if (vm == dev_priv->bar1_vm \|\| vm == dev_priv->bar3_vm)
	114	engine \|= 4;
4c74eb7f BS	115
	116	pinstmem->flush(vm->dev);
	117
04eb34a4	118	spin_lock_irqsave(&dev_priv->vm_lock, flags);
4c74eb7f	119	list_for_each_entry(vpgd, &vm->pgd_list, head) {
a719726f BS	120	/* looks like maybe a "free flush slots" counter, the
	121	* faster you write to 0x100cbc to more it decreases
	122	*/
	123	if (!nv_wait_ne(dev, 0x100c80, 0x00ff0000, 0x00000000)) {
	124	NV_ERROR(dev, "vm timeout 0: 0x%08x %d\n",
	125	nv_rd32(dev, 0x100c80), engine);
	126	}
4c74eb7f BS	127	nv_wr32(dev, 0x100cb8, vpgd->obj->vinst >> 8);
4c74eb7f BS	128	nv_wr32(dev, 0x100cbc, 0x80000000 \| engine);
a719726f BS	129	/* wait for flush to be queued? */
	130	if (!nv_wait(dev, 0x100c80, 0x00008000, 0x00008000)) {
	131	NV_ERROR(dev, "vm timeout 1: 0x%08x %d\n",
	132	nv_rd32(dev, 0x100c80), engine);
	133	}
4c74eb7f	134	}
04eb34a4	135	spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
4c74eb7f	136	}