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drm/nouveau/devinit: namespace + nvidia gpu names (no binary change)
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / engine / device / nvc0.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
70c0f263 25#include <subdev/bios.h>
a10220bb 26#include <subdev/bus.h>
e0996aea 27#include <subdev/gpio.h>
4196faa8 28#include <subdev/i2c.h>
3ca6cd43 29#include <subdev/fuse.h>
f3867f43 30#include <subdev/clk.h>
aa1b9b48 31#include <subdev/therm.h>
d38ac521 32#include <subdev/mxm.h>
cb75d97e 33#include <subdev/devinit.h>
7d9115de 34#include <subdev/mc.h>
5a5c7432 35#include <subdev/timer.h>
861d2107 36#include <subdev/fb.h>
95484b57 37#include <subdev/ltc.h>
c0abf5c9 38#include <subdev/ibus.h>
3863c9bc 39#include <subdev/instmem.h>
5ce3bf3c 40#include <subdev/mmu.h>
3863c9bc 41#include <subdev/bar.h>
ebb58dc2 42#include <subdev/pmu.h>
c9c0ccae 43#include <subdev/volt.h>
9274f4a9 44
dded35de 45#include <engine/device.h>
ebb945a9
BS		 46#include <engine/dmaobj.h>
47#include <engine/fifo.h>
8700287b 48#include <engine/sw.h>
b8bf04e1 49#include <engine/gr.h>
37a5d028 50#include <engine/mspdec.h>
ebb945a9 51#include <engine/bsp.h>
eccf7e8a 52#include <engine/msvld.h>
fd8666f7 53#include <engine/msppp.h>
aedf24ff 54#include <engine/ce.h>
ebb945a9 55#include <engine/disp.h>
d5752b9b 56#include <engine/pm.h>
ebb945a9 57
9274f4a9
BS		 58int
59nvc0_identify(struct nouveau_device *device)
60{
61 switch (device->chipset) {
62 case 0xc0:
2094dd82 63 device->cname = "GF100";
70c0f263 64 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 65 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 66 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 67 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 68 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 69 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 70 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 71 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
08f6fbdb 72 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
5f8824de 73 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 74 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 75 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 76 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 77 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 78 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 79 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 80 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 81 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 82 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 83 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 84 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 85 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 86 device->oclass[NVDEV_ENGINE_GR ] = nvc0_gr_oclass;
37a5d028 87 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 88 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 89 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff
BS		 90 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
91 device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
a8f8b489 92 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 93 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 94 break;
95 case 0xc4:
2094dd82 96 device->cname = "GF104";
70c0f263 97 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 98 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 99 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 100 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 101 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 102 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 103 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 104 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
08f6fbdb 105 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
5f8824de 106 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 107 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 108 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 109 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 110 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 111 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 112 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 113 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 114 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 115 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 116 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 117 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 118 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 119 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
37a5d028 120 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 121 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 122 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff
BS		 123 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
124 device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
a8f8b489 125 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 126 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 127 break;
128 case 0xc3:
2094dd82 129 device->cname = "GF106";
70c0f263 130 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 131 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 132 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 133 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 134 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 135 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 136 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 137 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
1b4fea0f 138 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
5f8824de 139 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 140 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 141 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 142 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 143 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 144 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 145 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 146 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 147 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 148 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 149 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 150 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 151 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 152 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
37a5d028 153 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 154 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 155 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff 156 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
a8f8b489 157 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 158 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 159 break;
160 case 0xce:
2094dd82 161 device->cname = "GF114";
70c0f263 162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 163 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 164 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 165 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 166 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 167 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 168 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 169 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
6e9cbb40 170 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
5f8824de 171 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 172 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 173 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 174 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 175 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 176 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 177 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 178 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 179 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 180 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 181 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 182 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 183 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 184 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
37a5d028 185 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 186 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 187 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff
BS		 188 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
189 device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
a8f8b489 190 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 191 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 192 break;
193 case 0xcf:
2094dd82 194 device->cname = "GF116";
70c0f263 195 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 196 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 197 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 198 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 199 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 200 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 201 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 202 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
1b4fea0f 203 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
5f8824de 204 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 205 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 206 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 207 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 208 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 209 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 210 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 211 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 212 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 213 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 214 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 215 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 216 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 217 device->oclass[NVDEV_ENGINE_GR ] = nvc4_gr_oclass;
37a5d028 218 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 219 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 220 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff 221 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
a8f8b489 222 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 223 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 224 break;
225 case 0xc1:
2094dd82 226 device->cname = "GF108";
70c0f263 227 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 228 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 229 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 230 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 231 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 232 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 233 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 234 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
1b4fea0f 235 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
5f8824de 236 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 237 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 238 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 239 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 240 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 241 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 242 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 243 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 244 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 245 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 246 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 247 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 248 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 249 device->oclass[NVDEV_ENGINE_GR ] = nvc1_gr_oclass;
37a5d028 250 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 251 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 252 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff 253 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
a8f8b489 254 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 255 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 256 break;
257 case 0xc8:
2094dd82 258 device->cname = "GF110";
70c0f263 259 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
b485a700 260 device->oclass[NVDEV_SUBDEV_GPIO ] = nv94_gpio_oclass;
c26fe843 261 device->oclass[NVDEV_SUBDEV_I2C ] = nv94_i2c_oclass;
3ca6cd43 262 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 263 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
7b49bd68 264 device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
d38ac521 265 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 266 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
0bae1d61 267 device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
5f8824de 268 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 269 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 270 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 271 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 272 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 273 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 274 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 275 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 276 device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass;
c9c0ccae 277 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 278 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvc0_dmaeng_oclass;
16c4f227 279 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 280 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 281 device->oclass[NVDEV_ENGINE_GR ] = nvc8_gr_oclass;
37a5d028 282 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 283 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 284 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff
BS		 285 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
286 device->oclass[NVDEV_ENGINE_CE1 ] = &nvc0_ce1_oclass;
a8f8b489 287 device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
d5752b9b 288 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 289 break;
290 case 0xd9:
2094dd82 291 device->cname = "GF119";
70c0f263 292 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 293 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
c26fe843 294 device->oclass[NVDEV_SUBDEV_I2C ] = nvd0_i2c_oclass;
3ca6cd43 295 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 296 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
bc79202f 297 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
d38ac521 298 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 299 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
1b4fea0f 300 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
5f8824de 301 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
5a5c7432 302 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 303 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 304 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
3f196a04 305 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 306 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 307 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 308 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
ebb58dc2 309 device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass;
c9c0ccae 310 device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
bc98540b 311 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
16c4f227 312 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 313 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 314 device->oclass[NVDEV_ENGINE_GR ] = nvd9_gr_oclass;
37a5d028 315 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 316 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 317 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff 318 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
a8f8b489 319 device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
d5752b9b 320 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
3f196a04
BS		 321 break;
322 case 0xd7:
323 device->cname = "GF117";
324 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
d93174ec 325 device->oclass[NVDEV_SUBDEV_GPIO ] = nvd0_gpio_oclass;
82c2b5ed 326 device->oclass[NVDEV_SUBDEV_I2C ] = gf117_i2c_oclass;
3ca6cd43 327 device->oclass[NVDEV_SUBDEV_FUSE ] = &gf100_fuse_oclass;
7632b30e 328 device->oclass[NVDEV_SUBDEV_CLK ] = &gf100_clk_oclass;
3f196a04
BS		 329 device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
330 device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
a8c4362b 331 device->oclass[NVDEV_SUBDEV_DEVINIT] = gf100_devinit_oclass;
1b4fea0f 332 device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
5f8824de 333 device->oclass[NVDEV_SUBDEV_BUS ] = gf100_bus_oclass;
3f196a04 334 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
1e9fc30e 335 device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
95484b57 336 device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass;
c0abf5c9 337 device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
24a4ae86 338 device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass;
5ce3bf3c 339 device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass;
245dcfe9 340 device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass;
bc98540b 341 device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass;
16c4f227 342 device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
8700287b 343 device->oclass[NVDEV_ENGINE_SW ] = nvc0_sw_oclass;
b8bf04e1 344 device->oclass[NVDEV_ENGINE_GR ] = nvd7_gr_oclass;
37a5d028 345 device->oclass[NVDEV_ENGINE_MSPDEC ] = &nvc0_mspdec_oclass;
eccf7e8a 346 device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
fd8666f7 347 device->oclass[NVDEV_ENGINE_MSPPP ] = &nvc0_msppp_oclass;
aedf24ff 348 device->oclass[NVDEV_ENGINE_CE0 ] = &nvc0_ce0_oclass;
a8f8b489 349 device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
d5752b9b 350 device->oclass[NVDEV_ENGINE_PM ] = &nvc0_pm_oclass;
9274f4a9
BS		 351 break;
352 default:
353 nv_fatal(device, "unknown Fermi chipset\n");
354 return -EINVAL;
355 }
356
357 return 0;
7b49bd68 358 }
Linux kernel - Deliverables
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