[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clock / nv04.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/clock.h>
#include <subdev/devinit/nv04.h>

#include "pll.h"

struct nv04_clock_priv {
	struct nouveau_clock base;
};

int
nv04_clock_pll_calc(struct nouveau_clock *clock, struct nvbios_pll *info,
		    int clk, struct nouveau_pll_vals *pv)
{
	int N1, M1, N2, M2, P;
	int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
	if (ret) {
		pv->refclk = info->refclk;
		pv->N1 = N1;
		pv->M1 = M1;
		pv->N2 = N2;
		pv->M2 = M2;
		pv->log2P = P;
	}
	return ret;
}

int
nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
		    struct nouveau_pll_vals *pv)
{
	struct nouveau_devinit *devinit = nouveau_devinit(clk);
	int cv = nouveau_bios(clk)->version.chip;

	if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
	    cv >= 0x40) {
		if (reg1 > 0x405c)
			setPLL_double_highregs(devinit, reg1, pv);
		else
			setPLL_double_lowregs(devinit, reg1, pv);
	} else
		setPLL_single(devinit, reg1, pv);

	return 0;
}

static struct nouveau_clocks
nv04_domain[] = {
	{ nv_clk_src_max }
};

static int
nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nv04_clock_priv *priv;
	int ret;

	ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0,
				   false, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.pll_calc = nv04_clock_pll_calc;
	priv->base.pll_prog = nv04_clock_pll_prog;
	return 0;
}

struct nouveau_oclass
nv04_clock_oclass = {
	.handle = NV_SUBDEV(CLOCK, 0x04),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv04_clock_ctor,
		.dtor = _nouveau_clock_dtor,
		.init = _nouveau_clock_init,
		.fini = _nouveau_clock_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
70790f4f BS	25	#include <subdev/bios.h>
70790f4f BS	26	#include <subdev/bios/pll.h>
88524bc0	27	#include <subdev/clock.h>
cf336014	28	#include <subdev/devinit/nv04.h>
70790f4f BS	29
70790f4f BS	30	#include "pll.h"
8aceb7de BS	31
	32	struct nv04_clock_priv {
	33	struct nouveau_clock base;
	34	};
	35
70790f4f BS	36	int
	37	nv04_clock_pll_calc(struct nouveau_clock clock, struct nvbios_pll info,
	38	int clk, struct nouveau_pll_vals *pv)
	39	{
	40	int N1, M1, N2, M2, P;
7ada785f	41	int ret = nv04_pll_calc(nv_subdev(clock), info, clk, &N1, &M1, &N2, &M2, &P);
70790f4f BS	42	if (ret) {
	43	pv->refclk = info->refclk;
	44	pv->N1 = N1;
	45	pv->M1 = M1;
	46	pv->N2 = N2;
	47	pv->M2 = M2;
	48	pv->log2P = P;
	49	}
	50	return ret;
	51	}
	52
	53	int
	54	nv04_clock_pll_prog(struct nouveau_clock *clk, u32 reg1,
	55	struct nouveau_pll_vals *pv)
	56	{
88524bc0	57	struct nouveau_devinit *devinit = nouveau_devinit(clk);
70790f4f BS	58	int cv = nouveau_bios(clk)->version.chip;
	59
	60	if (cv == 0x30 \|\| cv == 0x31 \|\| cv == 0x35 \|\| cv == 0x36 \|\|
	61	cv >= 0x40) {
	62	if (reg1 > 0x405c)
88524bc0	63	setPLL_double_highregs(devinit, reg1, pv);
70790f4f	64	else
88524bc0	65	setPLL_double_lowregs(devinit, reg1, pv);
70790f4f	66	} else
88524bc0	67	setPLL_single(devinit, reg1, pv);
70790f4f BS	68
70790f4f BS	69	return 0;
8aceb7de BS	70	}
8aceb7de BS	71
5b19f4f9 BS	72	static struct nouveau_clocks
	73	nv04_domain[] = {
	74	{ nv_clk_src_max }
	75	};
	76
8aceb7de BS	77	static int
	78	nv04_clock_ctor(struct nouveau_object parent, struct nouveau_object engine,
	79	struct nouveau_oclass oclass, void data, u32 size,
	80	struct nouveau_object **pobject)
	81	{
	82	struct nv04_clock_priv *priv;
	83	int ret;
	84
bb4d29df AC	85	ret = nouveau_clock_create(parent, engine, oclass, nv04_domain, NULL, 0,
bb4d29df AC	86	false, &priv);
8aceb7de BS	87	*pobject = nv_object(priv);
	88	if (ret)
	89	return ret;
	90
70790f4f BS	91	priv->base.pll_calc = nv04_clock_pll_calc;
70790f4f BS	92	priv->base.pll_prog = nv04_clock_pll_prog;
8aceb7de BS	93	return 0;
	94	}
	95
	96	struct nouveau_oclass
	97	nv04_clock_oclass = {
	98	.handle = NV_SUBDEV(CLOCK, 0x04),
	99	.ofuncs = &(struct nouveau_ofuncs) {
	100	.ctor = nv04_clock_ctor,
	101	.dtor = _nouveau_clock_dtor,
	102	.init = _nouveau_clock_init,
	103	.fini = _nouveau_clock_fini,
	104	},
	105	};