projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 88524bc0 BS |
1 | /* |
| 2 | * Copyright 2013 Red Hat Inc. | |
| 3 | * | |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 5 | * copy of this software and associated documentation files (the "Software"), | |
| 6 | * to deal in the Software without restriction, including without limitation | |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 9 | * Software is furnished to do so, subject to the following conditions: | |
| 10 | * | |
| 11 | * The above copyright notice and this permission notice shall be included in | |
| 12 | * all copies or substantial portions of the Software. | |
| 13 | * | |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 21 | * | |
| 22 | * Authors: Ben Skeggs | |
| 23 | */ | |
| 24 | ||
| cf336014 | 25 | #include "nv50.h" |
| 88524bc0 | 26 | |
| 4019aaa2 | 27 | int |
| 88524bc0 BS |
28 | nva3_devinit_pll_set(struct nouveau_devinit *devinit, u32 type, u32 freq) |
| 29 | { | |
| cf336014 | 30 | struct nv50_devinit_priv *priv = (void *)devinit; |
| 88524bc0 BS |
31 | struct nouveau_bios *bios = nouveau_bios(priv); |
| 32 | struct nvbios_pll info; | |
| 33 | int N, fN, M, P; | |
| 34 | int ret; | |
| 35 | ||
| 36 | ret = nvbios_pll_parse(bios, type, &info); | |
| 37 | if (ret) | |
| 38 | return ret; | |
| 39 | ||
| 40 | ret = nva3_pll_calc(nv_subdev(devinit), &info, freq, &N, &fN, &M, &P); | |
| 41 | if (ret < 0) | |
| 42 | return ret; | |
| 43 | ||
| 44 | switch (info.type) { | |
| 45 | case PLL_VPLL0: | |
| 46 | case PLL_VPLL1: | |
| 47 | nv_wr32(priv, info.reg + 0, 0x50000610); | |
| 48 | nv_mask(priv, info.reg + 4, 0x003fffff, | |
| 49 | (P << 16) | (M << 8) | N); | |
| 50 | nv_wr32(priv, info.reg + 8, fN); | |
| 51 | break; | |
| 52 | default: | |
| 53 | nv_warn(priv, "0x%08x/%dKhz unimplemented\n", type, freq); | |
| 54 | ret = -EINVAL; | |
| 55 | break; | |
| 56 | } | |
| 57 | ||
| 58 | return ret; | |
| 59 | } | |
| 60 | ||
| 4019aaa2 IM |
61 | static u64 |
| 62 | nva3_devinit_disable(struct nouveau_devinit *devinit) | |
| 63 | { | |
| 64 | struct nv50_devinit_priv *priv = (void *)devinit; | |
| 65 | u32 r001540 = nv_rd32(priv, 0x001540); | |
| 66 | u32 r00154c = nv_rd32(priv, 0x00154c); | |
| 67 | u64 disable = 0ULL; | |
| 68 | ||
| 69 | if (!(r001540 & 0x40000000)) { | |
| 37a5d028 | 70 | disable |= (1ULL << NVDEV_ENGINE_MSPDEC); |
| fd8666f7 | 71 | disable |= (1ULL << NVDEV_ENGINE_MSPPP); |
| 4019aaa2 IM |
72 | } |
| 73 | ||
| 74 | if (!(r00154c & 0x00000004)) | |
| 75 | disable |= (1ULL << NVDEV_ENGINE_DISP); | |
| 76 | if (!(r00154c & 0x00000020)) | |
| eccf7e8a | 77 | disable |= (1ULL << NVDEV_ENGINE_MSVLD); |
| 4019aaa2 | 78 | if (!(r00154c & 0x00000200)) |
| aedf24ff | 79 | disable |= (1ULL << NVDEV_ENGINE_CE0); |
| 4019aaa2 IM |
80 | |
| 81 | return disable; | |
| 82 | } | |
| 83 | ||
| 8687c5d7 BS |
84 | static u32 |
| 85 | nva3_devinit_mmio_part[] = { | |
| 86 | 0x100720, 0x1008bc, 4, | |
| 87 | 0x100a20, 0x100adc, 4, | |
| 88 | 0x100d80, 0x100ddc, 4, | |
| 89 | 0x110000, 0x110f9c, 4, | |
| 90 | 0x111000, 0x11103c, 8, | |
| 91 | 0x111080, 0x1110fc, 4, | |
| 92 | 0x111120, 0x1111fc, 4, | |
| 93 | 0x111300, 0x1114bc, 4, | |
| 94 | 0, | |
| 95 | }; | |
| 96 | ||
| 97 | static u32 | |
| 98 | nva3_devinit_mmio(struct nouveau_devinit *devinit, u32 addr) | |
| 99 | { | |
| 100 | struct nv50_devinit_priv *priv = (void *)devinit; | |
| 101 | u32 *mmio = nva3_devinit_mmio_part; | |
| 102 | ||
| 103 | /* the init tables on some boards have INIT_RAM_RESTRICT_ZM_REG_GROUP | |
| 104 | * instructions which touch registers that may not even exist on | |
| 105 | * some configurations (Quadro 400), which causes the register | |
| 106 | * interface to screw up for some amount of time after attempting to | |
| 107 | * write to one of these, and results in all sorts of things going | |
| 108 | * horribly wrong. | |
| 109 | * | |
| 110 | * the binary driver avoids touching these registers at all, however, | |
| 111 | * the video bios doesn't care and does what the scripts say. it's | |
| 112 | * presumed that the io-port access to priv registers isn't effected | |
| 113 | * by the screw-up bug mentioned above. | |
| 114 | * | |
| 115 | * really, a new opcode should've been invented to handle these | |
| 116 | * requirements, but whatever, it's too late for that now. | |
| 117 | */ | |
| 118 | while (mmio[0]) { | |
| 119 | if (addr >= mmio[0] && addr <= mmio[1]) { | |
| 120 | u32 part = (addr / mmio[2]) & 7; | |
| 121 | if (!priv->r001540) | |
| 122 | priv->r001540 = nv_rd32(priv, 0x001540); | |
| 123 | if (part >= hweight8((priv->r001540 >> 16) & 0xff)) | |
| 124 | return ~0; | |
| 125 | return addr; | |
| 126 | } | |
| 127 | mmio += 3; | |
| 128 | } | |
| 129 | ||
| 130 | return addr; | |
| 131 | } | |
| 132 | ||
| cf336014 BS |
133 | struct nouveau_oclass * |
| 134 | nva3_devinit_oclass = &(struct nouveau_devinit_impl) { | |
| 135 | .base.handle = NV_SUBDEV(DEVINIT, 0xa3), | |
| 136 | .base.ofuncs = &(struct nouveau_ofuncs) { | |
| 137 | .ctor = nv50_devinit_ctor, | |
| 88524bc0 BS |
138 | .dtor = _nouveau_devinit_dtor, |
| 139 | .init = nv50_devinit_init, | |
| 140 | .fini = _nouveau_devinit_fini, | |
| 141 | }, | |
| cf336014 | 142 | .pll_set = nva3_devinit_pll_set, |
| 4019aaa2 | 143 | .disable = nva3_devinit_disable, |
| 8687c5d7 | 144 | .mmio = nva3_devinit_mmio, |
| e21fd7c4 | 145 | .post = nvbios_init, |
| cf336014 | 146 | }.base; |