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861d2107 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
2799bba6 | 24 | #include "priv.h" |
861d2107 | 25 | |
2799bba6 | 26 | #include <core/enum.h> |
e30441ad CB |
27 | #include <subdev/fb.h> |
28 | #include <subdev/timer.h> | |
861d2107 | 29 | |
95484b57 BS |
30 | void |
31 | gf100_ltc_cbc_clear(struct nvkm_ltc_priv *priv, u32 start, u32 limit) | |
32 | { | |
33 | nv_wr32(priv, 0x17e8cc, start); | |
34 | nv_wr32(priv, 0x17e8d0, limit); | |
35 | nv_wr32(priv, 0x17e8c8, 0x00000004); | |
36 | } | |
37 | ||
38 | void | |
39 | gf100_ltc_cbc_wait(struct nvkm_ltc_priv *priv) | |
40 | { | |
41 | int c, s; | |
42 | for (c = 0; c < priv->ltc_nr; c++) { | |
43 | for (s = 0; s < priv->lts_nr; s++) | |
44 | nv_wait(priv, 0x1410c8 + c * 0x2000 + s * 0x400, ~0, 0); | |
45 | } | |
46 | } | |
861d2107 | 47 | |
f38fdb6a BS |
48 | void |
49 | gf100_ltc_zbc_clear_color(struct nvkm_ltc_priv *priv, int i, const u32 color[4]) | |
50 | { | |
51 | nv_mask(priv, 0x17ea44, 0x0000000f, i); | |
52 | nv_wr32(priv, 0x17ea48, color[0]); | |
53 | nv_wr32(priv, 0x17ea4c, color[1]); | |
54 | nv_wr32(priv, 0x17ea50, color[2]); | |
55 | nv_wr32(priv, 0x17ea54, color[3]); | |
56 | } | |
57 | ||
58 | void | |
59 | gf100_ltc_zbc_clear_depth(struct nvkm_ltc_priv *priv, int i, const u32 depth) | |
60 | { | |
61 | nv_mask(priv, 0x17ea44, 0x0000000f, i); | |
62 | nv_wr32(priv, 0x17ea58, depth); | |
63 | } | |
64 | ||
2799bba6 | 65 | static const struct nvkm_bitfield |
a1fc50b4 BS |
66 | gf100_ltc_lts_intr_name[] = { |
67 | { 0x00000001, "IDLE_ERROR_IQ" }, | |
68 | { 0x00000002, "IDLE_ERROR_CBC" }, | |
69 | { 0x00000004, "IDLE_ERROR_TSTG" }, | |
70 | { 0x00000008, "IDLE_ERROR_DSTG" }, | |
71 | { 0x00000010, "EVICTED_CB" }, | |
72 | { 0x00000020, "ILLEGAL_COMPSTAT" }, | |
73 | { 0x00000040, "BLOCKLINEAR_CB" }, | |
74 | { 0x00000100, "ECC_SEC_ERROR" }, | |
75 | { 0x00000200, "ECC_DED_ERROR" }, | |
76 | { 0x00000400, "DEBUG" }, | |
77 | { 0x00000800, "ATOMIC_TO_Z" }, | |
78 | { 0x00001000, "ILLEGAL_ATOMIC" }, | |
79 | { 0x00002000, "BLKACTIVITY_ERR" }, | |
80 | {} | |
81 | }; | |
82 | ||
861d2107 | 83 | static void |
a1fc50b4 | 84 | gf100_ltc_lts_intr(struct nvkm_ltc_priv *priv, int ltc, int lts) |
861d2107 | 85 | { |
f6bad8ab | 86 | u32 base = 0x141000 + (ltc * 0x2000) + (lts * 0x400); |
a1fc50b4 BS |
87 | u32 intr = nv_rd32(priv, base + 0x020); |
88 | u32 stat = intr & 0x0000ffff; | |
861d2107 BS |
89 | |
90 | if (stat) { | |
a1fc50b4 | 91 | nv_info(priv, "LTC%d_LTS%d:", ltc, lts); |
2799bba6 | 92 | nvkm_bitfield_print(gf100_ltc_lts_intr_name, stat); |
a1fc50b4 | 93 | pr_cont("\n"); |
861d2107 | 94 | } |
a1fc50b4 BS |
95 | |
96 | nv_wr32(priv, base + 0x020, intr); | |
861d2107 BS |
97 | } |
98 | ||
95484b57 | 99 | void |
2799bba6 | 100 | gf100_ltc_intr(struct nvkm_subdev *subdev) |
861d2107 | 101 | { |
95484b57 | 102 | struct nvkm_ltc_priv *priv = (void *)subdev; |
f6bad8ab BS |
103 | u32 mask; |
104 | ||
105 | mask = nv_rd32(priv, 0x00017c); | |
106 | while (mask) { | |
107 | u32 lts, ltc = __ffs(mask); | |
108 | for (lts = 0; lts < priv->lts_nr; lts++) | |
a1fc50b4 | 109 | gf100_ltc_lts_intr(priv, ltc, lts); |
f6bad8ab | 110 | mask &= ~(1 << ltc); |
861d2107 | 111 | } |
861d2107 BS |
112 | } |
113 | ||
95484b57 | 114 | static int |
2799bba6 | 115 | gf100_ltc_init(struct nvkm_object *object) |
e30441ad | 116 | { |
95484b57 | 117 | struct nvkm_ltc_priv *priv = (void *)object; |
fe3d9c4b | 118 | u32 lpg128 = !(nv_rd32(priv, 0x100c80) & 0x00000001); |
e30441ad CB |
119 | int ret; |
120 | ||
95484b57 | 121 | ret = nvkm_ltc_init(priv); |
e30441ad | 122 | if (ret) |
95484b57 | 123 | return ret; |
e30441ad | 124 | |
95484b57 BS |
125 | nv_mask(priv, 0x17e820, 0x00100000, 0x00000000); /* INTR_EN &= ~0x10 */ |
126 | nv_wr32(priv, 0x17e8d8, priv->ltc_nr); | |
127 | nv_wr32(priv, 0x17e8d4, priv->tag_base); | |
fe3d9c4b | 128 | nv_mask(priv, 0x17e8c0, 0x00000002, lpg128 ? 0x00000002 : 0x00000000); |
95484b57 | 129 | return 0; |
e30441ad CB |
130 | } |
131 | ||
f6bad8ab | 132 | void |
2799bba6 | 133 | gf100_ltc_dtor(struct nvkm_object *object) |
e30441ad | 134 | { |
2799bba6 | 135 | struct nvkm_fb *pfb = nvkm_fb(object); |
95484b57 | 136 | struct nvkm_ltc_priv *priv = (void *)object; |
e30441ad | 137 | |
2799bba6 | 138 | nvkm_mm_fini(&priv->tags); |
eaecf032 AC |
139 | if (pfb->ram) |
140 | nvkm_mm_free(&pfb->vram, &priv->tag_ram); | |
e30441ad | 141 | |
95484b57 | 142 | nvkm_ltc_destroy(priv); |
e30441ad CB |
143 | } |
144 | ||
145 | /* TODO: Figure out tag memory details and drop the over-cautious allocation. | |
146 | */ | |
f6bad8ab | 147 | int |
2799bba6 | 148 | gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv) |
e30441ad CB |
149 | { |
150 | u32 tag_size, tag_margin, tag_align; | |
151 | int ret; | |
152 | ||
eaecf032 AC |
153 | /* No VRAM, no tags for now. */ |
154 | if (!pfb->ram) { | |
155 | priv->num_tags = 0; | |
156 | goto mm_init; | |
157 | } | |
158 | ||
e30441ad | 159 | /* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */ |
dceef5d8 | 160 | priv->num_tags = (pfb->ram->size >> 17) / 4; |
e30441ad CB |
161 | if (priv->num_tags > (1 << 17)) |
162 | priv->num_tags = 1 << 17; /* we have 17 bits in PTE */ | |
163 | priv->num_tags = (priv->num_tags + 63) & ~63; /* round up to 64 */ | |
164 | ||
f6bad8ab | 165 | tag_align = priv->ltc_nr * 0x800; |
e30441ad CB |
166 | tag_margin = (tag_align < 0x6000) ? 0x6000 : tag_align; |
167 | ||
168 | /* 4 part 4 sub: 0x2000 bytes for 56 tags */ | |
169 | /* 3 part 4 sub: 0x6000 bytes for 168 tags */ | |
170 | /* | |
171 | * About 147 bytes per tag. Let's be safe and allocate x2, which makes | |
172 | * 0x4980 bytes for 64 tags, and round up to 0x6000 bytes for 64 tags. | |
173 | * | |
174 | * For 4 GiB of memory we'll have 8192 tags which makes 3 MiB, < 0.1 %. | |
175 | */ | |
176 | tag_size = (priv->num_tags / 64) * 0x6000 + tag_margin; | |
177 | tag_size += tag_align; | |
178 | tag_size = (tag_size + 0xfff) >> 12; /* round up */ | |
179 | ||
2799bba6 BS |
180 | ret = nvkm_mm_tail(&pfb->vram, 1, 1, tag_size, tag_size, 1, |
181 | &priv->tag_ram); | |
e30441ad CB |
182 | if (ret) { |
183 | priv->num_tags = 0; | |
184 | } else { | |
147ed897 | 185 | u64 tag_base = ((u64)priv->tag_ram->offset << 12) + tag_margin; |
e30441ad CB |
186 | |
187 | tag_base += tag_align - 1; | |
8cb303a8 | 188 | ret = do_div(tag_base, tag_align); |
e30441ad | 189 | |
52f9a4d7 | 190 | priv->tag_base = tag_base; |
e30441ad | 191 | } |
e30441ad | 192 | |
eaecf032 | 193 | mm_init: |
2799bba6 | 194 | ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1); |
e30441ad CB |
195 | return ret; |
196 | } | |
197 | ||
95484b57 | 198 | int |
2799bba6 BS |
199 | gf100_ltc_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
200 | struct nvkm_oclass *oclass, void *data, u32 size, | |
201 | struct nvkm_object **pobject) | |
861d2107 | 202 | { |
2799bba6 | 203 | struct nvkm_fb *pfb = nvkm_fb(parent); |
95484b57 | 204 | struct nvkm_ltc_priv *priv; |
49debbe4 BS |
205 | u32 parts, mask; |
206 | int ret, i; | |
861d2107 | 207 | |
95484b57 | 208 | ret = nvkm_ltc_create(parent, engine, oclass, &priv); |
861d2107 BS |
209 | *pobject = nv_object(priv); |
210 | if (ret) | |
211 | return ret; | |
212 | ||
49debbe4 BS |
213 | parts = nv_rd32(priv, 0x022438); |
214 | mask = nv_rd32(priv, 0x022554); | |
215 | for (i = 0; i < parts; i++) { | |
216 | if (!(mask & (1 << i))) | |
f6bad8ab | 217 | priv->ltc_nr++; |
49debbe4 | 218 | } |
f6bad8ab | 219 | priv->lts_nr = nv_rd32(priv, 0x17e8dc) >> 28; |
e30441ad | 220 | |
95484b57 | 221 | ret = gf100_ltc_init_tag_ram(pfb, priv); |
e30441ad CB |
222 | if (ret) |
223 | return ret; | |
224 | ||
95484b57 | 225 | nv_subdev(priv)->intr = gf100_ltc_intr; |
52f9a4d7 ML |
226 | return 0; |
227 | } | |
228 | ||
2799bba6 | 229 | struct nvkm_oclass * |
95484b57 BS |
230 | gf100_ltc_oclass = &(struct nvkm_ltc_impl) { |
231 | .base.handle = NV_SUBDEV(LTC, 0xc0), | |
2799bba6 | 232 | .base.ofuncs = &(struct nvkm_ofuncs) { |
95484b57 BS |
233 | .ctor = gf100_ltc_ctor, |
234 | .dtor = gf100_ltc_dtor, | |
235 | .init = gf100_ltc_init, | |
236 | .fini = _nvkm_ltc_fini, | |
861d2107 | 237 | }, |
95484b57 BS |
238 | .intr = gf100_ltc_intr, |
239 | .cbc_clear = gf100_ltc_cbc_clear, | |
240 | .cbc_wait = gf100_ltc_cbc_wait, | |
f38fdb6a BS |
241 | .zbc = 16, |
242 | .zbc_clear_color = gf100_ltc_zbc_clear_color, | |
243 | .zbc_clear_depth = gf100_ltc_zbc_clear_depth, | |
95484b57 | 244 | }.base; |