[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / mmu / nv04.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
#include "nv04.h"

#include <core/device.h>
#include <core/gpuobj.h>

#define NV04_PDMA_SIZE (128 * 1024 * 1024)
#define NV04_PDMA_PAGE (  4 * 1024)

/*******************************************************************************
 * VM map/unmap callbacks
 ******************************************************************************/

static void
nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
	       struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
	pte = 0x00008 + (pte * 4);
	while (cnt) {
		u32 page = PAGE_SIZE / NV04_PDMA_PAGE;
		u32 phys = (u32)*list++;
		while (cnt && page--) {
			nv_wo32(pgt, pte, phys | 3);
			phys += NV04_PDMA_PAGE;
			pte += 4;
			cnt -= 1;
		}
	}
}

static void
nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
{
	pte = 0x00008 + (pte * 4);
	while (cnt--) {
		nv_wo32(pgt, pte, 0x00000000);
		pte += 4;
	}
}

static void
nv04_vm_flush(struct nvkm_vm *vm)
{
}

/*******************************************************************************
 * VM object
 ******************************************************************************/

int
nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
	       struct nvkm_vm **pvm)
{
	return -EINVAL;
}

/*******************************************************************************
 * MMU subdev
 ******************************************************************************/

static int
nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
	      struct nvkm_oclass *oclass, void *data, u32 size,
	      struct nvkm_object **pobject)
{
	struct nv04_mmu_priv *priv;
	struct nvkm_gpuobj *dma;
	int ret;

	ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
			      "pcigart", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.create = nv04_vm_create;
	priv->base.limit = NV04_PDMA_SIZE;
	priv->base.dma_bits = 32;
	priv->base.pgt_bits = 32 - 12;
	priv->base.spg_shift = 12;
	priv->base.lpg_shift = 12;
	priv->base.map_sg = nv04_vm_map_sg;
	priv->base.unmap = nv04_vm_unmap;
	priv->base.flush = nv04_vm_flush;

	ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
			     &priv->vm);
	if (ret)
		return ret;

	ret = nvkm_gpuobj_new(nv_object(priv), NULL,
			      (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8,
			      16, NVOBJ_FLAG_ZERO_ALLOC,
			      &priv->vm->pgt[0].obj[0]);
	dma = priv->vm->pgt[0].obj[0];
	priv->vm->pgt[0].refcount[0] = 1;
	if (ret)
		return ret;

	nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */
	nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1);
	return 0;
}

void
nv04_mmu_dtor(struct nvkm_object *object)
{
	struct nv04_mmu_priv *priv = (void *)object;
	if (priv->vm) {
		nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
		nvkm_vm_ref(NULL, &priv->vm, NULL);
	}
	if (priv->nullp) {
		pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
				    priv->nullp, priv->null);
	}
	nvkm_mmu_destroy(&priv->base);
}

struct nvkm_oclass
nv04_mmu_oclass = {
	.handle = NV_SUBDEV(MMU, 0x04),
	.ofuncs = &(struct nvkm_ofuncs) {
		.ctor = nv04_mmu_ctor,
		.dtor = nv04_mmu_dtor,
		.init = _nvkm_mmu_init,
		.fini = _nvkm_mmu_fini,
	},
};
Commit	Line	Data
3863c9bc BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
42594600	24	#include "nv04.h"
3863c9bc	25
42594600	26	#include <core/device.h>
3863c9bc BS	27	#include <core/gpuobj.h>
3863c9bc BS	28
3863c9bc BS	29	#define NV04_PDMA_SIZE (128 * 1024 * 1024)
	30	#define NV04_PDMA_PAGE ( 4 * 1024)
	31
	32	/*******************************************************************************
	33	* VM map/unmap callbacks
	34	******************************************************************************/
	35
	36	static void
42594600 BS	37	nv04_vm_map_sg(struct nvkm_vma vma, struct nvkm_gpuobj pgt,
42594600 BS	38	struct nvkm_mem mem, u32 pte, u32 cnt, dma_addr_t list)
3863c9bc BS	39	{
	40	pte = 0x00008 + (pte * 4);
	41	while (cnt) {
	42	u32 page = PAGE_SIZE / NV04_PDMA_PAGE;
	43	u32 phys = (u32)*list++;
	44	while (cnt && page--) {
	45	nv_wo32(pgt, pte, phys \| 3);
	46	phys += NV04_PDMA_PAGE;
	47	pte += 4;
	48	cnt -= 1;
	49	}
	50	}
	51	}
	52
	53	static void
42594600	54	nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
3863c9bc BS	55	{
	56	pte = 0x00008 + (pte * 4);
	57	while (cnt--) {
	58	nv_wo32(pgt, pte, 0x00000000);
	59	pte += 4;
	60	}
	61	}
	62
	63	static void
42594600	64	nv04_vm_flush(struct nvkm_vm *vm)
3863c9bc BS	65	{
	66	}
	67
	68	/*******************************************************************************
	69	* VM object
	70	******************************************************************************/
	71
	72	int
42594600 BS	73	nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart,
42594600 BS	74	struct nvkm_vm **pvm)
3863c9bc BS	75	{
	76	return -EINVAL;
	77	}
	78
	79	/*******************************************************************************
5ce3bf3c	80	* MMU subdev
3863c9bc BS	81	******************************************************************************/
	82
	83	static int
42594600 BS	84	nv04_mmu_ctor(struct nvkm_object parent, struct nvkm_object engine,
	85	struct nvkm_oclass oclass, void data, u32 size,
	86	struct nvkm_object **pobject)
3863c9bc	87	{
5ce3bf3c	88	struct nv04_mmu_priv *priv;
42594600	89	struct nvkm_gpuobj *dma;
3863c9bc BS	90	int ret;
3863c9bc BS	91
42594600 BS	92	ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART",
42594600 BS	93	"pcigart", &priv);
3863c9bc BS	94	*pobject = nv_object(priv);
	95	if (ret)
	96	return ret;
	97
	98	priv->base.create = nv04_vm_create;
ebb945a9	99	priv->base.limit = NV04_PDMA_SIZE;
dc73b45a	100	priv->base.dma_bits = 32;
3863c9bc BS	101	priv->base.pgt_bits = 32 - 12;
	102	priv->base.spg_shift = 12;
	103	priv->base.lpg_shift = 12;
	104	priv->base.map_sg = nv04_vm_map_sg;
	105	priv->base.unmap = nv04_vm_unmap;
	106	priv->base.flush = nv04_vm_flush;
	107
42594600 BS	108	ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096,
42594600 BS	109	&priv->vm);
3863c9bc BS	110	if (ret)
	111	return ret;
	112
42594600 BS	113	ret = nvkm_gpuobj_new(nv_object(priv), NULL,
	114	(NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8,
	115	16, NVOBJ_FLAG_ZERO_ALLOC,
	116	&priv->vm->pgt[0].obj[0]);
3863c9bc BS	117	dma = priv->vm->pgt[0].obj[0];
	118	priv->vm->pgt[0].refcount[0] = 1;
	119	if (ret)
	120	return ret;
	121
	122	nv_wo32(dma, 0x00000, 0x0002103d); /* PCI, RW, PT, !LN */
	123	nv_wo32(dma, 0x00004, NV04_PDMA_SIZE - 1);
	124	return 0;
	125	}
	126
	127	void
42594600	128	nv04_mmu_dtor(struct nvkm_object *object)
3863c9bc	129	{
5ce3bf3c	130	struct nv04_mmu_priv priv = (void )object;
3863c9bc	131	if (priv->vm) {
42594600 BS	132	nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]);
42594600 BS	133	nvkm_vm_ref(NULL, &priv->vm, NULL);
3863c9bc	134	}
e5f186c4 BS	135	if (priv->nullp) {
	136	pci_free_consistent(nv_device(priv)->pdev, 16 * 1024,
	137	priv->nullp, priv->null);
3863c9bc	138	}
42594600	139	nvkm_mmu_destroy(&priv->base);
3863c9bc BS	140	}
3863c9bc BS	141
42594600	142	struct nvkm_oclass
5ce3bf3c BS	143	nv04_mmu_oclass = {
5ce3bf3c BS	144	.handle = NV_SUBDEV(MMU, 0x04),
42594600	145	.ofuncs = &(struct nvkm_ofuncs) {
5ce3bf3c BS	146	.ctor = nv04_mmu_ctor,
5ce3bf3c BS	147	.dtor = nv04_mmu_dtor,
42594600 BS	148	.init = _nvkm_mmu_init,
42594600 BS	149	.fini = _nvkm_mmu_fini,
3863c9bc BS	150	},
3863c9bc BS	151	};