[deliverable/linux.git] / drivers / gpu / drm / nouveau / nvkm / subdev / mmu / nv50.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <core/device.h>
#include <core/gpuobj.h>

#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/bar.h>
#include <subdev/mmu.h>

struct nv50_mmu_priv {
	struct nouveau_mmu base;
};

static void
nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
		struct nouveau_gpuobj *pgt[2])
{
	u64 phys = 0xdeadcafe00000000ULL;
	u32 coverage = 0;

	if (pgt[0]) {
		phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */
		coverage = (pgt[0]->size >> 3) << 12;
	} else
	if (pgt[1]) {
		phys = 0x00000001 | pgt[1]->addr; /* present */
		coverage = (pgt[1]->size >> 3) << 16;
	}

	if (phys & 1) {
		if (coverage <= 32 * 1024 * 1024)
			phys |= 0x60;
		else if (coverage <= 64 * 1024 * 1024)
			phys |= 0x40;
		else if (coverage <= 128 * 1024 * 1024)
			phys |= 0x20;
	}

	nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
	nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
}

static inline u64
vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
{
	phys |= 1; /* present */
	phys |= (u64)memtype << 40;
	phys |= target << 4;
	if (vma->access & NV_MEM_ACCESS_SYS)
		phys |= (1 << 6);
	if (!(vma->access & NV_MEM_ACCESS_WO))
		phys |= (1 << 3);
	return phys;
}

static void
nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	    struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
{
	u32 comp = (mem->memtype & 0x180) >> 7;
	u32 block, target;
	int i;

	/* IGPs don't have real VRAM, re-target to stolen system memory */
	target = 0;
	if (nouveau_fb(vma->vm->mmu)->ram->stolen) {
		phys += nouveau_fb(vma->vm->mmu)->ram->stolen;
		target = 3;
	}

	phys  = vm_addr(vma, phys, mem->memtype, target);
	pte <<= 3;
	cnt <<= 3;

	while (cnt) {
		u32 offset_h = upper_32_bits(phys);
		u32 offset_l = lower_32_bits(phys);

		for (i = 7; i >= 0; i--) {
			block = 1 << (i + 3);
			if (cnt >= block && !(pte & (block - 1)))
				break;
		}
		offset_l |= (i << 7);

		phys += block << (vma->node->type - 3);
		cnt  -= block;
		if (comp) {
			u32 tag = mem->tag->offset + ((delta >> 16) * comp);
			offset_h |= (tag << 17);
			delta    += block << (vma->node->type - 3);
		}

		while (block) {
			nv_wo32(pgt, pte + 0, offset_l);
			nv_wo32(pgt, pte + 4, offset_h);
			pte += 8;
			block -= 8;
		}
	}
}

static void
nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	       struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
{
	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
	pte <<= 3;
	while (cnt--) {
		u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target);
		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
		pte += 8;
	}
}

static void
nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
{
	pte <<= 3;
	while (cnt--) {
		nv_wo32(pgt, pte + 0, 0x00000000);
		nv_wo32(pgt, pte + 4, 0x00000000);
		pte += 8;
	}
}

static void
nv50_vm_flush(struct nouveau_vm *vm)
{
	struct nv50_mmu_priv *priv = (void *)vm->mmu;
	struct nouveau_bar *bar = nouveau_bar(priv);
	struct nouveau_engine *engine;
	int i, vme;

	bar->flush(bar);

	mutex_lock(&nv_subdev(priv)->mutex);
	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
		if (!atomic_read(&vm->engref[i]))
			continue;

		/* unfortunate hw bug workaround... */
		engine = nouveau_engine(priv, i);
		if (engine && engine->tlb_flush) {
			engine->tlb_flush(engine);
			continue;
		}

		switch (i) {
		case NVDEV_ENGINE_GR    : vme = 0x00; break;
		case NVDEV_ENGINE_VP    :
		case NVDEV_ENGINE_MSPDEC: vme = 0x01; break;
		case NVDEV_SUBDEV_BAR   : vme = 0x06; break;
		case NVDEV_ENGINE_MSPPP :
		case NVDEV_ENGINE_MPEG  : vme = 0x08; break;
		case NVDEV_ENGINE_BSP   :
		case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
		case NVDEV_ENGINE_CIPHER:
		case NVDEV_ENGINE_SEC   : vme = 0x0a; break;
		case NVDEV_ENGINE_CE0   : vme = 0x0d; break;
		default:
			continue;
		}

		nv_wr32(priv, 0x100c80, (vme << 16) | 1);
		if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
			nv_error(priv, "vm flush timeout: engine %d\n", vme);
	}
	mutex_unlock(&nv_subdev(priv)->mutex);
}

static int
nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
	       u64 mm_offset, struct nouveau_vm **pvm)
{
	u32 block = (1 << (mmu->pgt_bits + 12));
	if (block > length)
		block = length;

	return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm);
}

static int
nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nv50_mmu_priv *priv;
	int ret;

	ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.limit = 1ULL << 40;
	priv->base.dma_bits = 40;
	priv->base.pgt_bits  = 29 - 12;
	priv->base.spg_shift = 12;
	priv->base.lpg_shift = 16;
	priv->base.create = nv50_vm_create;
	priv->base.map_pgt = nv50_vm_map_pgt;
	priv->base.map = nv50_vm_map;
	priv->base.map_sg = nv50_vm_map_sg;
	priv->base.unmap = nv50_vm_unmap;
	priv->base.flush = nv50_vm_flush;
	return 0;
}

struct nouveau_oclass
nv50_mmu_oclass = {
	.handle = NV_SUBDEV(MMU, 0x50),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nv50_mmu_ctor,
		.dtor = _nouveau_mmu_dtor,
		.init = _nouveau_mmu_init,
		.fini = _nouveau_mmu_fini,
	},
};
Commit	Line	Data
a11c3198 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
3863c9bc BS	25	#include <core/device.h>
3863c9bc BS	26	#include <core/gpuobj.h>
a11c3198	27
3863c9bc BS	28	#include <subdev/timer.h>
3863c9bc BS	29	#include <subdev/fb.h>
36798b61	30	#include <subdev/bar.h>
5ce3bf3c	31	#include <subdev/mmu.h>
a11c3198	32
5ce3bf3c BS	33	struct nv50_mmu_priv {
5ce3bf3c BS	34	struct nouveau_mmu base;
3863c9bc BS	35	};
3863c9bc BS	36
5b8a43ae	37	static void
3ee01281 BS	38	nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
3ee01281 BS	39	struct nouveau_gpuobj *pgt[2])
a11c3198	40	{
3ee01281 BS	41	u64 phys = 0xdeadcafe00000000ULL;
3ee01281 BS	42	u32 coverage = 0;
a11c3198	43
3ee01281	44	if (pgt[0]) {
3863c9bc	45	phys = 0x00000003 \| pgt[0]->addr; /* present, 4KiB pages */
3ee01281 BS	46	coverage = (pgt[0]->size >> 3) << 12;
	47	} else
	48	if (pgt[1]) {
3863c9bc	49	phys = 0x00000001 \| pgt[1]->addr; /* present */
3ee01281	50	coverage = (pgt[1]->size >> 3) << 16;
a11c3198 BS	51	}
a11c3198 BS	52
3ee01281	53	if (phys & 1) {
3ee01281 BS	54	if (coverage <= 32 * 1024 * 1024)
	55	phys \|= 0x60;
	56	else if (coverage <= 64 * 1024 * 1024)
	57	phys \|= 0x40;
9e7f96aa	58	else if (coverage <= 128 * 1024 * 1024)
3ee01281 BS	59	phys \|= 0x20;
3ee01281 BS	60	}
a11c3198 BS	61
	62	nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
	63	nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
	64	}
	65
a11c3198	66	static inline u64
990449c7	67	vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target)
a11c3198	68	{
a11c3198 BS	69	phys \|= 1; /* present */
a11c3198 BS	70	phys \|= (u64)memtype << 40;
a11c3198	71	phys \|= target << 4;
a11c3198 BS	72	if (vma->access & NV_MEM_ACCESS_SYS)
a11c3198 BS	73	phys \|= (1 << 6);
a11c3198 BS	74	if (!(vma->access & NV_MEM_ACCESS_WO))
a11c3198 BS	75	phys \|= (1 << 3);
a11c3198 BS	76	return phys;
	77	}
	78
5b8a43ae	79	static void
a11c3198	80	nv50_vm_map(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
8f7286f8	81	struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)
a11c3198	82	{
8f7286f8	83	u32 comp = (mem->memtype & 0x180) >> 7;
990449c7	84	u32 block, target;
910d1b3a	85	int i;
a11c3198	86
990449c7 BS	87	/* IGPs don't have real VRAM, re-target to stolen system memory */
990449c7 BS	88	target = 0;
5ce3bf3c BS	89	if (nouveau_fb(vma->vm->mmu)->ram->stolen) {
5ce3bf3c BS	90	phys += nouveau_fb(vma->vm->mmu)->ram->stolen;
990449c7 BS	91	target = 3;
	92	}
	93
	94	phys = vm_addr(vma, phys, mem->memtype, target);
a11c3198 BS	95	pte <<= 3;
	96	cnt <<= 3;
	97
	98	while (cnt) {
	99	u32 offset_h = upper_32_bits(phys);
	100	u32 offset_l = lower_32_bits(phys);
	101
	102	for (i = 7; i >= 0; i--) {
	103	block = 1 << (i + 3);
	104	if (cnt >= block && !(pte & (block - 1)))
	105	break;
	106	}
	107	offset_l \|= (i << 7);
	108
	109	phys += block << (vma->node->type - 3);
	110	cnt -= block;
8f7286f8	111	if (comp) {
861d2107	112	u32 tag = mem->tag->offset + ((delta >> 16) * comp);
8f7286f8 BS	113	offset_h \|= (tag << 17);
	114	delta += block << (vma->node->type - 3);
	115	}
a11c3198 BS	116
	117	while (block) {
	118	nv_wo32(pgt, pte + 0, offset_l);
	119	nv_wo32(pgt, pte + 4, offset_h);
	120	pte += 8;
	121	block -= 8;
	122	}
	123	}
	124	}
	125
5b8a43ae	126	static void
a11c3198	127	nv50_vm_map_sg(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
26c0c9e3	128	struct nouveau_mem mem, u32 pte, u32 cnt, dma_addr_t list)
a11c3198	129	{
990449c7	130	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2;
a11c3198 BS	131	pte <<= 3;
a11c3198 BS	132	while (cnt--) {
990449c7	133	u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target);
a11c3198 BS	134	nv_wo32(pgt, pte + 0, lower_32_bits(phys));
	135	nv_wo32(pgt, pte + 4, upper_32_bits(phys));
	136	pte += 8;
	137	}
	138	}
	139
5b8a43ae	140	static void
a11c3198 BS	141	nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
	142	{
	143	pte <<= 3;
	144	while (cnt--) {
	145	nv_wo32(pgt, pte + 0, 0x00000000);
	146	nv_wo32(pgt, pte + 4, 0x00000000);
	147	pte += 8;
	148	}
	149	}
	150
5b8a43ae	151	static void
a11c3198 BS	152	nv50_vm_flush(struct nouveau_vm *vm)
a11c3198 BS	153	{
5ce3bf3c	154	struct nv50_mmu_priv priv = (void )vm->mmu;
36798b61	155	struct nouveau_bar *bar = nouveau_bar(priv);
3863c9bc	156	struct nouveau_engine *engine;
464d636b	157	int i, vme;
a11c3198	158
36798b61 ML	159	bar->flush(bar);
36798b61 ML	160
ca97a366	161	mutex_lock(&nv_subdev(priv)->mutex);
3863c9bc	162	for (i = 0; i < NVDEV_SUBDEV_NR; i++) {
464d636b BS	163	if (!atomic_read(&vm->engref[i]))
	164	continue;
	165
	166	/* unfortunate hw bug workaround... */
	167	engine = nouveau_engine(priv, i);
	168	if (engine && engine->tlb_flush) {
	169	engine->tlb_flush(engine);
	170	continue;
3863c9bc	171	}
a11c3198	172
464d636b	173	switch (i) {
93d90ad7	174	case NVDEV_ENGINE_GR : vme = 0x00; break;
37a5d028 BS	175	case NVDEV_ENGINE_VP :
37a5d028 BS	176	case NVDEV_ENGINE_MSPDEC: vme = 0x01; break;
93d90ad7	177	case NVDEV_SUBDEV_BAR : vme = 0x06; break;
fd8666f7	178	case NVDEV_ENGINE_MSPPP :
93d90ad7 BS	179	case NVDEV_ENGINE_MPEG : vme = 0x08; break;
	180	case NVDEV_ENGINE_BSP :
	181	case NVDEV_ENGINE_MSVLD : vme = 0x09; break;
	182	case NVDEV_ENGINE_CIPHER:
	183	case NVDEV_ENGINE_SEC : vme = 0x0a; break;
aedf24ff	184	case NVDEV_ENGINE_CE0 : vme = 0x0d; break;
464d636b BS	185	default:
	186	continue;
	187	}
6f70a4c3	188
464d636b BS	189	nv_wr32(priv, 0x100c80, (vme << 16) \| 1);
	190	if (!nv_wait(priv, 0x100c80, 0x00000001, 0x00000000))
	191	nv_error(priv, "vm flush timeout: engine %d\n", vme);
	192	}
ca97a366	193	mutex_unlock(&nv_subdev(priv)->mutex);
a11c3198	194	}
3863c9bc BS	195
3863c9bc BS	196	static int
5ce3bf3c	197	nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length,
3863c9bc BS	198	u64 mm_offset, struct nouveau_vm **pvm)
3863c9bc BS	199	{
5ce3bf3c	200	u32 block = (1 << (mmu->pgt_bits + 12));
3863c9bc BS	201	if (block > length)
	202	block = length;
	203
5ce3bf3c	204	return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm);
3863c9bc BS	205	}
	206
	207	static int
5ce3bf3c	208	nv50_mmu_ctor(struct nouveau_object parent, struct nouveau_object engine,
3863c9bc BS	209	struct nouveau_oclass oclass, void data, u32 size,
	210	struct nouveau_object **pobject)
	211	{
5ce3bf3c	212	struct nv50_mmu_priv *priv;
3863c9bc BS	213	int ret;
3863c9bc BS	214
5ce3bf3c	215	ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv);
3863c9bc BS	216	*pobject = nv_object(priv);
	217	if (ret)
	218	return ret;
	219
ebb945a9	220	priv->base.limit = 1ULL << 40;
dc73b45a	221	priv->base.dma_bits = 40;
3863c9bc BS	222	priv->base.pgt_bits = 29 - 12;
	223	priv->base.spg_shift = 12;
	224	priv->base.lpg_shift = 16;
	225	priv->base.create = nv50_vm_create;
	226	priv->base.map_pgt = nv50_vm_map_pgt;
	227	priv->base.map = nv50_vm_map;
	228	priv->base.map_sg = nv50_vm_map_sg;
	229	priv->base.unmap = nv50_vm_unmap;
	230	priv->base.flush = nv50_vm_flush;
3863c9bc BS	231	return 0;
	232	}
	233
	234	struct nouveau_oclass
5ce3bf3c BS	235	nv50_mmu_oclass = {
5ce3bf3c BS	236	.handle = NV_SUBDEV(MMU, 0x50),
3863c9bc	237	.ofuncs = &(struct nouveau_ofuncs) {
5ce3bf3c BS	238	.ctor = nv50_mmu_ctor,
	239	.dtor = _nouveau_mmu_dtor,
	240	.init = _nouveau_mmu_init,
	241	.fini = _nouveau_mmu_fini,
3863c9bc BS	242	},
3863c9bc BS	243	};