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drm/radeon: Pay more attention to object placement requested by userspace.
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs690.c
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771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
29#include "radeon_reg.h"
30#include "radeon.h"
c93bb85b
JG		 31#include "rs690r.h"
32#include "atom.h"
33#include "atom-bits.h"
771fe6b9
JG		 34
35/* rs690,rs740 depends on : */
36void r100_hdp_reset(struct radeon_device *rdev);
37int r300_mc_wait_for_idle(struct radeon_device *rdev);
38void r420_pipes_init(struct radeon_device *rdev);
39void rs400_gart_disable(struct radeon_device *rdev);
40int rs400_gart_enable(struct radeon_device *rdev);
41void rs400_gart_adjust_size(struct radeon_device *rdev);
42void rs600_mc_disable_clients(struct radeon_device *rdev);
43void rs600_disable_vga(struct radeon_device *rdev);
44
45/* This files gather functions specifics to :
46 * rs690,rs740
47 *
48 * Some of these functions might be used by newer ASICs.
49 */
50void rs690_gpu_init(struct radeon_device *rdev);
51int rs690_mc_wait_for_idle(struct radeon_device *rdev);
52
53
54/*
55 * MC functions.
56 */
57int rs690_mc_init(struct radeon_device *rdev)
58{
59 uint32_t tmp;
60 int r;
61
62 if (r100_debugfs_rbbm_init(rdev)) {
63 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
64 }
65
66 rs690_gpu_init(rdev);
67 rs400_gart_disable(rdev);
68
69 /* Setup GPU memory space */
70 rdev->mc.gtt_location = rdev->mc.vram_size;
71 rdev->mc.gtt_location += (rdev->mc.gtt_size - 1);
72 rdev->mc.gtt_location &= ~(rdev->mc.gtt_size - 1);
73 rdev->mc.vram_location = 0xFFFFFFFFUL;
74 r = radeon_mc_setup(rdev);
75 if (r) {
76 return r;
77 }
78
79 /* Program GPU memory space */
80 rs600_mc_disable_clients(rdev);
81 if (rs690_mc_wait_for_idle(rdev)) {
82 printk(KERN_WARNING "Failed to wait MC idle while "
83 "programming pipes. Bad things might happen.\n");
84 }
85 tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
86 tmp = REG_SET(RS690_MC_FB_TOP, tmp >> 16);
87 tmp |= REG_SET(RS690_MC_FB_START, rdev->mc.vram_location >> 16);
88 WREG32_MC(RS690_MCCFG_FB_LOCATION, tmp);
89 /* FIXME: Does this reg exist on RS480,RS740 ? */
90 WREG32(0x310, rdev->mc.vram_location);
91 WREG32(RS690_HDP_FB_LOCATION, rdev->mc.vram_location >> 16);
92 return 0;
93}
94
95void rs690_mc_fini(struct radeon_device *rdev)
96{
97 rs400_gart_disable(rdev);
98 radeon_gart_table_ram_free(rdev);
99 radeon_gart_fini(rdev);
100}
101
102
103/*
104 * Global GPU functions
105 */
106int rs690_mc_wait_for_idle(struct radeon_device *rdev)
107{
108 unsigned i;
109 uint32_t tmp;
110
111 for (i = 0; i < rdev->usec_timeout; i++) {
112 /* read MC_STATUS */
113 tmp = RREG32_MC(RS690_MC_STATUS);
114 if (tmp & RS690_MC_STATUS_IDLE) {
115 return 0;
116 }
117 DRM_UDELAY(1);
118 }
119 return -1;
120}
121
122void rs690_errata(struct radeon_device *rdev)
123{
124 rdev->pll_errata = 0;
125}
126
127void rs690_gpu_init(struct radeon_device *rdev)
128{
129 /* FIXME: HDP same place on rs690 ? */
130 r100_hdp_reset(rdev);
131 rs600_disable_vga(rdev);
132 /* FIXME: is this correct ? */
133 r420_pipes_init(rdev);
134 if (rs690_mc_wait_for_idle(rdev)) {
135 printk(KERN_WARNING "Failed to wait MC idle while "
136 "programming pipes. Bad things might happen.\n");
137 }
138}
139
140
141/*
142 * VRAM info.
143 */
c93bb85b
JG		 144void rs690_pm_info(struct radeon_device *rdev)
145{
146 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
147 struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
148 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
149 void *ptr;
150 uint16_t data_offset;
151 uint8_t frev, crev;
152 fixed20_12 tmp;
153
154 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
155 &frev, &crev, &data_offset);
156 ptr = rdev->mode_info.atom_context->bios + data_offset;
157 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
158 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
159 /* Get various system informations from bios */
160 switch (crev) {
161 case 1:
162 tmp.full = rfixed_const(100);
163 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
164 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
165 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
166 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
167 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
168 break;
169 case 2:
170 tmp.full = rfixed_const(100);
171 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
172 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
173 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
174 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
175 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
176 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
177 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
178 break;
179 default:
180 tmp.full = rfixed_const(100);
181 /* We assume the slower possible clock ie worst case */
182 /* DDR 333Mhz */
183 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
184 /* FIXME: system clock ? */
185 rdev->pm.igp_system_mclk.full = rfixed_const(100);
186 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
187 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
188 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
189 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
190 break;
191 }
192 /* Compute various bandwidth */
193 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
194 tmp.full = rfixed_const(4);
195 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
196 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
197 * = ht_clk * ht_width / 5
198 */
199 tmp.full = rfixed_const(5);
200 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
201 rdev->pm.igp_ht_link_width);
202 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
203 if (tmp.full < rdev->pm.max_bandwidth.full) {
204 /* HT link is a limiting factor */
205 rdev->pm.max_bandwidth.full = tmp.full;
206 }
207 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
208 * = (sideport_clk * 14) / 10
209 */
210 tmp.full = rfixed_const(14);
211 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
212 tmp.full = rfixed_const(10);
213 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
214}
215
771fe6b9
JG		 216void rs690_vram_info(struct radeon_device *rdev)
217{
218 uint32_t tmp;
c93bb85b 219 fixed20_12 a;
771fe6b9
JG		 220
221 rs400_gart_adjust_size(rdev);
222 /* DDR for all card after R300 & IGP */
223 rdev->mc.vram_is_ddr = true;
224 /* FIXME: is this correct for RS690/RS740 ? */
225 tmp = RREG32(RADEON_MEM_CNTL);
226 if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
227 rdev->mc.vram_width = 128;
228 } else {
229 rdev->mc.vram_width = 64;
230 }
231 rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
232
233 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
234 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
c93bb85b
JG		 235 rs690_pm_info(rdev);
236 /* FIXME: we should enforce default clock in case GPU is not in
237 * default setup
238 */
239 a.full = rfixed_const(100);
240 rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
241 rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
242 a.full = rfixed_const(16);
243 /* core_bandwidth = sclk(Mhz) * 16 */
244 rdev->pm.core_bandwidth.full = rfixed_div(rdev->pm.sclk, a);
245}
246
247void rs690_line_buffer_adjust(struct radeon_device *rdev,
248 struct drm_display_mode *mode1,
249 struct drm_display_mode *mode2)
250{
251 u32 tmp;
252
253 /*
254 * Line Buffer Setup
255 * There is a single line buffer shared by both display controllers.
256 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
257 * the display controllers. The paritioning can either be done
258 * manually or via one of four preset allocations specified in bits 1:0:
259 * 0 - line buffer is divided in half and shared between crtc
260 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
261 * 2 - D1 gets the whole buffer
262 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
263 * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual
264 * allocation mode. In manual allocation mode, D1 always starts at 0,
265 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
266 */
267 tmp = RREG32(DC_LB_MEMORY_SPLIT) & ~DC_LB_MEMORY_SPLIT_MASK;
268 tmp &= ~DC_LB_MEMORY_SPLIT_SHIFT_MODE;
269 /* auto */
270 if (mode1 && mode2) {
271 if (mode1->hdisplay > mode2->hdisplay) {
272 if (mode1->hdisplay > 2560)
273 tmp |= DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
274 else
275 tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
276 } else if (mode2->hdisplay > mode1->hdisplay) {
277 if (mode2->hdisplay > 2560)
278 tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
279 else
280 tmp |= DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
281 } else
282 tmp |= AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
283 } else if (mode1) {
284 tmp |= DC_LB_MEMORY_SPLIT_D1_ONLY;
285 } else if (mode2) {
286 tmp |= DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
287 }
288 WREG32(DC_LB_MEMORY_SPLIT, tmp);
771fe6b9
JG		 289}
290
c93bb85b
JG		 291struct rs690_watermark {
292 u32 lb_request_fifo_depth;
293 fixed20_12 num_line_pair;
294 fixed20_12 estimated_width;
295 fixed20_12 worst_case_latency;
296 fixed20_12 consumption_rate;
297 fixed20_12 active_time;
298 fixed20_12 dbpp;
299 fixed20_12 priority_mark_max;
300 fixed20_12 priority_mark;
301 fixed20_12 sclk;
302};
303
304void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
305 struct radeon_crtc *crtc,
306 struct rs690_watermark *wm)
307{
308 struct drm_display_mode *mode = &crtc->base.mode;
309 fixed20_12 a, b, c;
310 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
311 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
312 /* FIXME: detect IGP with sideport memory, i don't think there is any
313 * such product available
314 */
315 bool sideport = false;
316
317 if (!crtc->base.enabled) {
318 /* FIXME: wouldn't it better to set priority mark to maximum */
319 wm->lb_request_fifo_depth = 4;
320 return;
321 }
322
323 if (crtc->vsc.full > rfixed_const(2))
324 wm->num_line_pair.full = rfixed_const(2);
325 else
326 wm->num_line_pair.full = rfixed_const(1);
327
328 b.full = rfixed_const(mode->crtc_hdisplay);
329 c.full = rfixed_const(256);
330 a.full = rfixed_mul(wm->num_line_pair, b);
331 request_fifo_depth.full = rfixed_div(a, c);
332 if (a.full < rfixed_const(4)) {
333 wm->lb_request_fifo_depth = 4;
334 } else {
335 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
336 }
337
338 /* Determine consumption rate
339 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
340 * vtaps = number of vertical taps,
341 * vsc = vertical scaling ratio, defined as source/destination
342 * hsc = horizontal scaling ration, defined as source/destination
343 */
344 a.full = rfixed_const(mode->clock);
345 b.full = rfixed_const(1000);
346 a.full = rfixed_div(a, b);
347 pclk.full = rfixed_div(b, a);
348 if (crtc->rmx_type != RMX_OFF) {
349 b.full = rfixed_const(2);
350 if (crtc->vsc.full > b.full)
351 b.full = crtc->vsc.full;
352 b.full = rfixed_mul(b, crtc->hsc);
353 c.full = rfixed_const(2);
354 b.full = rfixed_div(b, c);
355 consumption_time.full = rfixed_div(pclk, b);
356 } else {
357 consumption_time.full = pclk.full;
358 }
359 a.full = rfixed_const(1);
360 wm->consumption_rate.full = rfixed_div(a, consumption_time);
361
362
363 /* Determine line time
364 * LineTime = total time for one line of displayhtotal
365 * LineTime = total number of horizontal pixels
366 * pclk = pixel clock period(ns)
367 */
368 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
369 line_time.full = rfixed_mul(a, pclk);
370
371 /* Determine active time
372 * ActiveTime = time of active region of display within one line,
373 * hactive = total number of horizontal active pixels
374 * htotal = total number of horizontal pixels
375 */
376 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
377 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
378 wm->active_time.full = rfixed_mul(line_time, b);
379 wm->active_time.full = rfixed_div(wm->active_time, a);
380
381 /* Maximun bandwidth is the minimun bandwidth of all component */
382 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
383 if (sideport) {
384 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
385 rdev->pm.sideport_bandwidth.full)
386 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
387 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
388 read_delay_latency.full = rfixed_div(read_delay_latency,
389 rdev->pm.igp_sideport_mclk);
390 } else {
391 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
392 rdev->pm.k8_bandwidth.full)
393 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
394 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
395 rdev->pm.ht_bandwidth.full)
396 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
397 read_delay_latency.full = rfixed_const(5000);
398 }
399
400 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
401 a.full = rfixed_const(16);
402 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
403 a.full = rfixed_const(1000);
404 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
405 /* Determine chunk time
406 * ChunkTime = the time it takes the DCP to send one chunk of data
407 * to the LB which consists of pipeline delay and inter chunk gap
408 * sclk = system clock(ns)
409 */
410 a.full = rfixed_const(256 * 13);
411 chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
412 a.full = rfixed_const(10);
413 chunk_time.full = rfixed_div(chunk_time, a);
414
415 /* Determine the worst case latency
416 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
417 * WorstCaseLatency = worst case time from urgent to when the MC starts
418 * to return data
419 * READ_DELAY_IDLE_MAX = constant of 1us
420 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
421 * which consists of pipeline delay and inter chunk gap
422 */
423 if (rfixed_trunc(wm->num_line_pair) > 1) {
424 a.full = rfixed_const(3);
425 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
426 wm->worst_case_latency.full += read_delay_latency.full;
427 } else {
428 a.full = rfixed_const(2);
429 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
430 wm->worst_case_latency.full += read_delay_latency.full;
431 }
432
433 /* Determine the tolerable latency
434 * TolerableLatency = Any given request has only 1 line time
435 * for the data to be returned
436 * LBRequestFifoDepth = Number of chunk requests the LB can
437 * put into the request FIFO for a display
438 * LineTime = total time for one line of display
439 * ChunkTime = the time it takes the DCP to send one chunk
440 * of data to the LB which consists of
441 * pipeline delay and inter chunk gap
442 */
443 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
444 tolerable_latency.full = line_time.full;
445 } else {
446 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
447 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
448 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
449 tolerable_latency.full = line_time.full - tolerable_latency.full;
450 }
451 /* We assume worst case 32bits (4 bytes) */
452 wm->dbpp.full = rfixed_const(4 * 8);
453
454 /* Determine the maximum priority mark
455 * width = viewport width in pixels
456 */
457 a.full = rfixed_const(16);
458 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
459 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
460
461 /* Determine estimated width */
462 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
463 estimated_width.full = rfixed_div(estimated_width, consumption_time);
464 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
465 wm->priority_mark.full = rfixed_const(10);
466 } else {
467 a.full = rfixed_const(16);
468 wm->priority_mark.full = rfixed_div(estimated_width, a);
469 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
470 }
471}
472
473void rs690_bandwidth_update(struct radeon_device *rdev)
474{
475 struct drm_display_mode *mode0 = NULL;
476 struct drm_display_mode *mode1 = NULL;
477 struct rs690_watermark wm0;
478 struct rs690_watermark wm1;
479 u32 tmp;
480 fixed20_12 priority_mark02, priority_mark12, fill_rate;
481 fixed20_12 a, b;
482
483 if (rdev->mode_info.crtcs[0]->base.enabled)
484 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
485 if (rdev->mode_info.crtcs[1]->base.enabled)
486 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
487 /*
488 * Set display0/1 priority up in the memory controller for
489 * modes if the user specifies HIGH for displaypriority
490 * option.
491 */
492 if (rdev->disp_priority == 2) {
493 tmp = RREG32_MC(MC_INIT_MISC_LAT_TIMER);
494 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
495 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
496 if (mode1)
497 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
498 if (mode0)
499 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
500 WREG32_MC(MC_INIT_MISC_LAT_TIMER, tmp);
501 }
502 rs690_line_buffer_adjust(rdev, mode0, mode1);
503
504 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
505 WREG32(DCP_CONTROL, 0);
506 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
507 WREG32(DCP_CONTROL, 2);
508
509 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
510 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
511
512 tmp = (wm0.lb_request_fifo_depth - 1);
513 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
514 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
515
516 if (mode0 && mode1) {
517 if (rfixed_trunc(wm0.dbpp) > 64)
518 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
519 else
520 a.full = wm0.num_line_pair.full;
521 if (rfixed_trunc(wm1.dbpp) > 64)
522 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
523 else
524 b.full = wm1.num_line_pair.full;
525 a.full += b.full;
526 fill_rate.full = rfixed_div(wm0.sclk, a);
527 if (wm0.consumption_rate.full > fill_rate.full) {
528 b.full = wm0.consumption_rate.full - fill_rate.full;
529 b.full = rfixed_mul(b, wm0.active_time);
530 a.full = rfixed_mul(wm0.worst_case_latency,
531 wm0.consumption_rate);
532 a.full = a.full + b.full;
533 b.full = rfixed_const(16 * 1000);
534 priority_mark02.full = rfixed_div(a, b);
535 } else {
536 a.full = rfixed_mul(wm0.worst_case_latency,
537 wm0.consumption_rate);
538 b.full = rfixed_const(16 * 1000);
539 priority_mark02.full = rfixed_div(a, b);
540 }
541 if (wm1.consumption_rate.full > fill_rate.full) {
542 b.full = wm1.consumption_rate.full - fill_rate.full;
543 b.full = rfixed_mul(b, wm1.active_time);
544 a.full = rfixed_mul(wm1.worst_case_latency,
545 wm1.consumption_rate);
546 a.full = a.full + b.full;
547 b.full = rfixed_const(16 * 1000);
548 priority_mark12.full = rfixed_div(a, b);
549 } else {
550 a.full = rfixed_mul(wm1.worst_case_latency,
551 wm1.consumption_rate);
552 b.full = rfixed_const(16 * 1000);
553 priority_mark12.full = rfixed_div(a, b);
554 }
555 if (wm0.priority_mark.full > priority_mark02.full)
556 priority_mark02.full = wm0.priority_mark.full;
557 if (rfixed_trunc(priority_mark02) < 0)
558 priority_mark02.full = 0;
559 if (wm0.priority_mark_max.full > priority_mark02.full)
560 priority_mark02.full = wm0.priority_mark_max.full;
561 if (wm1.priority_mark.full > priority_mark12.full)
562 priority_mark12.full = wm1.priority_mark.full;
563 if (rfixed_trunc(priority_mark12) < 0)
564 priority_mark12.full = 0;
565 if (wm1.priority_mark_max.full > priority_mark12.full)
566 priority_mark12.full = wm1.priority_mark_max.full;
567 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
568 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
569 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
570 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
571 } else if (mode0) {
572 if (rfixed_trunc(wm0.dbpp) > 64)
573 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
574 else
575 a.full = wm0.num_line_pair.full;
576 fill_rate.full = rfixed_div(wm0.sclk, a);
577 if (wm0.consumption_rate.full > fill_rate.full) {
578 b.full = wm0.consumption_rate.full - fill_rate.full;
579 b.full = rfixed_mul(b, wm0.active_time);
580 a.full = rfixed_mul(wm0.worst_case_latency,
581 wm0.consumption_rate);
582 a.full = a.full + b.full;
583 b.full = rfixed_const(16 * 1000);
584 priority_mark02.full = rfixed_div(a, b);
585 } else {
586 a.full = rfixed_mul(wm0.worst_case_latency,
587 wm0.consumption_rate);
588 b.full = rfixed_const(16 * 1000);
589 priority_mark02.full = rfixed_div(a, b);
590 }
591 if (wm0.priority_mark.full > priority_mark02.full)
592 priority_mark02.full = wm0.priority_mark.full;
593 if (rfixed_trunc(priority_mark02) < 0)
594 priority_mark02.full = 0;
595 if (wm0.priority_mark_max.full > priority_mark02.full)
596 priority_mark02.full = wm0.priority_mark_max.full;
597 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
598 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
599 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
600 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
601 } else {
602 if (rfixed_trunc(wm1.dbpp) > 64)
603 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
604 else
605 a.full = wm1.num_line_pair.full;
606 fill_rate.full = rfixed_div(wm1.sclk, a);
607 if (wm1.consumption_rate.full > fill_rate.full) {
608 b.full = wm1.consumption_rate.full - fill_rate.full;
609 b.full = rfixed_mul(b, wm1.active_time);
610 a.full = rfixed_mul(wm1.worst_case_latency,
611 wm1.consumption_rate);
612 a.full = a.full + b.full;
613 b.full = rfixed_const(16 * 1000);
614 priority_mark12.full = rfixed_div(a, b);
615 } else {
616 a.full = rfixed_mul(wm1.worst_case_latency,
617 wm1.consumption_rate);
618 b.full = rfixed_const(16 * 1000);
619 priority_mark12.full = rfixed_div(a, b);
620 }
621 if (wm1.priority_mark.full > priority_mark12.full)
622 priority_mark12.full = wm1.priority_mark.full;
623 if (rfixed_trunc(priority_mark12) < 0)
624 priority_mark12.full = 0;
625 if (wm1.priority_mark_max.full > priority_mark12.full)
626 priority_mark12.full = wm1.priority_mark_max.full;
627 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
628 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
629 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
630 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
631 }
632}
771fe6b9
JG		 633
634/*
635 * Indirect registers accessor
636 */
637uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
638{
639 uint32_t r;
640
641 WREG32(RS690_MC_INDEX, (reg & RS690_MC_INDEX_MASK));
642 r = RREG32(RS690_MC_DATA);
643 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
644 return r;
645}
646
647void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
648{
649 WREG32(RS690_MC_INDEX,
650 RS690_MC_INDEX_WR_EN | ((reg) & RS690_MC_INDEX_MASK));
651 WREG32(RS690_MC_DATA, v);
652 WREG32(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK);
653}
Linux kernel - Deliverables
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