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drm/radeon/kms: remove lvds quirks
[deliverable/linux.git] / drivers / gpu / drm / radeon / rs690.c
CommitLineData
771fe6b9
JG		 1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
771fe6b9 29#include "radeon.h"
e6990375 30#include "radeon_asic.h"
c93bb85b 31#include "atom.h"
3bc68535 32#include "rs690d.h"
771fe6b9 33
3bc68535 34static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
771fe6b9
JG		 35{
36 unsigned i;
37 uint32_t tmp;
38
39 for (i = 0; i < rdev->usec_timeout; i++) {
40 /* read MC_STATUS */
3bc68535
JG		 41 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42 if (G_000090_MC_SYSTEM_IDLE(tmp))
771fe6b9 43 return 0;
3bc68535 44 udelay(1);
771fe6b9
JG		 45 }
46 return -1;
47}
48
3bc68535 49static void rs690_gpu_init(struct radeon_device *rdev)
771fe6b9
JG		 50{
51 /* FIXME: HDP same place on rs690 ? */
52 r100_hdp_reset(rdev);
771fe6b9
JG		 53 /* FIXME: is this correct ? */
54 r420_pipes_init(rdev);
55 if (rs690_mc_wait_for_idle(rdev)) {
56 printk(KERN_WARNING "Failed to wait MC idle while "
57 "programming pipes. Bad things might happen.\n");
58 }
59}
60
c93bb85b
JG		 61void rs690_pm_info(struct radeon_device *rdev)
62{
63 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
64 struct _ATOM_INTEGRATED_SYSTEM_INFO *info;
65 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *info_v2;
66 void *ptr;
67 uint16_t data_offset;
68 uint8_t frev, crev;
69 fixed20_12 tmp;
70
71 atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
72 &frev, &crev, &data_offset);
73 ptr = rdev->mode_info.atom_context->bios + data_offset;
74 info = (struct _ATOM_INTEGRATED_SYSTEM_INFO *)ptr;
75 info_v2 = (struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 *)ptr;
76 /* Get various system informations from bios */
77 switch (crev) {
78 case 1:
79 tmp.full = rfixed_const(100);
80 rdev->pm.igp_sideport_mclk.full = rfixed_const(info->ulBootUpMemoryClock);
81 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82 rdev->pm.igp_system_mclk.full = rfixed_const(le16_to_cpu(info->usK8MemoryClock));
83 rdev->pm.igp_ht_link_clk.full = rfixed_const(le16_to_cpu(info->usFSBClock));
84 rdev->pm.igp_ht_link_width.full = rfixed_const(info->ucHTLinkWidth);
85 break;
86 case 2:
87 tmp.full = rfixed_const(100);
88 rdev->pm.igp_sideport_mclk.full = rfixed_const(info_v2->ulBootUpSidePortClock);
89 rdev->pm.igp_sideport_mclk.full = rfixed_div(rdev->pm.igp_sideport_mclk, tmp);
90 rdev->pm.igp_system_mclk.full = rfixed_const(info_v2->ulBootUpUMAClock);
91 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
92 rdev->pm.igp_ht_link_clk.full = rfixed_const(info_v2->ulHTLinkFreq);
93 rdev->pm.igp_ht_link_clk.full = rfixed_div(rdev->pm.igp_ht_link_clk, tmp);
94 rdev->pm.igp_ht_link_width.full = rfixed_const(le16_to_cpu(info_v2->usMinHTLinkWidth));
95 break;
96 default:
97 tmp.full = rfixed_const(100);
98 /* We assume the slower possible clock ie worst case */
99 /* DDR 333Mhz */
100 rdev->pm.igp_sideport_mclk.full = rfixed_const(333);
101 /* FIXME: system clock ? */
102 rdev->pm.igp_system_mclk.full = rfixed_const(100);
103 rdev->pm.igp_system_mclk.full = rfixed_div(rdev->pm.igp_system_mclk, tmp);
104 rdev->pm.igp_ht_link_clk.full = rfixed_const(200);
105 rdev->pm.igp_ht_link_width.full = rfixed_const(8);
106 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
107 break;
108 }
109 /* Compute various bandwidth */
110 /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4 */
111 tmp.full = rfixed_const(4);
112 rdev->pm.k8_bandwidth.full = rfixed_mul(rdev->pm.igp_system_mclk, tmp);
113 /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
114 * = ht_clk * ht_width / 5
115 */
116 tmp.full = rfixed_const(5);
117 rdev->pm.ht_bandwidth.full = rfixed_mul(rdev->pm.igp_ht_link_clk,
118 rdev->pm.igp_ht_link_width);
119 rdev->pm.ht_bandwidth.full = rfixed_div(rdev->pm.ht_bandwidth, tmp);
120 if (tmp.full < rdev->pm.max_bandwidth.full) {
121 /* HT link is a limiting factor */
122 rdev->pm.max_bandwidth.full = tmp.full;
123 }
124 /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
125 * = (sideport_clk * 14) / 10
126 */
127 tmp.full = rfixed_const(14);
128 rdev->pm.sideport_bandwidth.full = rfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
129 tmp.full = rfixed_const(10);
130 rdev->pm.sideport_bandwidth.full = rfixed_div(rdev->pm.sideport_bandwidth, tmp);
131}
132
d594e46a 133void rs690_mc_init(struct radeon_device *rdev)
771fe6b9 134{
d594e46a 135 u64 base;
771fe6b9
JG		 136
137 rs400_gart_adjust_size(rdev);
771fe6b9 138 rdev->mc.vram_is_ddr = true;
722f2943 139 rdev->mc.vram_width = 128;
7a50f01a
DA		 140 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
141 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
771fe6b9
JG		 142 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
143 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
51e5fcd3 144 rdev->mc.visible_vram_size = rdev->mc.aper_size;
d594e46a
JG		 145 base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
146 base = G_000100_MC_FB_START(base) << 16;
c93bb85b 147 rs690_pm_info(rdev);
06b6476d 148 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
d594e46a
JG		 149 radeon_vram_location(rdev, &rdev->mc, base);
150 radeon_gtt_location(rdev, &rdev->mc);
f47299c5 151 radeon_update_bandwidth_info(rdev);
22dd5013
AD		 152}
153
c93bb85b
JG		 154void rs690_line_buffer_adjust(struct radeon_device *rdev,
155 struct drm_display_mode *mode1,
156 struct drm_display_mode *mode2)
157{
158 u32 tmp;
159
160 /*
161 * Line Buffer Setup
162 * There is a single line buffer shared by both display controllers.
3bc68535 163 * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
c93bb85b
JG		 164 * the display controllers. The paritioning can either be done
165 * manually or via one of four preset allocations specified in bits 1:0:
166 * 0 - line buffer is divided in half and shared between crtc
167 * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
168 * 2 - D1 gets the whole buffer
169 * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
3bc68535 170 * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
c93bb85b
JG		 171 * allocation mode. In manual allocation mode, D1 always starts at 0,
172 * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
173 */
3bc68535
JG		 174 tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
175 tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
c93bb85b
JG		 176 /* auto */
177 if (mode1 && mode2) {
178 if (mode1->hdisplay > mode2->hdisplay) {
179 if (mode1->hdisplay > 2560)
3bc68535 180 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
c93bb85b 181 else
3bc68535 182 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b
JG		 183 } else if (mode2->hdisplay > mode1->hdisplay) {
184 if (mode2->hdisplay > 2560)
3bc68535 185 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 186 else
3bc68535 187 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 188 } else
3bc68535 189 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
c93bb85b 190 } else if (mode1) {
3bc68535 191 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
c93bb85b 192 } else if (mode2) {
3bc68535 193 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
c93bb85b 194 }
3bc68535 195 WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
771fe6b9
JG		 196}
197
c93bb85b
JG		 198struct rs690_watermark {
199 u32 lb_request_fifo_depth;
200 fixed20_12 num_line_pair;
201 fixed20_12 estimated_width;
202 fixed20_12 worst_case_latency;
203 fixed20_12 consumption_rate;
204 fixed20_12 active_time;
205 fixed20_12 dbpp;
206 fixed20_12 priority_mark_max;
207 fixed20_12 priority_mark;
208 fixed20_12 sclk;
209};
210
211void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
212 struct radeon_crtc *crtc,
213 struct rs690_watermark *wm)
214{
215 struct drm_display_mode *mode = &crtc->base.mode;
216 fixed20_12 a, b, c;
217 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
218 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
219 /* FIXME: detect IGP with sideport memory, i don't think there is any
220 * such product available
221 */
222 bool sideport = false;
223
224 if (!crtc->base.enabled) {
225 /* FIXME: wouldn't it better to set priority mark to maximum */
226 wm->lb_request_fifo_depth = 4;
227 return;
228 }
229
230 if (crtc->vsc.full > rfixed_const(2))
231 wm->num_line_pair.full = rfixed_const(2);
232 else
233 wm->num_line_pair.full = rfixed_const(1);
234
235 b.full = rfixed_const(mode->crtc_hdisplay);
236 c.full = rfixed_const(256);
69b3b5e5
AD		 237 a.full = rfixed_div(b, c);
238 request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
239 request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
c93bb85b
JG		 240 if (a.full < rfixed_const(4)) {
241 wm->lb_request_fifo_depth = 4;
242 } else {
243 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
244 }
245
246 /* Determine consumption rate
247 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
248 * vtaps = number of vertical taps,
249 * vsc = vertical scaling ratio, defined as source/destination
250 * hsc = horizontal scaling ration, defined as source/destination
251 */
252 a.full = rfixed_const(mode->clock);
253 b.full = rfixed_const(1000);
254 a.full = rfixed_div(a, b);
255 pclk.full = rfixed_div(b, a);
256 if (crtc->rmx_type != RMX_OFF) {
257 b.full = rfixed_const(2);
258 if (crtc->vsc.full > b.full)
259 b.full = crtc->vsc.full;
260 b.full = rfixed_mul(b, crtc->hsc);
261 c.full = rfixed_const(2);
262 b.full = rfixed_div(b, c);
263 consumption_time.full = rfixed_div(pclk, b);
264 } else {
265 consumption_time.full = pclk.full;
266 }
267 a.full = rfixed_const(1);
268 wm->consumption_rate.full = rfixed_div(a, consumption_time);
269
270
271 /* Determine line time
272 * LineTime = total time for one line of displayhtotal
273 * LineTime = total number of horizontal pixels
274 * pclk = pixel clock period(ns)
275 */
276 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
277 line_time.full = rfixed_mul(a, pclk);
278
279 /* Determine active time
280 * ActiveTime = time of active region of display within one line,
281 * hactive = total number of horizontal active pixels
282 * htotal = total number of horizontal pixels
283 */
284 a.full = rfixed_const(crtc->base.mode.crtc_htotal);
285 b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
286 wm->active_time.full = rfixed_mul(line_time, b);
287 wm->active_time.full = rfixed_div(wm->active_time, a);
288
289 /* Maximun bandwidth is the minimun bandwidth of all component */
290 rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
291 if (sideport) {
292 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
293 rdev->pm.sideport_bandwidth.full)
294 rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
295 read_delay_latency.full = rfixed_const(370 * 800 * 1000);
296 read_delay_latency.full = rfixed_div(read_delay_latency,
297 rdev->pm.igp_sideport_mclk);
298 } else {
299 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
300 rdev->pm.k8_bandwidth.full)
301 rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
302 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
303 rdev->pm.ht_bandwidth.full)
304 rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
305 read_delay_latency.full = rfixed_const(5000);
306 }
307
308 /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
309 a.full = rfixed_const(16);
310 rdev->pm.sclk.full = rfixed_mul(rdev->pm.max_bandwidth, a);
311 a.full = rfixed_const(1000);
312 rdev->pm.sclk.full = rfixed_div(a, rdev->pm.sclk);
313 /* Determine chunk time
314 * ChunkTime = the time it takes the DCP to send one chunk of data
315 * to the LB which consists of pipeline delay and inter chunk gap
316 * sclk = system clock(ns)
317 */
318 a.full = rfixed_const(256 * 13);
319 chunk_time.full = rfixed_mul(rdev->pm.sclk, a);
320 a.full = rfixed_const(10);
321 chunk_time.full = rfixed_div(chunk_time, a);
322
323 /* Determine the worst case latency
324 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
325 * WorstCaseLatency = worst case time from urgent to when the MC starts
326 * to return data
327 * READ_DELAY_IDLE_MAX = constant of 1us
328 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
329 * which consists of pipeline delay and inter chunk gap
330 */
331 if (rfixed_trunc(wm->num_line_pair) > 1) {
332 a.full = rfixed_const(3);
333 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
334 wm->worst_case_latency.full += read_delay_latency.full;
335 } else {
336 a.full = rfixed_const(2);
337 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
338 wm->worst_case_latency.full += read_delay_latency.full;
339 }
340
341 /* Determine the tolerable latency
342 * TolerableLatency = Any given request has only 1 line time
343 * for the data to be returned
344 * LBRequestFifoDepth = Number of chunk requests the LB can
345 * put into the request FIFO for a display
346 * LineTime = total time for one line of display
347 * ChunkTime = the time it takes the DCP to send one chunk
348 * of data to the LB which consists of
349 * pipeline delay and inter chunk gap
350 */
351 if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
352 tolerable_latency.full = line_time.full;
353 } else {
354 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
355 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
356 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
357 tolerable_latency.full = line_time.full - tolerable_latency.full;
358 }
359 /* We assume worst case 32bits (4 bytes) */
360 wm->dbpp.full = rfixed_const(4 * 8);
361
362 /* Determine the maximum priority mark
363 * width = viewport width in pixels
364 */
365 a.full = rfixed_const(16);
366 wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
367 wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
69b3b5e5 368 wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
c93bb85b
JG		 369
370 /* Determine estimated width */
371 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
372 estimated_width.full = rfixed_div(estimated_width, consumption_time);
373 if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
374 wm->priority_mark.full = rfixed_const(10);
375 } else {
376 a.full = rfixed_const(16);
377 wm->priority_mark.full = rfixed_div(estimated_width, a);
69b3b5e5 378 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
c93bb85b
JG		 379 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
380 }
381}
382
383void rs690_bandwidth_update(struct radeon_device *rdev)
384{
385 struct drm_display_mode *mode0 = NULL;
386 struct drm_display_mode *mode1 = NULL;
387 struct rs690_watermark wm0;
388 struct rs690_watermark wm1;
389 u32 tmp;
390 fixed20_12 priority_mark02, priority_mark12, fill_rate;
391 fixed20_12 a, b;
392
393 if (rdev->mode_info.crtcs[0]->base.enabled)
394 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
395 if (rdev->mode_info.crtcs[1]->base.enabled)
396 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
397 /*
398 * Set display0/1 priority up in the memory controller for
399 * modes if the user specifies HIGH for displaypriority
400 * option.
401 */
402 if (rdev->disp_priority == 2) {
3bc68535
JG		 403 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
404 tmp &= C_000104_MC_DISP0R_INIT_LAT;
405 tmp &= C_000104_MC_DISP1R_INIT_LAT;
c93bb85b 406 if (mode0)
3bc68535
JG		 407 tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
408 if (mode1)
409 tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
410 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
c93bb85b
JG		 411 }
412 rs690_line_buffer_adjust(rdev, mode0, mode1);
413
414 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
3bc68535 415 WREG32(R_006C9C_DCP_CONTROL, 0);
c93bb85b 416 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
3bc68535 417 WREG32(R_006C9C_DCP_CONTROL, 2);
c93bb85b
JG		 418
419 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
420 rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
421
422 tmp = (wm0.lb_request_fifo_depth - 1);
423 tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
3bc68535 424 WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
c93bb85b
JG		 425
426 if (mode0 && mode1) {
427 if (rfixed_trunc(wm0.dbpp) > 64)
428 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
429 else
430 a.full = wm0.num_line_pair.full;
431 if (rfixed_trunc(wm1.dbpp) > 64)
432 b.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
433 else
434 b.full = wm1.num_line_pair.full;
435 a.full += b.full;
436 fill_rate.full = rfixed_div(wm0.sclk, a);
437 if (wm0.consumption_rate.full > fill_rate.full) {
438 b.full = wm0.consumption_rate.full - fill_rate.full;
439 b.full = rfixed_mul(b, wm0.active_time);
440 a.full = rfixed_mul(wm0.worst_case_latency,
441 wm0.consumption_rate);
442 a.full = a.full + b.full;
443 b.full = rfixed_const(16 * 1000);
444 priority_mark02.full = rfixed_div(a, b);
445 } else {
446 a.full = rfixed_mul(wm0.worst_case_latency,
447 wm0.consumption_rate);
448 b.full = rfixed_const(16 * 1000);
449 priority_mark02.full = rfixed_div(a, b);
450 }
451 if (wm1.consumption_rate.full > fill_rate.full) {
452 b.full = wm1.consumption_rate.full - fill_rate.full;
453 b.full = rfixed_mul(b, wm1.active_time);
454 a.full = rfixed_mul(wm1.worst_case_latency,
455 wm1.consumption_rate);
456 a.full = a.full + b.full;
457 b.full = rfixed_const(16 * 1000);
458 priority_mark12.full = rfixed_div(a, b);
459 } else {
460 a.full = rfixed_mul(wm1.worst_case_latency,
461 wm1.consumption_rate);
462 b.full = rfixed_const(16 * 1000);
463 priority_mark12.full = rfixed_div(a, b);
464 }
465 if (wm0.priority_mark.full > priority_mark02.full)
466 priority_mark02.full = wm0.priority_mark.full;
467 if (rfixed_trunc(priority_mark02) < 0)
468 priority_mark02.full = 0;
469 if (wm0.priority_mark_max.full > priority_mark02.full)
470 priority_mark02.full = wm0.priority_mark_max.full;
471 if (wm1.priority_mark.full > priority_mark12.full)
472 priority_mark12.full = wm1.priority_mark.full;
473 if (rfixed_trunc(priority_mark12) < 0)
474 priority_mark12.full = 0;
475 if (wm1.priority_mark_max.full > priority_mark12.full)
476 priority_mark12.full = wm1.priority_mark_max.full;
3bc68535
JG		 477 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
478 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
479 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
480 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
c93bb85b
JG		 481 } else if (mode0) {
482 if (rfixed_trunc(wm0.dbpp) > 64)
483 a.full = rfixed_mul(wm0.dbpp, wm0.num_line_pair);
484 else
485 a.full = wm0.num_line_pair.full;
486 fill_rate.full = rfixed_div(wm0.sclk, a);
487 if (wm0.consumption_rate.full > fill_rate.full) {
488 b.full = wm0.consumption_rate.full - fill_rate.full;
489 b.full = rfixed_mul(b, wm0.active_time);
490 a.full = rfixed_mul(wm0.worst_case_latency,
491 wm0.consumption_rate);
492 a.full = a.full + b.full;
493 b.full = rfixed_const(16 * 1000);
494 priority_mark02.full = rfixed_div(a, b);
495 } else {
496 a.full = rfixed_mul(wm0.worst_case_latency,
497 wm0.consumption_rate);
498 b.full = rfixed_const(16 * 1000);
499 priority_mark02.full = rfixed_div(a, b);
500 }
501 if (wm0.priority_mark.full > priority_mark02.full)
502 priority_mark02.full = wm0.priority_mark.full;
503 if (rfixed_trunc(priority_mark02) < 0)
504 priority_mark02.full = 0;
505 if (wm0.priority_mark_max.full > priority_mark02.full)
506 priority_mark02.full = wm0.priority_mark_max.full;
3bc68535
JG		 507 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
508 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
509 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT,
510 S_006D48_D2MODE_PRIORITY_A_OFF(1));
511 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT,
512 S_006D4C_D2MODE_PRIORITY_B_OFF(1));
c93bb85b
JG		 513 } else {
514 if (rfixed_trunc(wm1.dbpp) > 64)
515 a.full = rfixed_mul(wm1.dbpp, wm1.num_line_pair);
516 else
517 a.full = wm1.num_line_pair.full;
518 fill_rate.full = rfixed_div(wm1.sclk, a);
519 if (wm1.consumption_rate.full > fill_rate.full) {
520 b.full = wm1.consumption_rate.full - fill_rate.full;
521 b.full = rfixed_mul(b, wm1.active_time);
522 a.full = rfixed_mul(wm1.worst_case_latency,
523 wm1.consumption_rate);
524 a.full = a.full + b.full;
525 b.full = rfixed_const(16 * 1000);
526 priority_mark12.full = rfixed_div(a, b);
527 } else {
528 a.full = rfixed_mul(wm1.worst_case_latency,
529 wm1.consumption_rate);
530 b.full = rfixed_const(16 * 1000);
531 priority_mark12.full = rfixed_div(a, b);
532 }
533 if (wm1.priority_mark.full > priority_mark12.full)
534 priority_mark12.full = wm1.priority_mark.full;
535 if (rfixed_trunc(priority_mark12) < 0)
536 priority_mark12.full = 0;
537 if (wm1.priority_mark_max.full > priority_mark12.full)
538 priority_mark12.full = wm1.priority_mark_max.full;
3bc68535
JG		 539 WREG32(R_006548_D1MODE_PRIORITY_A_CNT,
540 S_006548_D1MODE_PRIORITY_A_OFF(1));
541 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT,
542 S_00654C_D1MODE_PRIORITY_B_OFF(1));
543 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
544 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
c93bb85b
JG		 545 }
546}
771fe6b9 547
771fe6b9
JG		 548uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
549{
550 uint32_t r;
551
3bc68535
JG		 552 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
553 r = RREG32(R_00007C_MC_DATA);
554 WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
771fe6b9
JG		 555 return r;
556}
557
558void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
559{
3bc68535
JG		 560 WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
561 S_000078_MC_IND_WR_EN(1));
562 WREG32(R_00007C_MC_DATA, v);
563 WREG32(R_000078_MC_INDEX, 0x7F);
564}
565
566void rs690_mc_program(struct radeon_device *rdev)
567{
568 struct rv515_mc_save save;
569
570 /* Stops all mc clients */
571 rv515_mc_stop(rdev, &save);
572
573 /* Wait for mc idle */
574 if (rs690_mc_wait_for_idle(rdev))
575 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
576 /* Program MC, should be a 32bits limited address space */
577 WREG32_MC(R_000100_MCCFG_FB_LOCATION,
578 S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
579 S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
580 WREG32(R_000134_HDP_FB_LOCATION,
581 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
582
583 rv515_mc_resume(rdev, &save);
584}
585
586static int rs690_startup(struct radeon_device *rdev)
587{
588 int r;
589
590 rs690_mc_program(rdev);
591 /* Resume clock */
592 rv515_clock_startup(rdev);
593 /* Initialize GPU configuration (# pipes, ...) */
594 rs690_gpu_init(rdev);
595 /* Initialize GART (initialize after TTM so we can allocate
596 * memory through TTM but finalize after TTM) */
597 r = rs400_gart_enable(rdev);
598 if (r)
599 return r;
600 /* Enable IRQ */
ac447df4 601 rs600_irq_set(rdev);
cafe6609 602 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3bc68535
JG		 603 /* 1M ring buffer */
604 r = r100_cp_init(rdev, 1024 * 1024);
605 if (r) {
606 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
607 return r;
608 }
609 r = r100_wb_init(rdev);
610 if (r)
611 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
612 r = r100_ib_init(rdev);
613 if (r) {
614 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
615 return r;
616 }
617 return 0;
618}
619
620int rs690_resume(struct radeon_device *rdev)
621{
622 /* Make sur GART are not working */
623 rs400_gart_disable(rdev);
624 /* Resume clock before doing reset */
625 rv515_clock_startup(rdev);
626 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
627 if (radeon_gpu_reset(rdev)) {
628 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
629 RREG32(R_000E40_RBBM_STATUS),
630 RREG32(R_0007C0_CP_STAT));
631 }
632 /* post */
633 atom_asic_init(rdev->mode_info.atom_context);
634 /* Resume clock after posting */
635 rv515_clock_startup(rdev);
550e2d92
DA		 636 /* Initialize surface registers */
637 radeon_surface_init(rdev);
3bc68535
JG		 638 return rs690_startup(rdev);
639}
640
641int rs690_suspend(struct radeon_device *rdev)
642{
643 r100_cp_disable(rdev);
644 r100_wb_disable(rdev);
ac447df4 645 rs600_irq_disable(rdev);
3bc68535
JG		 646 rs400_gart_disable(rdev);
647 return 0;
648}
649
650void rs690_fini(struct radeon_device *rdev)
651{
29fb52ca 652 radeon_pm_fini(rdev);
3bc68535
JG		 653 r100_cp_fini(rdev);
654 r100_wb_fini(rdev);
655 r100_ib_fini(rdev);
656 radeon_gem_fini(rdev);
657 rs400_gart_fini(rdev);
658 radeon_irq_kms_fini(rdev);
659 radeon_fence_driver_fini(rdev);
4c788679 660 radeon_bo_fini(rdev);
3bc68535
JG		 661 radeon_atombios_fini(rdev);
662 kfree(rdev->bios);
663 rdev->bios = NULL;
664}
665
666int rs690_init(struct radeon_device *rdev)
667{
668 int r;
669
3bc68535
JG		 670 /* Disable VGA */
671 rv515_vga_render_disable(rdev);
672 /* Initialize scratch registers */
673 radeon_scratch_init(rdev);
674 /* Initialize surface registers */
675 radeon_surface_init(rdev);
676 /* TODO: disable VGA need to use VGA request */
677 /* BIOS*/
678 if (!radeon_get_bios(rdev)) {
679 if (ASIC_IS_AVIVO(rdev))
680 return -EINVAL;
681 }
682 if (rdev->is_atom_bios) {
683 r = radeon_atombios_init(rdev);
684 if (r)
685 return r;
686 } else {
687 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
688 return -EINVAL;
689 }
690 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
691 if (radeon_gpu_reset(rdev)) {
692 dev_warn(rdev->dev,
693 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
694 RREG32(R_000E40_RBBM_STATUS),
695 RREG32(R_0007C0_CP_STAT));
696 }
697 /* check if cards are posted or not */
72542d77
DA		 698 if (radeon_boot_test_post_card(rdev) == false)
699 return -EINVAL;
700
3bc68535
JG		 701 /* Initialize clocks */
702 radeon_get_clock_info(rdev->ddev);
7433874e
RM		 703 /* Initialize power management */
704 radeon_pm_init(rdev);
d594e46a
JG		 705 /* initialize memory controller */
706 rs690_mc_init(rdev);
3bc68535
JG		 707 rv515_debugfs(rdev);
708 /* Fence driver */
709 r = radeon_fence_driver_init(rdev);
710 if (r)
711 return r;
712 r = radeon_irq_kms_init(rdev);
713 if (r)
714 return r;
715 /* Memory manager */
4c788679 716 r = radeon_bo_init(rdev);
3bc68535
JG		 717 if (r)
718 return r;
719 r = rs400_gart_init(rdev);
720 if (r)
721 return r;
722 rs600_set_safe_registers(rdev);
723 rdev->accel_working = true;
724 r = rs690_startup(rdev);
725 if (r) {
726 /* Somethings want wront with the accel init stop accel */
727 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3bc68535
JG		 728 r100_cp_fini(rdev);
729 r100_wb_fini(rdev);
730 r100_ib_fini(rdev);
731 rs400_gart_fini(rdev);
732 radeon_irq_kms_fini(rdev);
733 rdev->accel_working = false;
734 }
735 return 0;
771fe6b9 736}
Linux kernel - Deliverables
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