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drm/vmwgfx: Fix copyright headers
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_drv.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
54fbde8a 3 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA
fb1d9738
JB		 4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
e0cd3608 27#include <linux/module.h>
fb1d9738 28
760285e7 29#include <drm/drmP.h>
fb1d9738 30#include "vmwgfx_drv.h"
d80efd5c 31#include "vmwgfx_binding.h"
760285e7
DH		 32#include <drm/ttm/ttm_placement.h>
33#include <drm/ttm/ttm_bo_driver.h>
34#include <drm/ttm/ttm_object.h>
35#include <drm/ttm/ttm_module.h>
d92d9851 36#include <linux/dma_remapping.h>
fb1d9738
JB		 37
38#define VMWGFX_DRIVER_NAME "vmwgfx"
39#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
40#define VMWGFX_CHIP_SVGAII 0
41#define VMW_FB_RESERVATION 0
42
eb4f923b
JB		 43#define VMW_MIN_INITIAL_WIDTH 800
44#define VMW_MIN_INITIAL_HEIGHT 600
45
46
fb1d9738
JB		 47/**
48 * Fully encoded drm commands. Might move to vmw_drm.h
49 */
50
51#define DRM_IOCTL_VMW_GET_PARAM \
52 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \
53 struct drm_vmw_getparam_arg)
54#define DRM_IOCTL_VMW_ALLOC_DMABUF \
55 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \
56 union drm_vmw_alloc_dmabuf_arg)
57#define DRM_IOCTL_VMW_UNREF_DMABUF \
58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \
59 struct drm_vmw_unref_dmabuf_arg)
60#define DRM_IOCTL_VMW_CURSOR_BYPASS \
61 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \
62 struct drm_vmw_cursor_bypass_arg)
63
64#define DRM_IOCTL_VMW_CONTROL_STREAM \
65 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \
66 struct drm_vmw_control_stream_arg)
67#define DRM_IOCTL_VMW_CLAIM_STREAM \
68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \
69 struct drm_vmw_stream_arg)
70#define DRM_IOCTL_VMW_UNREF_STREAM \
71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \
72 struct drm_vmw_stream_arg)
73
74#define DRM_IOCTL_VMW_CREATE_CONTEXT \
75 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \
76 struct drm_vmw_context_arg)
77#define DRM_IOCTL_VMW_UNREF_CONTEXT \
78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \
79 struct drm_vmw_context_arg)
80#define DRM_IOCTL_VMW_CREATE_SURFACE \
81 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \
82 union drm_vmw_surface_create_arg)
83#define DRM_IOCTL_VMW_UNREF_SURFACE \
84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \
85 struct drm_vmw_surface_arg)
86#define DRM_IOCTL_VMW_REF_SURFACE \
87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \
88 union drm_vmw_surface_reference_arg)
89#define DRM_IOCTL_VMW_EXECBUF \
90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \
91 struct drm_vmw_execbuf_arg)
ae2a1040
TH		 92#define DRM_IOCTL_VMW_GET_3D_CAP \
93 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \
94 struct drm_vmw_get_3d_cap_arg)
fb1d9738
JB		 95#define DRM_IOCTL_VMW_FENCE_WAIT \
96 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \
97 struct drm_vmw_fence_wait_arg)
ae2a1040
TH		 98#define DRM_IOCTL_VMW_FENCE_SIGNALED \
99 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \
100 struct drm_vmw_fence_signaled_arg)
101#define DRM_IOCTL_VMW_FENCE_UNREF \
102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \
103 struct drm_vmw_fence_arg)
57c5ee79
TH		 104#define DRM_IOCTL_VMW_FENCE_EVENT \
105 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \
106 struct drm_vmw_fence_event_arg)
2fcd5a73
JB		 107#define DRM_IOCTL_VMW_PRESENT \
108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \
109 struct drm_vmw_present_arg)
110#define DRM_IOCTL_VMW_PRESENT_READBACK \
111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \
112 struct drm_vmw_present_readback_arg)
cd2b89e7
TH		 113#define DRM_IOCTL_VMW_UPDATE_LAYOUT \
114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \
115 struct drm_vmw_update_layout_arg)
c74c162f
TH		 116#define DRM_IOCTL_VMW_CREATE_SHADER \
117 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \
118 struct drm_vmw_shader_create_arg)
119#define DRM_IOCTL_VMW_UNREF_SHADER \
120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \
121 struct drm_vmw_shader_arg)
a97e2192
TH		 122#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \
123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \
124 union drm_vmw_gb_surface_create_arg)
125#define DRM_IOCTL_VMW_GB_SURFACE_REF \
126 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \
127 union drm_vmw_gb_surface_reference_arg)
1d7a5cbf
TH		 128#define DRM_IOCTL_VMW_SYNCCPU \
129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \
130 struct drm_vmw_synccpu_arg)
d80efd5c
TH		 131#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \
132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \
133 struct drm_vmw_context_arg)
fb1d9738
JB		 134
135/**
136 * The core DRM version of this macro doesn't account for
137 * DRM_COMMAND_BASE.
138 */
139
140#define VMW_IOCTL_DEF(ioctl, func, flags) \
7e7392a6 141 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
fb1d9738
JB		 142
143/**
144 * Ioctl definitions.
145 */
146
baa70943 147static const struct drm_ioctl_desc vmw_ioctls[] = {
1b2f1489 148 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
03f80263 149 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 150 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
03f80263 151 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 152 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
03f80263 153 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 154 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
e1f78003
TH		 155 vmw_kms_cursor_bypass_ioctl,
156 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 157
1b2f1489 158 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
e1f78003 159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 160 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
e1f78003 161 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
1b2f1489 162 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
e1f78003 163 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
fb1d9738 164
1b2f1489 165 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
03f80263 166 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 167 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
03f80263 168 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 169 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
03f80263 170 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 171 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
03f80263 172 DRM_UNLOCKED | DRM_RENDER_ALLOW),
1b2f1489 173 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
03f80263 174 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
d80efd5c
TH		 175 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | DRM_UNLOCKED |
176 DRM_RENDER_ALLOW),
ae2a1040 177 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
89dcbda6 178 DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040
TH		 179 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
180 vmw_fence_obj_signaled_ioctl,
89dcbda6 181 DRM_UNLOCKED | DRM_RENDER_ALLOW),
ae2a1040 182 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
03f80263
TH		 183 DRM_UNLOCKED | DRM_RENDER_ALLOW),
184 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
185 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
f63f6a59 186 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
03f80263 187 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
2fcd5a73
JB		 188
189 /* these allow direct access to the framebuffers mark as master only */
190 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
191 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
192 VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
193 vmw_present_readback_ioctl,
194 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
cd2b89e7
TH		 195 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
196 vmw_kms_update_layout_ioctl,
197 DRM_MASTER | DRM_UNLOCKED),
c74c162f
TH		 198 VMW_IOCTL_DEF(VMW_CREATE_SHADER,
199 vmw_shader_define_ioctl,
03f80263 200 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
c74c162f
TH		 201 VMW_IOCTL_DEF(VMW_UNREF_SHADER,
202 vmw_shader_destroy_ioctl,
03f80263 203 DRM_UNLOCKED | DRM_RENDER_ALLOW),
a97e2192
TH		 204 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
205 vmw_gb_surface_define_ioctl,
03f80263 206 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
a97e2192
TH		 207 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
208 vmw_gb_surface_reference_ioctl,
03f80263 209 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
1d7a5cbf
TH		 210 VMW_IOCTL_DEF(VMW_SYNCCPU,
211 vmw_user_dmabuf_synccpu_ioctl,
89dcbda6 212 DRM_UNLOCKED | DRM_RENDER_ALLOW),
d80efd5c
TH		 213 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
214 vmw_extended_context_define_ioctl,
215 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW),
fb1d9738
JB		 216};
217
218static struct pci_device_id vmw_pci_id_list[] = {
219 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
220 {0, 0, 0}
221};
c4903429 222MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
fb1d9738 223
5d2afab9 224static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
d92d9851
TH		 225static int vmw_force_iommu;
226static int vmw_restrict_iommu;
227static int vmw_force_coherent;
0d00c488 228static int vmw_restrict_dma_mask;
fb1d9738
JB		 229
230static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
231static void vmw_master_init(struct vmw_master *);
d9f36a00
TH		 232static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
233 void *ptr);
fb1d9738 234
30c78bb8
TH		 235MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
236module_param_named(enable_fbdev, enable_fbdev, int, 0600);
d92d9851
TH		 237MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
238module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
239MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
240module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
241MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
242module_param_named(force_coherent, vmw_force_coherent, int, 0600);
0d00c488
TH		 243MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
244module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
d92d9851 245
30c78bb8 246
fb1d9738
JB		 247static void vmw_print_capabilities(uint32_t capabilities)
248{
249 DRM_INFO("Capabilities:\n");
250 if (capabilities & SVGA_CAP_RECT_COPY)
251 DRM_INFO(" Rect copy.\n");
252 if (capabilities & SVGA_CAP_CURSOR)
253 DRM_INFO(" Cursor.\n");
254 if (capabilities & SVGA_CAP_CURSOR_BYPASS)
255 DRM_INFO(" Cursor bypass.\n");
256 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
257 DRM_INFO(" Cursor bypass 2.\n");
258 if (capabilities & SVGA_CAP_8BIT_EMULATION)
259 DRM_INFO(" 8bit emulation.\n");
260 if (capabilities & SVGA_CAP_ALPHA_CURSOR)
261 DRM_INFO(" Alpha cursor.\n");
262 if (capabilities & SVGA_CAP_3D)
263 DRM_INFO(" 3D.\n");
264 if (capabilities & SVGA_CAP_EXTENDED_FIFO)
265 DRM_INFO(" Extended Fifo.\n");
266 if (capabilities & SVGA_CAP_MULTIMON)
267 DRM_INFO(" Multimon.\n");
268 if (capabilities & SVGA_CAP_PITCHLOCK)
269 DRM_INFO(" Pitchlock.\n");
270 if (capabilities & SVGA_CAP_IRQMASK)
271 DRM_INFO(" Irq mask.\n");
272 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
273 DRM_INFO(" Display Topology.\n");
274 if (capabilities & SVGA_CAP_GMR)
275 DRM_INFO(" GMR.\n");
276 if (capabilities & SVGA_CAP_TRACES)
277 DRM_INFO(" Traces.\n");
dcca2862
TH		 278 if (capabilities & SVGA_CAP_GMR2)
279 DRM_INFO(" GMR2.\n");
280 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
281 DRM_INFO(" Screen Object 2.\n");
c1234db7
TH		 282 if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
283 DRM_INFO(" Command Buffers.\n");
284 if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
285 DRM_INFO(" Command Buffers 2.\n");
286 if (capabilities & SVGA_CAP_GBOBJECTS)
287 DRM_INFO(" Guest Backed Resources.\n");
8ce75f8a
SY		 288 if (capabilities & SVGA_CAP_DX)
289 DRM_INFO(" DX Features.\n");
fb1d9738
JB		 290}
291
e2fa3a76 292/**
4b9e45e6 293 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
e2fa3a76 294 *
4b9e45e6 295 * @dev_priv: A device private structure.
e2fa3a76 296 *
4b9e45e6
TH		 297 * This function creates a small buffer object that holds the query
298 * result for dummy queries emitted as query barriers.
299 * The function will then map the first page and initialize a pending
300 * occlusion query result structure, Finally it will unmap the buffer.
301 * No interruptible waits are done within this function.
e2fa3a76 302 *
4b9e45e6 303 * Returns an error if bo creation or initialization fails.
e2fa3a76 304 */
4b9e45e6 305static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
e2fa3a76 306{
4b9e45e6 307 int ret;
459d0fa7 308 struct vmw_dma_buffer *vbo;
e2fa3a76
TH		 309 struct ttm_bo_kmap_obj map;
310 volatile SVGA3dQueryResult *result;
311 bool dummy;
e2fa3a76 312
4b9e45e6 313 /*
459d0fa7 314 * Create the vbo as pinned, so that a tryreserve will
4b9e45e6
TH		 315 * immediately succeed. This is because we're the only
316 * user of the bo currently.
317 */
459d0fa7
TH		 318 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
319 if (!vbo)
320 return -ENOMEM;
4b9e45e6 321
459d0fa7
TH		 322 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE,
323 &vmw_sys_ne_placement, false,
324 &vmw_dmabuf_bo_free);
e2fa3a76 325 if (unlikely(ret != 0))
4b9e45e6
TH		 326 return ret;
327
459d0fa7 328 ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL);
4b9e45e6 329 BUG_ON(ret != 0);
459d0fa7 330 vmw_bo_pin_reserved(vbo, true);
e2fa3a76 331
459d0fa7 332 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
e2fa3a76
TH		 333 if (likely(ret == 0)) {
334 result = ttm_kmap_obj_virtual(&map, &dummy);
335 result->totalSize = sizeof(*result);
336 result->state = SVGA3D_QUERYSTATE_PENDING;
337 result->result32 = 0xff;
338 ttm_bo_kunmap(&map);
4b9e45e6 339 }
459d0fa7
TH		 340 vmw_bo_pin_reserved(vbo, false);
341 ttm_bo_unreserve(&vbo->base);
e2fa3a76 342
4b9e45e6
TH		 343 if (unlikely(ret != 0)) {
344 DRM_ERROR("Dummy query buffer map failed.\n");
459d0fa7 345 vmw_dmabuf_unreference(&vbo);
4b9e45e6 346 } else
459d0fa7 347 dev_priv->dummy_query_bo = vbo;
e2fa3a76 348
4b9e45e6 349 return ret;
e2fa3a76
TH		 350}
351
153b3d5b
TH		 352/**
353 * vmw_request_device_late - Perform late device setup
354 *
355 * @dev_priv: Pointer to device private.
356 *
357 * This function performs setup of otables and enables large command
358 * buffer submission. These tasks are split out to a separate function
359 * because it reverts vmw_release_device_early and is intended to be used
360 * by an error path in the hibernation code.
361 */
362static int vmw_request_device_late(struct vmw_private *dev_priv)
fb1d9738
JB		 363{
364 int ret;
365
3530bdc3
TH		 366 if (dev_priv->has_mob) {
367 ret = vmw_otables_setup(dev_priv);
368 if (unlikely(ret != 0)) {
369 DRM_ERROR("Unable to initialize "
370 "guest Memory OBjects.\n");
153b3d5b 371 return ret;
3530bdc3
TH		 372 }
373 }
153b3d5b 374
3eab3d9e
TH		 375 if (dev_priv->cman) {
376 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman,
377 256*4096, 2*4096);
378 if (ret) {
379 struct vmw_cmdbuf_man *man = dev_priv->cman;
380
381 dev_priv->cman = NULL;
382 vmw_cmdbuf_man_destroy(man);
383 }
384 }
385
153b3d5b
TH		 386 return 0;
387}
388
389static int vmw_request_device(struct vmw_private *dev_priv)
390{
391 int ret;
392
393 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
394 if (unlikely(ret != 0)) {
395 DRM_ERROR("Unable to initialize FIFO.\n");
396 return ret;
397 }
398 vmw_fence_fifo_up(dev_priv->fman);
3eab3d9e 399 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
d80efd5c 400 if (IS_ERR(dev_priv->cman)) {
3eab3d9e 401 dev_priv->cman = NULL;
d80efd5c
TH		 402 dev_priv->has_dx = false;
403 }
153b3d5b
TH		 404
405 ret = vmw_request_device_late(dev_priv);
406 if (ret)
407 goto out_no_mob;
408
e2fa3a76
TH		 409 ret = vmw_dummy_query_bo_create(dev_priv);
410 if (unlikely(ret != 0))
411 goto out_no_query_bo;
fb1d9738
JB		 412
413 return 0;
e2fa3a76
TH		 414
415out_no_query_bo:
3eab3d9e
TH		 416 if (dev_priv->cman)
417 vmw_cmdbuf_remove_pool(dev_priv->cman);
153b3d5b
TH		 418 if (dev_priv->has_mob) {
419 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
3530bdc3 420 vmw_otables_takedown(dev_priv);
153b3d5b 421 }
3eab3d9e
TH		 422 if (dev_priv->cman)
423 vmw_cmdbuf_man_destroy(dev_priv->cman);
3530bdc3 424out_no_mob:
e2fa3a76
TH		 425 vmw_fence_fifo_down(dev_priv->fman);
426 vmw_fifo_release(dev_priv, &dev_priv->fifo);
427 return ret;
fb1d9738
JB		 428}
429
153b3d5b
TH		 430/**
431 * vmw_release_device_early - Early part of fifo takedown.
432 *
433 * @dev_priv: Pointer to device private struct.
434 *
435 * This is the first part of command submission takedown, to be called before
436 * buffer management is taken down.
437 */
438static void vmw_release_device_early(struct vmw_private *dev_priv)
fb1d9738 439{
e2fa3a76
TH		 440 /*
441 * Previous destructions should've released
442 * the pinned bo.
443 */
444
445 BUG_ON(dev_priv->pinned_bo != NULL);
446
459d0fa7 447 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo);
3eab3d9e
TH		 448 if (dev_priv->cman)
449 vmw_cmdbuf_remove_pool(dev_priv->cman);
450
153b3d5b
TH		 451 if (dev_priv->has_mob) {
452 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB);
3530bdc3 453 vmw_otables_takedown(dev_priv);
30c78bb8 454 }
fb1d9738
JB		 455}
456
05730b32 457/**
153b3d5b
TH		 458 * vmw_release_device_late - Late part of fifo takedown.
459 *
460 * @dev_priv: Pointer to device private struct.
461 *
462 * This is the last part of the command submission takedown, to be called when
463 * command submission is no longer needed. It may wait on pending fences.
05730b32 464 */
153b3d5b 465static void vmw_release_device_late(struct vmw_private *dev_priv)
30c78bb8 466{
153b3d5b 467 vmw_fence_fifo_down(dev_priv->fman);
3eab3d9e
TH		 468 if (dev_priv->cman)
469 vmw_cmdbuf_man_destroy(dev_priv->cman);
470
153b3d5b 471 vmw_fifo_release(dev_priv, &dev_priv->fifo);
30c78bb8
TH		 472}
473
eb4f923b
JB		 474/**
475 * Sets the initial_[width|height] fields on the given vmw_private.
476 *
477 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
67d4a87b
TH		 478 * clamping the value to fb_max_[width|height] fields and the
479 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
480 * If the values appear to be invalid, set them to
eb4f923b
JB		 481 * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
482 */
483static void vmw_get_initial_size(struct vmw_private *dev_priv)
484{
485 uint32_t width;
486 uint32_t height;
487
488 width = vmw_read(dev_priv, SVGA_REG_WIDTH);
489 height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
490
491 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
eb4f923b 492 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
67d4a87b
TH		 493
494 if (width > dev_priv->fb_max_width ||
495 height > dev_priv->fb_max_height) {
496
497 /*
498 * This is a host error and shouldn't occur.
499 */
500
501 width = VMW_MIN_INITIAL_WIDTH;
502 height = VMW_MIN_INITIAL_HEIGHT;
503 }
eb4f923b
JB		 504
505 dev_priv->initial_width = width;
506 dev_priv->initial_height = height;
507}
508
d92d9851
TH		 509/**
510 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
511 * system.
512 *
513 * @dev_priv: Pointer to a struct vmw_private
514 *
515 * This functions tries to determine the IOMMU setup and what actions
516 * need to be taken by the driver to make system pages visible to the
517 * device.
518 * If this function decides that DMA is not possible, it returns -EINVAL.
519 * The driver may then try to disable features of the device that require
520 * DMA.
521 */
522static int vmw_dma_select_mode(struct vmw_private *dev_priv)
523{
d92d9851
TH		 524 static const char *names[vmw_dma_map_max] = {
525 [vmw_dma_phys] = "Using physical TTM page addresses.",
526 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
527 [vmw_dma_map_populate] = "Keeping DMA mappings.",
528 [vmw_dma_map_bind] = "Giving up DMA mappings early."};
e14cd953
TH		 529#ifdef CONFIG_X86
530 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev);
d92d9851
TH		 531
532#ifdef CONFIG_INTEL_IOMMU
533 if (intel_iommu_enabled) {
534 dev_priv->map_mode = vmw_dma_map_populate;
535 goto out_fixup;
536 }
537#endif
538
539 if (!(vmw_force_iommu || vmw_force_coherent)) {
540 dev_priv->map_mode = vmw_dma_phys;
541 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
542 return 0;
543 }
544
545 dev_priv->map_mode = vmw_dma_map_populate;
546
547 if (dma_ops->sync_single_for_cpu)
548 dev_priv->map_mode = vmw_dma_alloc_coherent;
549#ifdef CONFIG_SWIOTLB
550 if (swiotlb_nr_tbl() == 0)
551 dev_priv->map_mode = vmw_dma_map_populate;
552#endif
553
21136946 554#ifdef CONFIG_INTEL_IOMMU
d92d9851 555out_fixup:
21136946 556#endif
d92d9851
TH		 557 if (dev_priv->map_mode == vmw_dma_map_populate &&
558 vmw_restrict_iommu)
559 dev_priv->map_mode = vmw_dma_map_bind;
560
561 if (vmw_force_coherent)
562 dev_priv->map_mode = vmw_dma_alloc_coherent;
563
564#if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU)
565 /*
566 * No coherent page pool
567 */
568 if (dev_priv->map_mode == vmw_dma_alloc_coherent)
569 return -EINVAL;
570#endif
571
e14cd953
TH		 572#else /* CONFIG_X86 */
573 dev_priv->map_mode = vmw_dma_map_populate;
574#endif /* CONFIG_X86 */
575
d92d9851
TH		 576 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
577
578 return 0;
579}
580
0d00c488
TH		 581/**
582 * vmw_dma_masks - set required page- and dma masks
583 *
584 * @dev: Pointer to struct drm-device
585 *
586 * With 32-bit we can only handle 32 bit PFNs. Optionally set that
587 * restriction also for 64-bit systems.
588 */
589#ifdef CONFIG_INTEL_IOMMU
590static int vmw_dma_masks(struct vmw_private *dev_priv)
591{
592 struct drm_device *dev = dev_priv->dev;
593
594 if (intel_iommu_enabled &&
595 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
596 DRM_INFO("Restricting DMA addresses to 44 bits.\n");
597 return dma_set_mask(dev->dev, DMA_BIT_MASK(44));
598 }
599 return 0;
600}
601#else
602static int vmw_dma_masks(struct vmw_private *dev_priv)
603{
604 return 0;
605}
606#endif
607
fb1d9738
JB		 608static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
609{
610 struct vmw_private *dev_priv;
611 int ret;
c188660f 612 uint32_t svga_id;
c0951b79 613 enum vmw_res_type i;
d92d9851 614 bool refuse_dma = false;
fb1d9738
JB		 615
616 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
617 if (unlikely(dev_priv == NULL)) {
618 DRM_ERROR("Failed allocating a device private struct.\n");
619 return -ENOMEM;
620 }
fb1d9738 621
466e69b8
DA		 622 pci_set_master(dev->pdev);
623
fb1d9738
JB		 624 dev_priv->dev = dev;
625 dev_priv->vmw_chipset = chipset;
6bcd8d3c 626 dev_priv->last_read_seqno = (uint32_t) -100;
fb1d9738 627 mutex_init(&dev_priv->cmdbuf_mutex);
30c78bb8 628 mutex_init(&dev_priv->release_mutex);
173fb7d4 629 mutex_init(&dev_priv->binding_mutex);
fb1d9738 630 rwlock_init(&dev_priv->resource_lock);
294adf7d 631 ttm_lock_init(&dev_priv->reservation_sem);
496eb6fd
TH		 632 spin_lock_init(&dev_priv->hw_lock);
633 spin_lock_init(&dev_priv->waiter_lock);
634 spin_lock_init(&dev_priv->cap_lock);
153b3d5b 635 spin_lock_init(&dev_priv->svga_lock);
c0951b79
TH		 636
637 for (i = vmw_res_context; i < vmw_res_max; ++i) {
638 idr_init(&dev_priv->res_idr[i]);
639 INIT_LIST_HEAD(&dev_priv->res_lru[i]);
640 }
641
fb1d9738
JB		 642 mutex_init(&dev_priv->init_mutex);
643 init_waitqueue_head(&dev_priv->fence_queue);
644 init_waitqueue_head(&dev_priv->fifo_queue);
4f73a96b 645 dev_priv->fence_queue_waiters = 0;
fb1d9738 646 atomic_set(&dev_priv->fifo_queue_waiters, 0);
c0951b79 647
5bb39e81 648 dev_priv->used_memory_size = 0;
fb1d9738
JB		 649
650 dev_priv->io_start = pci_resource_start(dev->pdev, 0);
651 dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
652 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
653
30c78bb8
TH		 654 dev_priv->enable_fb = enable_fbdev;
655
c188660f
PH		 656 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
657 svga_id = vmw_read(dev_priv, SVGA_REG_ID);
658 if (svga_id != SVGA_ID_2) {
659 ret = -ENOSYS;
49625904 660 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id);
c188660f
PH		 661 goto out_err0;
662 }
663
fb1d9738 664 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
d92d9851
TH		 665 ret = vmw_dma_select_mode(dev_priv);
666 if (unlikely(ret != 0)) {
667 DRM_INFO("Restricting capabilities due to IOMMU setup.\n");
668 refuse_dma = true;
669 }
fb1d9738 670
5bb39e81
TH		 671 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
672 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
673 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
674 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
eb4f923b
JB		 675
676 vmw_get_initial_size(dev_priv);
677
0d00c488 678 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 679 dev_priv->max_gmr_ids =
680 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
fb17f189
TH		 681 dev_priv->max_gmr_pages =
682 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
683 dev_priv->memory_size =
684 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
5bb39e81
TH		 685 dev_priv->memory_size -= dev_priv->vram_size;
686 } else {
687 /*
688 * An arbitrary limit of 512MiB on surface
689 * memory. But all HWV8 hardware supports GMR2.
690 */
691 dev_priv->memory_size = 512*1024*1024;
fb17f189 692 }
6da768aa 693 dev_priv->max_mob_pages = 0;
857aea1c 694 dev_priv->max_mob_size = 0;
6da768aa
TH		 695 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
696 uint64_t mem_size =
697 vmw_read(dev_priv,
698 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
699
700 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
afb0e50f
TH		 701 dev_priv->prim_bb_mem =
702 vmw_read(dev_priv,
703 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
857aea1c
CL		 704 dev_priv->max_mob_size =
705 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
35c05125
SY		 706 dev_priv->stdu_max_width =
707 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
708 dev_priv->stdu_max_height =
709 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
710
711 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
712 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
713 dev_priv->texture_max_width = vmw_read(dev_priv,
714 SVGA_REG_DEV_CAP);
715 vmw_write(dev_priv, SVGA_REG_DEV_CAP,
716 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
717 dev_priv->texture_max_height = vmw_read(dev_priv,
718 SVGA_REG_DEV_CAP);
df45e9d4
TH		 719 } else {
720 dev_priv->texture_max_width = 8192;
721 dev_priv->texture_max_height = 8192;
afb0e50f 722 dev_priv->prim_bb_mem = dev_priv->vram_size;
df45e9d4
TH		 723 }
724
35c05125 725 vmw_print_capabilities(dev_priv->capabilities);
fb1d9738 726
0d00c488 727 ret = vmw_dma_masks(dev_priv);
496eb6fd 728 if (unlikely(ret != 0))
0d00c488
TH		 729 goto out_err0;
730
0d00c488 731 if (dev_priv->capabilities & SVGA_CAP_GMR2) {
fb1d9738
JB		 732 DRM_INFO("Max GMR ids is %u\n",
733 (unsigned)dev_priv->max_gmr_ids);
fb17f189
TH		 734 DRM_INFO("Max number of GMR pages is %u\n",
735 (unsigned)dev_priv->max_gmr_pages);
5bb39e81
TH		 736 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
737 (unsigned)dev_priv->memory_size / 1024);
fb17f189 738 }
bc2d6508
TH		 739 DRM_INFO("Maximum display memory size is %u kiB\n",
740 dev_priv->prim_bb_mem / 1024);
fb1d9738
JB		 741 DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
742 dev_priv->vram_start, dev_priv->vram_size / 1024);
743 DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
744 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
745
746 ret = vmw_ttm_global_init(dev_priv);
747 if (unlikely(ret != 0))
748 goto out_err0;
749
750
751 vmw_master_init(&dev_priv->fbdev_master);
752 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
753 dev_priv->active_master = &dev_priv->fbdev_master;
754
a2c06ee2 755
247d36d7
AL		 756 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start,
757 dev_priv->mmio_size);
fb1d9738
JB		 758
759 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
760 dev_priv->mmio_size);
761
762 if (unlikely(dev_priv->mmio_virt == NULL)) {
763 ret = -ENOMEM;
764 DRM_ERROR("Failed mapping MMIO.\n");
765 goto out_err3;
766 }
767
d7e1958d
JB		 768 /* Need mmio memory to check for fifo pitchlock cap. */
769 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
770 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
771 !vmw_fifo_have_pitchlock(dev_priv)) {
772 ret = -ENOSYS;
773 DRM_ERROR("Hardware has no pitchlock\n");
774 goto out_err4;
775 }
776
fb1d9738 777 dev_priv->tdev = ttm_object_device_init
69977ff5 778 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops);
fb1d9738
JB		 779
780 if (unlikely(dev_priv->tdev == NULL)) {
781 DRM_ERROR("Unable to initialize TTM object management.\n");
782 ret = -ENOMEM;
783 goto out_err4;
784 }
785
786 dev->dev_private = dev_priv;
787
fb1d9738
JB		 788 ret = pci_request_regions(dev->pdev, "vmwgfx probe");
789 dev_priv->stealth = (ret != 0);
790 if (dev_priv->stealth) {
791 /**
792 * Request at least the mmio PCI resource.
793 */
794
795 DRM_INFO("It appears like vesafb is loaded. "
f2d12b8e 796 "Ignore above error if any.\n");
fb1d9738
JB		 797 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
798 if (unlikely(ret != 0)) {
799 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
800 goto out_no_device;
801 }
fb1d9738 802 }
ae2a1040 803
506ff75c 804 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
bb0f1b5c 805 ret = drm_irq_install(dev, dev->pdev->irq);
506ff75c
TH		 806 if (ret != 0) {
807 DRM_ERROR("Failed installing irq: %d\n", ret);
808 goto out_no_irq;
809 }
810 }
811
ae2a1040 812 dev_priv->fman = vmw_fence_manager_init(dev_priv);
14bbf20c
WY		 813 if (unlikely(dev_priv->fman == NULL)) {
814 ret = -ENOMEM;
ae2a1040 815 goto out_no_fman;
14bbf20c 816 }
56d1c78d 817
153b3d5b
TH		 818 ret = ttm_bo_device_init(&dev_priv->bdev,
819 dev_priv->bo_global_ref.ref.object,
820 &vmw_bo_driver,
821 dev->anon_inode->i_mapping,
822 VMWGFX_FILE_PAGE_OFFSET,
823 false);
824 if (unlikely(ret != 0)) {
825 DRM_ERROR("Failed initializing TTM buffer object driver.\n");
826 goto out_no_bdev;
827 }
3458390b 828
153b3d5b
TH		 829 /*
830 * Enable VRAM, but initially don't use it until SVGA is enabled and
831 * unhidden.
832 */
3458390b
TH		 833 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
834 (dev_priv->vram_size >> PAGE_SHIFT));
835 if (unlikely(ret != 0)) {
836 DRM_ERROR("Failed initializing memory manager for VRAM.\n");
837 goto out_no_vram;
838 }
153b3d5b 839 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
3458390b
TH		 840
841 dev_priv->has_gmr = true;
842 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
843 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
844 VMW_PL_GMR) != 0) {
845 DRM_INFO("No GMR memory available. "
846 "Graphics memory resources are very limited.\n");
847 dev_priv->has_gmr = false;
848 }
849
850 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
851 dev_priv->has_mob = true;
852 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB,
853 VMW_PL_MOB) != 0) {
854 DRM_INFO("No MOB memory available. "
855 "3D will be disabled.\n");
856 dev_priv->has_mob = false;
857 }
858 }
859
d80efd5c
TH		 860 if (dev_priv->has_mob) {
861 spin_lock(&dev_priv->cap_lock);
862 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX);
863 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP);
864 spin_unlock(&dev_priv->cap_lock);
865 }
866
867
7a1c2f6c
TH		 868 ret = vmw_kms_init(dev_priv);
869 if (unlikely(ret != 0))
870 goto out_no_kms;
f2d12b8e 871 vmw_overlay_init(dev_priv);
56d1c78d 872
153b3d5b
TH		 873 ret = vmw_request_device(dev_priv);
874 if (ret)
875 goto out_no_fifo;
876
d80efd5c
TH		 877 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no.");
878
30c78bb8 879 if (dev_priv->enable_fb) {
153b3d5b
TH		 880 vmw_fifo_resource_inc(dev_priv);
881 vmw_svga_enable(dev_priv);
30c78bb8 882 vmw_fb_init(dev_priv);
7a1c2f6c
TH		 883 }
884
d9f36a00
TH		 885 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
886 register_pm_notifier(&dev_priv->pm_nb);
887
fb1d9738
JB		 888 return 0;
889
506ff75c 890out_no_fifo:
56d1c78d
JB		 891 vmw_overlay_close(dev_priv);
892 vmw_kms_close(dev_priv);
893out_no_kms:
3458390b
TH		 894 if (dev_priv->has_mob)
895 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
896 if (dev_priv->has_gmr)
897 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
898 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
899out_no_vram:
153b3d5b
TH		 900 (void)ttm_bo_device_release(&dev_priv->bdev);
901out_no_bdev:
ae2a1040
TH		 902 vmw_fence_manager_takedown(dev_priv->fman);
903out_no_fman:
506ff75c
TH		 904 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
905 drm_irq_uninstall(dev_priv->dev);
906out_no_irq:
30c78bb8
TH		 907 if (dev_priv->stealth)
908 pci_release_region(dev->pdev, 2);
909 else
910 pci_release_regions(dev->pdev);
fb1d9738 911out_no_device:
fb1d9738
JB		 912 ttm_object_device_release(&dev_priv->tdev);
913out_err4:
914 iounmap(dev_priv->mmio_virt);
915out_err3:
247d36d7 916 arch_phys_wc_del(dev_priv->mmio_mtrr);
fb1d9738
JB		 917 vmw_ttm_global_release(dev_priv);
918out_err0:
c0951b79
TH		 919 for (i = vmw_res_context; i < vmw_res_max; ++i)
920 idr_destroy(&dev_priv->res_idr[i]);
921
d80efd5c
TH		 922 if (dev_priv->ctx.staged_bindings)
923 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
fb1d9738
JB		 924 kfree(dev_priv);
925 return ret;
926}
927
928static int vmw_driver_unload(struct drm_device *dev)
929{
930 struct vmw_private *dev_priv = vmw_priv(dev);
c0951b79 931 enum vmw_res_type i;
fb1d9738 932
d9f36a00
TH		 933 unregister_pm_notifier(&dev_priv->pm_nb);
934
c0951b79
TH		 935 if (dev_priv->ctx.res_ht_initialized)
936 drm_ht_remove(&dev_priv->ctx.res_ht);
a3a1a667 937 vfree(dev_priv->ctx.cmd_bounce);
30c78bb8 938 if (dev_priv->enable_fb) {
05c95018 939 vmw_fb_off(dev_priv);
30c78bb8 940 vmw_fb_close(dev_priv);
153b3d5b
TH		 941 vmw_fifo_resource_dec(dev_priv);
942 vmw_svga_disable(dev_priv);
30c78bb8 943 }
153b3d5b 944
f2d12b8e
TH		 945 vmw_kms_close(dev_priv);
946 vmw_overlay_close(dev_priv);
3458390b 947
3458390b
TH		 948 if (dev_priv->has_gmr)
949 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
950 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
951
153b3d5b
TH		 952 vmw_release_device_early(dev_priv);
953 if (dev_priv->has_mob)
954 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB);
955 (void) ttm_bo_device_release(&dev_priv->bdev);
956 vmw_release_device_late(dev_priv);
ae2a1040 957 vmw_fence_manager_takedown(dev_priv->fman);
506ff75c
TH		 958 if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
959 drm_irq_uninstall(dev_priv->dev);
f2d12b8e 960 if (dev_priv->stealth)
fb1d9738 961 pci_release_region(dev->pdev, 2);
f2d12b8e
TH		 962 else
963 pci_release_regions(dev->pdev);
964
fb1d9738
JB		 965 ttm_object_device_release(&dev_priv->tdev);
966 iounmap(dev_priv->mmio_virt);
247d36d7 967 arch_phys_wc_del(dev_priv->mmio_mtrr);
fb1d9738 968 (void)ttm_bo_device_release(&dev_priv->bdev);
d80efd5c
TH		 969 if (dev_priv->ctx.staged_bindings)
970 vmw_binding_state_free(dev_priv->ctx.staged_bindings);
fb1d9738 971 vmw_ttm_global_release(dev_priv);
c0951b79
TH		 972
973 for (i = vmw_res_context; i < vmw_res_max; ++i)
974 idr_destroy(&dev_priv->res_idr[i]);
fb1d9738
JB		 975
976 kfree(dev_priv);
977
978 return 0;
979}
980
6b82ef50
TH		 981static void vmw_preclose(struct drm_device *dev,
982 struct drm_file *file_priv)
983{
984 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
985 struct vmw_private *dev_priv = vmw_priv(dev);
986
987 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events);
988}
989
fb1d9738
JB		 990static void vmw_postclose(struct drm_device *dev,
991 struct drm_file *file_priv)
992{
993 struct vmw_fpriv *vmw_fp;
994
995 vmw_fp = vmw_fpriv(file_priv);
c4249855
TH		 996
997 if (vmw_fp->locked_master) {
998 struct vmw_master *vmaster =
999 vmw_master(vmw_fp->locked_master);
1000
1001 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1002 ttm_vt_unlock(&vmaster->lock);
fb1d9738 1003 drm_master_put(&vmw_fp->locked_master);
c4249855
TH		 1004 }
1005
1006 ttm_object_file_release(&vmw_fp->tfile);
fb1d9738
JB		 1007 kfree(vmw_fp);
1008}
1009
1010static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1011{
1012 struct vmw_private *dev_priv = vmw_priv(dev);
1013 struct vmw_fpriv *vmw_fp;
1014 int ret = -ENOMEM;
1015
1016 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1017 if (unlikely(vmw_fp == NULL))
1018 return ret;
1019
6b82ef50 1020 INIT_LIST_HEAD(&vmw_fp->fence_events);
fb1d9738
JB		 1021 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1022 if (unlikely(vmw_fp->tfile == NULL))
1023 goto out_no_tfile;
1024
1025 file_priv->driver_priv = vmw_fp;
fb1d9738
JB		 1026
1027 return 0;
1028
1029out_no_tfile:
1030 kfree(vmw_fp);
1031 return ret;
1032}
1033
64190bde
TH		 1034static struct vmw_master *vmw_master_check(struct drm_device *dev,
1035 struct drm_file *file_priv,
1036 unsigned int flags)
1037{
1038 int ret;
1039 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1040 struct vmw_master *vmaster;
1041
1042 if (file_priv->minor->type != DRM_MINOR_LEGACY ||
1043 !(flags & DRM_AUTH))
1044 return NULL;
1045
1046 ret = mutex_lock_interruptible(&dev->master_mutex);
1047 if (unlikely(ret != 0))
1048 return ERR_PTR(-ERESTARTSYS);
1049
7963e9db 1050 if (file_priv->is_master) {
64190bde
TH		 1051 mutex_unlock(&dev->master_mutex);
1052 return NULL;
1053 }
1054
1055 /*
1056 * Check if we were previously master, but now dropped.
1057 */
1058 if (vmw_fp->locked_master) {
1059 mutex_unlock(&dev->master_mutex);
1060 DRM_ERROR("Dropped master trying to access ioctl that "
1061 "requires authentication.\n");
1062 return ERR_PTR(-EACCES);
1063 }
1064 mutex_unlock(&dev->master_mutex);
1065
1066 /*
1067 * Taking the drm_global_mutex after the TTM lock might deadlock
1068 */
1069 if (!(flags & DRM_UNLOCKED)) {
1070 DRM_ERROR("Refusing locked ioctl access.\n");
1071 return ERR_PTR(-EDEADLK);
1072 }
1073
1074 /*
1075 * Take the TTM lock. Possibly sleep waiting for the authenticating
1076 * master to become master again, or for a SIGTERM if the
1077 * authenticating master exits.
1078 */
1079 vmaster = vmw_master(file_priv->master);
1080 ret = ttm_read_lock(&vmaster->lock, true);
1081 if (unlikely(ret != 0))
1082 vmaster = ERR_PTR(ret);
1083
1084 return vmaster;
1085}
1086
1087static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1088 unsigned long arg,
1089 long (*ioctl_func)(struct file *, unsigned int,
1090 unsigned long))
fb1d9738
JB		 1091{
1092 struct drm_file *file_priv = filp->private_data;
1093 struct drm_device *dev = file_priv->minor->dev;
1094 unsigned int nr = DRM_IOCTL_NR(cmd);
64190bde
TH		 1095 struct vmw_master *vmaster;
1096 unsigned int flags;
1097 long ret;
fb1d9738
JB		 1098
1099 /*
e1f78003 1100 * Do extra checking on driver private ioctls.
fb1d9738
JB		 1101 */
1102
1103 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1104 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
baa70943 1105 const struct drm_ioctl_desc *ioctl =
64190bde 1106 &vmw_ioctls[nr - DRM_COMMAND_BASE];
fb1d9738 1107
d80efd5c
TH		 1108 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1109 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv);
1110 if (unlikely(ret != 0))
1111 return ret;
1112
1113 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN))
1114 goto out_io_encoding;
1115
1116 return (long) vmw_execbuf_ioctl(dev, arg, file_priv,
1117 _IOC_SIZE(cmd));
fb1d9738 1118 }
d80efd5c
TH		 1119
1120 if (unlikely(ioctl->cmd != cmd))
1121 goto out_io_encoding;
1122
64190bde
TH		 1123 flags = ioctl->flags;
1124 } else if (!drm_ioctl_flags(nr, &flags))
1125 return -EINVAL;
1126
1127 vmaster = vmw_master_check(dev, file_priv, flags);
1128 if (unlikely(IS_ERR(vmaster))) {
e338c4c2
TH		 1129 ret = PTR_ERR(vmaster);
1130
1131 if (ret != -ERESTARTSYS)
1132 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n",
1133 nr, ret);
1134 return ret;
fb1d9738
JB		 1135 }
1136
64190bde
TH		 1137 ret = ioctl_func(filp, cmd, arg);
1138 if (vmaster)
1139 ttm_read_unlock(&vmaster->lock);
1140
1141 return ret;
d80efd5c
TH		 1142
1143out_io_encoding:
1144 DRM_ERROR("Invalid command format, ioctl %d\n",
1145 nr - DRM_COMMAND_BASE);
1146
1147 return -EINVAL;
64190bde
TH		 1148}
1149
1150static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1151 unsigned long arg)
1152{
1153 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
fb1d9738
JB		 1154}
1155
64190bde
TH		 1156#ifdef CONFIG_COMPAT
1157static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1158 unsigned long arg)
1159{
1160 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1161}
1162#endif
1163
fb1d9738
JB		 1164static void vmw_lastclose(struct drm_device *dev)
1165{
fb1d9738
JB		 1166}
1167
1168static void vmw_master_init(struct vmw_master *vmaster)
1169{
1170 ttm_lock_init(&vmaster->lock);
1171}
1172
1173static int vmw_master_create(struct drm_device *dev,
1174 struct drm_master *master)
1175{
1176 struct vmw_master *vmaster;
1177
fb1d9738
JB		 1178 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
1179 if (unlikely(vmaster == NULL))
1180 return -ENOMEM;
1181
3a939a5e 1182 vmw_master_init(vmaster);
fb1d9738
JB		 1183 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
1184 master->driver_priv = vmaster;
1185
1186 return 0;
1187}
1188
1189static void vmw_master_destroy(struct drm_device *dev,
1190 struct drm_master *master)
1191{
1192 struct vmw_master *vmaster = vmw_master(master);
1193
fb1d9738
JB		 1194 master->driver_priv = NULL;
1195 kfree(vmaster);
1196}
1197
fb1d9738
JB		 1198static int vmw_master_set(struct drm_device *dev,
1199 struct drm_file *file_priv,
1200 bool from_open)
1201{
1202 struct vmw_private *dev_priv = vmw_priv(dev);
1203 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1204 struct vmw_master *active = dev_priv->active_master;
1205 struct vmw_master *vmaster = vmw_master(file_priv->master);
1206 int ret = 0;
1207
fb1d9738
JB		 1208 if (active) {
1209 BUG_ON(active != &dev_priv->fbdev_master);
1210 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
1211 if (unlikely(ret != 0))
153b3d5b 1212 return ret;
fb1d9738
JB		 1213
1214 ttm_lock_set_kill(&active->lock, true, SIGTERM);
fb1d9738
JB		 1215 dev_priv->active_master = NULL;
1216 }
1217
1218 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
1219 if (!from_open) {
1220 ttm_vt_unlock(&vmaster->lock);
1221 BUG_ON(vmw_fp->locked_master != file_priv->master);
1222 drm_master_put(&vmw_fp->locked_master);
1223 }
1224
1225 dev_priv->active_master = vmaster;
1226
1227 return 0;
fb1d9738
JB		 1228}
1229
1230static void vmw_master_drop(struct drm_device *dev,
1231 struct drm_file *file_priv,
1232 bool from_release)
1233{
1234 struct vmw_private *dev_priv = vmw_priv(dev);
1235 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1236 struct vmw_master *vmaster = vmw_master(file_priv->master);
1237 int ret;
1238
fb1d9738
JB		 1239 /**
1240 * Make sure the master doesn't disappear while we have
1241 * it locked.
1242 */
1243
1244 vmw_fp->locked_master = drm_master_get(file_priv->master);
1245 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
fb1d9738
JB		 1246 if (unlikely((ret != 0))) {
1247 DRM_ERROR("Unable to lock TTM at VT switch.\n");
1248 drm_master_put(&vmw_fp->locked_master);
1249 }
1250
c4249855 1251 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
fb1d9738 1252
153b3d5b
TH		 1253 if (!dev_priv->enable_fb)
1254 vmw_svga_disable(dev_priv);
30c78bb8 1255
fb1d9738
JB		 1256 dev_priv->active_master = &dev_priv->fbdev_master;
1257 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
1258 ttm_vt_unlock(&dev_priv->fbdev_master.lock);
1259
30c78bb8
TH		 1260 if (dev_priv->enable_fb)
1261 vmw_fb_on(dev_priv);
fb1d9738
JB		 1262}
1263
153b3d5b
TH		 1264/**
1265 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1266 *
1267 * @dev_priv: Pointer to device private struct.
1268 * Needs the reservation sem to be held in non-exclusive mode.
1269 */
b9eb1a61 1270static void __vmw_svga_enable(struct vmw_private *dev_priv)
153b3d5b
TH		 1271{
1272 spin_lock(&dev_priv->svga_lock);
1273 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1274 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1275 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true;
1276 }
1277 spin_unlock(&dev_priv->svga_lock);
1278}
1279
1280/**
1281 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1282 *
1283 * @dev_priv: Pointer to device private struct.
1284 */
1285void vmw_svga_enable(struct vmw_private *dev_priv)
1286{
1287 ttm_read_lock(&dev_priv->reservation_sem, false);
1288 __vmw_svga_enable(dev_priv);
1289 ttm_read_unlock(&dev_priv->reservation_sem);
1290}
1291
1292/**
1293 * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1294 *
1295 * @dev_priv: Pointer to device private struct.
1296 * Needs the reservation sem to be held in exclusive mode.
1297 * Will not empty VRAM. VRAM must be emptied by caller.
1298 */
b9eb1a61 1299static void __vmw_svga_disable(struct vmw_private *dev_priv)
153b3d5b
TH		 1300{
1301 spin_lock(&dev_priv->svga_lock);
1302 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1303 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
1304 vmw_write(dev_priv, SVGA_REG_ENABLE,
8ce75f8a
SY		 1305 SVGA_REG_ENABLE_HIDE |
1306 SVGA_REG_ENABLE_ENABLE);
153b3d5b
TH		 1307 }
1308 spin_unlock(&dev_priv->svga_lock);
1309}
1310
1311/**
1312 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1313 * running.
1314 *
1315 * @dev_priv: Pointer to device private struct.
1316 * Will empty VRAM.
1317 */
1318void vmw_svga_disable(struct vmw_private *dev_priv)
1319{
1320 ttm_write_lock(&dev_priv->reservation_sem, false);
1321 spin_lock(&dev_priv->svga_lock);
1322 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) {
1323 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false;
153b3d5b
TH		 1324 spin_unlock(&dev_priv->svga_lock);
1325 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM))
1326 DRM_ERROR("Failed evicting VRAM buffers.\n");
8ce75f8a
SY		 1327 vmw_write(dev_priv, SVGA_REG_ENABLE,
1328 SVGA_REG_ENABLE_HIDE |
1329 SVGA_REG_ENABLE_ENABLE);
153b3d5b
TH		 1330 } else
1331 spin_unlock(&dev_priv->svga_lock);
1332 ttm_write_unlock(&dev_priv->reservation_sem);
1333}
fb1d9738
JB		 1334
1335static void vmw_remove(struct pci_dev *pdev)
1336{
1337 struct drm_device *dev = pci_get_drvdata(pdev);
1338
fd3e4d6e 1339 pci_disable_device(pdev);
fb1d9738
JB		 1340 drm_put_dev(dev);
1341}
1342
d9f36a00
TH		 1343static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1344 void *ptr)
1345{
1346 struct vmw_private *dev_priv =
1347 container_of(nb, struct vmw_private, pm_nb);
d9f36a00
TH		 1348
1349 switch (val) {
1350 case PM_HIBERNATION_PREPARE:
a278724a
TH		 1351 if (dev_priv->enable_fb)
1352 vmw_fb_off(dev_priv);
294adf7d 1353 ttm_suspend_lock(&dev_priv->reservation_sem);
d9f36a00 1354
153b3d5b 1355 /*
d9f36a00
TH		 1356 * This empties VRAM and unbinds all GMR bindings.
1357 * Buffer contents is moved to swappable memory.
1358 */
c0951b79
TH		 1359 vmw_execbuf_release_pinned_bo(dev_priv);
1360 vmw_resource_evict_all(dev_priv);
153b3d5b 1361 vmw_release_device_early(dev_priv);
d9f36a00 1362 ttm_bo_swapout_all(&dev_priv->bdev);
153b3d5b 1363 vmw_fence_fifo_down(dev_priv->fman);
d9f36a00
TH		 1364 break;
1365 case PM_POST_HIBERNATION:
094e0fa8 1366 case PM_POST_RESTORE:
153b3d5b 1367 vmw_fence_fifo_up(dev_priv->fman);
294adf7d 1368 ttm_suspend_unlock(&dev_priv->reservation_sem);
a278724a
TH		 1369 if (dev_priv->enable_fb)
1370 vmw_fb_on(dev_priv);
d9f36a00
TH		 1371 break;
1372 case PM_RESTORE_PREPARE:
1373 break;
d9f36a00
TH		 1374 default:
1375 break;
1376 }
1377 return 0;
1378}
1379
7fbd721a 1380static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
d9f36a00 1381{
094e0fa8
TH		 1382 struct drm_device *dev = pci_get_drvdata(pdev);
1383 struct vmw_private *dev_priv = vmw_priv(dev);
1384
153b3d5b 1385 if (dev_priv->refuse_hibernation)
094e0fa8 1386 return -EBUSY;
094e0fa8 1387
d9f36a00
TH		 1388 pci_save_state(pdev);
1389 pci_disable_device(pdev);
1390 pci_set_power_state(pdev, PCI_D3hot);
1391 return 0;
1392}
1393
7fbd721a 1394static int vmw_pci_resume(struct pci_dev *pdev)
d9f36a00
TH		 1395{
1396 pci_set_power_state(pdev, PCI_D0);
1397 pci_restore_state(pdev);
1398 return pci_enable_device(pdev);
1399}
1400
7fbd721a
TH		 1401static int vmw_pm_suspend(struct device *kdev)
1402{
1403 struct pci_dev *pdev = to_pci_dev(kdev);
1404 struct pm_message dummy;
1405
1406 dummy.event = 0;
1407
1408 return vmw_pci_suspend(pdev, dummy);
1409}
1410
1411static int vmw_pm_resume(struct device *kdev)
1412{
1413 struct pci_dev *pdev = to_pci_dev(kdev);
1414
1415 return vmw_pci_resume(pdev);
1416}
1417
153b3d5b 1418static int vmw_pm_freeze(struct device *kdev)
7fbd721a
TH		 1419{
1420 struct pci_dev *pdev = to_pci_dev(kdev);
1421 struct drm_device *dev = pci_get_drvdata(pdev);
1422 struct vmw_private *dev_priv = vmw_priv(dev);
1423
7fbd721a
TH		 1424 dev_priv->suspended = true;
1425 if (dev_priv->enable_fb)
153b3d5b 1426 vmw_fifo_resource_dec(dev_priv);
7fbd721a 1427
153b3d5b
TH		 1428 if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1429 DRM_ERROR("Can't hibernate while 3D resources are active.\n");
7fbd721a 1430 if (dev_priv->enable_fb)
153b3d5b
TH		 1431 vmw_fifo_resource_inc(dev_priv);
1432 WARN_ON(vmw_request_device_late(dev_priv));
7fbd721a
TH		 1433 dev_priv->suspended = false;
1434 return -EBUSY;
1435 }
1436
153b3d5b
TH		 1437 if (dev_priv->enable_fb)
1438 __vmw_svga_disable(dev_priv);
1439
1440 vmw_release_device_late(dev_priv);
1441
7fbd721a
TH		 1442 return 0;
1443}
1444
153b3d5b 1445static int vmw_pm_restore(struct device *kdev)
7fbd721a
TH		 1446{
1447 struct pci_dev *pdev = to_pci_dev(kdev);
1448 struct drm_device *dev = pci_get_drvdata(pdev);
1449 struct vmw_private *dev_priv = vmw_priv(dev);
153b3d5b 1450 int ret;
7fbd721a 1451
95e8f6a2
TH		 1452 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1453 (void) vmw_read(dev_priv, SVGA_REG_ID);
95e8f6a2 1454
7fbd721a 1455 if (dev_priv->enable_fb)
153b3d5b
TH		 1456 vmw_fifo_resource_inc(dev_priv);
1457
1458 ret = vmw_request_device(dev_priv);
1459 if (ret)
1460 return ret;
1461
1462 if (dev_priv->enable_fb)
1463 __vmw_svga_enable(dev_priv);
7fbd721a
TH		 1464
1465 dev_priv->suspended = false;
153b3d5b
TH		 1466
1467 return 0;
7fbd721a
TH		 1468}
1469
1470static const struct dev_pm_ops vmw_pm_ops = {
153b3d5b
TH		 1471 .freeze = vmw_pm_freeze,
1472 .thaw = vmw_pm_restore,
1473 .restore = vmw_pm_restore,
7fbd721a
TH		 1474 .suspend = vmw_pm_suspend,
1475 .resume = vmw_pm_resume,
1476};
1477
e08e96de
AV		 1478static const struct file_operations vmwgfx_driver_fops = {
1479 .owner = THIS_MODULE,
1480 .open = drm_open,
1481 .release = drm_release,
1482 .unlocked_ioctl = vmw_unlocked_ioctl,
1483 .mmap = vmw_mmap,
1484 .poll = vmw_fops_poll,
1485 .read = vmw_fops_read,
e08e96de 1486#if defined(CONFIG_COMPAT)
64190bde 1487 .compat_ioctl = vmw_compat_ioctl,
e08e96de
AV		 1488#endif
1489 .llseek = noop_llseek,
1490};
1491
fb1d9738
JB		 1492static struct drm_driver driver = {
1493 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
03f80263 1494 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER,
fb1d9738
JB		 1495 .load = vmw_driver_load,
1496 .unload = vmw_driver_unload,
fb1d9738
JB		 1497 .lastclose = vmw_lastclose,
1498 .irq_preinstall = vmw_irq_preinstall,
1499 .irq_postinstall = vmw_irq_postinstall,
1500 .irq_uninstall = vmw_irq_uninstall,
1501 .irq_handler = vmw_irq_handler,
7a1c2f6c 1502 .get_vblank_counter = vmw_get_vblank_counter,
1c482ab3
JB		 1503 .enable_vblank = vmw_enable_vblank,
1504 .disable_vblank = vmw_disable_vblank,
fb1d9738 1505 .ioctls = vmw_ioctls,
f95aeb17 1506 .num_ioctls = ARRAY_SIZE(vmw_ioctls),
fb1d9738
JB		 1507 .master_create = vmw_master_create,
1508 .master_destroy = vmw_master_destroy,
1509 .master_set = vmw_master_set,
1510 .master_drop = vmw_master_drop,
1511 .open = vmw_driver_open,
6b82ef50 1512 .preclose = vmw_preclose,
fb1d9738 1513 .postclose = vmw_postclose,
915b4d11 1514 .set_busid = drm_pci_set_busid,
5e1782d2
DA		 1515
1516 .dumb_create = vmw_dumb_create,
1517 .dumb_map_offset = vmw_dumb_map_offset,
1518 .dumb_destroy = vmw_dumb_destroy,
1519
69977ff5
TH		 1520 .prime_fd_to_handle = vmw_prime_fd_to_handle,
1521 .prime_handle_to_fd = vmw_prime_handle_to_fd,
1522
e08e96de 1523 .fops = &vmwgfx_driver_fops,
fb1d9738
JB		 1524 .name = VMWGFX_DRIVER_NAME,
1525 .desc = VMWGFX_DRIVER_DESC,
1526 .date = VMWGFX_DRIVER_DATE,
1527 .major = VMWGFX_DRIVER_MAJOR,
1528 .minor = VMWGFX_DRIVER_MINOR,
1529 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1530};
1531
8410ea3b
DA		 1532static struct pci_driver vmw_pci_driver = {
1533 .name = VMWGFX_DRIVER_NAME,
1534 .id_table = vmw_pci_id_list,
1535 .probe = vmw_probe,
1536 .remove = vmw_remove,
1537 .driver = {
1538 .pm = &vmw_pm_ops
1539 }
1540};
1541
fb1d9738
JB		 1542static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1543{
dcdb1674 1544 return drm_get_pci_dev(pdev, ent, &driver);
fb1d9738
JB		 1545}
1546
1547static int __init vmwgfx_init(void)
1548{
1549 int ret;
8410ea3b 1550 ret = drm_pci_init(&driver, &vmw_pci_driver);
fb1d9738
JB		 1551 if (ret)
1552 DRM_ERROR("Failed initializing DRM.\n");
1553 return ret;
1554}
1555
1556static void __exit vmwgfx_exit(void)
1557{
8410ea3b 1558 drm_pci_exit(&driver, &vmw_pci_driver);
fb1d9738
JB		 1559}
1560
1561module_init(vmwgfx_init);
1562module_exit(vmwgfx_exit);
1563
1564MODULE_AUTHOR("VMware Inc. and others");
1565MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1566MODULE_LICENSE("GPL and additional rights");
73558ead
TH		 1567MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1568 __stringify(VMWGFX_DRIVER_MINOR) "."
1569 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1570 "0");
Linux kernel - Deliverables
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