[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_fifo.c

/**************************************************************************
 *
 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 **************************************************************************/

#include "vmwgfx_drv.h"
#include "drmP.h"
#include "ttm/ttm_placement.h"

bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t fifo_min, hwversion;

	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;

	fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
		return false;

	hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
	if (hwversion == 0)
		return false;

	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
		return false;

	/* Non-Screen Object path does not support surfaces */
	if (!dev_priv->sou_priv)
		return false;

	return true;
}

bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t caps;

	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
		return false;

	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
		return true;

	return false;
}

int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t dummy;

	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
	fifo->static_buffer = vmalloc(fifo->static_buffer_size);
	if (unlikely(fifo->static_buffer == NULL))
		return -ENOMEM;

	fifo->dynamic_buffer = NULL;
	fifo->reserved_size = 0;
	fifo->using_bounce_buffer = false;

	mutex_init(&fifo->fifo_mutex);
	init_rwsem(&fifo->rwsem);

	/*
	 * Allow mapping the first page read-only to user-space.
	 */

	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));

	mutex_lock(&dev_priv->hw_mutex);
	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);

	min = 4;
	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
		min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	min <<= 2;

	if (min < PAGE_SIZE)
		min = PAGE_SIZE;

	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	wmb();
	iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
	iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
	mb();

	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	mutex_unlock(&dev_priv->hw_mutex);

	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);

	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
		 (unsigned int) max,
		 (unsigned int) min,
		 (unsigned int) fifo->capabilities);

	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
	vmw_marker_queue_init(&fifo->marker_queue);
	return vmw_fifo_send_fence(dev_priv, &dummy);
}

void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

	mutex_lock(&dev_priv->hw_mutex);

	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
		iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
		vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	}

	mutex_unlock(&dev_priv->hw_mutex);
}

void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;

	mutex_lock(&dev_priv->hw_mutex);

	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
		vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);

	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);

	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
		  dev_priv->config_done_state);
	vmw_write(dev_priv, SVGA_REG_ENABLE,
		  dev_priv->enable_state);
	vmw_write(dev_priv, SVGA_REG_TRACES,
		  dev_priv->traces_state);

	mutex_unlock(&dev_priv->hw_mutex);
	vmw_marker_queue_takedown(&fifo->marker_queue);

	if (likely(fifo->static_buffer != NULL)) {
		vfree(fifo->static_buffer);
		fifo->static_buffer = NULL;
	}

	if (likely(fifo->dynamic_buffer != NULL)) {
		vfree(fifo->dynamic_buffer);
		fifo->dynamic_buffer = NULL;
	}
}

static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
{
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);

	return ((max - next_cmd) + (stop - min) <= bytes);
}

static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
			       uint32_t bytes, bool interruptible,
			       unsigned long timeout)
{
	int ret = 0;
	unsigned long end_jiffies = jiffies + timeout;
	DEFINE_WAIT(__wait);

	DRM_INFO("Fifo wait noirq.\n");

	for (;;) {
		prepare_to_wait(&dev_priv->fifo_queue, &__wait,
				(interruptible) ?
				TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
		if (!vmw_fifo_is_full(dev_priv, bytes))
			break;
		if (time_after_eq(jiffies, end_jiffies)) {
			ret = -EBUSY;
			DRM_ERROR("SVGA device lockup.\n");
			break;
		}
		schedule_timeout(1);
		if (interruptible && signal_pending(current)) {
			ret = -ERESTARTSYS;
			break;
		}
	}
	finish_wait(&dev_priv->fifo_queue, &__wait);
	wake_up_all(&dev_priv->fifo_queue);
	DRM_INFO("Fifo noirq exit.\n");
	return ret;
}

static int vmw_fifo_wait(struct vmw_private *dev_priv,
			 uint32_t bytes, bool interruptible,
			 unsigned long timeout)
{
	long ret = 1L;
	unsigned long irq_flags;

	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
		return 0;

	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
		return vmw_fifo_wait_noirq(dev_priv, bytes,
					   interruptible, timeout);

	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		outl(SVGA_IRQFLAG_FIFO_PROGRESS,
		     dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
		vmw_write(dev_priv, SVGA_REG_IRQMASK,
			  vmw_read(dev_priv, SVGA_REG_IRQMASK) |
			  SVGA_IRQFLAG_FIFO_PROGRESS);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);

	if (interruptible)
		ret = wait_event_interruptible_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);
	else
		ret = wait_event_timeout
		    (dev_priv->fifo_queue,
		     !vmw_fifo_is_full(dev_priv, bytes), timeout);

	if (unlikely(ret == 0))
		ret = -EBUSY;
	else if (likely(ret > 0))
		ret = 0;

	mutex_lock(&dev_priv->hw_mutex);
	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
		spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
		vmw_write(dev_priv, SVGA_REG_IRQMASK,
			  vmw_read(dev_priv, SVGA_REG_IRQMASK) &
			  ~SVGA_IRQFLAG_FIFO_PROGRESS);
		spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	}
	mutex_unlock(&dev_priv->hw_mutex);

	return ret;
}

/**
 * Reserve @bytes number of bytes in the fifo.
 *
 * This function will return NULL (error) on two conditions:
 *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 *   available fifo space.
 *
 * Returns:
 *   Pointer to the fifo, or null on error (possible hardware hang).
 */
void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t max;
	uint32_t min;
	uint32_t next_cmd;
	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	int ret;

	mutex_lock(&fifo_state->fifo_mutex);
	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);

	if (unlikely(bytes >= (max - min)))
		goto out_err;

	BUG_ON(fifo_state->reserved_size != 0);
	BUG_ON(fifo_state->dynamic_buffer != NULL);

	fifo_state->reserved_size = bytes;

	while (1) {
		uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
		bool need_bounce = false;
		bool reserve_in_place = false;

		if (next_cmd >= stop) {
			if (likely((next_cmd + bytes < max ||
				    (next_cmd + bytes == max && stop > min))))
				reserve_in_place = true;

			else if (vmw_fifo_is_full(dev_priv, bytes)) {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			} else
				need_bounce = true;

		} else {

			if (likely((next_cmd + bytes < stop)))
				reserve_in_place = true;
			else {
				ret = vmw_fifo_wait(dev_priv, bytes,
						    false, 3 * HZ);
				if (unlikely(ret != 0))
					goto out_err;
			}
		}

		if (reserve_in_place) {
			if (reserveable || bytes <= sizeof(uint32_t)) {
				fifo_state->using_bounce_buffer = false;

				if (reserveable)
					iowrite32(bytes, fifo_mem +
						  SVGA_FIFO_RESERVED);
				return fifo_mem + (next_cmd >> 2);
			} else {
				need_bounce = true;
			}
		}

		if (need_bounce) {
			fifo_state->using_bounce_buffer = true;
			if (bytes < fifo_state->static_buffer_size)
				return fifo_state->static_buffer;
			else {
				fifo_state->dynamic_buffer = vmalloc(bytes);
				return fifo_state->dynamic_buffer;
			}
		}
	}
out_err:
	fifo_state->reserved_size = 0;
	mutex_unlock(&fifo_state->fifo_mutex);
	return NULL;
}

static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
			      __le32 __iomem *fifo_mem,
			      uint32_t next_cmd,
			      uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t chunk_size = max - next_cmd;
	uint32_t rest;
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;

	if (bytes < chunk_size)
		chunk_size = bytes;

	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	mb();
	memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	rest = bytes - chunk_size;
	if (rest)
		memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
			    rest);
}

static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
			       __le32 __iomem *fifo_mem,
			       uint32_t next_cmd,
			       uint32_t max, uint32_t min, uint32_t bytes)
{
	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	    fifo_state->dynamic_buffer : fifo_state->static_buffer;

	while (bytes > 0) {
		iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
		next_cmd += sizeof(uint32_t);
		if (unlikely(next_cmd == max))
			next_cmd = min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
		mb();
		bytes -= sizeof(uint32_t);
	}
}

void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;

	BUG_ON((bytes & 3) != 0);
	BUG_ON(bytes > fifo_state->reserved_size);

	fifo_state->reserved_size = 0;

	if (fifo_state->using_bounce_buffer) {
		if (reserveable)
			vmw_fifo_res_copy(fifo_state, fifo_mem,
					  next_cmd, max, min, bytes);
		else
			vmw_fifo_slow_copy(fifo_state, fifo_mem,
					   next_cmd, max, min, bytes);

		if (fifo_state->dynamic_buffer) {
			vfree(fifo_state->dynamic_buffer);
			fifo_state->dynamic_buffer = NULL;
		}

	}

	down_write(&fifo_state->rwsem);
	if (fifo_state->using_bounce_buffer || reserveable) {
		next_cmd += bytes;
		if (next_cmd >= max)
			next_cmd -= max - min;
		mb();
		iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	}

	if (reserveable)
		iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
	mb();
	up_write(&fifo_state->rwsem);
	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
	mutex_unlock(&fifo_state->fifo_mutex);
}

int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
{
	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	struct svga_fifo_cmd_fence *cmd_fence;
	void *fm;
	int ret = 0;
	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);

	fm = vmw_fifo_reserve(dev_priv, bytes);
	if (unlikely(fm == NULL)) {
		*seqno = atomic_read(&dev_priv->marker_seq);
		ret = -ENOMEM;
		(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
					false, 3*HZ);
		goto out_err;
	}

	do {
		*seqno = atomic_add_return(1, &dev_priv->marker_seq);
	} while (*seqno == 0);

	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {

		/*
		 * Don't request hardware to send a fence. The
		 * waiting code in vmwgfx_irq.c will emulate this.
		 */

		vmw_fifo_commit(dev_priv, 0);
		return 0;
	}

	*(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
	cmd_fence = (struct svga_fifo_cmd_fence *)
	    ((unsigned long)fm + sizeof(__le32));

	iowrite32(*seqno, &cmd_fence->fence);
	vmw_fifo_commit(dev_priv, bytes);
	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
	vmw_update_seqno(dev_priv, fifo_state);

out_err:
	return ret;
}

/**
 * vmw_fifo_emit_dummy_query - emits a dummy query to the fifo.
 *
 * @dev_priv: The device private structure.
 * @cid: The hardware context id used for the query.
 *
 * This function is used to emit a dummy occlusion query with
 * no primitives rendered between query begin and query end.
 * It's used to provide a query barrier, in order to know that when
 * this query is finished, all preceding queries are also finished.
 *
 * A Query results structure should have been initialized at the start
 * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 * must also be either reserved or pinned when this function is called.
 *
 * Returns -ENOMEM on failure to reserve fifo space.
 */
int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
			      uint32_t cid)
{
	/*
	 * A query wait without a preceding query end will
	 * actually finish all queries for this cid
	 * without writing to the query result structure.
	 */

	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	struct {
		SVGA3dCmdHeader header;
		SVGA3dCmdWaitForQuery body;
	} *cmd;

	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));

	if (unlikely(cmd == NULL)) {
		DRM_ERROR("Out of fifo space for dummy query.\n");
		return -ENOMEM;
	}

	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	cmd->header.size = sizeof(cmd->body);
	cmd->body.cid = cid;
	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;

	if (bo->mem.mem_type == TTM_PL_VRAM) {
		cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
		cmd->body.guestResult.offset = bo->offset;
	} else {
		cmd->body.guestResult.gmrId = bo->mem.start;
		cmd->body.guestResult.offset = 0;
	}

	vmw_fifo_commit(dev_priv, sizeof(*cmd));

	return 0;
}
Commit	Line	Data
fb1d9738 JB	1	/**************************************************************************
	2	*
	3	* Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sub license, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial portions
	16	* of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
	21	* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
	22	* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
	23	* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
	24	* USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	**************************************************************************/
	27
	28	#include "vmwgfx_drv.h"
	29	#include "drmP.h"
	30	#include "ttm/ttm_placement.h"
	31
8e19a951 JB	32	bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
	33	{
	34	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	35	uint32_t fifo_min, hwversion;
	36
d7e1958d JB	37	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
	38	return false;
	39
8e19a951 JB	40	fifo_min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	41	if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
	42	return false;
	43
	44	hwversion = ioread32(fifo_mem + SVGA_FIFO_3D_HWVERSION);
	45	if (hwversion == 0)
	46	return false;
	47
b7b70024	48	if (hwversion < SVGA3D_HWVERSION_WS8_B1)
8e19a951 JB	49	return false;
8e19a951 JB	50
01e81419 JB	51	/* Non-Screen Object path does not support surfaces */
	52	if (!dev_priv->sou_priv)
	53	return false;
	54
8e19a951 JB	55	return true;
	56	}
	57
d7e1958d JB	58	bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
	59	{
	60	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	61	uint32_t caps;
	62
	63	if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
	64	return false;
	65
	66	caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	67	if (caps & SVGA_FIFO_CAP_PITCHLOCK)
	68	return true;
	69
	70	return false;
	71	}
	72
fb1d9738 JB	73	int vmw_fifo_init(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
	74	{
	75	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	76	uint32_t max;
	77	uint32_t min;
	78	uint32_t dummy;
fb1d9738 JB	79
	80	fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
	81	fifo->static_buffer = vmalloc(fifo->static_buffer_size);
	82	if (unlikely(fifo->static_buffer == NULL))
	83	return -ENOMEM;
	84
fb1d9738 JB	85	fifo->dynamic_buffer = NULL;
	86	fifo->reserved_size = 0;
	87	fifo->using_bounce_buffer = false;
	88
85b9e487	89	mutex_init(&fifo->fifo_mutex);
fb1d9738 JB	90	init_rwsem(&fifo->rwsem);
	91
	92	/*
	93	* Allow mapping the first page read-only to user-space.
	94	*/
	95
	96	DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
	97	DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
	98	DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
	99
	100	mutex_lock(&dev_priv->hw_mutex);
	101	dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
	102	dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
30c78bb8	103	dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
fb1d9738 JB	104	vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
	105
	106	min = 4;
	107	if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
	108	min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
	109	min <<= 2;
	110
	111	if (min < PAGE_SIZE)
	112	min = PAGE_SIZE;
	113
	114	iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
	115	iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
	116	wmb();
	117	iowrite32(min, fifo_mem + SVGA_FIFO_NEXT_CMD);
	118	iowrite32(min, fifo_mem + SVGA_FIFO_STOP);
	119	iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
	120	mb();
	121
	122	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
	123	mutex_unlock(&dev_priv->hw_mutex);
	124
	125	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	126	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	127	fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
	128
	129	DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
	130	(unsigned int) max,
	131	(unsigned int) min,
	132	(unsigned int) fifo->capabilities);
	133
6bcd8d3c TH	134	atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
	135	iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
	136	vmw_marker_queue_init(&fifo->marker_queue);
fb1d9738	137	return vmw_fifo_send_fence(dev_priv, &dummy);
fb1d9738 JB	138	}
	139
	140	void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
	141	{
	142	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	143
	144	mutex_lock(&dev_priv->hw_mutex);
	145
	146	if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
	147	iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
	148	vmw_write(dev_priv, SVGA_REG_SYNC, reason);
	149	}
	150
	151	mutex_unlock(&dev_priv->hw_mutex);
	152	}
	153
	154	void vmw_fifo_release(struct vmw_private dev_priv, struct vmw_fifo_state fifo)
	155	{
	156	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	157
	158	mutex_lock(&dev_priv->hw_mutex);
	159
	160	while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
	161	vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
	162
6bcd8d3c	163	dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
fb1d9738 JB	164
	165	vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
	166	dev_priv->config_done_state);
	167	vmw_write(dev_priv, SVGA_REG_ENABLE,
	168	dev_priv->enable_state);
30c78bb8 TH	169	vmw_write(dev_priv, SVGA_REG_TRACES,
30c78bb8 TH	170	dev_priv->traces_state);
fb1d9738 JB	171
fb1d9738 JB	172	mutex_unlock(&dev_priv->hw_mutex);
6bcd8d3c	173	vmw_marker_queue_takedown(&fifo->marker_queue);
fb1d9738	174
fb1d9738 JB	175	if (likely(fifo->static_buffer != NULL)) {
	176	vfree(fifo->static_buffer);
	177	fifo->static_buffer = NULL;
	178	}
	179
	180	if (likely(fifo->dynamic_buffer != NULL)) {
	181	vfree(fifo->dynamic_buffer);
	182	fifo->dynamic_buffer = NULL;
	183	}
	184	}
	185
	186	static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
	187	{
	188	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	189	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	190	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	191	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	192	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
	193
	194	return ((max - next_cmd) + (stop - min) <= bytes);
	195	}
	196
	197	static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
	198	uint32_t bytes, bool interruptible,
	199	unsigned long timeout)
	200	{
	201	int ret = 0;
	202	unsigned long end_jiffies = jiffies + timeout;
	203	DEFINE_WAIT(__wait);
	204
	205	DRM_INFO("Fifo wait noirq.\n");
	206
	207	for (;;) {
	208	prepare_to_wait(&dev_priv->fifo_queue, &__wait,
	209	(interruptible) ?
	210	TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
	211	if (!vmw_fifo_is_full(dev_priv, bytes))
	212	break;
	213	if (time_after_eq(jiffies, end_jiffies)) {
	214	ret = -EBUSY;
	215	DRM_ERROR("SVGA device lockup.\n");
	216	break;
	217	}
	218	schedule_timeout(1);
	219	if (interruptible && signal_pending(current)) {
3d3a5b32	220	ret = -ERESTARTSYS;
fb1d9738 JB	221	break;
	222	}
	223	}
	224	finish_wait(&dev_priv->fifo_queue, &__wait);
	225	wake_up_all(&dev_priv->fifo_queue);
	226	DRM_INFO("Fifo noirq exit.\n");
	227	return ret;
	228	}
	229
	230	static int vmw_fifo_wait(struct vmw_private *dev_priv,
	231	uint32_t bytes, bool interruptible,
	232	unsigned long timeout)
	233	{
	234	long ret = 1L;
	235	unsigned long irq_flags;
	236
	237	if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
	238	return 0;
	239
	240	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
	241	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
	242	return vmw_fifo_wait_noirq(dev_priv, bytes,
	243	interruptible, timeout);
	244
	245	mutex_lock(&dev_priv->hw_mutex);
	246	if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
	247	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
	248	outl(SVGA_IRQFLAG_FIFO_PROGRESS,
	249	dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
	250	vmw_write(dev_priv, SVGA_REG_IRQMASK,
	251	vmw_read(dev_priv, SVGA_REG_IRQMASK) \|
	252	SVGA_IRQFLAG_FIFO_PROGRESS);
	253	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	254	}
	255	mutex_unlock(&dev_priv->hw_mutex);
	256
	257	if (interruptible)
	258	ret = wait_event_interruptible_timeout
	259	(dev_priv->fifo_queue,
	260	!vmw_fifo_is_full(dev_priv, bytes), timeout);
	261	else
	262	ret = wait_event_timeout
	263	(dev_priv->fifo_queue,
	264	!vmw_fifo_is_full(dev_priv, bytes), timeout);
	265
3d3a5b32	266	if (unlikely(ret == 0))
fb1d9738 JB	267	ret = -EBUSY;
	268	else if (likely(ret > 0))
	269	ret = 0;
	270
	271	mutex_lock(&dev_priv->hw_mutex);
	272	if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
	273	spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
	274	vmw_write(dev_priv, SVGA_REG_IRQMASK,
	275	vmw_read(dev_priv, SVGA_REG_IRQMASK) &
	276	~SVGA_IRQFLAG_FIFO_PROGRESS);
	277	spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
	278	}
	279	mutex_unlock(&dev_priv->hw_mutex);
	280
	281	return ret;
	282	}
	283
de12d44f JB	284	/**
	285	* Reserve @bytes number of bytes in the fifo.
	286	*
	287	* This function will return NULL (error) on two conditions:
	288	* If it timeouts waiting for fifo space, or if @bytes is larger than the
	289	* available fifo space.
	290	*
	291	* Returns:
	292	* Pointer to the fifo, or null on error (possible hardware hang).
	293	*/
fb1d9738 JB	294	void vmw_fifo_reserve(struct vmw_private dev_priv, uint32_t bytes)
	295	{
	296	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	297	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	298	uint32_t max;
	299	uint32_t min;
	300	uint32_t next_cmd;
	301	uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	302	int ret;
	303
85b9e487	304	mutex_lock(&fifo_state->fifo_mutex);
fb1d9738 JB	305	max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	306	min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	307	next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	308
	309	if (unlikely(bytes >= (max - min)))
	310	goto out_err;
	311
	312	BUG_ON(fifo_state->reserved_size != 0);
	313	BUG_ON(fifo_state->dynamic_buffer != NULL);
	314
	315	fifo_state->reserved_size = bytes;
	316
	317	while (1) {
	318	uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
	319	bool need_bounce = false;
	320	bool reserve_in_place = false;
	321
	322	if (next_cmd >= stop) {
	323	if (likely((next_cmd + bytes < max \|\|
	324	(next_cmd + bytes == max && stop > min))))
	325	reserve_in_place = true;
	326
	327	else if (vmw_fifo_is_full(dev_priv, bytes)) {
	328	ret = vmw_fifo_wait(dev_priv, bytes,
	329	false, 3 * HZ);
	330	if (unlikely(ret != 0))
	331	goto out_err;
	332	} else
	333	need_bounce = true;
	334
	335	} else {
	336
	337	if (likely((next_cmd + bytes < stop)))
	338	reserve_in_place = true;
	339	else {
	340	ret = vmw_fifo_wait(dev_priv, bytes,
	341	false, 3 * HZ);
	342	if (unlikely(ret != 0))
	343	goto out_err;
	344	}
	345	}
	346
	347	if (reserve_in_place) {
	348	if (reserveable \|\| bytes <= sizeof(uint32_t)) {
	349	fifo_state->using_bounce_buffer = false;
	350
	351	if (reserveable)
	352	iowrite32(bytes, fifo_mem +
	353	SVGA_FIFO_RESERVED);
	354	return fifo_mem + (next_cmd >> 2);
	355	} else {
	356	need_bounce = true;
	357	}
	358	}
	359
	360	if (need_bounce) {
	361	fifo_state->using_bounce_buffer = true;
	362	if (bytes < fifo_state->static_buffer_size)
	363	return fifo_state->static_buffer;
	364	else {
	365	fifo_state->dynamic_buffer = vmalloc(bytes);
	366	return fifo_state->dynamic_buffer;
	367	}
	368	}
369	}
370	out_err:
371	fifo_state->reserved_size = 0;
85b9e487	372	mutex_unlock(&fifo_state->fifo_mutex);
fb1d9738 JB	373	return NULL;
	374	}
	375
	376	static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
	377	__le32 __iomem *fifo_mem,
	378	uint32_t next_cmd,
	379	uint32_t max, uint32_t min, uint32_t bytes)
	380	{
	381	uint32_t chunk_size = max - next_cmd;
	382	uint32_t rest;
	383	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	384	fifo_state->dynamic_buffer : fifo_state->static_buffer;
	385
	386	if (bytes < chunk_size)
	387	chunk_size = bytes;
	388
	389	iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
	390	mb();
	391	memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
	392	rest = bytes - chunk_size;
	393	if (rest)
	394	memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
	395	rest);
	396	}
	397
	398	static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
	399	__le32 __iomem *fifo_mem,
	400	uint32_t next_cmd,
	401	uint32_t max, uint32_t min, uint32_t bytes)
	402	{
	403	uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
	404	fifo_state->dynamic_buffer : fifo_state->static_buffer;
	405
	406	while (bytes > 0) {
	407	iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
	408	next_cmd += sizeof(uint32_t);
	409	if (unlikely(next_cmd == max))
	410	next_cmd = min;
	411	mb();
	412	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	413	mb();
	414	bytes -= sizeof(uint32_t);
	415	}
	416	}
	417
	418	void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
	419	{
	420	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	421	__le32 __iomem *fifo_mem = dev_priv->mmio_virt;
	422	uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
	423	uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
	424	uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
	425	bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
	426
	427	BUG_ON((bytes & 3) != 0);
	428	BUG_ON(bytes > fifo_state->reserved_size);
	429
	430	fifo_state->reserved_size = 0;
	431
	432	if (fifo_state->using_bounce_buffer) {
	433	if (reserveable)
	434	vmw_fifo_res_copy(fifo_state, fifo_mem,
	435	next_cmd, max, min, bytes);
	436	else
437	vmw_fifo_slow_copy(fifo_state, fifo_mem,
438	next_cmd, max, min, bytes);
439
440	if (fifo_state->dynamic_buffer) {
441	vfree(fifo_state->dynamic_buffer);
442	fifo_state->dynamic_buffer = NULL;
443	}
444
445	}
446
85b9e487	447	down_write(&fifo_state->rwsem);
fb1d9738 JB	448	if (fifo_state->using_bounce_buffer \|\| reserveable) {
	449	next_cmd += bytes;
	450	if (next_cmd >= max)
	451	next_cmd -= max - min;
	452	mb();
	453	iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
	454	}
	455
	456	if (reserveable)
	457	iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
	458	mb();
fb1d9738	459	up_write(&fifo_state->rwsem);
85b9e487 TH	460	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
85b9e487 TH	461	mutex_unlock(&fifo_state->fifo_mutex);
fb1d9738 JB	462	}
fb1d9738 JB	463
6bcd8d3c	464	int vmw_fifo_send_fence(struct vmw_private dev_priv, uint32_t seqno)
fb1d9738 JB	465	{
	466	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
	467	struct svga_fifo_cmd_fence *cmd_fence;
	468	void *fm;
	469	int ret = 0;
	470	uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
	471
	472	fm = vmw_fifo_reserve(dev_priv, bytes);
	473	if (unlikely(fm == NULL)) {
6bcd8d3c	474	*seqno = atomic_read(&dev_priv->marker_seq);
fb1d9738	475	ret = -ENOMEM;
6bcd8d3c	476	(void)vmw_fallback_wait(dev_priv, false, true, *seqno,
fb1d9738 JB	477	false, 3*HZ);
	478	goto out_err;
	479	}
	480
	481	do {
6bcd8d3c TH	482	*seqno = atomic_add_return(1, &dev_priv->marker_seq);
6bcd8d3c TH	483	} while (*seqno == 0);
fb1d9738 JB	484
	485	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
	486
	487	/*
	488	* Don't request hardware to send a fence. The
	489	* waiting code in vmwgfx_irq.c will emulate this.
	490	*/
	491
	492	vmw_fifo_commit(dev_priv, 0);
	493	return 0;
	494	}
	495
	496	(__le32 ) fm = cpu_to_le32(SVGA_CMD_FENCE);
	497	cmd_fence = (struct svga_fifo_cmd_fence *)
	498	((unsigned long)fm + sizeof(__le32));
	499
6bcd8d3c	500	iowrite32(*seqno, &cmd_fence->fence);
fb1d9738	501	vmw_fifo_commit(dev_priv, bytes);
6bcd8d3c TH	502	(void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
6bcd8d3c TH	503	vmw_update_seqno(dev_priv, fifo_state);
fb1d9738 JB	504
	505	out_err:
	506	return ret;
	507	}
e2fa3a76 TH	508
	509	/**
	510	* vmw_fifo_emit_dummy_query - emits a dummy query to the fifo.
	511	*
	512	* @dev_priv: The device private structure.
	513	* @cid: The hardware context id used for the query.
	514	*
	515	* This function is used to emit a dummy occlusion query with
	516	* no primitives rendered between query begin and query end.
	517	* It's used to provide a query barrier, in order to know that when
	518	* this query is finished, all preceding queries are also finished.
	519	*
	520	* A Query results structure should have been initialized at the start
	521	* of the dev_priv->dummy_query_bo buffer object. And that buffer object
	522	* must also be either reserved or pinned when this function is called.
	523	*
	524	* Returns -ENOMEM on failure to reserve fifo space.
	525	*/
	526	int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
	527	uint32_t cid)
	528	{
	529	/*
	530	* A query wait without a preceding query end will
	531	* actually finish all queries for this cid
	532	* without writing to the query result structure.
	533	*/
	534
	535	struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
	536	struct {
	537	SVGA3dCmdHeader header;
	538	SVGA3dCmdWaitForQuery body;
	539	} *cmd;
	540
	541	cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
	542
	543	if (unlikely(cmd == NULL)) {
	544	DRM_ERROR("Out of fifo space for dummy query.\n");
	545	return -ENOMEM;
	546	}
	547
	548	cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
	549	cmd->header.size = sizeof(cmd->body);
	550	cmd->body.cid = cid;
	551	cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
	552
	553	if (bo->mem.mem_type == TTM_PL_VRAM) {
	554	cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
	555	cmd->body.guestResult.offset = bo->offset;
	556	} else {
	557	cmd->body.guestResult.gmrId = bo->mem.start;
	558	cmd->body.guestResult.offset = 0;
	559	}
	560
	561	vmw_fifo_commit(dev_priv, sizeof(*cmd));
	562
	563	return 0;
	564	}