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vmwgfx: Whitespace & code style in display unit
[deliverable/linux.git] / drivers / gpu / drm / vmwgfx / vmwgfx_kms.c
CommitLineData
fb1d9738
JB		 1/**************************************************************************
2 *
3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "vmwgfx_kms.h"
29
56d1c78d 30
fb1d9738
JB		 31/* Might need a hrtimer here? */
32#define VMWGFX_PRESENT_RATE ((HZ / 60 > 0) ? HZ / 60 : 1)
33
fb1d9738
JB		 34void vmw_display_unit_cleanup(struct vmw_display_unit *du)
35{
36 if (du->cursor_surface)
37 vmw_surface_unreference(&du->cursor_surface);
38 if (du->cursor_dmabuf)
39 vmw_dmabuf_unreference(&du->cursor_dmabuf);
40 drm_crtc_cleanup(&du->crtc);
41 drm_encoder_cleanup(&du->encoder);
42 drm_connector_cleanup(&du->connector);
43}
44
45/*
46 * Display Unit Cursor functions
47 */
48
49int vmw_cursor_update_image(struct vmw_private *dev_priv,
50 u32 *image, u32 width, u32 height,
51 u32 hotspotX, u32 hotspotY)
52{
53 struct {
54 u32 cmd;
55 SVGAFifoCmdDefineAlphaCursor cursor;
56 } *cmd;
57 u32 image_size = width * height * 4;
58 u32 cmd_size = sizeof(*cmd) + image_size;
59
60 if (!image)
61 return -EINVAL;
62
63 cmd = vmw_fifo_reserve(dev_priv, cmd_size);
64 if (unlikely(cmd == NULL)) {
65 DRM_ERROR("Fifo reserve failed.\n");
66 return -ENOMEM;
67 }
68
69 memset(cmd, 0, sizeof(*cmd));
70
71 memcpy(&cmd[1], image, image_size);
72
73 cmd->cmd = cpu_to_le32(SVGA_CMD_DEFINE_ALPHA_CURSOR);
74 cmd->cursor.id = cpu_to_le32(0);
75 cmd->cursor.width = cpu_to_le32(width);
76 cmd->cursor.height = cpu_to_le32(height);
77 cmd->cursor.hotspotX = cpu_to_le32(hotspotX);
78 cmd->cursor.hotspotY = cpu_to_le32(hotspotY);
79
80 vmw_fifo_commit(dev_priv, cmd_size);
81
82 return 0;
83}
84
85void vmw_cursor_update_position(struct vmw_private *dev_priv,
86 bool show, int x, int y)
87{
88 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
89 uint32_t count;
90
91 iowrite32(show ? 1 : 0, fifo_mem + SVGA_FIFO_CURSOR_ON);
92 iowrite32(x, fifo_mem + SVGA_FIFO_CURSOR_X);
93 iowrite32(y, fifo_mem + SVGA_FIFO_CURSOR_Y);
94 count = ioread32(fifo_mem + SVGA_FIFO_CURSOR_COUNT);
95 iowrite32(++count, fifo_mem + SVGA_FIFO_CURSOR_COUNT);
96}
97
98int vmw_du_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
99 uint32_t handle, uint32_t width, uint32_t height)
100{
101 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
102 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
103 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
104 struct vmw_surface *surface = NULL;
105 struct vmw_dma_buffer *dmabuf = NULL;
106 int ret;
107
108 if (handle) {
7a73ba74
TH		 109 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
110 handle, &surface);
fb1d9738
JB		 111 if (!ret) {
112 if (!surface->snooper.image) {
113 DRM_ERROR("surface not suitable for cursor\n");
114 return -EINVAL;
115 }
116 } else {
117 ret = vmw_user_dmabuf_lookup(tfile,
118 handle, &dmabuf);
119 if (ret) {
120 DRM_ERROR("failed to find surface or dmabuf: %i\n", ret);
121 return -EINVAL;
122 }
123 }
124 }
125
126 /* takedown old cursor */
127 if (du->cursor_surface) {
128 du->cursor_surface->snooper.crtc = NULL;
129 vmw_surface_unreference(&du->cursor_surface);
130 }
131 if (du->cursor_dmabuf)
132 vmw_dmabuf_unreference(&du->cursor_dmabuf);
133
134 /* setup new image */
135 if (surface) {
136 /* vmw_user_surface_lookup takes one reference */
137 du->cursor_surface = surface;
138
139 du->cursor_surface->snooper.crtc = crtc;
140 du->cursor_age = du->cursor_surface->snooper.age;
141 vmw_cursor_update_image(dev_priv, surface->snooper.image,
142 64, 64, du->hotspot_x, du->hotspot_y);
143 } else if (dmabuf) {
144 struct ttm_bo_kmap_obj map;
145 unsigned long kmap_offset;
146 unsigned long kmap_num;
147 void *virtual;
148 bool dummy;
149
150 /* vmw_user_surface_lookup takes one reference */
151 du->cursor_dmabuf = dmabuf;
152
153 kmap_offset = 0;
154 kmap_num = (64*64*4) >> PAGE_SHIFT;
155
156 ret = ttm_bo_reserve(&dmabuf->base, true, false, false, 0);
157 if (unlikely(ret != 0)) {
158 DRM_ERROR("reserve failed\n");
159 return -EINVAL;
160 }
161
162 ret = ttm_bo_kmap(&dmabuf->base, kmap_offset, kmap_num, &map);
163 if (unlikely(ret != 0))
164 goto err_unreserve;
165
166 virtual = ttm_kmap_obj_virtual(&map, &dummy);
167 vmw_cursor_update_image(dev_priv, virtual, 64, 64,
168 du->hotspot_x, du->hotspot_y);
169
170 ttm_bo_kunmap(&map);
171err_unreserve:
172 ttm_bo_unreserve(&dmabuf->base);
173
174 } else {
175 vmw_cursor_update_position(dev_priv, false, 0, 0);
176 return 0;
177 }
178
179 vmw_cursor_update_position(dev_priv, true, du->cursor_x, du->cursor_y);
180
181 return 0;
182}
183
184int vmw_du_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
185{
186 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
187 struct vmw_display_unit *du = vmw_crtc_to_du(crtc);
188 bool shown = du->cursor_surface || du->cursor_dmabuf ? true : false;
189
190 du->cursor_x = x + crtc->x;
191 du->cursor_y = y + crtc->y;
192
193 vmw_cursor_update_position(dev_priv, shown,
194 du->cursor_x, du->cursor_y);
195
196 return 0;
197}
198
199void vmw_kms_cursor_snoop(struct vmw_surface *srf,
200 struct ttm_object_file *tfile,
201 struct ttm_buffer_object *bo,
202 SVGA3dCmdHeader *header)
203{
204 struct ttm_bo_kmap_obj map;
205 unsigned long kmap_offset;
206 unsigned long kmap_num;
207 SVGA3dCopyBox *box;
208 unsigned box_count;
209 void *virtual;
210 bool dummy;
211 struct vmw_dma_cmd {
212 SVGA3dCmdHeader header;
213 SVGA3dCmdSurfaceDMA dma;
214 } *cmd;
215 int ret;
216
217 cmd = container_of(header, struct vmw_dma_cmd, header);
218
219 /* No snooper installed */
220 if (!srf->snooper.image)
221 return;
222
223 if (cmd->dma.host.face != 0 || cmd->dma.host.mipmap != 0) {
224 DRM_ERROR("face and mipmap for cursors should never != 0\n");
225 return;
226 }
227
228 if (cmd->header.size < 64) {
229 DRM_ERROR("at least one full copy box must be given\n");
230 return;
231 }
232
233 box = (SVGA3dCopyBox *)&cmd[1];
234 box_count = (cmd->header.size - sizeof(SVGA3dCmdSurfaceDMA)) /
235 sizeof(SVGA3dCopyBox);
236
237 if (cmd->dma.guest.pitch != (64 * 4) ||
238 cmd->dma.guest.ptr.offset % PAGE_SIZE ||
239 box->x != 0 || box->y != 0 || box->z != 0 ||
240 box->srcx != 0 || box->srcy != 0 || box->srcz != 0 ||
241 box->w != 64 || box->h != 64 || box->d != 1 ||
242 box_count != 1) {
243 /* TODO handle none page aligned offsets */
244 /* TODO handle partial uploads and pitch != 256 */
245 /* TODO handle more then one copy (size != 64) */
25985edc 246 DRM_ERROR("lazy programmer, can't handle weird stuff\n");
fb1d9738
JB		 247 return;
248 }
249
250 kmap_offset = cmd->dma.guest.ptr.offset >> PAGE_SHIFT;
251 kmap_num = (64*64*4) >> PAGE_SHIFT;
252
253 ret = ttm_bo_reserve(bo, true, false, false, 0);
254 if (unlikely(ret != 0)) {
255 DRM_ERROR("reserve failed\n");
256 return;
257 }
258
259 ret = ttm_bo_kmap(bo, kmap_offset, kmap_num, &map);
260 if (unlikely(ret != 0))
261 goto err_unreserve;
262
263 virtual = ttm_kmap_obj_virtual(&map, &dummy);
264
265 memcpy(srf->snooper.image, virtual, 64*64*4);
266 srf->snooper.age++;
267
268 /* we can't call this function from this function since execbuf has
269 * reserved fifo space.
270 *
271 * if (srf->snooper.crtc)
272 * vmw_ldu_crtc_cursor_update_image(dev_priv,
273 * srf->snooper.image, 64, 64,
274 * du->hotspot_x, du->hotspot_y);
275 */
276
277 ttm_bo_kunmap(&map);
278err_unreserve:
279 ttm_bo_unreserve(bo);
280}
281
282void vmw_kms_cursor_post_execbuf(struct vmw_private *dev_priv)
283{
284 struct drm_device *dev = dev_priv->dev;
285 struct vmw_display_unit *du;
286 struct drm_crtc *crtc;
287
288 mutex_lock(&dev->mode_config.mutex);
289
290 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
291 du = vmw_crtc_to_du(crtc);
292 if (!du->cursor_surface ||
293 du->cursor_age == du->cursor_surface->snooper.age)
294 continue;
295
296 du->cursor_age = du->cursor_surface->snooper.age;
297 vmw_cursor_update_image(dev_priv,
298 du->cursor_surface->snooper.image,
299 64, 64, du->hotspot_x, du->hotspot_y);
300 }
301
302 mutex_unlock(&dev->mode_config.mutex);
303}
304
305/*
306 * Generic framebuffer code
307 */
308
309int vmw_framebuffer_create_handle(struct drm_framebuffer *fb,
310 struct drm_file *file_priv,
311 unsigned int *handle)
312{
313 if (handle)
314 handle = 0;
315
316 return 0;
317}
318
319/*
320 * Surface framebuffer code
321 */
322
323#define vmw_framebuffer_to_vfbs(x) \
324 container_of(x, struct vmw_framebuffer_surface, base.base)
325
326struct vmw_framebuffer_surface {
327 struct vmw_framebuffer base;
328 struct vmw_surface *surface;
22ee861c 329 struct vmw_dma_buffer *buffer;
3a939a5e
TH		 330 struct list_head head;
331 struct drm_master *master;
fb1d9738
JB		 332};
333
334void vmw_framebuffer_surface_destroy(struct drm_framebuffer *framebuffer)
335{
3a939a5e 336 struct vmw_framebuffer_surface *vfbs =
fb1d9738 337 vmw_framebuffer_to_vfbs(framebuffer);
3a939a5e
TH		 338 struct vmw_master *vmaster = vmw_master(vfbs->master);
339
340
341 mutex_lock(&vmaster->fb_surf_mutex);
342 list_del(&vfbs->head);
343 mutex_unlock(&vmaster->fb_surf_mutex);
fb1d9738 344
3a939a5e 345 drm_master_put(&vfbs->master);
fb1d9738 346 drm_framebuffer_cleanup(framebuffer);
3a939a5e 347 vmw_surface_unreference(&vfbs->surface);
90ff18bc 348 ttm_base_object_unref(&vfbs->base.user_obj);
fb1d9738 349
3a939a5e 350 kfree(vfbs);
fb1d9738
JB		 351}
352
56d1c78d 353static int do_surface_dirty_sou(struct vmw_private *dev_priv,
90ff18bc 354 struct drm_file *file_priv,
56d1c78d
JB		 355 struct vmw_framebuffer *framebuffer,
356 struct vmw_surface *surf,
357 unsigned flags, unsigned color,
358 struct drm_clip_rect *clips,
359 unsigned num_clips, int inc)
360{
c6ca8391
JB		 361 struct drm_clip_rect *clips_ptr;
362 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
363 struct drm_crtc *crtc;
56d1c78d 364 size_t fifo_size;
c6ca8391
JB		 365 int i, num_units;
366 int ret = 0; /* silence warning */
367 int left, right, top, bottom;
56d1c78d
JB		 368
369 struct {
370 SVGA3dCmdHeader header;
371 SVGA3dCmdBlitSurfaceToScreen body;
372 } *cmd;
c6ca8391 373 SVGASignedRect *blits;
56d1c78d
JB		 374
375
c6ca8391
JB		 376 num_units = 0;
377 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list,
378 head) {
379 if (crtc->fb != &framebuffer->base)
380 continue;
381 units[num_units++] = vmw_crtc_to_du(crtc);
382 }
383
384 BUG_ON(surf == NULL);
385 BUG_ON(!clips || !num_clips);
386
387 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
90ff18bc 388 cmd = kzalloc(fifo_size, GFP_KERNEL);
56d1c78d 389 if (unlikely(cmd == NULL)) {
90ff18bc 390 DRM_ERROR("Temporary fifo memory alloc failed.\n");
56d1c78d
JB		 391 return -ENOMEM;
392 }
393
c6ca8391
JB		 394 left = clips->x1;
395 right = clips->x2;
396 top = clips->y1;
397 bottom = clips->y2;
398
399 clips_ptr = clips;
400 for (i = 1; i < num_clips; i++, clips_ptr += inc) {
401 left = min_t(int, left, (int)clips_ptr->x1);
402 right = max_t(int, right, (int)clips_ptr->x2);
403 top = min_t(int, top, (int)clips_ptr->y1);
404 bottom = max_t(int, bottom, (int)clips_ptr->y2);
56d1c78d
JB		 405 }
406
c6ca8391
JB		 407 /* only need to do this once */
408 memset(cmd, 0, fifo_size);
409 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
410 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
411
56d1c78d
JB		 412 cmd->body.srcRect.left = left;
413 cmd->body.srcRect.right = right;
414 cmd->body.srcRect.top = top;
415 cmd->body.srcRect.bottom = bottom;
416
c6ca8391
JB		 417 clips_ptr = clips;
418 blits = (SVGASignedRect *)&cmd[1];
419 for (i = 0; i < num_clips; i++, clips_ptr += inc) {
420 blits[i].left = clips_ptr->x1 - left;
421 blits[i].right = clips_ptr->x2 - left;
422 blits[i].top = clips_ptr->y1 - top;
423 blits[i].bottom = clips_ptr->y2 - top;
424 }
425
426 /* do per unit writing, reuse fifo for each */
427 for (i = 0; i < num_units; i++) {
428 struct vmw_display_unit *unit = units[i];
429 int clip_x1 = left - unit->crtc.x;
430 int clip_y1 = top - unit->crtc.y;
431 int clip_x2 = right - unit->crtc.x;
432 int clip_y2 = bottom - unit->crtc.y;
433
434 /* skip any crtcs that misses the clip region */
435 if (clip_x1 >= unit->crtc.mode.hdisplay ||
436 clip_y1 >= unit->crtc.mode.vdisplay ||
437 clip_x2 <= 0 || clip_y2 <= 0)
438 continue;
439
440 /* need to reset sid as it is changed by execbuf */
441 cmd->body.srcImage.sid = cpu_to_le32(framebuffer->user_handle);
442
443 cmd->body.destScreenId = unit->unit;
444
445 /*
446 * The blit command is a lot more resilient then the
447 * readback command when it comes to clip rects. So its
448 * okay to go out of bounds.
449 */
450
451 cmd->body.destRect.left = clip_x1;
452 cmd->body.destRect.right = clip_x2;
453 cmd->body.destRect.top = clip_y1;
454 cmd->body.destRect.bottom = clip_y2;
455
456
457 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
458 fifo_size, 0, NULL);
459
460 if (unlikely(ret != 0))
461 break;
462 }
56d1c78d 463
90ff18bc 464 kfree(cmd);
56d1c78d 465
90ff18bc 466 return ret;
5deb65cf 467}
fb1d9738
JB		 468
469int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer,
02b00162 470 struct drm_file *file_priv,
fb1d9738
JB		 471 unsigned flags, unsigned color,
472 struct drm_clip_rect *clips,
473 unsigned num_clips)
474{
475 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 476 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 477 struct vmw_framebuffer_surface *vfbs =
478 vmw_framebuffer_to_vfbs(framebuffer);
479 struct vmw_surface *surf = vfbs->surface;
480 struct drm_clip_rect norect;
5deb65cf 481 int ret, inc = 1;
fb1d9738 482
3a939a5e
TH		 483 if (unlikely(vfbs->master != file_priv->master))
484 return -EINVAL;
485
01e81419
JB		 486 /* Require ScreenObject support for 3D */
487 if (!dev_priv->sou_priv)
488 return -EINVAL;
489
3a939a5e
TH		 490 ret = ttm_read_lock(&vmaster->lock, true);
491 if (unlikely(ret != 0))
492 return ret;
493
fb1d9738
JB		 494 if (!num_clips) {
495 num_clips = 1;
496 clips = &norect;
497 norect.x1 = norect.y1 = 0;
498 norect.x2 = framebuffer->width;
499 norect.y2 = framebuffer->height;
500 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
501 num_clips /= 2;
502 inc = 2; /* skip source rects */
503 }
504
90ff18bc 505 ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base, surf,
01e81419
JB		 506 flags, color,
507 clips, num_clips, inc);
fb1d9738 508
3a939a5e 509 ttm_read_unlock(&vmaster->lock);
fb1d9738
JB		 510 return 0;
511}
512
513static struct drm_framebuffer_funcs vmw_framebuffer_surface_funcs = {
514 .destroy = vmw_framebuffer_surface_destroy,
515 .dirty = vmw_framebuffer_surface_dirty,
516 .create_handle = vmw_framebuffer_create_handle,
517};
518
d3216a0c 519static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv,
3a939a5e 520 struct drm_file *file_priv,
d3216a0c
TH		 521 struct vmw_surface *surface,
522 struct vmw_framebuffer **out,
523 const struct drm_mode_fb_cmd
524 *mode_cmd)
fb1d9738
JB		 525
526{
527 struct drm_device *dev = dev_priv->dev;
528 struct vmw_framebuffer_surface *vfbs;
d3216a0c 529 enum SVGA3dSurfaceFormat format;
3a939a5e 530 struct vmw_master *vmaster = vmw_master(file_priv->master);
fb1d9738
JB		 531 int ret;
532
01e81419
JB		 533 /* 3D is only supported on HWv8 hosts which supports screen objects */
534 if (!dev_priv->sou_priv)
535 return -ENOSYS;
536
d3216a0c
TH		 537 /*
538 * Sanity checks.
539 */
540
541 if (unlikely(surface->mip_levels[0] != 1 ||
542 surface->num_sizes != 1 ||
543 surface->sizes[0].width < mode_cmd->width ||
544 surface->sizes[0].height < mode_cmd->height ||
545 surface->sizes[0].depth != 1)) {
546 DRM_ERROR("Incompatible surface dimensions "
547 "for requested mode.\n");
548 return -EINVAL;
549 }
550
551 switch (mode_cmd->depth) {
552 case 32:
553 format = SVGA3D_A8R8G8B8;
554 break;
555 case 24:
556 format = SVGA3D_X8R8G8B8;
557 break;
558 case 16:
559 format = SVGA3D_R5G6B5;
560 break;
561 case 15:
562 format = SVGA3D_A1R5G5B5;
563 break;
f01b7ba0
MD		 564 case 8:
565 format = SVGA3D_LUMINANCE8;
566 break;
d3216a0c
TH		 567 default:
568 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
569 return -EINVAL;
570 }
571
572 if (unlikely(format != surface->format)) {
573 DRM_ERROR("Invalid surface format for requested mode.\n");
574 return -EINVAL;
575 }
576
fb1d9738
JB		 577 vfbs = kzalloc(sizeof(*vfbs), GFP_KERNEL);
578 if (!vfbs) {
579 ret = -ENOMEM;
580 goto out_err1;
581 }
582
583 ret = drm_framebuffer_init(dev, &vfbs->base.base,
584 &vmw_framebuffer_surface_funcs);
585 if (ret)
586 goto out_err2;
587
588 if (!vmw_surface_reference(surface)) {
589 DRM_ERROR("failed to reference surface %p\n", surface);
590 goto out_err3;
591 }
592
593 /* XXX get the first 3 from the surface info */
d3216a0c
TH		 594 vfbs->base.base.bits_per_pixel = mode_cmd->bpp;
595 vfbs->base.base.pitch = mode_cmd->pitch;
596 vfbs->base.base.depth = mode_cmd->depth;
597 vfbs->base.base.width = mode_cmd->width;
598 vfbs->base.base.height = mode_cmd->height;
fb1d9738 599 vfbs->surface = surface;
90ff18bc 600 vfbs->base.user_handle = mode_cmd->handle;
3a939a5e 601 vfbs->master = drm_master_get(file_priv->master);
3a939a5e
TH		 602
603 mutex_lock(&vmaster->fb_surf_mutex);
3a939a5e
TH		 604 list_add_tail(&vfbs->head, &vmaster->fb_surf);
605 mutex_unlock(&vmaster->fb_surf_mutex);
606
fb1d9738
JB		 607 *out = &vfbs->base;
608
609 return 0;
610
611out_err3:
612 drm_framebuffer_cleanup(&vfbs->base.base);
613out_err2:
614 kfree(vfbs);
615out_err1:
616 return ret;
617}
618
619/*
620 * Dmabuf framebuffer code
621 */
622
623#define vmw_framebuffer_to_vfbd(x) \
624 container_of(x, struct vmw_framebuffer_dmabuf, base.base)
625
626struct vmw_framebuffer_dmabuf {
627 struct vmw_framebuffer base;
628 struct vmw_dma_buffer *buffer;
629};
630
631void vmw_framebuffer_dmabuf_destroy(struct drm_framebuffer *framebuffer)
632{
633 struct vmw_framebuffer_dmabuf *vfbd =
634 vmw_framebuffer_to_vfbd(framebuffer);
635
636 drm_framebuffer_cleanup(framebuffer);
637 vmw_dmabuf_unreference(&vfbd->buffer);
90ff18bc 638 ttm_base_object_unref(&vfbd->base.user_obj);
fb1d9738
JB		 639
640 kfree(vfbd);
641}
642
5deb65cf
JB		 643static int do_dmabuf_dirty_ldu(struct vmw_private *dev_priv,
644 struct vmw_framebuffer *framebuffer,
645 struct vmw_dma_buffer *buffer,
646 unsigned flags, unsigned color,
647 struct drm_clip_rect *clips,
648 unsigned num_clips, int increment)
649{
650 size_t fifo_size;
651 int i;
652
653 struct {
654 uint32_t header;
655 SVGAFifoCmdUpdate body;
656 } *cmd;
657
658 fifo_size = sizeof(*cmd) * num_clips;
659 cmd = vmw_fifo_reserve(dev_priv, fifo_size);
660 if (unlikely(cmd == NULL)) {
661 DRM_ERROR("Fifo reserve failed.\n");
662 return -ENOMEM;
663 }
664
665 memset(cmd, 0, fifo_size);
666 for (i = 0; i < num_clips; i++, clips += increment) {
667 cmd[i].header = cpu_to_le32(SVGA_CMD_UPDATE);
668 cmd[i].body.x = cpu_to_le32(clips->x1);
669 cmd[i].body.y = cpu_to_le32(clips->y1);
670 cmd[i].body.width = cpu_to_le32(clips->x2 - clips->x1);
671 cmd[i].body.height = cpu_to_le32(clips->y2 - clips->y1);
672 }
673
674 vmw_fifo_commit(dev_priv, fifo_size);
675 return 0;
676}
677
c6ca8391
JB		 678static int do_dmabuf_define_gmrfb(struct drm_file *file_priv,
679 struct vmw_private *dev_priv,
680 struct vmw_framebuffer *framebuffer)
56d1c78d 681{
56d1c78d 682 size_t fifo_size;
c6ca8391 683 int ret;
56d1c78d
JB		 684
685 struct {
686 uint32_t header;
687 SVGAFifoCmdDefineGMRFB body;
688 } *cmd;
56d1c78d 689
c6ca8391 690 fifo_size = sizeof(*cmd);
56d1c78d
JB		 691 cmd = kmalloc(fifo_size, GFP_KERNEL);
692 if (unlikely(cmd == NULL)) {
693 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
694 return -ENOMEM;
695 }
696
697 memset(cmd, 0, fifo_size);
698 cmd->header = SVGA_CMD_DEFINE_GMRFB;
699 cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel;
700 cmd->body.format.colorDepth = framebuffer->base.depth;
701 cmd->body.format.reserved = 0;
702 cmd->body.bytesPerLine = framebuffer->base.pitch;
90ff18bc 703 cmd->body.ptr.gmrId = framebuffer->user_handle;
56d1c78d
JB		 704 cmd->body.ptr.offset = 0;
705
56d1c78d
JB		 706 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
707 fifo_size, 0, NULL);
708
709 kfree(cmd);
710
711 return ret;
712}
713
c6ca8391
JB		 714static int do_dmabuf_dirty_sou(struct drm_file *file_priv,
715 struct vmw_private *dev_priv,
716 struct vmw_framebuffer *framebuffer,
717 struct vmw_dma_buffer *buffer,
718 unsigned flags, unsigned color,
719 struct drm_clip_rect *clips,
720 unsigned num_clips, int increment)
721{
722 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
723 struct drm_clip_rect *clips_ptr;
724 int i, k, num_units, ret;
725 struct drm_crtc *crtc;
726 size_t fifo_size;
727
728 struct {
729 uint32_t header;
730 SVGAFifoCmdBlitGMRFBToScreen body;
731 } *blits;
732
733 ret = do_dmabuf_define_gmrfb(file_priv, dev_priv, framebuffer);
734 if (unlikely(ret != 0))
735 return ret; /* define_gmrfb prints warnings */
736
737 fifo_size = sizeof(*blits) * num_clips;
738 blits = kmalloc(fifo_size, GFP_KERNEL);
739 if (unlikely(blits == NULL)) {
740 DRM_ERROR("Failed to allocate temporary cmd buffer.\n");
741 return -ENOMEM;
742 }
743
744 num_units = 0;
745 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
746 if (crtc->fb != &framebuffer->base)
747 continue;
748 units[num_units++] = vmw_crtc_to_du(crtc);
749 }
750
751 for (k = 0; k < num_units; k++) {
752 struct vmw_display_unit *unit = units[k];
753 int hit_num = 0;
754
755 clips_ptr = clips;
756 for (i = 0; i < num_clips; i++, clips_ptr += increment) {
757 int clip_x1 = clips_ptr->x1 - unit->crtc.x;
758 int clip_y1 = clips_ptr->y1 - unit->crtc.y;
759 int clip_x2 = clips_ptr->x2 - unit->crtc.x;
760 int clip_y2 = clips_ptr->y2 - unit->crtc.y;
761
762 /* skip any crtcs that misses the clip region */
763 if (clip_x1 >= unit->crtc.mode.hdisplay ||
764 clip_y1 >= unit->crtc.mode.vdisplay ||
765 clip_x2 <= 0 || clip_y2 <= 0)
766 continue;
767
768 blits[hit_num].header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
769 blits[hit_num].body.destScreenId = unit->unit;
770 blits[hit_num].body.srcOrigin.x = clips_ptr->x1;
771 blits[hit_num].body.srcOrigin.y = clips_ptr->y1;
772 blits[hit_num].body.destRect.left = clip_x1;
773 blits[hit_num].body.destRect.top = clip_y1;
774 blits[hit_num].body.destRect.right = clip_x2;
775 blits[hit_num].body.destRect.bottom = clip_y2;
776 hit_num++;
777 }
778
779 /* no clips hit the crtc */
780 if (hit_num == 0)
781 continue;
782
783 fifo_size = sizeof(*blits) * hit_num;
784 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, blits,
785 fifo_size, 0, NULL);
786
787 if (unlikely(ret != 0))
788 break;
789 }
790
791 kfree(blits);
792
793 return ret;
794}
795
fb1d9738 796int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer,
02b00162 797 struct drm_file *file_priv,
fb1d9738
JB		 798 unsigned flags, unsigned color,
799 struct drm_clip_rect *clips,
800 unsigned num_clips)
801{
802 struct vmw_private *dev_priv = vmw_priv(framebuffer->dev);
3a939a5e 803 struct vmw_master *vmaster = vmw_master(file_priv->master);
5deb65cf
JB		 804 struct vmw_framebuffer_dmabuf *vfbd =
805 vmw_framebuffer_to_vfbd(framebuffer);
806 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
fb1d9738 807 struct drm_clip_rect norect;
5deb65cf 808 int ret, increment = 1;
fb1d9738 809
3a939a5e
TH		 810 ret = ttm_read_lock(&vmaster->lock, true);
811 if (unlikely(ret != 0))
812 return ret;
813
df1c93ba 814 if (!num_clips) {
fb1d9738
JB		 815 num_clips = 1;
816 clips = &norect;
817 norect.x1 = norect.y1 = 0;
818 norect.x2 = framebuffer->width;
819 norect.y2 = framebuffer->height;
820 } else if (flags & DRM_MODE_FB_DIRTY_ANNOTATE_COPY) {
821 num_clips /= 2;
822 increment = 2;
823 }
824
56d1c78d
JB		 825 if (dev_priv->ldu_priv) {
826 ret = do_dmabuf_dirty_ldu(dev_priv, &vfbd->base, dmabuf,
827 flags, color,
828 clips, num_clips, increment);
829 } else {
830 ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base,
831 dmabuf, flags, color,
832 clips, num_clips, increment);
833 }
fb1d9738 834
3a939a5e 835 ttm_read_unlock(&vmaster->lock);
5deb65cf 836 return ret;
fb1d9738
JB		 837}
838
839static struct drm_framebuffer_funcs vmw_framebuffer_dmabuf_funcs = {
840 .destroy = vmw_framebuffer_dmabuf_destroy,
841 .dirty = vmw_framebuffer_dmabuf_dirty,
842 .create_handle = vmw_framebuffer_create_handle,
843};
844
497a3ff9
JB		 845/**
846 * Pin the dmabuffer to the start of vram.
847 */
fb1d9738
JB		 848static int vmw_framebuffer_dmabuf_pin(struct vmw_framebuffer *vfb)
849{
850 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
851 struct vmw_framebuffer_dmabuf *vfbd =
852 vmw_framebuffer_to_vfbd(&vfb->base);
853 int ret;
854
56d1c78d
JB		 855 /* This code should not be used with screen objects */
856 BUG_ON(dev_priv->sou_priv);
d7e1958d 857
fb1d9738
JB		 858 vmw_overlay_pause_all(dev_priv);
859
d991ef03 860 ret = vmw_dmabuf_to_start_of_vram(dev_priv, vfbd->buffer, true, false);
fb1d9738 861
fb1d9738
JB		 862 vmw_overlay_resume_all(dev_priv);
863
316ab13a
JB		 864 WARN_ON(ret != 0);
865
fb1d9738
JB		 866 return 0;
867}
868
869static int vmw_framebuffer_dmabuf_unpin(struct vmw_framebuffer *vfb)
870{
871 struct vmw_private *dev_priv = vmw_priv(vfb->base.dev);
872 struct vmw_framebuffer_dmabuf *vfbd =
873 vmw_framebuffer_to_vfbd(&vfb->base);
874
875 if (!vfbd->buffer) {
876 WARN_ON(!vfbd->buffer);
877 return 0;
878 }
879
d991ef03 880 return vmw_dmabuf_unpin(dev_priv, vfbd->buffer, false);
fb1d9738
JB		 881}
882
d3216a0c
TH		 883static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv,
884 struct vmw_dma_buffer *dmabuf,
885 struct vmw_framebuffer **out,
886 const struct drm_mode_fb_cmd
887 *mode_cmd)
fb1d9738
JB		 888
889{
890 struct drm_device *dev = dev_priv->dev;
891 struct vmw_framebuffer_dmabuf *vfbd;
d3216a0c 892 unsigned int requested_size;
fb1d9738
JB		 893 int ret;
894
d3216a0c
TH		 895 requested_size = mode_cmd->height * mode_cmd->pitch;
896 if (unlikely(requested_size > dmabuf->base.num_pages * PAGE_SIZE)) {
897 DRM_ERROR("Screen buffer object size is too small "
898 "for requested mode.\n");
899 return -EINVAL;
900 }
901
c337ada7
JB		 902 /* Limited framebuffer color depth support for screen objects */
903 if (dev_priv->sou_priv) {
904 switch (mode_cmd->depth) {
905 case 32:
906 case 24:
907 /* Only support 32 bpp for 32 and 24 depth fbs */
908 if (mode_cmd->bpp == 32)
909 break;
910
911 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
912 mode_cmd->depth, mode_cmd->bpp);
913 return -EINVAL;
914 case 16:
915 case 15:
916 /* Only support 16 bpp for 16 and 15 depth fbs */
917 if (mode_cmd->bpp == 16)
918 break;
919
920 DRM_ERROR("Invalid color depth/bbp: %d %d\n",
921 mode_cmd->depth, mode_cmd->bpp);
922 return -EINVAL;
923 default:
924 DRM_ERROR("Invalid color depth: %d\n", mode_cmd->depth);
925 return -EINVAL;
926 }
927 }
928
fb1d9738
JB		 929 vfbd = kzalloc(sizeof(*vfbd), GFP_KERNEL);
930 if (!vfbd) {
931 ret = -ENOMEM;
932 goto out_err1;
933 }
934
935 ret = drm_framebuffer_init(dev, &vfbd->base.base,
936 &vmw_framebuffer_dmabuf_funcs);
937 if (ret)
938 goto out_err2;
939
940 if (!vmw_dmabuf_reference(dmabuf)) {
941 DRM_ERROR("failed to reference dmabuf %p\n", dmabuf);
942 goto out_err3;
943 }
944
d3216a0c
TH		 945 vfbd->base.base.bits_per_pixel = mode_cmd->bpp;
946 vfbd->base.base.pitch = mode_cmd->pitch;
947 vfbd->base.base.depth = mode_cmd->depth;
948 vfbd->base.base.width = mode_cmd->width;
949 vfbd->base.base.height = mode_cmd->height;
56d1c78d
JB		 950 if (!dev_priv->sou_priv) {
951 vfbd->base.pin = vmw_framebuffer_dmabuf_pin;
952 vfbd->base.unpin = vmw_framebuffer_dmabuf_unpin;
953 }
2fcd5a73 954 vfbd->base.dmabuf = true;
fb1d9738 955 vfbd->buffer = dmabuf;
90ff18bc 956 vfbd->base.user_handle = mode_cmd->handle;
fb1d9738
JB		 957 *out = &vfbd->base;
958
959 return 0;
960
961out_err3:
962 drm_framebuffer_cleanup(&vfbd->base.base);
963out_err2:
964 kfree(vfbd);
965out_err1:
966 return ret;
967}
968
969/*
970 * Generic Kernel modesetting functions
971 */
972
973static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev,
974 struct drm_file *file_priv,
975 struct drm_mode_fb_cmd *mode_cmd)
976{
977 struct vmw_private *dev_priv = vmw_priv(dev);
978 struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile;
979 struct vmw_framebuffer *vfb = NULL;
980 struct vmw_surface *surface = NULL;
981 struct vmw_dma_buffer *bo = NULL;
90ff18bc 982 struct ttm_base_object *user_obj;
e133e737 983 u64 required_size;
fb1d9738
JB		 984 int ret;
985
d3216a0c
TH		 986 /**
987 * This code should be conditioned on Screen Objects not being used.
988 * If screen objects are used, we can allocate a GMR to hold the
989 * requested framebuffer.
990 */
991
992 required_size = mode_cmd->pitch * mode_cmd->height;
e133e737 993 if (unlikely(required_size > (u64) dev_priv->vram_size)) {
d3216a0c
TH		 994 DRM_ERROR("VRAM size is too small for requested mode.\n");
995 return NULL;
996 }
997
90ff18bc
TH		 998 /*
999 * Take a reference on the user object of the resource
1000 * backing the kms fb. This ensures that user-space handle
1001 * lookups on that resource will always work as long as
1002 * it's registered with a kms framebuffer. This is important,
1003 * since vmw_execbuf_process identifies resources in the
1004 * command stream using user-space handles.
1005 */
1006
1007 user_obj = ttm_base_object_lookup(tfile, mode_cmd->handle);
1008 if (unlikely(user_obj == NULL)) {
1009 DRM_ERROR("Could not locate requested kms frame buffer.\n");
1010 return ERR_PTR(-ENOENT);
1011 }
1012
d3216a0c
TH		 1013 /**
1014 * End conditioned code.
1015 */
1016
7a73ba74
TH		 1017 ret = vmw_user_surface_lookup_handle(dev_priv, tfile,
1018 mode_cmd->handle, &surface);
fb1d9738
JB		 1019 if (ret)
1020 goto try_dmabuf;
1021
5ffdb658
JB		 1022 if (!surface->scanout)
1023 goto err_not_scanout;
1024
3a939a5e
TH		 1025 ret = vmw_kms_new_framebuffer_surface(dev_priv, file_priv, surface,
1026 &vfb, mode_cmd);
fb1d9738
JB		 1027
1028 /* vmw_user_surface_lookup takes one ref so does new_fb */
1029 vmw_surface_unreference(&surface);
1030
1031 if (ret) {
1032 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 1033 ttm_base_object_unref(&user_obj);
cce13ff7 1034 return ERR_PTR(ret);
90ff18bc
TH		 1035 } else
1036 vfb->user_obj = user_obj;
fb1d9738
JB		 1037 return &vfb->base;
1038
1039try_dmabuf:
1040 DRM_INFO("%s: trying buffer\n", __func__);
1041
1042 ret = vmw_user_dmabuf_lookup(tfile, mode_cmd->handle, &bo);
1043 if (ret) {
1044 DRM_ERROR("failed to find buffer: %i\n", ret);
cce13ff7 1045 return ERR_PTR(-ENOENT);
fb1d9738
JB		 1046 }
1047
1048 ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb,
d3216a0c 1049 mode_cmd);
fb1d9738
JB		 1050
1051 /* vmw_user_dmabuf_lookup takes one ref so does new_fb */
1052 vmw_dmabuf_unreference(&bo);
1053
1054 if (ret) {
1055 DRM_ERROR("failed to create vmw_framebuffer: %i\n", ret);
90ff18bc 1056 ttm_base_object_unref(&user_obj);
cce13ff7 1057 return ERR_PTR(ret);
90ff18bc
TH		 1058 } else
1059 vfb->user_obj = user_obj;
fb1d9738
JB		 1060
1061 return &vfb->base;
5ffdb658
JB		 1062
1063err_not_scanout:
1064 DRM_ERROR("surface not marked as scanout\n");
1065 /* vmw_user_surface_lookup takes one ref */
1066 vmw_surface_unreference(&surface);
90ff18bc 1067 ttm_base_object_unref(&user_obj);
5ffdb658 1068
cce13ff7 1069 return ERR_PTR(-EINVAL);
fb1d9738
JB		 1070}
1071
fb1d9738
JB		 1072static struct drm_mode_config_funcs vmw_kms_funcs = {
1073 .fb_create = vmw_kms_fb_create,
fb1d9738
JB		 1074};
1075
2fcd5a73
JB		 1076int vmw_kms_present(struct vmw_private *dev_priv,
1077 struct drm_file *file_priv,
1078 struct vmw_framebuffer *vfb,
1079 struct vmw_surface *surface,
1080 uint32_t sid,
1081 int32_t destX, int32_t destY,
1082 struct drm_vmw_rect *clips,
1083 uint32_t num_clips)
1084{
c6ca8391
JB		 1085 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1086 struct drm_crtc *crtc;
2fcd5a73 1087 size_t fifo_size;
c6ca8391
JB		 1088 int i, k, num_units;
1089 int ret = 0; /* silence warning */
2fcd5a73
JB		 1090
1091 struct {
1092 SVGA3dCmdHeader header;
1093 SVGA3dCmdBlitSurfaceToScreen body;
1094 } *cmd;
1095 SVGASignedRect *blits;
1096
c6ca8391
JB		 1097 num_units = 0;
1098 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1099 if (crtc->fb != &vfb->base)
1100 continue;
1101 units[num_units++] = vmw_crtc_to_du(crtc);
1102 }
1103
2fcd5a73
JB		 1104 BUG_ON(surface == NULL);
1105 BUG_ON(!clips || !num_clips);
1106
1107 fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num_clips;
1108 cmd = kmalloc(fifo_size, GFP_KERNEL);
1109 if (unlikely(cmd == NULL)) {
1110 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1111 return -ENOMEM;
1112 }
1113
c6ca8391 1114 /* only need to do this once */
2fcd5a73 1115 memset(cmd, 0, fifo_size);
2fcd5a73
JB		 1116 cmd->header.id = cpu_to_le32(SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN);
1117 cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header));
1118
2fcd5a73
JB		 1119 cmd->body.srcRect.left = 0;
1120 cmd->body.srcRect.right = surface->sizes[0].width;
1121 cmd->body.srcRect.top = 0;
1122 cmd->body.srcRect.bottom = surface->sizes[0].height;
1123
2fcd5a73
JB		 1124 blits = (SVGASignedRect *)&cmd[1];
1125 for (i = 0; i < num_clips; i++) {
1126 blits[i].left = clips[i].x;
1127 blits[i].right = clips[i].x + clips[i].w;
1128 blits[i].top = clips[i].y;
1129 blits[i].bottom = clips[i].y + clips[i].h;
1130 }
1131
c6ca8391
JB		 1132 for (k = 0; k < num_units; k++) {
1133 struct vmw_display_unit *unit = units[k];
1134 int clip_x1 = destX - unit->crtc.x;
1135 int clip_y1 = destY - unit->crtc.y;
1136 int clip_x2 = clip_x1 + surface->sizes[0].width;
1137 int clip_y2 = clip_y1 + surface->sizes[0].height;
1138
1139 /* skip any crtcs that misses the clip region */
1140 if (clip_x1 >= unit->crtc.mode.hdisplay ||
1141 clip_y1 >= unit->crtc.mode.vdisplay ||
1142 clip_x2 <= 0 || clip_y2 <= 0)
1143 continue;
1144
1145 /* need to reset sid as it is changed by execbuf */
1146 cmd->body.srcImage.sid = sid;
1147
1148 cmd->body.destScreenId = unit->unit;
1149
1150 /*
1151 * The blit command is a lot more resilient then the
1152 * readback command when it comes to clip rects. So its
1153 * okay to go out of bounds.
1154 */
1155
1156 cmd->body.destRect.left = clip_x1;
1157 cmd->body.destRect.right = clip_x2;
1158 cmd->body.destRect.top = clip_y1;
1159 cmd->body.destRect.bottom = clip_y2;
1160
1161 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd,
1162 fifo_size, 0, NULL);
1163
1164 if (unlikely(ret != 0))
1165 break;
1166 }
2fcd5a73
JB		 1167
1168 kfree(cmd);
1169
1170 return ret;
1171}
1172
1173int vmw_kms_readback(struct vmw_private *dev_priv,
1174 struct drm_file *file_priv,
1175 struct vmw_framebuffer *vfb,
1176 struct drm_vmw_fence_rep __user *user_fence_rep,
1177 struct drm_vmw_rect *clips,
1178 uint32_t num_clips)
1179{
1180 struct vmw_framebuffer_dmabuf *vfbd =
1181 vmw_framebuffer_to_vfbd(&vfb->base);
1182 struct vmw_dma_buffer *dmabuf = vfbd->buffer;
1183 struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS];
1184 struct drm_crtc *crtc;
1185 size_t fifo_size;
1186 int i, k, ret, num_units, blits_pos;
1187
1188 struct {
1189 uint32_t header;
1190 SVGAFifoCmdDefineGMRFB body;
1191 } *cmd;
1192 struct {
1193 uint32_t header;
1194 SVGAFifoCmdBlitScreenToGMRFB body;
1195 } *blits;
1196
1197 num_units = 0;
1198 list_for_each_entry(crtc, &dev_priv->dev->mode_config.crtc_list, head) {
1199 if (crtc->fb != &vfb->base)
1200 continue;
1201 units[num_units++] = vmw_crtc_to_du(crtc);
1202 }
1203
1204 BUG_ON(dmabuf == NULL);
1205 BUG_ON(!clips || !num_clips);
1206
1207 /* take a safe guess at fifo size */
1208 fifo_size = sizeof(*cmd) + sizeof(*blits) * num_clips * num_units;
1209 cmd = kmalloc(fifo_size, GFP_KERNEL);
1210 if (unlikely(cmd == NULL)) {
1211 DRM_ERROR("Failed to allocate temporary fifo memory.\n");
1212 return -ENOMEM;
1213 }
1214
1215 memset(cmd, 0, fifo_size);
1216 cmd->header = SVGA_CMD_DEFINE_GMRFB;
1217 cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel;
1218 cmd->body.format.colorDepth = vfb->base.depth;
1219 cmd->body.format.reserved = 0;
1220 cmd->body.bytesPerLine = vfb->base.pitch;
90ff18bc 1221 cmd->body.ptr.gmrId = vfb->user_handle;
2fcd5a73
JB		 1222 cmd->body.ptr.offset = 0;
1223
1224 blits = (void *)&cmd[1];
1225 blits_pos = 0;
1226 for (i = 0; i < num_units; i++) {
1227 struct drm_vmw_rect *c = clips;
1228 for (k = 0; k < num_clips; k++, c++) {
1229 /* transform clip coords to crtc origin based coords */
1230 int clip_x1 = c->x - units[i]->crtc.x;
1231 int clip_x2 = c->x - units[i]->crtc.x + c->w;
1232 int clip_y1 = c->y - units[i]->crtc.y;
1233 int clip_y2 = c->y - units[i]->crtc.y + c->h;
1234 int dest_x = c->x;
1235 int dest_y = c->y;
1236
1237 /* compensate for clipping, we negate
1238 * a negative number and add that.
1239 */
1240 if (clip_x1 < 0)
1241 dest_x += -clip_x1;
1242 if (clip_y1 < 0)
1243 dest_y += -clip_y1;
1244
1245 /* clip */
1246 clip_x1 = max(clip_x1, 0);
1247 clip_y1 = max(clip_y1, 0);
1248 clip_x2 = min(clip_x2, units[i]->crtc.mode.hdisplay);
1249 clip_y2 = min(clip_y2, units[i]->crtc.mode.vdisplay);
1250
1251 /* and cull any rects that misses the crtc */
1252 if (clip_x1 >= units[i]->crtc.mode.hdisplay ||
1253 clip_y1 >= units[i]->crtc.mode.vdisplay ||
1254 clip_x2 <= 0 || clip_y2 <= 0)
1255 continue;
1256
1257 blits[blits_pos].header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1258 blits[blits_pos].body.srcScreenId = units[i]->unit;
1259 blits[blits_pos].body.destOrigin.x = dest_x;
1260 blits[blits_pos].body.destOrigin.y = dest_y;
1261
1262 blits[blits_pos].body.srcRect.left = clip_x1;
1263 blits[blits_pos].body.srcRect.top = clip_y1;
1264 blits[blits_pos].body.srcRect.right = clip_x2;
1265 blits[blits_pos].body.srcRect.bottom = clip_y2;
1266 blits_pos++;
1267 }
1268 }
1269 /* reset size here and use calculated exact size from loops */
1270 fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos;
1271
1272 ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size,
1273 0, user_fence_rep);
1274
1275 kfree(cmd);
1276
1277 return ret;
1278}
1279
fb1d9738
JB		 1280int vmw_kms_init(struct vmw_private *dev_priv)
1281{
1282 struct drm_device *dev = dev_priv->dev;
1283 int ret;
1284
1285 drm_mode_config_init(dev);
1286 dev->mode_config.funcs = &vmw_kms_funcs;
3bef3572
JB		 1287 dev->mode_config.min_width = 1;
1288 dev->mode_config.min_height = 1;
7e71f8a5
JB		 1289 /* assumed largest fb size */
1290 dev->mode_config.max_width = 8192;
1291 dev->mode_config.max_height = 8192;
fb1d9738 1292
56d1c78d
JB		 1293 ret = vmw_kms_init_screen_object_display(dev_priv);
1294 if (ret) /* Fallback */
1295 (void)vmw_kms_init_legacy_display_system(dev_priv);
fb1d9738
JB		 1296
1297 return 0;
1298}
1299
1300int vmw_kms_close(struct vmw_private *dev_priv)
1301{
1302 /*
1303 * Docs says we should take the lock before calling this function
1304 * but since it destroys encoders and our destructor calls
1305 * drm_encoder_cleanup which takes the lock we deadlock.
1306 */
1307 drm_mode_config_cleanup(dev_priv->dev);
1308 vmw_kms_close_legacy_display_system(dev_priv);
1309 return 0;
1310}
1311
1312int vmw_kms_cursor_bypass_ioctl(struct drm_device *dev, void *data,
1313 struct drm_file *file_priv)
1314{
1315 struct drm_vmw_cursor_bypass_arg *arg = data;
1316 struct vmw_display_unit *du;
1317 struct drm_mode_object *obj;
1318 struct drm_crtc *crtc;
1319 int ret = 0;
1320
1321
1322 mutex_lock(&dev->mode_config.mutex);
1323 if (arg->flags & DRM_VMW_CURSOR_BYPASS_ALL) {
1324
1325 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1326 du = vmw_crtc_to_du(crtc);
1327 du->hotspot_x = arg->xhot;
1328 du->hotspot_y = arg->yhot;
1329 }
1330
1331 mutex_unlock(&dev->mode_config.mutex);
1332 return 0;
1333 }
1334
1335 obj = drm_mode_object_find(dev, arg->crtc_id, DRM_MODE_OBJECT_CRTC);
1336 if (!obj) {
1337 ret = -EINVAL;
1338 goto out;
1339 }
1340
1341 crtc = obj_to_crtc(obj);
1342 du = vmw_crtc_to_du(crtc);
1343
1344 du->hotspot_x = arg->xhot;
1345 du->hotspot_y = arg->yhot;
1346
1347out:
1348 mutex_unlock(&dev->mode_config.mutex);
1349
1350 return ret;
1351}
1352
0bef23f9 1353int vmw_kms_write_svga(struct vmw_private *vmw_priv,
d7e1958d 1354 unsigned width, unsigned height, unsigned pitch,
6558429b 1355 unsigned bpp, unsigned depth)
fb1d9738 1356{
d7e1958d
JB		 1357 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1358 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch);
1359 else if (vmw_fifo_have_pitchlock(vmw_priv))
1360 iowrite32(pitch, vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
1361 vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
1362 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
6558429b 1363 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp);
0bef23f9
MD		 1364
1365 if (vmw_read(vmw_priv, SVGA_REG_DEPTH) != depth) {
1366 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n",
1367 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH));
1368 return -EINVAL;
1369 }
1370
1371 return 0;
d7e1958d 1372}
fb1d9738 1373
d7e1958d
JB		 1374int vmw_kms_save_vga(struct vmw_private *vmw_priv)
1375{
7c4f7780
TH		 1376 struct vmw_vga_topology_state *save;
1377 uint32_t i;
1378
fb1d9738
JB		 1379 vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
1380 vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
7c4f7780 1381 vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
d7e1958d
JB		 1382 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1383 vmw_priv->vga_pitchlock =
7c4f7780 1384 vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
d7e1958d 1385 else if (vmw_fifo_have_pitchlock(vmw_priv))
7c4f7780
TH		 1386 vmw_priv->vga_pitchlock = ioread32(vmw_priv->mmio_virt +
1387 SVGA_FIFO_PITCHLOCK);
1388
1389 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1390 return 0;
fb1d9738 1391
7c4f7780
TH		 1392 vmw_priv->num_displays = vmw_read(vmw_priv,
1393 SVGA_REG_NUM_GUEST_DISPLAYS);
1394
029e50bf
TH		 1395 if (vmw_priv->num_displays == 0)
1396 vmw_priv->num_displays = 1;
1397
7c4f7780
TH		 1398 for (i = 0; i < vmw_priv->num_displays; ++i) {
1399 save = &vmw_priv->vga_save[i];
1400 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1401 save->primary = vmw_read(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY);
1402 save->pos_x = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_X);
1403 save->pos_y = vmw_read(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y);
1404 save->width = vmw_read(vmw_priv, SVGA_REG_DISPLAY_WIDTH);
1405 save->height = vmw_read(vmw_priv, SVGA_REG_DISPLAY_HEIGHT);
1406 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
30c78bb8
TH		 1407 if (i == 0 && vmw_priv->num_displays == 1 &&
1408 save->width == 0 && save->height == 0) {
1409
1410 /*
1411 * It should be fairly safe to assume that these
1412 * values are uninitialized.
1413 */
1414
1415 save->width = vmw_priv->vga_width - save->pos_x;
1416 save->height = vmw_priv->vga_height - save->pos_y;
1417 }
7c4f7780 1418 }
30c78bb8 1419
fb1d9738
JB		 1420 return 0;
1421}
1422
1423int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
1424{
7c4f7780
TH		 1425 struct vmw_vga_topology_state *save;
1426 uint32_t i;
1427
fb1d9738
JB		 1428 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
1429 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
7c4f7780 1430 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
d7e1958d
JB		 1431 if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
1432 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
1433 vmw_priv->vga_pitchlock);
1434 else if (vmw_fifo_have_pitchlock(vmw_priv))
1435 iowrite32(vmw_priv->vga_pitchlock,
1436 vmw_priv->mmio_virt + SVGA_FIFO_PITCHLOCK);
fb1d9738 1437
7c4f7780
TH		 1438 if (!(vmw_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY))
1439 return 0;
1440
1441 for (i = 0; i < vmw_priv->num_displays; ++i) {
1442 save = &vmw_priv->vga_save[i];
1443 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i);
1444 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, save->primary);
1445 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, save->pos_x);
1446 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, save->pos_y);
1447 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, save->width);
1448 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, save->height);
1449 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID);
1450 }
1451
fb1d9738
JB		 1452 return 0;
1453}
d8bd19d2 1454
e133e737
TH		 1455bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
1456 uint32_t pitch,
1457 uint32_t height)
1458{
1459 return ((u64) pitch * (u64) height) < (u64) dev_priv->vram_size;
1460}
1461
7a1c2f6c
TH		 1462u32 vmw_get_vblank_counter(struct drm_device *dev, int crtc)
1463{
1464 return 0;
1465}
626ab771
JB		 1466
1467
1468/*
1469 * Small shared kms functions.
1470 */
1471
1472int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num,
1473 struct drm_vmw_rect *rects)
1474{
1475 struct drm_device *dev = dev_priv->dev;
1476 struct vmw_display_unit *du;
1477 struct drm_connector *con;
626ab771
JB		 1478
1479 mutex_lock(&dev->mode_config.mutex);
1480
1481#if 0
6ea77d13
TH		 1482 {
1483 unsigned int i;
1484
1485 DRM_INFO("%s: new layout ", __func__);
1486 for (i = 0; i < num; i++)
1487 DRM_INFO("(%i, %i %ux%u) ", rects[i].x, rects[i].y,
1488 rects[i].w, rects[i].h);
1489 DRM_INFO("\n");
1490 }
626ab771
JB		 1491#endif
1492
1493 list_for_each_entry(con, &dev->mode_config.connector_list, head) {
1494 du = vmw_connector_to_du(con);
1495 if (num > du->unit) {
1496 du->pref_width = rects[du->unit].w;
1497 du->pref_height = rects[du->unit].h;
1498 du->pref_active = true;
1499 } else {
1500 du->pref_width = 800;
1501 du->pref_height = 600;
1502 du->pref_active = false;
1503 }
1504 con->status = vmw_du_connector_detect(con, true);
1505 }
1506
1507 mutex_unlock(&dev->mode_config.mutex);
1508
1509 return 0;
1510}
1511
1512void vmw_du_crtc_save(struct drm_crtc *crtc)
1513{
1514}
1515
1516void vmw_du_crtc_restore(struct drm_crtc *crtc)
1517{
1518}
1519
1520void vmw_du_crtc_gamma_set(struct drm_crtc *crtc,
1521 u16 *r, u16 *g, u16 *b,
1522 uint32_t start, uint32_t size)
1523{
1524 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
1525 int i;
1526
1527 for (i = 0; i < size; i++) {
1528 DRM_DEBUG("%d r/g/b = 0x%04x / 0x%04x / 0x%04x\n", i,
1529 r[i], g[i], b[i]);
1530 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 0, r[i] >> 8);
1531 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 1, g[i] >> 8);
1532 vmw_write(dev_priv, SVGA_PALETTE_BASE + i * 3 + 2, b[i] >> 8);
1533 }
1534}
1535
1536void vmw_du_connector_dpms(struct drm_connector *connector, int mode)
1537{
1538}
1539
1540void vmw_du_connector_save(struct drm_connector *connector)
1541{
1542}
1543
1544void vmw_du_connector_restore(struct drm_connector *connector)
1545{
1546}
1547
1548enum drm_connector_status
1549vmw_du_connector_detect(struct drm_connector *connector, bool force)
1550{
1551 uint32_t num_displays;
1552 struct drm_device *dev = connector->dev;
1553 struct vmw_private *dev_priv = vmw_priv(dev);
1554
1555 mutex_lock(&dev_priv->hw_mutex);
1556 num_displays = vmw_read(dev_priv, SVGA_REG_NUM_DISPLAYS);
1557 mutex_unlock(&dev_priv->hw_mutex);
1558
1559 return ((vmw_connector_to_du(connector)->unit < num_displays) ?
1560 connector_status_connected : connector_status_disconnected);
1561}
1562
1563static struct drm_display_mode vmw_kms_connector_builtin[] = {
1564 /* 640x480@60Hz */
1565 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
1566 752, 800, 0, 480, 489, 492, 525, 0,
1567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1568 /* 800x600@60Hz */
1569 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
1570 968, 1056, 0, 600, 601, 605, 628, 0,
1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1572 /* 1024x768@60Hz */
1573 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
1574 1184, 1344, 0, 768, 771, 777, 806, 0,
1575 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
1576 /* 1152x864@75Hz */
1577 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
1578 1344, 1600, 0, 864, 865, 868, 900, 0,
1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1580 /* 1280x768@60Hz */
1581 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
1582 1472, 1664, 0, 768, 771, 778, 798, 0,
1583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1584 /* 1280x800@60Hz */
1585 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
1586 1480, 1680, 0, 800, 803, 809, 831, 0,
1587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
1588 /* 1280x960@60Hz */
1589 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
1590 1488, 1800, 0, 960, 961, 964, 1000, 0,
1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1592 /* 1280x1024@60Hz */
1593 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
1594 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
1595 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1596 /* 1360x768@60Hz */
1597 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
1598 1536, 1792, 0, 768, 771, 777, 795, 0,
1599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1600 /* 1440x1050@60Hz */
1601 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
1602 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
1603 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1604 /* 1440x900@60Hz */
1605 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
1606 1672, 1904, 0, 900, 903, 909, 934, 0,
1607 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1608 /* 1600x1200@60Hz */
1609 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
1610 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
1611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1612 /* 1680x1050@60Hz */
1613 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
1614 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
1615 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1616 /* 1792x1344@60Hz */
1617 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
1618 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
1619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1620 /* 1853x1392@60Hz */
1621 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
1622 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
1623 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1624 /* 1920x1200@60Hz */
1625 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
1626 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
1627 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1628 /* 1920x1440@60Hz */
1629 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
1630 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
1631 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1632 /* 2560x1600@60Hz */
1633 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
1634 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
1635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
1636 /* Terminate */
1637 { DRM_MODE("", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) },
1638};
1639
1640int vmw_du_connector_fill_modes(struct drm_connector *connector,
1641 uint32_t max_width, uint32_t max_height)
1642{
1643 struct vmw_display_unit *du = vmw_connector_to_du(connector);
1644 struct drm_device *dev = connector->dev;
1645 struct vmw_private *dev_priv = vmw_priv(dev);
1646 struct drm_display_mode *mode = NULL;
1647 struct drm_display_mode *bmode;
1648 struct drm_display_mode prefmode = { DRM_MODE("preferred",
1649 DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
1650 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1651 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC)
1652 };
1653 int i;
1654
1655 /* Add preferred mode */
1656 {
1657 mode = drm_mode_duplicate(dev, &prefmode);
1658 if (!mode)
1659 return 0;
1660 mode->hdisplay = du->pref_width;
1661 mode->vdisplay = du->pref_height;
1662 mode->vrefresh = drm_mode_vrefresh(mode);
1663 if (vmw_kms_validate_mode_vram(dev_priv, mode->hdisplay * 2,
1664 mode->vdisplay)) {
1665 drm_mode_probed_add(connector, mode);
1666
1667 if (du->pref_mode) {
1668 list_del_init(&du->pref_mode->head);
1669 drm_mode_destroy(dev, du->pref_mode);
1670 }
1671
1672 du->pref_mode = mode;
1673 }
1674 }
1675
1676 for (i = 0; vmw_kms_connector_builtin[i].type != 0; i++) {
1677 bmode = &vmw_kms_connector_builtin[i];
1678 if (bmode->hdisplay > max_width ||
1679 bmode->vdisplay > max_height)
1680 continue;
1681
1682 if (!vmw_kms_validate_mode_vram(dev_priv, bmode->hdisplay * 2,
1683 bmode->vdisplay))
1684 continue;
1685
1686 mode = drm_mode_duplicate(dev, bmode);
1687 if (!mode)
1688 return 0;
1689 mode->vrefresh = drm_mode_vrefresh(mode);
1690
1691 drm_mode_probed_add(connector, mode);
1692 }
1693
1694 drm_mode_connector_list_update(connector);
1695
1696 return 1;
1697}
1698
1699int vmw_du_connector_set_property(struct drm_connector *connector,
1700 struct drm_property *property,
1701 uint64_t val)
1702{
1703 return 0;
1704}
Linux kernel - Deliverables
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